1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> |
4 | */ |
5 | |
6 | #include <linux/kernel.h> |
7 | #include <linux/bitops.h> |
8 | #include <linux/err.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/reset-controller.h> |
15 | |
16 | #include <dt-bindings/clock/qcom,gcc-mdm9607.h> |
17 | |
18 | #include "common.h" |
19 | #include "clk-regmap.h" |
20 | #include "clk-alpha-pll.h" |
21 | #include "clk-pll.h" |
22 | #include "clk-rcg.h" |
23 | #include "clk-branch.h" |
24 | #include "reset.h" |
25 | #include "gdsc.h" |
26 | |
27 | enum { |
28 | P_XO, |
29 | P_BIMC, |
30 | P_GPLL0, |
31 | P_GPLL1, |
32 | P_GPLL2, |
33 | P_SLEEP_CLK, |
34 | }; |
35 | |
36 | static struct clk_alpha_pll gpll0_early = { |
37 | .offset = 0x21000, |
38 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
39 | .clkr = { |
40 | .enable_reg = 0x45000, |
41 | .enable_mask = BIT(0), |
42 | .hw.init = &(struct clk_init_data) |
43 | { |
44 | .name = "gpll0_early" , |
45 | .parent_data = &(const struct clk_parent_data){ |
46 | .fw_name = "xo" , |
47 | }, |
48 | .num_parents = 1, |
49 | .ops = &clk_alpha_pll_ops, |
50 | }, |
51 | }, |
52 | }; |
53 | |
54 | static struct clk_alpha_pll_postdiv gpll0 = { |
55 | .offset = 0x21000, |
56 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
57 | .clkr.hw.init = &(struct clk_init_data) |
58 | { |
59 | .name = "gpll0" , |
60 | .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw }, |
61 | .num_parents = 1, |
62 | .ops = &clk_alpha_pll_postdiv_ops, |
63 | }, |
64 | }; |
65 | |
66 | static const struct parent_map gcc_xo_gpll0_map[] = { |
67 | { P_XO, 0 }, |
68 | { P_GPLL0, 1 }, |
69 | }; |
70 | |
71 | static const struct clk_parent_data gcc_xo_gpll0[] = { |
72 | { .fw_name = "xo" }, |
73 | { .hw = &gpll0.clkr.hw }, |
74 | }; |
75 | |
76 | static struct clk_pll gpll1 = { |
77 | .l_reg = 0x20004, |
78 | .m_reg = 0x20008, |
79 | .n_reg = 0x2000c, |
80 | .config_reg = 0x20010, |
81 | .mode_reg = 0x20000, |
82 | .status_reg = 0x2001c, |
83 | .status_bit = 17, |
84 | .clkr.hw.init = &(struct clk_init_data){ |
85 | .name = "gpll1" , |
86 | .parent_data = &(const struct clk_parent_data){ |
87 | .fw_name = "xo" , |
88 | }, |
89 | .num_parents = 1, |
90 | .ops = &clk_pll_ops, |
91 | }, |
92 | }; |
93 | |
94 | static struct clk_regmap gpll1_vote = { |
95 | .enable_reg = 0x45000, |
96 | .enable_mask = BIT(1), |
97 | .hw.init = &(struct clk_init_data){ |
98 | .name = "gpll1_vote" , |
99 | .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw }, |
100 | .num_parents = 1, |
101 | .ops = &clk_pll_vote_ops, |
102 | }, |
103 | }; |
104 | |
105 | static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { |
106 | { P_XO, 0 }, |
107 | { P_GPLL0, 1 }, |
108 | { P_GPLL1, 2 }, |
109 | { P_SLEEP_CLK, 6 }, |
110 | }; |
111 | |
112 | static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = { |
113 | { .fw_name = "xo" }, |
114 | { .hw = &gpll0.clkr.hw }, |
115 | { .hw = &gpll1_vote.hw }, |
116 | { .fw_name = "sleep_clk" }, |
117 | }; |
118 | |
119 | static struct clk_alpha_pll gpll2_early = { |
120 | .offset = 0x25000, |
121 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
122 | .clkr = { |
123 | .enable_reg = 0x45000, |
124 | .enable_mask = BIT(3), /* Yeah, apparently it's not 2 */ |
125 | .hw.init = &(struct clk_init_data) |
126 | { |
127 | .name = "gpll2_early" , |
128 | .parent_data = &(const struct clk_parent_data){ |
129 | .fw_name = "xo" , |
130 | }, |
131 | .num_parents = 1, |
132 | .ops = &clk_alpha_pll_ops, |
133 | }, |
134 | }, |
135 | }; |
136 | |
137 | static struct clk_alpha_pll_postdiv gpll2 = { |
138 | .offset = 0x25000, |
139 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], |
140 | .clkr.hw.init = &(struct clk_init_data) |
141 | { |
142 | .name = "gpll2" , |
143 | .parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw }, |
144 | .num_parents = 1, |
145 | .ops = &clk_alpha_pll_postdiv_ops, |
146 | }, |
147 | }; |
148 | |
149 | static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { |
150 | { P_XO, 0 }, |
151 | { P_GPLL0, 1 }, |
152 | { P_GPLL2, 2 }, |
153 | }; |
154 | |
155 | static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { |
156 | { .fw_name = "xo" }, |
157 | { .hw = &gpll0.clkr.hw }, |
158 | { .hw = &gpll2.clkr.hw }, |
159 | }; |
160 | |
161 | static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = { |
162 | { P_XO, 0 }, |
163 | { P_GPLL0, 1 }, |
164 | { P_GPLL1, 2 }, |
165 | { P_GPLL2, 3 }, |
166 | }; |
167 | |
168 | static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = { |
169 | { .fw_name = "xo" }, |
170 | { .hw = &gpll0.clkr.hw }, |
171 | { .hw = &gpll1_vote.hw }, |
172 | { .hw = &gpll2.clkr.hw }, |
173 | }; |
174 | |
175 | static const struct freq_tbl ftbl_apss_ahb_clk[] = { |
176 | F(19200000, P_XO, 1, 0, 0), |
177 | F(50000000, P_GPLL0, 16, 0, 0), |
178 | F(100000000, P_GPLL0, 8, 0, 0), |
179 | { } |
180 | }; |
181 | |
182 | static struct clk_rcg2 apss_ahb_clk_src = { |
183 | .cmd_rcgr = 0x46000, |
184 | .hid_width = 5, |
185 | .parent_map = gcc_xo_gpll0_map, |
186 | .freq_tbl = ftbl_apss_ahb_clk, |
187 | .clkr.hw.init = &(struct clk_init_data){ |
188 | .name = "apss_ahb_clk_src" , |
189 | .parent_data = gcc_xo_gpll0, |
190 | .num_parents = 2, |
191 | .ops = &clk_rcg2_ops, |
192 | }, |
193 | }; |
194 | |
195 | static struct clk_pll bimc_pll = { |
196 | .l_reg = 0x23004, |
197 | .m_reg = 0x23008, |
198 | .n_reg = 0x2300c, |
199 | .config_reg = 0x23010, |
200 | .mode_reg = 0x23000, |
201 | .status_reg = 0x2301c, |
202 | .status_bit = 17, |
203 | .clkr.hw.init = &(struct clk_init_data){ |
204 | .name = "bimc_pll" , |
205 | .parent_data = &(const struct clk_parent_data){ |
206 | .fw_name = "xo" , |
207 | }, |
208 | .num_parents = 1, |
209 | .ops = &clk_pll_ops, |
210 | }, |
211 | }; |
212 | |
213 | static struct clk_regmap bimc_pll_vote = { |
214 | .enable_reg = 0x45000, |
215 | .enable_mask = BIT(3), |
216 | .hw.init = &(struct clk_init_data){ |
217 | .name = "bimc_pll_vote" , |
218 | .parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw }, |
219 | .num_parents = 1, |
220 | .ops = &clk_pll_vote_ops, |
221 | }, |
222 | }; |
223 | |
224 | static const struct parent_map gcc_xo_gpll0_bimc_map[] = { |
225 | { P_XO, 0 }, |
226 | { P_GPLL0, 1 }, |
227 | { P_BIMC, 2 }, |
228 | }; |
229 | |
230 | static const struct clk_parent_data gcc_xo_gpll0_bimc[] = { |
231 | { .fw_name = "xo" }, |
232 | { .hw = &gpll0.clkr.hw }, |
233 | { .hw = &bimc_pll_vote.hw }, |
234 | }; |
235 | |
236 | static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { |
237 | F(19200000, P_XO, 1, 0, 0), |
238 | F(50000000, P_GPLL0, 16, 0, 0), |
239 | F(100000000, P_GPLL0, 8, 0, 0), |
240 | { } |
241 | }; |
242 | |
243 | static struct clk_rcg2 pcnoc_bfdcd_clk_src = { |
244 | .cmd_rcgr = 0x27000, |
245 | .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, |
246 | .hid_width = 5, |
247 | .parent_map = gcc_xo_gpll0_bimc_map, |
248 | .clkr.hw.init = &(struct clk_init_data){ |
249 | .name = "pcnoc_bfdcd_clk_src" , |
250 | .parent_data = gcc_xo_gpll0_bimc, |
251 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), |
252 | .ops = &clk_rcg2_ops, |
253 | .flags = CLK_IS_CRITICAL, |
254 | }, |
255 | }; |
256 | |
257 | static struct clk_rcg2 system_noc_bfdcd_clk_src = { |
258 | .cmd_rcgr = 0x26004, |
259 | .hid_width = 5, |
260 | .parent_map = gcc_xo_gpll0_bimc_map, |
261 | .clkr.hw.init = &(struct clk_init_data){ |
262 | .name = "system_noc_bfdcd_clk_src" , |
263 | .parent_data = gcc_xo_gpll0_bimc, |
264 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), |
265 | .ops = &clk_rcg2_ops, |
266 | }, |
267 | }; |
268 | |
269 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { |
270 | F(19200000, P_XO, 1, 0, 0), |
271 | F(50000000, P_GPLL0, 16, 0, 0), |
272 | { } |
273 | }; |
274 | |
275 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { |
276 | .cmd_rcgr = 0x200c, |
277 | .hid_width = 5, |
278 | .parent_map = gcc_xo_gpll0_map, |
279 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
280 | .clkr.hw.init = &(struct clk_init_data){ |
281 | .name = "blsp1_qup1_i2c_apps_clk_src" , |
282 | .parent_data = gcc_xo_gpll0, |
283 | .num_parents = 2, |
284 | .ops = &clk_rcg2_ops, |
285 | }, |
286 | }; |
287 | |
288 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { |
289 | F(960000, P_XO, 10, 1, 2), |
290 | F(4800000, P_XO, 4, 0, 0), |
291 | F(9600000, P_XO, 2, 0, 0), |
292 | F(16000000, P_GPLL0, 10, 1, 5), |
293 | F(19200000, P_XO, 1, 0, 0), |
294 | F(25000000, P_GPLL0, 16, 1, 2), |
295 | F(50000000, P_GPLL0, 16, 0, 0), |
296 | { } |
297 | }; |
298 | |
299 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { |
300 | .cmd_rcgr = 0x2024, |
301 | .mnd_width = 8, |
302 | .hid_width = 5, |
303 | .parent_map = gcc_xo_gpll0_map, |
304 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
305 | .clkr.hw.init = &(struct clk_init_data){ |
306 | .name = "blsp1_qup1_spi_apps_clk_src" , |
307 | .parent_data = gcc_xo_gpll0, |
308 | .num_parents = 2, |
309 | .ops = &clk_rcg2_ops, |
310 | }, |
311 | }; |
312 | |
313 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { |
314 | .cmd_rcgr = 0x3000, |
315 | .hid_width = 5, |
316 | .parent_map = gcc_xo_gpll0_map, |
317 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
318 | .clkr.hw.init = &(struct clk_init_data){ |
319 | .name = "blsp1_qup2_i2c_apps_clk_src" , |
320 | .parent_data = gcc_xo_gpll0, |
321 | .num_parents = 2, |
322 | .ops = &clk_rcg2_ops, |
323 | }, |
324 | }; |
325 | |
326 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { |
327 | .cmd_rcgr = 0x3014, |
328 | .mnd_width = 8, |
329 | .hid_width = 5, |
330 | .parent_map = gcc_xo_gpll0_map, |
331 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
332 | .clkr.hw.init = &(struct clk_init_data){ |
333 | .name = "blsp1_qup2_spi_apps_clk_src" , |
334 | .parent_data = gcc_xo_gpll0, |
335 | .num_parents = 2, |
336 | .ops = &clk_rcg2_ops, |
337 | }, |
338 | }; |
339 | |
340 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { |
341 | .cmd_rcgr = 0x4000, |
342 | .hid_width = 5, |
343 | .parent_map = gcc_xo_gpll0_map, |
344 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
345 | .clkr.hw.init = &(struct clk_init_data){ |
346 | .name = "blsp1_qup3_i2c_apps_clk_src" , |
347 | .parent_data = gcc_xo_gpll0, |
348 | .num_parents = 2, |
349 | .ops = &clk_rcg2_ops, |
350 | }, |
351 | }; |
352 | |
353 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { |
354 | .cmd_rcgr = 0x4024, |
355 | .mnd_width = 8, |
356 | .hid_width = 5, |
357 | .parent_map = gcc_xo_gpll0_map, |
358 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
359 | .clkr.hw.init = &(struct clk_init_data){ |
360 | .name = "blsp1_qup3_spi_apps_clk_src" , |
361 | .parent_data = gcc_xo_gpll0, |
362 | .num_parents = 2, |
363 | .ops = &clk_rcg2_ops, |
364 | }, |
365 | }; |
366 | |
367 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { |
368 | .cmd_rcgr = 0x5000, |
369 | .hid_width = 5, |
370 | .parent_map = gcc_xo_gpll0_map, |
371 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
372 | .clkr.hw.init = &(struct clk_init_data){ |
373 | .name = "blsp1_qup4_i2c_apps_clk_src" , |
374 | .parent_data = gcc_xo_gpll0, |
375 | .num_parents = 2, |
376 | .ops = &clk_rcg2_ops, |
377 | }, |
378 | }; |
379 | |
380 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { |
381 | .cmd_rcgr = 0x5024, |
382 | .mnd_width = 8, |
383 | .hid_width = 5, |
384 | .parent_map = gcc_xo_gpll0_map, |
385 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
386 | .clkr.hw.init = &(struct clk_init_data){ |
387 | .name = "blsp1_qup4_spi_apps_clk_src" , |
388 | .parent_data = gcc_xo_gpll0, |
389 | .num_parents = 2, |
390 | .ops = &clk_rcg2_ops, |
391 | }, |
392 | }; |
393 | |
394 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { |
395 | .cmd_rcgr = 0x6000, |
396 | .hid_width = 5, |
397 | .parent_map = gcc_xo_gpll0_map, |
398 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
399 | .clkr.hw.init = &(struct clk_init_data){ |
400 | .name = "blsp1_qup5_i2c_apps_clk_src" , |
401 | .parent_data = gcc_xo_gpll0, |
402 | .num_parents = 2, |
403 | .ops = &clk_rcg2_ops, |
404 | }, |
405 | }; |
406 | |
407 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { |
408 | .cmd_rcgr = 0x6024, |
409 | .mnd_width = 8, |
410 | .hid_width = 5, |
411 | .parent_map = gcc_xo_gpll0_map, |
412 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
413 | .clkr.hw.init = &(struct clk_init_data){ |
414 | .name = "blsp1_qup5_spi_apps_clk_src" , |
415 | .parent_data = gcc_xo_gpll0, |
416 | .num_parents = 2, |
417 | .ops = &clk_rcg2_ops, |
418 | }, |
419 | }; |
420 | |
421 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { |
422 | .cmd_rcgr = 0x7000, |
423 | .hid_width = 5, |
424 | .parent_map = gcc_xo_gpll0_map, |
425 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
426 | .clkr.hw.init = &(struct clk_init_data){ |
427 | .name = "blsp1_qup6_i2c_apps_clk_src" , |
428 | .parent_data = gcc_xo_gpll0, |
429 | .num_parents = 2, |
430 | .ops = &clk_rcg2_ops, |
431 | }, |
432 | }; |
433 | |
434 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { |
435 | .cmd_rcgr = 0x7024, |
436 | .mnd_width = 8, |
437 | .hid_width = 5, |
438 | .parent_map = gcc_xo_gpll0_map, |
439 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
440 | .clkr.hw.init = &(struct clk_init_data){ |
441 | .name = "blsp1_qup6_spi_apps_clk_src" , |
442 | .parent_data = gcc_xo_gpll0, |
443 | .num_parents = 2, |
444 | .ops = &clk_rcg2_ops, |
445 | }, |
446 | }; |
447 | |
448 | static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { |
449 | F(3686400, P_GPLL0, 1, 72, 15625), |
450 | F(7372800, P_GPLL0, 1, 144, 15625), |
451 | F(14745600, P_GPLL0, 1, 288, 15625), |
452 | F(16000000, P_GPLL0, 10, 1, 5), |
453 | F(19200000, P_XO, 1, 0, 0), |
454 | F(24000000, P_GPLL0, 1, 3, 100), |
455 | F(25000000, P_GPLL0, 16, 1, 2), |
456 | F(32000000, P_GPLL0, 1, 1, 25), |
457 | F(40000000, P_GPLL0, 1, 1, 20), |
458 | F(46400000, P_GPLL0, 1, 29, 500), |
459 | F(48000000, P_GPLL0, 1, 3, 50), |
460 | F(51200000, P_GPLL0, 1, 8, 125), |
461 | F(56000000, P_GPLL0, 1, 7, 100), |
462 | F(58982400, P_GPLL0, 1, 1152, 15625), |
463 | F(60000000, P_GPLL0, 1, 3, 40), |
464 | { } |
465 | }; |
466 | |
467 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { |
468 | .cmd_rcgr = 0x2044, |
469 | .mnd_width = 16, |
470 | .hid_width = 5, |
471 | .parent_map = gcc_xo_gpll0_map, |
472 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
473 | .clkr.hw.init = &(struct clk_init_data){ |
474 | .name = "blsp1_uart1_apps_clk_src" , |
475 | .parent_data = gcc_xo_gpll0, |
476 | .num_parents = 2, |
477 | .ops = &clk_rcg2_ops, |
478 | }, |
479 | }; |
480 | |
481 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { |
482 | .cmd_rcgr = 0x3034, |
483 | .mnd_width = 16, |
484 | .hid_width = 5, |
485 | .parent_map = gcc_xo_gpll0_map, |
486 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
487 | .clkr.hw.init = &(struct clk_init_data){ |
488 | .name = "blsp1_uart2_apps_clk_src" , |
489 | .parent_data = gcc_xo_gpll0, |
490 | .num_parents = 2, |
491 | .ops = &clk_rcg2_ops, |
492 | }, |
493 | }; |
494 | |
495 | static struct clk_rcg2 blsp1_uart3_apps_clk_src = { |
496 | .cmd_rcgr = 0x4044, |
497 | .mnd_width = 16, |
498 | .hid_width = 5, |
499 | .parent_map = gcc_xo_gpll0_map, |
500 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
501 | .clkr.hw.init = &(struct clk_init_data){ |
502 | .name = "blsp1_uart3_apps_clk_src" , |
503 | .parent_data = gcc_xo_gpll0, |
504 | .num_parents = 2, |
505 | .ops = &clk_rcg2_ops, |
506 | }, |
507 | }; |
508 | |
509 | static struct clk_rcg2 blsp1_uart4_apps_clk_src = { |
510 | .cmd_rcgr = 0x5044, |
511 | .mnd_width = 16, |
512 | .hid_width = 5, |
513 | .parent_map = gcc_xo_gpll0_map, |
514 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
515 | .clkr.hw.init = &(struct clk_init_data){ |
516 | .name = "blsp1_uart4_apps_clk_src" , |
517 | .parent_data = gcc_xo_gpll0, |
518 | .num_parents = 2, |
519 | .ops = &clk_rcg2_ops, |
520 | }, |
521 | }; |
522 | |
523 | static struct clk_rcg2 blsp1_uart5_apps_clk_src = { |
524 | .cmd_rcgr = 0x6044, |
525 | .mnd_width = 16, |
526 | .hid_width = 5, |
527 | .parent_map = gcc_xo_gpll0_map, |
528 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
529 | .clkr.hw.init = &(struct clk_init_data){ |
530 | .name = "blsp1_uart5_apps_clk_src" , |
531 | .parent_data = gcc_xo_gpll0, |
532 | .num_parents = 2, |
533 | .ops = &clk_rcg2_ops, |
534 | }, |
535 | }; |
536 | |
537 | static struct clk_rcg2 blsp1_uart6_apps_clk_src = { |
538 | .cmd_rcgr = 0x6044, |
539 | .mnd_width = 16, |
540 | .hid_width = 5, |
541 | .parent_map = gcc_xo_gpll0_map, |
542 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
543 | .clkr.hw.init = &(struct clk_init_data){ |
544 | .name = "blsp1_uart6_apps_clk_src" , |
545 | .parent_data = gcc_xo_gpll0, |
546 | .num_parents = 2, |
547 | .ops = &clk_rcg2_ops, |
548 | }, |
549 | }; |
550 | |
551 | static const struct freq_tbl ftbl_gcc_crypto_clk[] = { |
552 | F(50000000, P_GPLL0, 16, 0, 0), |
553 | F(80000000, P_GPLL0, 10, 0, 0), |
554 | F(100000000, P_GPLL0, 8, 0, 0), |
555 | F(160000000, P_GPLL0, 5, 0, 0), |
556 | { } |
557 | }; |
558 | |
559 | static struct clk_rcg2 crypto_clk_src = { |
560 | .cmd_rcgr = 0x16004, |
561 | .hid_width = 5, |
562 | .parent_map = gcc_xo_gpll0_map, |
563 | .freq_tbl = ftbl_gcc_crypto_clk, |
564 | .clkr.hw.init = &(struct clk_init_data){ |
565 | .name = "crypto_clk_src" , |
566 | .parent_data = gcc_xo_gpll0, |
567 | .num_parents = 2, |
568 | .ops = &clk_rcg2_ops, |
569 | }, |
570 | }; |
571 | |
572 | static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { |
573 | F(19200000, P_XO, 1, 0, 0), |
574 | { } |
575 | }; |
576 | |
577 | static struct clk_rcg2 gp1_clk_src = { |
578 | .cmd_rcgr = 0x8004, |
579 | .mnd_width = 8, |
580 | .hid_width = 5, |
581 | .parent_map = gcc_xo_gpll0_gpll1_sleep_map, |
582 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
583 | .clkr.hw.init = &(struct clk_init_data){ |
584 | .name = "gp1_clk_src" , |
585 | .parent_data = gcc_xo_gpll0_gpll1_sleep, |
586 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), |
587 | .ops = &clk_rcg2_ops, |
588 | }, |
589 | }; |
590 | |
591 | static struct clk_rcg2 gp2_clk_src = { |
592 | .cmd_rcgr = 0x09004, |
593 | .mnd_width = 8, |
594 | .hid_width = 5, |
595 | .parent_map = gcc_xo_gpll0_gpll1_sleep_map, |
596 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
597 | .clkr.hw.init = &(struct clk_init_data){ |
598 | .name = "gp2_clk_src" , |
599 | .parent_data = gcc_xo_gpll0_gpll1_sleep, |
600 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), |
601 | .ops = &clk_rcg2_ops, |
602 | }, |
603 | }; |
604 | |
605 | static struct clk_rcg2 gp3_clk_src = { |
606 | .cmd_rcgr = 0x0a004, |
607 | .mnd_width = 8, |
608 | .hid_width = 5, |
609 | .parent_map = gcc_xo_gpll0_gpll1_sleep_map, |
610 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
611 | .clkr.hw.init = &(struct clk_init_data){ |
612 | .name = "gp3_clk_src" , |
613 | .parent_data = gcc_xo_gpll0_gpll1_sleep, |
614 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), |
615 | .ops = &clk_rcg2_ops, |
616 | }, |
617 | }; |
618 | |
619 | static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { |
620 | F(64000000, P_GPLL0, 12.5, 0, 0), |
621 | { } |
622 | }; |
623 | |
624 | static struct clk_rcg2 pdm2_clk_src = { |
625 | .cmd_rcgr = 0x44010, |
626 | .hid_width = 5, |
627 | .parent_map = gcc_xo_gpll0_map, |
628 | .freq_tbl = ftbl_gcc_pdm2_clk, |
629 | .clkr.hw.init = &(struct clk_init_data){ |
630 | .name = "pdm2_clk_src" , |
631 | .parent_data = gcc_xo_gpll0, |
632 | .num_parents = 2, |
633 | .ops = &clk_rcg2_ops, |
634 | }, |
635 | }; |
636 | |
637 | static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = { |
638 | F(144000, P_XO, 16, 3, 25), |
639 | F(400000, P_XO, 12, 1, 4), |
640 | F(20000000, P_GPLL0, 10, 1, 4), |
641 | F(25000000, P_GPLL0, 16, 1, 2), |
642 | F(50000000, P_GPLL0, 16, 0, 0), |
643 | F(100000000, P_GPLL0, 8, 0, 0), |
644 | F(177770000, P_GPLL0, 4.5, 0, 0), |
645 | F(200000000, P_GPLL0, 4, 0, 0), |
646 | { } |
647 | }; |
648 | |
649 | static struct clk_rcg2 sdcc1_apps_clk_src = { |
650 | .cmd_rcgr = 0x42004, |
651 | .mnd_width = 8, |
652 | .hid_width = 5, |
653 | .parent_map = gcc_xo_gpll0_map, |
654 | .freq_tbl = ftbl_gcc_sdcc_apps_clk, |
655 | .clkr.hw.init = &(struct clk_init_data){ |
656 | .name = "sdcc1_apps_clk_src" , |
657 | .parent_data = gcc_xo_gpll0, |
658 | .num_parents = 2, |
659 | .ops = &clk_rcg2_floor_ops, |
660 | }, |
661 | }; |
662 | |
663 | static struct clk_rcg2 sdcc2_apps_clk_src = { |
664 | .cmd_rcgr = 0x43004, |
665 | .mnd_width = 8, |
666 | .hid_width = 5, |
667 | .parent_map = gcc_xo_gpll0_map, |
668 | .freq_tbl = ftbl_gcc_sdcc_apps_clk, |
669 | .clkr.hw.init = &(struct clk_init_data){ |
670 | .name = "sdcc2_apps_clk_src" , |
671 | .parent_data = gcc_xo_gpll0, |
672 | .num_parents = 2, |
673 | .ops = &clk_rcg2_floor_ops, |
674 | }, |
675 | }; |
676 | |
677 | static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { |
678 | F(155000000, P_GPLL2, 6, 0, 0), |
679 | F(310000000, P_GPLL2, 3, 0, 0), |
680 | F(400000000, P_GPLL0, 2, 0, 0), |
681 | { } |
682 | }; |
683 | |
684 | static struct clk_rcg2 apss_tcu_clk_src = { |
685 | .cmd_rcgr = 0x1207c, |
686 | .hid_width = 5, |
687 | .parent_map = gcc_xo_gpll0_gpll1_gpll2_map, |
688 | .freq_tbl = ftbl_gcc_apss_tcu_clk, |
689 | .clkr.hw.init = &(struct clk_init_data){ |
690 | .name = "apss_tcu_clk_src" , |
691 | .parent_data = gcc_xo_gpll0_gpll1_gpll2, |
692 | .num_parents = 4, |
693 | .ops = &clk_rcg2_ops, |
694 | }, |
695 | }; |
696 | |
697 | static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
698 | F(19200000, P_XO, 1, 0, 0), |
699 | F(57140000, P_GPLL0, 14, 0, 0), |
700 | F(69565000, P_GPLL0, 11.5, 0, 0), |
701 | F(133330000, P_GPLL0, 6, 0, 0), |
702 | F(177778000, P_GPLL0, 4.5, 0, 0), |
703 | { } |
704 | }; |
705 | |
706 | static struct clk_rcg2 usb_hs_system_clk_src = { |
707 | .cmd_rcgr = 0x41010, |
708 | .hid_width = 5, |
709 | .parent_map = gcc_xo_gpll0_map, |
710 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
711 | .clkr.hw.init = &(struct clk_init_data){ |
712 | .name = "usb_hs_system_clk_src" , |
713 | .parent_data = gcc_xo_gpll0, |
714 | .num_parents = 2, |
715 | .ops = &clk_rcg2_ops, |
716 | }, |
717 | }; |
718 | |
719 | static const struct freq_tbl ftbl_usb_hsic_clk_src[] = { |
720 | F(480000000, P_GPLL2, 1, 0, 0), |
721 | { } |
722 | }; |
723 | |
724 | static struct clk_rcg2 usb_hsic_clk_src = { |
725 | .cmd_rcgr = 0x3d018, |
726 | .hid_width = 5, |
727 | .parent_map = gcc_xo_gpll0_gpll2_map, |
728 | .freq_tbl = ftbl_usb_hsic_clk_src, |
729 | .clkr.hw.init = &(struct clk_init_data){ |
730 | .name = "usb_hsic_clk_src" , |
731 | .parent_data = gcc_xo_gpll0_gpll2, |
732 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), |
733 | .ops = &clk_rcg2_ops, |
734 | }, |
735 | }; |
736 | |
737 | static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = { |
738 | F(9600000, P_XO, 2, 0, 0), |
739 | { } |
740 | }; |
741 | |
742 | static struct clk_rcg2 usb_hsic_io_cal_clk_src = { |
743 | .cmd_rcgr = 0x3d030, |
744 | .hid_width = 5, |
745 | .parent_map = gcc_xo_gpll0_map, |
746 | .freq_tbl = ftbl_usb_hsic_io_cal_clk_src, |
747 | .clkr.hw.init = &(struct clk_init_data){ |
748 | .name = "usb_hsic_io_cal_clk_src" , |
749 | .parent_data = gcc_xo_gpll0, |
750 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
751 | .ops = &clk_rcg2_ops, |
752 | }, |
753 | }; |
754 | |
755 | static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = { |
756 | F(19200000, P_XO, 1, 0, 0), |
757 | F(57140000, P_GPLL0, 14, 0, 0), |
758 | F(133330000, P_GPLL0, 6, 0, 0), |
759 | F(177778000, P_GPLL0, 4.5, 0, 0), |
760 | { } |
761 | }; |
762 | |
763 | static struct clk_rcg2 usb_hsic_system_clk_src = { |
764 | .cmd_rcgr = 0x3d000, |
765 | .hid_width = 5, |
766 | .parent_map = gcc_xo_gpll0_map, |
767 | .freq_tbl = ftbl_usb_hsic_system_clk_src, |
768 | .clkr.hw.init = &(struct clk_init_data){ |
769 | .name = "usb_hsic_system_clk_src" , |
770 | .parent_data = gcc_xo_gpll0, |
771 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0), |
772 | .ops = &clk_rcg2_ops, |
773 | }, |
774 | }; |
775 | |
776 | static struct clk_branch gcc_blsp1_ahb_clk = { |
777 | .halt_reg = 0x1008, |
778 | .halt_check = BRANCH_HALT_VOTED, |
779 | .clkr = { |
780 | .enable_reg = 0x45004, |
781 | .enable_mask = BIT(10), |
782 | .hw.init = &(struct clk_init_data){ |
783 | .name = "gcc_blsp1_ahb_clk" , |
784 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
785 | .num_parents = 1, |
786 | .ops = &clk_branch2_ops, |
787 | }, |
788 | }, |
789 | }; |
790 | |
791 | static struct clk_branch gcc_blsp1_sleep_clk = { |
792 | .halt_reg = 0x1004, |
793 | .clkr = { |
794 | .enable_reg = 0x1004, |
795 | .enable_mask = BIT(0), |
796 | .hw.init = &(struct clk_init_data){ |
797 | .name = "gcc_blsp1_sleep_clk" , |
798 | .parent_data = &(const struct clk_parent_data){ |
799 | .fw_name = "sleep_clk" , |
800 | }, |
801 | .num_parents = 1, |
802 | .flags = CLK_SET_RATE_PARENT, |
803 | .ops = &clk_branch2_ops, |
804 | }, |
805 | }, |
806 | }; |
807 | |
808 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
809 | .halt_reg = 0x2008, |
810 | .clkr = { |
811 | .enable_reg = 0x2008, |
812 | .enable_mask = BIT(0), |
813 | .hw.init = &(struct clk_init_data){ |
814 | .name = "gcc_blsp1_qup1_i2c_apps_clk" , |
815 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, |
816 | .num_parents = 1, |
817 | .flags = CLK_SET_RATE_PARENT, |
818 | .ops = &clk_branch2_ops, |
819 | }, |
820 | }, |
821 | }; |
822 | |
823 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
824 | .halt_reg = 0x2004, |
825 | .clkr = { |
826 | .enable_reg = 0x2004, |
827 | .enable_mask = BIT(0), |
828 | .hw.init = &(struct clk_init_data){ |
829 | .name = "gcc_blsp1_qup1_spi_apps_clk" , |
830 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, |
831 | .num_parents = 1, |
832 | .flags = CLK_SET_RATE_PARENT, |
833 | .ops = &clk_branch2_ops, |
834 | }, |
835 | }, |
836 | }; |
837 | |
838 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
839 | .halt_reg = 0x3010, |
840 | .clkr = { |
841 | .enable_reg = 0x3010, |
842 | .enable_mask = BIT(0), |
843 | .hw.init = &(struct clk_init_data){ |
844 | .name = "gcc_blsp1_qup2_i2c_apps_clk" , |
845 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, |
846 | .num_parents = 1, |
847 | .flags = CLK_SET_RATE_PARENT, |
848 | .ops = &clk_branch2_ops, |
849 | }, |
850 | }, |
851 | }; |
852 | |
853 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
854 | .halt_reg = 0x300c, |
855 | .clkr = { |
856 | .enable_reg = 0x300c, |
857 | .enable_mask = BIT(0), |
858 | .hw.init = &(struct clk_init_data){ |
859 | .name = "gcc_blsp1_qup2_spi_apps_clk" , |
860 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, |
861 | .num_parents = 1, |
862 | .flags = CLK_SET_RATE_PARENT, |
863 | .ops = &clk_branch2_ops, |
864 | }, |
865 | }, |
866 | }; |
867 | |
868 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
869 | .halt_reg = 0x4020, |
870 | .clkr = { |
871 | .enable_reg = 0x4020, |
872 | .enable_mask = BIT(0), |
873 | .hw.init = &(struct clk_init_data){ |
874 | .name = "gcc_blsp1_qup3_i2c_apps_clk" , |
875 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, |
876 | .num_parents = 1, |
877 | .flags = CLK_SET_RATE_PARENT, |
878 | .ops = &clk_branch2_ops, |
879 | }, |
880 | }, |
881 | }; |
882 | |
883 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
884 | .halt_reg = 0x401c, |
885 | .clkr = { |
886 | .enable_reg = 0x401c, |
887 | .enable_mask = BIT(0), |
888 | .hw.init = &(struct clk_init_data){ |
889 | .name = "gcc_blsp1_qup3_spi_apps_clk" , |
890 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, |
891 | .num_parents = 1, |
892 | .flags = CLK_SET_RATE_PARENT, |
893 | .ops = &clk_branch2_ops, |
894 | }, |
895 | }, |
896 | }; |
897 | |
898 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
899 | .halt_reg = 0x5020, |
900 | .clkr = { |
901 | .enable_reg = 0x5020, |
902 | .enable_mask = BIT(0), |
903 | .hw.init = &(struct clk_init_data){ |
904 | .name = "gcc_blsp1_qup4_i2c_apps_clk" , |
905 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, |
906 | .num_parents = 1, |
907 | .flags = CLK_SET_RATE_PARENT, |
908 | .ops = &clk_branch2_ops, |
909 | }, |
910 | }, |
911 | }; |
912 | |
913 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
914 | .halt_reg = 0x501c, |
915 | .clkr = { |
916 | .enable_reg = 0x501c, |
917 | .enable_mask = BIT(0), |
918 | .hw.init = &(struct clk_init_data){ |
919 | .name = "gcc_blsp1_qup4_spi_apps_clk" , |
920 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, |
921 | .num_parents = 1, |
922 | .flags = CLK_SET_RATE_PARENT, |
923 | .ops = &clk_branch2_ops, |
924 | }, |
925 | }, |
926 | }; |
927 | |
928 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { |
929 | .halt_reg = 0x6020, |
930 | .clkr = { |
931 | .enable_reg = 0x6020, |
932 | .enable_mask = BIT(0), |
933 | .hw.init = &(struct clk_init_data){ |
934 | .name = "gcc_blsp1_qup5_i2c_apps_clk" , |
935 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, |
936 | .num_parents = 1, |
937 | .flags = CLK_SET_RATE_PARENT, |
938 | .ops = &clk_branch2_ops, |
939 | }, |
940 | }, |
941 | }; |
942 | |
943 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { |
944 | .halt_reg = 0x601c, |
945 | .clkr = { |
946 | .enable_reg = 0x601c, |
947 | .enable_mask = BIT(0), |
948 | .hw.init = &(struct clk_init_data){ |
949 | .name = "gcc_blsp1_qup5_spi_apps_clk" , |
950 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, |
951 | .num_parents = 1, |
952 | .flags = CLK_SET_RATE_PARENT, |
953 | .ops = &clk_branch2_ops, |
954 | }, |
955 | }, |
956 | }; |
957 | |
958 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { |
959 | .halt_reg = 0x7020, |
960 | .clkr = { |
961 | .enable_reg = 0x7020, |
962 | .enable_mask = BIT(0), |
963 | .hw.init = &(struct clk_init_data){ |
964 | .name = "gcc_blsp1_qup6_i2c_apps_clk" , |
965 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, |
966 | .num_parents = 1, |
967 | .flags = CLK_SET_RATE_PARENT, |
968 | .ops = &clk_branch2_ops, |
969 | }, |
970 | }, |
971 | }; |
972 | |
973 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { |
974 | .halt_reg = 0x701c, |
975 | .clkr = { |
976 | .enable_reg = 0x701c, |
977 | .enable_mask = BIT(0), |
978 | .hw.init = &(struct clk_init_data){ |
979 | .name = "gcc_blsp1_qup6_spi_apps_clk" , |
980 | .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, |
981 | .num_parents = 1, |
982 | .flags = CLK_SET_RATE_PARENT, |
983 | .ops = &clk_branch2_ops, |
984 | }, |
985 | }, |
986 | }; |
987 | |
988 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
989 | .halt_reg = 0x203c, |
990 | .clkr = { |
991 | .enable_reg = 0x203c, |
992 | .enable_mask = BIT(0), |
993 | .hw.init = &(struct clk_init_data){ |
994 | .name = "gcc_blsp1_uart1_apps_clk" , |
995 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, |
996 | .num_parents = 1, |
997 | .flags = CLK_SET_RATE_PARENT, |
998 | .ops = &clk_branch2_ops, |
999 | }, |
1000 | }, |
1001 | }; |
1002 | |
1003 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
1004 | .halt_reg = 0x302c, |
1005 | .clkr = { |
1006 | .enable_reg = 0x302c, |
1007 | .enable_mask = BIT(0), |
1008 | .hw.init = &(struct clk_init_data){ |
1009 | .name = "gcc_blsp1_uart2_apps_clk" , |
1010 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, |
1011 | .num_parents = 1, |
1012 | .flags = CLK_SET_RATE_PARENT, |
1013 | .ops = &clk_branch2_ops, |
1014 | }, |
1015 | }, |
1016 | }; |
1017 | |
1018 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { |
1019 | .halt_reg = 0x403c, |
1020 | .clkr = { |
1021 | .enable_reg = 0x403c, |
1022 | .enable_mask = BIT(0), |
1023 | .hw.init = &(struct clk_init_data){ |
1024 | .name = "gcc_blsp1_uart3_apps_clk" , |
1025 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, |
1026 | .num_parents = 1, |
1027 | .flags = CLK_SET_RATE_PARENT, |
1028 | .ops = &clk_branch2_ops, |
1029 | }, |
1030 | }, |
1031 | }; |
1032 | |
1033 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { |
1034 | .halt_reg = 0x503c, |
1035 | .clkr = { |
1036 | .enable_reg = 0x503c, |
1037 | .enable_mask = BIT(0), |
1038 | .hw.init = &(struct clk_init_data){ |
1039 | .name = "gcc_blsp1_uart4_apps_clk" , |
1040 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, |
1041 | .num_parents = 1, |
1042 | .flags = CLK_SET_RATE_PARENT, |
1043 | .ops = &clk_branch2_ops, |
1044 | }, |
1045 | }, |
1046 | }; |
1047 | |
1048 | static struct clk_branch gcc_blsp1_uart5_apps_clk = { |
1049 | .halt_reg = 0x603c, |
1050 | .clkr = { |
1051 | .enable_reg = 0x603c, |
1052 | .enable_mask = BIT(0), |
1053 | .hw.init = &(struct clk_init_data){ |
1054 | .name = "gcc_blsp1_uart5_apps_clk" , |
1055 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, |
1056 | .num_parents = 1, |
1057 | .flags = CLK_SET_RATE_PARENT, |
1058 | .ops = &clk_branch2_ops, |
1059 | }, |
1060 | }, |
1061 | }; |
1062 | |
1063 | static struct clk_branch gcc_blsp1_uart6_apps_clk = { |
1064 | .halt_reg = 0x703c, |
1065 | .clkr = { |
1066 | .enable_reg = 0x703c, |
1067 | .enable_mask = BIT(0), |
1068 | .hw.init = &(struct clk_init_data){ |
1069 | .name = "gcc_blsp1_uart6_apps_clk" , |
1070 | .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, |
1071 | .num_parents = 1, |
1072 | .flags = CLK_SET_RATE_PARENT, |
1073 | .ops = &clk_branch2_ops, |
1074 | }, |
1075 | }, |
1076 | }; |
1077 | |
1078 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
1079 | .halt_reg = 0x1300c, |
1080 | .halt_check = BRANCH_HALT_VOTED, |
1081 | .clkr = { |
1082 | .enable_reg = 0x45004, |
1083 | .enable_mask = BIT(7), |
1084 | .hw.init = &(struct clk_init_data){ |
1085 | .name = "gcc_boot_rom_ahb_clk" , |
1086 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1087 | .num_parents = 1, |
1088 | .ops = &clk_branch2_ops, |
1089 | }, |
1090 | }, |
1091 | }; |
1092 | |
1093 | static struct clk_branch gcc_crypto_ahb_clk = { |
1094 | .halt_reg = 0x16024, |
1095 | .halt_check = BRANCH_HALT_VOTED, |
1096 | .clkr = { |
1097 | .enable_reg = 0x45004, |
1098 | .enable_mask = BIT(0), |
1099 | .hw.init = &(struct clk_init_data){ |
1100 | .name = "gcc_crypto_ahb_clk" , |
1101 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1102 | .num_parents = 1, |
1103 | .flags = CLK_SET_RATE_PARENT, |
1104 | .ops = &clk_branch2_ops, |
1105 | }, |
1106 | }, |
1107 | }; |
1108 | |
1109 | static struct clk_branch gcc_crypto_axi_clk = { |
1110 | .halt_reg = 0x16020, |
1111 | .halt_check = BRANCH_HALT_VOTED, |
1112 | .clkr = { |
1113 | .enable_reg = 0x45004, |
1114 | .enable_mask = BIT(1), |
1115 | .hw.init = &(struct clk_init_data){ |
1116 | .name = "gcc_crypto_axi_clk" , |
1117 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1118 | .num_parents = 1, |
1119 | .flags = CLK_SET_RATE_PARENT, |
1120 | .ops = &clk_branch2_ops, |
1121 | }, |
1122 | }, |
1123 | }; |
1124 | |
1125 | static struct clk_branch gcc_crypto_clk = { |
1126 | .halt_reg = 0x1601c, |
1127 | .halt_check = BRANCH_HALT_VOTED, |
1128 | .clkr = { |
1129 | .enable_reg = 0x45004, |
1130 | .enable_mask = BIT(2), |
1131 | .hw.init = &(struct clk_init_data){ |
1132 | .name = "gcc_crypto_clk" , |
1133 | .parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw }, |
1134 | .num_parents = 1, |
1135 | .flags = CLK_SET_RATE_PARENT, |
1136 | .ops = &clk_branch2_ops, |
1137 | }, |
1138 | }, |
1139 | }; |
1140 | |
1141 | static struct clk_branch gcc_gp1_clk = { |
1142 | .halt_reg = 0x08000, |
1143 | .clkr = { |
1144 | .enable_reg = 0x08000, |
1145 | .enable_mask = BIT(0), |
1146 | .hw.init = &(struct clk_init_data){ |
1147 | .name = "gcc_gp1_clk" , |
1148 | .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, |
1149 | .num_parents = 1, |
1150 | .flags = CLK_SET_RATE_PARENT, |
1151 | .ops = &clk_branch2_ops, |
1152 | }, |
1153 | }, |
1154 | }; |
1155 | |
1156 | static struct clk_branch gcc_gp2_clk = { |
1157 | .halt_reg = 0x09000, |
1158 | .clkr = { |
1159 | .enable_reg = 0x09000, |
1160 | .enable_mask = BIT(0), |
1161 | .hw.init = &(struct clk_init_data){ |
1162 | .name = "gcc_gp2_clk" , |
1163 | .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, |
1164 | .num_parents = 1, |
1165 | .flags = CLK_SET_RATE_PARENT, |
1166 | .ops = &clk_branch2_ops, |
1167 | }, |
1168 | }, |
1169 | }; |
1170 | |
1171 | static struct clk_branch gcc_gp3_clk = { |
1172 | .halt_reg = 0x0a000, |
1173 | .clkr = { |
1174 | .enable_reg = 0x0a000, |
1175 | .enable_mask = BIT(0), |
1176 | .hw.init = &(struct clk_init_data){ |
1177 | .name = "gcc_gp3_clk" , |
1178 | .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, |
1179 | .num_parents = 1, |
1180 | .flags = CLK_SET_RATE_PARENT, |
1181 | .ops = &clk_branch2_ops, |
1182 | }, |
1183 | }, |
1184 | }; |
1185 | |
1186 | static struct clk_branch gcc_mss_cfg_ahb_clk = { |
1187 | .halt_reg = 0x49000, |
1188 | .clkr = { |
1189 | .enable_reg = 0x49000, |
1190 | .enable_mask = BIT(0), |
1191 | .hw.init = &(struct clk_init_data){ |
1192 | .name = "gcc_mss_cfg_ahb_clk" , |
1193 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1194 | .num_parents = 1, |
1195 | .flags = CLK_SET_RATE_PARENT, |
1196 | .ops = &clk_branch2_ops, |
1197 | }, |
1198 | }, |
1199 | }; |
1200 | |
1201 | static struct clk_branch gcc_pdm2_clk = { |
1202 | .halt_reg = 0x4400c, |
1203 | .clkr = { |
1204 | .enable_reg = 0x4400c, |
1205 | .enable_mask = BIT(0), |
1206 | .hw.init = &(struct clk_init_data){ |
1207 | .name = "gcc_pdm2_clk" , |
1208 | .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, |
1209 | .num_parents = 1, |
1210 | .flags = CLK_SET_RATE_PARENT, |
1211 | .ops = &clk_branch2_ops, |
1212 | }, |
1213 | }, |
1214 | }; |
1215 | |
1216 | static struct clk_branch gcc_pdm_ahb_clk = { |
1217 | .halt_reg = 0x44004, |
1218 | .clkr = { |
1219 | .enable_reg = 0x44004, |
1220 | .enable_mask = BIT(0), |
1221 | .hw.init = &(struct clk_init_data){ |
1222 | .name = "gcc_pdm_ahb_clk" , |
1223 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1224 | .num_parents = 1, |
1225 | .flags = CLK_SET_RATE_PARENT, |
1226 | .ops = &clk_branch2_ops, |
1227 | }, |
1228 | }, |
1229 | }; |
1230 | |
1231 | static struct clk_branch gcc_prng_ahb_clk = { |
1232 | .halt_reg = 0x13004, |
1233 | .halt_check = BRANCH_HALT_VOTED, |
1234 | .clkr = { |
1235 | .enable_reg = 0x45004, |
1236 | .enable_mask = BIT(8), |
1237 | .hw.init = &(struct clk_init_data){ |
1238 | .name = "gcc_prng_ahb_clk" , |
1239 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1240 | .num_parents = 1, |
1241 | .flags = CLK_SET_RATE_PARENT, |
1242 | .ops = &clk_branch2_ops, |
1243 | }, |
1244 | }, |
1245 | }; |
1246 | |
1247 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
1248 | .halt_reg = 0x4201c, |
1249 | .clkr = { |
1250 | .enable_reg = 0x4201c, |
1251 | .enable_mask = BIT(0), |
1252 | .hw.init = &(struct clk_init_data){ |
1253 | .name = "gcc_sdcc1_ahb_clk" , |
1254 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1255 | .num_parents = 1, |
1256 | .flags = CLK_SET_RATE_PARENT, |
1257 | .ops = &clk_branch2_ops, |
1258 | }, |
1259 | }, |
1260 | }; |
1261 | |
1262 | static struct clk_branch gcc_sdcc1_apps_clk = { |
1263 | .halt_reg = 0x42018, |
1264 | .clkr = { |
1265 | .enable_reg = 0x42018, |
1266 | .enable_mask = BIT(0), |
1267 | .hw.init = &(struct clk_init_data){ |
1268 | .name = "gcc_sdcc1_apps_clk" , |
1269 | .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, |
1270 | .num_parents = 1, |
1271 | .flags = CLK_SET_RATE_PARENT, |
1272 | .ops = &clk_branch2_ops, |
1273 | }, |
1274 | }, |
1275 | }; |
1276 | |
1277 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
1278 | .halt_reg = 0x4301c, |
1279 | .clkr = { |
1280 | .enable_reg = 0x4301c, |
1281 | .enable_mask = BIT(0), |
1282 | .hw.init = &(struct clk_init_data){ |
1283 | .name = "gcc_sdcc2_ahb_clk" , |
1284 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1285 | .num_parents = 1, |
1286 | .flags = CLK_SET_RATE_PARENT, |
1287 | .ops = &clk_branch2_ops, |
1288 | }, |
1289 | }, |
1290 | }; |
1291 | |
1292 | static struct clk_branch gcc_sdcc2_apps_clk = { |
1293 | .halt_reg = 0x43018, |
1294 | .clkr = { |
1295 | .enable_reg = 0x43018, |
1296 | .enable_mask = BIT(0), |
1297 | .hw.init = &(struct clk_init_data){ |
1298 | .name = "gcc_sdcc2_apps_clk" , |
1299 | .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, |
1300 | .num_parents = 1, |
1301 | .flags = CLK_SET_RATE_PARENT, |
1302 | .ops = &clk_branch2_ops, |
1303 | }, |
1304 | }, |
1305 | }; |
1306 | |
1307 | static struct clk_rcg2 bimc_ddr_clk_src = { |
1308 | .cmd_rcgr = 0x32004, |
1309 | .hid_width = 5, |
1310 | .parent_map = gcc_xo_gpll0_bimc_map, |
1311 | .clkr.hw.init = &(struct clk_init_data){ |
1312 | .name = "bimc_ddr_clk_src" , |
1313 | .parent_data = gcc_xo_gpll0_bimc, |
1314 | .num_parents = 3, |
1315 | .ops = &clk_rcg2_ops, |
1316 | .flags = CLK_GET_RATE_NOCACHE, |
1317 | }, |
1318 | }; |
1319 | |
1320 | static struct clk_branch gcc_mss_q6_bimc_axi_clk = { |
1321 | .halt_reg = 0x49004, |
1322 | .clkr = { |
1323 | .enable_reg = 0x49004, |
1324 | .enable_mask = BIT(0), |
1325 | .hw.init = &(struct clk_init_data){ |
1326 | .name = "gcc_mss_q6_bimc_axi_clk" , |
1327 | .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw }, |
1328 | .num_parents = 1, |
1329 | .flags = CLK_SET_RATE_PARENT, |
1330 | .ops = &clk_branch2_ops, |
1331 | }, |
1332 | }, |
1333 | }; |
1334 | |
1335 | static struct clk_branch gcc_apss_tcu_clk = { |
1336 | .halt_reg = 0x12018, |
1337 | .halt_check = BRANCH_HALT_VOTED, |
1338 | .clkr = { |
1339 | .enable_reg = 0x4500c, |
1340 | .enable_mask = BIT(1), |
1341 | .hw.init = &(struct clk_init_data){ |
1342 | .name = "gcc_apss_tcu_clk" , |
1343 | .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw }, |
1344 | .num_parents = 1, |
1345 | .ops = &clk_branch2_ops, |
1346 | }, |
1347 | }, |
1348 | }; |
1349 | |
1350 | static struct clk_branch gcc_smmu_cfg_clk = { |
1351 | .halt_reg = 0x12038, |
1352 | .halt_check = BRANCH_HALT_VOTED, |
1353 | .clkr = { |
1354 | .enable_reg = 0x4500c, |
1355 | .enable_mask = BIT(12), |
1356 | .hw.init = &(struct clk_init_data){ |
1357 | .name = "gcc_smmu_cfg_clk" , |
1358 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1359 | .num_parents = 1, |
1360 | .flags = CLK_SET_RATE_PARENT, |
1361 | .ops = &clk_branch2_ops, |
1362 | }, |
1363 | }, |
1364 | }; |
1365 | |
1366 | static struct clk_branch gcc_qdss_dap_clk = { |
1367 | .halt_reg = 0x29084, |
1368 | .halt_check = BRANCH_HALT_VOTED, |
1369 | .clkr = { |
1370 | .enable_reg = 0x45004, |
1371 | .enable_mask = BIT(19), |
1372 | .hw.init = &(struct clk_init_data){ |
1373 | .name = "gcc_qdss_dap_clk" , |
1374 | .parent_data = &(const struct clk_parent_data){ |
1375 | .fw_name = "xo" , |
1376 | }, |
1377 | .num_parents = 1, |
1378 | .ops = &clk_branch2_ops, |
1379 | }, |
1380 | }, |
1381 | }; |
1382 | |
1383 | static struct clk_branch gcc_usb2a_phy_sleep_clk = { |
1384 | .halt_reg = 0x4102c, |
1385 | .clkr = { |
1386 | .enable_reg = 0x4102c, |
1387 | .enable_mask = BIT(0), |
1388 | .hw.init = &(struct clk_init_data){ |
1389 | .name = "gcc_usb2a_phy_sleep_clk" , |
1390 | .parent_data = &(const struct clk_parent_data){ |
1391 | .fw_name = "sleep_clk" , |
1392 | }, |
1393 | .num_parents = 1, |
1394 | .flags = CLK_SET_RATE_PARENT, |
1395 | .ops = &clk_branch2_ops, |
1396 | }, |
1397 | }, |
1398 | }; |
1399 | |
1400 | static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = { |
1401 | .halt_reg = 0x41030, |
1402 | .halt_check = BRANCH_HALT, |
1403 | .clkr = { |
1404 | .enable_reg = 0x41030, |
1405 | .enable_mask = BIT(0), |
1406 | .hw.init = &(struct clk_init_data){ |
1407 | .name = "gcc_usb_hs_phy_cfg_ahb_clk" , |
1408 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1409 | .num_parents = 1, |
1410 | .flags = CLK_SET_RATE_PARENT, |
1411 | .ops = &clk_branch2_ops, |
1412 | }, |
1413 | }, |
1414 | }; |
1415 | |
1416 | static struct clk_branch gcc_usb_hs_ahb_clk = { |
1417 | .halt_reg = 0x41008, |
1418 | .clkr = { |
1419 | .enable_reg = 0x41008, |
1420 | .enable_mask = BIT(0), |
1421 | .hw.init = &(struct clk_init_data){ |
1422 | .name = "gcc_usb_hs_ahb_clk" , |
1423 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1424 | .num_parents = 1, |
1425 | .flags = CLK_SET_RATE_PARENT, |
1426 | .ops = &clk_branch2_ops, |
1427 | }, |
1428 | }, |
1429 | }; |
1430 | |
1431 | static struct clk_branch gcc_usb_hs_system_clk = { |
1432 | .halt_reg = 0x41004, |
1433 | .clkr = { |
1434 | .enable_reg = 0x41004, |
1435 | .enable_mask = BIT(0), |
1436 | .hw.init = &(struct clk_init_data){ |
1437 | .name = "gcc_usb_hs_system_clk" , |
1438 | .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, |
1439 | .num_parents = 1, |
1440 | .flags = CLK_SET_RATE_PARENT, |
1441 | .ops = &clk_branch2_ops, |
1442 | }, |
1443 | }, |
1444 | }; |
1445 | |
1446 | static struct clk_branch gcc_apss_ahb_clk = { |
1447 | .halt_reg = 0x4601c, |
1448 | .halt_check = BRANCH_HALT_VOTED, |
1449 | .clkr = { |
1450 | .enable_reg = 0x45004, |
1451 | .enable_mask = BIT(14), |
1452 | .hw.init = &(struct clk_init_data){ |
1453 | .name = "gcc_apss_ahb_clk" , |
1454 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1455 | .num_parents = 1, |
1456 | .ops = &clk_branch2_ops, |
1457 | }, |
1458 | }, |
1459 | }; |
1460 | |
1461 | static struct clk_branch gcc_apss_axi_clk = { |
1462 | .halt_reg = 0x4601c, |
1463 | .halt_check = BRANCH_HALT_VOTED, |
1464 | .clkr = { |
1465 | .enable_reg = 0x45004, |
1466 | .enable_mask = BIT(13), |
1467 | .hw.init = &(struct clk_init_data){ |
1468 | .name = "gcc_apss_axi_clk" , |
1469 | .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw }, |
1470 | .num_parents = 1, |
1471 | .ops = &clk_branch2_ops, |
1472 | }, |
1473 | }, |
1474 | }; |
1475 | |
1476 | static struct clk_regmap *gcc_mdm9607_clocks[] = { |
1477 | [GPLL0] = &gpll0.clkr, |
1478 | [GPLL0_EARLY] = &gpll0_early.clkr, |
1479 | [GPLL1] = &gpll1.clkr, |
1480 | [GPLL1_VOTE] = &gpll1_vote, |
1481 | [GPLL2] = &gpll2.clkr, |
1482 | [GPLL2_EARLY] = &gpll2_early.clkr, |
1483 | [BIMC_PLL] = &bimc_pll.clkr, |
1484 | [BIMC_PLL_VOTE] = &bimc_pll_vote, |
1485 | [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, |
1486 | [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, |
1487 | [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, |
1488 | [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, |
1489 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, |
1490 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, |
1491 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, |
1492 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, |
1493 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, |
1494 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, |
1495 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, |
1496 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, |
1497 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, |
1498 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, |
1499 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, |
1500 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, |
1501 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, |
1502 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, |
1503 | [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, |
1504 | [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, |
1505 | [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, |
1506 | [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, |
1507 | [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, |
1508 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, |
1509 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, |
1510 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, |
1511 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, |
1512 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, |
1513 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, |
1514 | [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, |
1515 | [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, |
1516 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, |
1517 | [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, |
1518 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, |
1519 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, |
1520 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, |
1521 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, |
1522 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, |
1523 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, |
1524 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, |
1525 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, |
1526 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, |
1527 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, |
1528 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, |
1529 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, |
1530 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, |
1531 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, |
1532 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, |
1533 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, |
1534 | [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, |
1535 | [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, |
1536 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
1537 | [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, |
1538 | [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, |
1539 | [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, |
1540 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
1541 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
1542 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
1543 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, |
1544 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
1545 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
1546 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
1547 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
1548 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, |
1549 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, |
1550 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, |
1551 | [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, |
1552 | [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, |
1553 | [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, |
1554 | [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, |
1555 | [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, |
1556 | [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, |
1557 | [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, |
1558 | [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, |
1559 | [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, |
1560 | [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, |
1561 | [GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, |
1562 | [GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, |
1563 | [GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, |
1564 | }; |
1565 | |
1566 | static const struct qcom_reset_map gcc_mdm9607_resets[] = { |
1567 | [USB_HS_HSIC_BCR] = { 0x3d05c }, |
1568 | [GCC_MSS_RESTART] = { 0x3e000 }, |
1569 | [USB_HS_BCR] = { 0x41000 }, |
1570 | [USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, |
1571 | [QUSB2_PHY_BCR] = { 0x4103c }, |
1572 | }; |
1573 | |
1574 | static const struct regmap_config gcc_mdm9607_regmap_config = { |
1575 | .reg_bits = 32, |
1576 | .reg_stride = 4, |
1577 | .val_bits = 32, |
1578 | .max_register = 0x80000, |
1579 | .fast_io = true, |
1580 | }; |
1581 | |
1582 | static const struct qcom_cc_desc gcc_mdm9607_desc = { |
1583 | .config = &gcc_mdm9607_regmap_config, |
1584 | .clks = gcc_mdm9607_clocks, |
1585 | .num_clks = ARRAY_SIZE(gcc_mdm9607_clocks), |
1586 | .resets = gcc_mdm9607_resets, |
1587 | .num_resets = ARRAY_SIZE(gcc_mdm9607_resets), |
1588 | }; |
1589 | |
1590 | static const struct of_device_id gcc_mdm9607_match_table[] = { |
1591 | { .compatible = "qcom,gcc-mdm9607" }, |
1592 | { } |
1593 | }; |
1594 | MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table); |
1595 | |
1596 | static int gcc_mdm9607_probe(struct platform_device *pdev) |
1597 | { |
1598 | struct regmap *regmap; |
1599 | |
1600 | regmap = qcom_cc_map(pdev, desc: &gcc_mdm9607_desc); |
1601 | if (IS_ERR(ptr: regmap)) |
1602 | return PTR_ERR(ptr: regmap); |
1603 | |
1604 | /* Vote for GPLL0 to turn on. Needed by acpuclock. */ |
1605 | regmap_update_bits(map: regmap, reg: 0x45000, BIT(0), BIT(0)); |
1606 | |
1607 | return qcom_cc_really_probe(pdev, desc: &gcc_mdm9607_desc, regmap); |
1608 | } |
1609 | |
1610 | static struct platform_driver gcc_mdm9607_driver = { |
1611 | .probe = gcc_mdm9607_probe, |
1612 | .driver = { |
1613 | .name = "gcc-mdm9607" , |
1614 | .of_match_table = gcc_mdm9607_match_table, |
1615 | }, |
1616 | }; |
1617 | |
1618 | static int __init gcc_mdm9607_init(void) |
1619 | { |
1620 | return platform_driver_register(&gcc_mdm9607_driver); |
1621 | } |
1622 | core_initcall(gcc_mdm9607_init); |
1623 | |
1624 | static void __exit gcc_mdm9607_exit(void) |
1625 | { |
1626 | platform_driver_unregister(&gcc_mdm9607_driver); |
1627 | } |
1628 | module_exit(gcc_mdm9607_exit); |
1629 | |
1630 | MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver" ); |
1631 | MODULE_LICENSE("GPL v2" ); |
1632 | |