1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright 2020 Linaro Limited |
4 | */ |
5 | |
6 | #include <linux/kernel.h> |
7 | #include <linux/bitops.h> |
8 | #include <linux/err.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/reset-controller.h> |
15 | |
16 | #include <dt-bindings/clock/qcom,gcc-msm8939.h> |
17 | #include <dt-bindings/reset/qcom,gcc-msm8939.h> |
18 | |
19 | #include "common.h" |
20 | #include "clk-regmap.h" |
21 | #include "clk-pll.h" |
22 | #include "clk-rcg.h" |
23 | #include "clk-branch.h" |
24 | #include "reset.h" |
25 | #include "gdsc.h" |
26 | |
27 | enum { |
28 | P_XO, |
29 | P_GPLL0, |
30 | P_GPLL0_AUX, |
31 | P_BIMC, |
32 | P_GPLL1, |
33 | P_GPLL1_AUX, |
34 | P_GPLL2, |
35 | P_GPLL2_AUX, |
36 | P_GPLL3, |
37 | P_GPLL3_AUX, |
38 | P_GPLL4, |
39 | P_GPLL5, |
40 | P_GPLL5_AUX, |
41 | P_GPLL5_EARLY, |
42 | P_GPLL6, |
43 | P_GPLL6_AUX, |
44 | P_SLEEP_CLK, |
45 | P_DSI0_PHYPLL_BYTE, |
46 | P_DSI0_PHYPLL_DSI, |
47 | P_EXT_PRI_I2S, |
48 | P_EXT_SEC_I2S, |
49 | P_EXT_MCLK, |
50 | }; |
51 | |
52 | static struct clk_pll gpll0 = { |
53 | .l_reg = 0x21004, |
54 | .m_reg = 0x21008, |
55 | .n_reg = 0x2100c, |
56 | .config_reg = 0x21010, |
57 | .mode_reg = 0x21000, |
58 | .status_reg = 0x2101c, |
59 | .status_bit = 17, |
60 | .clkr.hw.init = &(struct clk_init_data){ |
61 | .name = "gpll0" , |
62 | .parent_data = &(const struct clk_parent_data) { |
63 | .fw_name = "xo" , |
64 | }, |
65 | .num_parents = 1, |
66 | .ops = &clk_pll_ops, |
67 | }, |
68 | }; |
69 | |
70 | static struct clk_regmap gpll0_vote = { |
71 | .enable_reg = 0x45000, |
72 | .enable_mask = BIT(0), |
73 | .hw.init = &(struct clk_init_data){ |
74 | .name = "gpll0_vote" , |
75 | .parent_hws = (const struct clk_hw*[]) { |
76 | &gpll0.clkr.hw, |
77 | }, |
78 | .num_parents = 1, |
79 | .ops = &clk_pll_vote_ops, |
80 | }, |
81 | }; |
82 | |
83 | static struct clk_pll gpll1 = { |
84 | .l_reg = 0x20004, |
85 | .m_reg = 0x20008, |
86 | .n_reg = 0x2000c, |
87 | .config_reg = 0x20010, |
88 | .mode_reg = 0x20000, |
89 | .status_reg = 0x2001c, |
90 | .status_bit = 17, |
91 | .clkr.hw.init = &(struct clk_init_data){ |
92 | .name = "gpll1" , |
93 | .parent_data = &(const struct clk_parent_data) { |
94 | .fw_name = "xo" , |
95 | }, |
96 | .num_parents = 1, |
97 | .ops = &clk_pll_ops, |
98 | }, |
99 | }; |
100 | |
101 | static struct clk_regmap gpll1_vote = { |
102 | .enable_reg = 0x45000, |
103 | .enable_mask = BIT(1), |
104 | .hw.init = &(struct clk_init_data){ |
105 | .name = "gpll1_vote" , |
106 | .parent_hws = (const struct clk_hw*[]) { |
107 | &gpll1.clkr.hw, |
108 | }, |
109 | .num_parents = 1, |
110 | .ops = &clk_pll_vote_ops, |
111 | }, |
112 | }; |
113 | |
114 | static struct clk_pll gpll2 = { |
115 | .l_reg = 0x4a004, |
116 | .m_reg = 0x4a008, |
117 | .n_reg = 0x4a00c, |
118 | .config_reg = 0x4a010, |
119 | .mode_reg = 0x4a000, |
120 | .status_reg = 0x4a01c, |
121 | .status_bit = 17, |
122 | .clkr.hw.init = &(struct clk_init_data){ |
123 | .name = "gpll2" , |
124 | .parent_data = &(const struct clk_parent_data) { |
125 | .fw_name = "xo" , |
126 | }, |
127 | .num_parents = 1, |
128 | .ops = &clk_pll_ops, |
129 | }, |
130 | }; |
131 | |
132 | static struct clk_regmap gpll2_vote = { |
133 | .enable_reg = 0x45000, |
134 | .enable_mask = BIT(2), |
135 | .hw.init = &(struct clk_init_data){ |
136 | .name = "gpll2_vote" , |
137 | .parent_hws = (const struct clk_hw*[]) { |
138 | &gpll2.clkr.hw, |
139 | }, |
140 | .num_parents = 1, |
141 | .ops = &clk_pll_vote_ops, |
142 | }, |
143 | }; |
144 | |
145 | static struct clk_pll bimc_pll = { |
146 | .l_reg = 0x23004, |
147 | .m_reg = 0x23008, |
148 | .n_reg = 0x2300c, |
149 | .config_reg = 0x23010, |
150 | .mode_reg = 0x23000, |
151 | .status_reg = 0x2301c, |
152 | .status_bit = 17, |
153 | .clkr.hw.init = &(struct clk_init_data){ |
154 | .name = "bimc_pll" , |
155 | .parent_data = &(const struct clk_parent_data) { |
156 | .fw_name = "xo" , |
157 | }, |
158 | .num_parents = 1, |
159 | .ops = &clk_pll_ops, |
160 | }, |
161 | }; |
162 | |
163 | static struct clk_regmap bimc_pll_vote = { |
164 | .enable_reg = 0x45000, |
165 | .enable_mask = BIT(3), |
166 | .hw.init = &(struct clk_init_data){ |
167 | .name = "bimc_pll_vote" , |
168 | .parent_hws = (const struct clk_hw*[]) { |
169 | &bimc_pll.clkr.hw, |
170 | }, |
171 | .num_parents = 1, |
172 | .ops = &clk_pll_vote_ops, |
173 | }, |
174 | }; |
175 | |
176 | static struct clk_pll gpll3 = { |
177 | .l_reg = 0x22004, |
178 | .m_reg = 0x22008, |
179 | .n_reg = 0x2200c, |
180 | .config_reg = 0x22010, |
181 | .mode_reg = 0x22000, |
182 | .status_reg = 0x2201c, |
183 | .status_bit = 17, |
184 | .clkr.hw.init = &(struct clk_init_data){ |
185 | .name = "gpll3" , |
186 | .parent_data = &(const struct clk_parent_data) { |
187 | .fw_name = "xo" , |
188 | }, |
189 | .num_parents = 1, |
190 | .ops = &clk_pll_ops, |
191 | }, |
192 | }; |
193 | |
194 | static struct clk_regmap gpll3_vote = { |
195 | .enable_reg = 0x45000, |
196 | .enable_mask = BIT(4), |
197 | .hw.init = &(struct clk_init_data){ |
198 | .name = "gpll3_vote" , |
199 | .parent_hws = (const struct clk_hw*[]) { |
200 | &gpll3.clkr.hw, |
201 | }, |
202 | .num_parents = 1, |
203 | .ops = &clk_pll_vote_ops, |
204 | }, |
205 | }; |
206 | |
207 | /* GPLL3 at 1100 MHz, main output enabled. */ |
208 | static const struct pll_config gpll3_config = { |
209 | .l = 57, |
210 | .m = 7, |
211 | .n = 24, |
212 | .vco_val = 0x0, |
213 | .vco_mask = BIT(20), |
214 | .pre_div_val = 0x0, |
215 | .pre_div_mask = BIT(12), |
216 | .post_div_val = 0x0, |
217 | .post_div_mask = BIT(9) | BIT(8), |
218 | .mn_ena_mask = BIT(24), |
219 | .main_output_mask = BIT(0), |
220 | .aux_output_mask = BIT(1), |
221 | }; |
222 | |
223 | static struct clk_pll gpll4 = { |
224 | .l_reg = 0x24004, |
225 | .m_reg = 0x24008, |
226 | .n_reg = 0x2400c, |
227 | .config_reg = 0x24010, |
228 | .mode_reg = 0x24000, |
229 | .status_reg = 0x2401c, |
230 | .status_bit = 17, |
231 | .clkr.hw.init = &(struct clk_init_data){ |
232 | .name = "gpll4" , |
233 | .parent_data = &(const struct clk_parent_data) { |
234 | .fw_name = "xo" , |
235 | }, |
236 | .num_parents = 1, |
237 | .ops = &clk_pll_ops, |
238 | }, |
239 | }; |
240 | |
241 | static struct clk_regmap gpll4_vote = { |
242 | .enable_reg = 0x45000, |
243 | .enable_mask = BIT(5), |
244 | .hw.init = &(struct clk_init_data){ |
245 | .name = "gpll4_vote" , |
246 | .parent_hws = (const struct clk_hw*[]) { |
247 | &gpll4.clkr.hw, |
248 | }, |
249 | .num_parents = 1, |
250 | .ops = &clk_pll_vote_ops, |
251 | }, |
252 | }; |
253 | |
254 | /* GPLL4 at 1200 MHz, main output enabled. */ |
255 | static struct pll_config gpll4_config = { |
256 | .l = 62, |
257 | .m = 1, |
258 | .n = 2, |
259 | .vco_val = 0x0, |
260 | .vco_mask = BIT(20), |
261 | .pre_div_val = 0x0, |
262 | .pre_div_mask = BIT(12), |
263 | .post_div_val = 0x0, |
264 | .post_div_mask = BIT(9) | BIT(8), |
265 | .mn_ena_mask = BIT(24), |
266 | .main_output_mask = BIT(0), |
267 | }; |
268 | |
269 | static struct clk_pll gpll5 = { |
270 | .l_reg = 0x25004, |
271 | .m_reg = 0x25008, |
272 | .n_reg = 0x2500c, |
273 | .config_reg = 0x25010, |
274 | .mode_reg = 0x25000, |
275 | .status_reg = 0x2501c, |
276 | .status_bit = 17, |
277 | .clkr.hw.init = &(struct clk_init_data){ |
278 | .name = "gpll5" , |
279 | .parent_data = &(const struct clk_parent_data) { |
280 | .fw_name = "xo" , |
281 | }, |
282 | .num_parents = 1, |
283 | .ops = &clk_pll_ops, |
284 | }, |
285 | }; |
286 | |
287 | static struct clk_regmap gpll5_vote = { |
288 | .enable_reg = 0x45000, |
289 | .enable_mask = BIT(6), |
290 | .hw.init = &(struct clk_init_data){ |
291 | .name = "gpll5_vote" , |
292 | .parent_hws = (const struct clk_hw*[]) { |
293 | &gpll5.clkr.hw, |
294 | }, |
295 | .num_parents = 1, |
296 | .ops = &clk_pll_vote_ops, |
297 | }, |
298 | }; |
299 | |
300 | static struct clk_pll gpll6 = { |
301 | .l_reg = 0x37004, |
302 | .m_reg = 0x37008, |
303 | .n_reg = 0x3700c, |
304 | .config_reg = 0x37010, |
305 | .mode_reg = 0x37000, |
306 | .status_reg = 0x3701c, |
307 | .status_bit = 17, |
308 | .clkr.hw.init = &(struct clk_init_data){ |
309 | .name = "gpll6" , |
310 | .parent_data = &(const struct clk_parent_data) { |
311 | .fw_name = "xo" , |
312 | }, |
313 | .num_parents = 1, |
314 | .ops = &clk_pll_ops, |
315 | }, |
316 | }; |
317 | |
318 | static struct clk_regmap gpll6_vote = { |
319 | .enable_reg = 0x45000, |
320 | .enable_mask = BIT(7), |
321 | .hw.init = &(struct clk_init_data){ |
322 | .name = "gpll6_vote" , |
323 | .parent_hws = (const struct clk_hw*[]) { |
324 | &gpll6.clkr.hw, |
325 | }, |
326 | .num_parents = 1, |
327 | .ops = &clk_pll_vote_ops, |
328 | }, |
329 | }; |
330 | |
331 | static const struct parent_map gcc_xo_gpll0_map[] = { |
332 | { P_XO, 0 }, |
333 | { P_GPLL0, 1 }, |
334 | }; |
335 | |
336 | static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = { |
337 | { .fw_name = "xo" }, |
338 | { .hw = &gpll0_vote.hw }, |
339 | }; |
340 | |
341 | static const struct parent_map gcc_xo_gpll0_bimc_map[] = { |
342 | { P_XO, 0 }, |
343 | { P_GPLL0, 1 }, |
344 | { P_BIMC, 2 }, |
345 | }; |
346 | |
347 | static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = { |
348 | { .fw_name = "xo" }, |
349 | { .hw = &gpll0_vote.hw }, |
350 | { .hw = &bimc_pll_vote.hw }, |
351 | }; |
352 | |
353 | static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = { |
354 | { P_XO, 0 }, |
355 | { P_GPLL0, 1 }, |
356 | { P_GPLL6_AUX, 2 }, |
357 | }; |
358 | |
359 | static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = { |
360 | { .fw_name = "xo" }, |
361 | { .hw = &gpll0_vote.hw }, |
362 | { .hw = &gpll6_vote.hw }, |
363 | }; |
364 | |
365 | static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = { |
366 | { P_XO, 0 }, |
367 | { P_GPLL0, 1 }, |
368 | { P_GPLL2_AUX, 4 }, |
369 | { P_GPLL3, 2 }, |
370 | { P_GPLL6_AUX, 3 }, |
371 | }; |
372 | |
373 | static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = { |
374 | { .fw_name = "xo" }, |
375 | { .hw = &gpll0_vote.hw }, |
376 | { .hw = &gpll2_vote.hw }, |
377 | { .hw = &gpll3_vote.hw }, |
378 | { .hw = &gpll6_vote.hw }, |
379 | }; |
380 | |
381 | static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { |
382 | { P_XO, 0 }, |
383 | { P_GPLL0, 1 }, |
384 | { P_GPLL2, 2 }, |
385 | }; |
386 | |
387 | static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = { |
388 | { .fw_name = "xo" }, |
389 | { .hw = &gpll0_vote.hw }, |
390 | { .hw = &gpll2_vote.hw }, |
391 | }; |
392 | |
393 | static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = { |
394 | { P_XO, 0 }, |
395 | { P_GPLL0, 1 }, |
396 | { P_GPLL2, 3 }, |
397 | { P_GPLL4, 2 }, |
398 | }; |
399 | |
400 | static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = { |
401 | { .fw_name = "xo" }, |
402 | { .hw = &gpll0_vote.hw }, |
403 | { .hw = &gpll2_vote.hw }, |
404 | { .hw = &gpll4_vote.hw }, |
405 | }; |
406 | |
407 | static const struct parent_map gcc_xo_gpll0a_map[] = { |
408 | { P_XO, 0 }, |
409 | { P_GPLL0_AUX, 2 }, |
410 | }; |
411 | |
412 | static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = { |
413 | { .fw_name = "xo" }, |
414 | { .hw = &gpll0_vote.hw }, |
415 | }; |
416 | |
417 | static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { |
418 | { P_XO, 0 }, |
419 | { P_GPLL0, 1 }, |
420 | { P_GPLL1_AUX, 2 }, |
421 | { P_SLEEP_CLK, 6 }, |
422 | }; |
423 | |
424 | static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = { |
425 | { .fw_name = "xo" }, |
426 | { .hw = &gpll0_vote.hw }, |
427 | { .hw = &gpll1_vote.hw }, |
428 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
429 | }; |
430 | |
431 | static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = { |
432 | { P_XO, 0 }, |
433 | { P_GPLL0, 1 }, |
434 | { P_GPLL1_AUX, 2 }, |
435 | { P_GPLL6, 2 }, |
436 | { P_SLEEP_CLK, 6 }, |
437 | }; |
438 | |
439 | static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = { |
440 | { .fw_name = "xo" }, |
441 | { .hw = &gpll0_vote.hw }, |
442 | { .hw = &gpll1_vote.hw }, |
443 | { .hw = &gpll6_vote.hw }, |
444 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
445 | }; |
446 | |
447 | static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { |
448 | { P_XO, 0 }, |
449 | { P_GPLL0, 1 }, |
450 | { P_GPLL1_AUX, 2 }, |
451 | }; |
452 | |
453 | static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = { |
454 | { .fw_name = "xo" }, |
455 | { .hw = &gpll0_vote.hw }, |
456 | { .hw = &gpll1_vote.hw }, |
457 | }; |
458 | |
459 | static const struct parent_map gcc_xo_dsibyte_map[] = { |
460 | { P_XO, 0, }, |
461 | { P_DSI0_PHYPLL_BYTE, 2 }, |
462 | }; |
463 | |
464 | static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = { |
465 | { .fw_name = "xo" }, |
466 | { .fw_name = "dsi0pllbyte" , .name = "dsi0pllbyte" }, |
467 | }; |
468 | |
469 | static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { |
470 | { P_XO, 0 }, |
471 | { P_GPLL0_AUX, 2 }, |
472 | { P_DSI0_PHYPLL_BYTE, 1 }, |
473 | }; |
474 | |
475 | static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = { |
476 | { .fw_name = "xo" }, |
477 | { .hw = &gpll0_vote.hw }, |
478 | { .fw_name = "dsi0pllbyte" , .name = "dsi0pllbyte" }, |
479 | }; |
480 | |
481 | static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = { |
482 | { P_XO, 0 }, |
483 | { P_GPLL1, 1 }, |
484 | { P_DSI0_PHYPLL_DSI, 2 }, |
485 | { P_GPLL6, 3 }, |
486 | { P_GPLL3_AUX, 4 }, |
487 | { P_GPLL0_AUX, 5 }, |
488 | }; |
489 | |
490 | static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = { |
491 | { .fw_name = "xo" }, |
492 | { .hw = &gpll1_vote.hw }, |
493 | { .fw_name = "dsi0pll" , .name = "dsi0pll" }, |
494 | { .hw = &gpll6_vote.hw }, |
495 | { .hw = &gpll3_vote.hw }, |
496 | { .hw = &gpll0_vote.hw }, |
497 | }; |
498 | |
499 | static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { |
500 | { P_XO, 0 }, |
501 | { P_GPLL0_AUX, 2 }, |
502 | { P_DSI0_PHYPLL_DSI, 1 }, |
503 | }; |
504 | |
505 | static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = { |
506 | { .fw_name = "xo" }, |
507 | { .hw = &gpll0_vote.hw }, |
508 | { .fw_name = "dsi0pll" , .name = "dsi0pll" }, |
509 | }; |
510 | |
511 | static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = { |
512 | { P_XO, 0 }, |
513 | { P_GPLL0, 1 }, |
514 | { P_GPLL5_AUX, 3 }, |
515 | { P_GPLL6, 2 }, |
516 | { P_BIMC, 4 }, |
517 | }; |
518 | |
519 | static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = { |
520 | { .fw_name = "xo" }, |
521 | { .hw = &gpll0_vote.hw }, |
522 | { .hw = &gpll5_vote.hw }, |
523 | { .hw = &gpll6_vote.hw }, |
524 | { .hw = &bimc_pll_vote.hw }, |
525 | }; |
526 | |
527 | static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { |
528 | { P_XO, 0 }, |
529 | { P_GPLL0, 1 }, |
530 | { P_GPLL1, 2 }, |
531 | { P_SLEEP_CLK, 6 } |
532 | }; |
533 | |
534 | static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = { |
535 | { .fw_name = "xo" }, |
536 | { .hw = &gpll0_vote.hw }, |
537 | { .hw = &gpll1_vote.hw }, |
538 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
539 | }; |
540 | |
541 | static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { |
542 | { P_XO, 0 }, |
543 | { P_GPLL1, 1 }, |
544 | { P_EXT_PRI_I2S, 2 }, |
545 | { P_EXT_MCLK, 3 }, |
546 | { P_SLEEP_CLK, 6 } |
547 | }; |
548 | |
549 | static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = { |
550 | { .fw_name = "xo" }, |
551 | { .hw = &gpll0_vote.hw }, |
552 | { .fw_name = "ext_pri_i2s" , .name = "ext_pri_i2s" }, |
553 | { .fw_name = "ext_mclk" , .name = "ext_mclk" }, |
554 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
555 | }; |
556 | |
557 | static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { |
558 | { P_XO, 0 }, |
559 | { P_GPLL1, 1 }, |
560 | { P_EXT_SEC_I2S, 2 }, |
561 | { P_EXT_MCLK, 3 }, |
562 | { P_SLEEP_CLK, 6 } |
563 | }; |
564 | |
565 | static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = { |
566 | { .fw_name = "xo" }, |
567 | { .hw = &gpll1_vote.hw }, |
568 | { .fw_name = "ext_sec_i2s" , .name = "ext_sec_i2s" }, |
569 | { .fw_name = "ext_mclk" , .name = "ext_mclk" }, |
570 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
571 | }; |
572 | |
573 | static const struct parent_map gcc_xo_sleep_map[] = { |
574 | { P_XO, 0 }, |
575 | { P_SLEEP_CLK, 6 } |
576 | }; |
577 | |
578 | static const struct clk_parent_data gcc_xo_sleep_parent_data[] = { |
579 | { .fw_name = "xo" }, |
580 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
581 | }; |
582 | |
583 | static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { |
584 | { P_XO, 0 }, |
585 | { P_GPLL1, 1 }, |
586 | { P_EXT_MCLK, 2 }, |
587 | { P_SLEEP_CLK, 6 } |
588 | }; |
589 | |
590 | static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = { |
591 | { .fw_name = "xo" }, |
592 | { .hw = &gpll1_vote.hw }, |
593 | { .fw_name = "ext_mclk" , .name = "ext_mclk" }, |
594 | { .fw_name = "sleep_clk" , .name = "sleep_clk" }, |
595 | }; |
596 | |
597 | static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = { |
598 | { .fw_name = "xo" }, |
599 | { .hw = &gpll6_vote.hw }, |
600 | { .hw = &gpll0_vote.hw }, |
601 | }; |
602 | |
603 | static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = { |
604 | { .fw_name = "xo" }, |
605 | { .hw = &gpll6_vote.hw }, |
606 | { .hw = &gpll0_vote.hw }, |
607 | }; |
608 | |
609 | static struct clk_rcg2 pcnoc_bfdcd_clk_src = { |
610 | .cmd_rcgr = 0x27000, |
611 | .hid_width = 5, |
612 | .parent_map = gcc_xo_gpll0_map, |
613 | .clkr.hw.init = &(struct clk_init_data){ |
614 | .name = "pcnoc_bfdcd_clk_src" , |
615 | .parent_data = gcc_xo_gpll0_parent_data, |
616 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
617 | .ops = &clk_rcg2_ops, |
618 | }, |
619 | }; |
620 | |
621 | static struct clk_rcg2 system_noc_bfdcd_clk_src = { |
622 | .cmd_rcgr = 0x26004, |
623 | .hid_width = 5, |
624 | .parent_map = gcc_xo_gpll0_gpll6a_map, |
625 | .clkr.hw.init = &(struct clk_init_data){ |
626 | .name = "system_noc_bfdcd_clk_src" , |
627 | .parent_data = gcc_xo_gpll0_gpll6a_parent_data, |
628 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data), |
629 | .ops = &clk_rcg2_ops, |
630 | }, |
631 | }; |
632 | |
633 | static struct clk_rcg2 bimc_ddr_clk_src = { |
634 | .cmd_rcgr = 0x32024, |
635 | .hid_width = 5, |
636 | .parent_map = gcc_xo_gpll0_bimc_map, |
637 | .clkr.hw.init = &(struct clk_init_data){ |
638 | .name = "bimc_ddr_clk_src" , |
639 | .parent_data = gcc_xo_gpll0_bimc_parent_data, |
640 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data), |
641 | .ops = &clk_rcg2_ops, |
642 | .flags = CLK_GET_RATE_NOCACHE, |
643 | }, |
644 | }; |
645 | |
646 | static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = { |
647 | .cmd_rcgr = 0x2600c, |
648 | .hid_width = 5, |
649 | .parent_map = gcc_xo_gpll0_gpll6a_map, |
650 | .clkr.hw.init = &(struct clk_init_data){ |
651 | .name = "system_mm_noc_bfdcd_clk_src" , |
652 | .parent_data = gcc_xo_gpll0_gpll6a_parent_data, |
653 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data), |
654 | .ops = &clk_rcg2_ops, |
655 | }, |
656 | }; |
657 | |
658 | static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { |
659 | F(40000000, P_GPLL0, 10, 1, 2), |
660 | F(80000000, P_GPLL0, 10, 0, 0), |
661 | { } |
662 | }; |
663 | |
664 | static struct clk_rcg2 camss_ahb_clk_src = { |
665 | .cmd_rcgr = 0x5a000, |
666 | .mnd_width = 8, |
667 | .hid_width = 5, |
668 | .parent_map = gcc_xo_gpll0_map, |
669 | .freq_tbl = ftbl_gcc_camss_ahb_clk, |
670 | .clkr.hw.init = &(struct clk_init_data){ |
671 | .name = "camss_ahb_clk_src" , |
672 | .parent_data = gcc_xo_gpll0_parent_data, |
673 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
674 | .ops = &clk_rcg2_ops, |
675 | }, |
676 | }; |
677 | |
678 | static const struct freq_tbl ftbl_apss_ahb_clk[] = { |
679 | F(19200000, P_XO, 1, 0, 0), |
680 | F(50000000, P_GPLL0, 16, 0, 0), |
681 | F(100000000, P_GPLL0, 8, 0, 0), |
682 | F(133330000, P_GPLL0, 6, 0, 0), |
683 | { } |
684 | }; |
685 | |
686 | static struct clk_rcg2 apss_ahb_clk_src = { |
687 | .cmd_rcgr = 0x46000, |
688 | .hid_width = 5, |
689 | .parent_map = gcc_xo_gpll0_map, |
690 | .freq_tbl = ftbl_apss_ahb_clk, |
691 | .clkr.hw.init = &(struct clk_init_data){ |
692 | .name = "apss_ahb_clk_src" , |
693 | .parent_data = gcc_xo_gpll0_parent_data, |
694 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
695 | .ops = &clk_rcg2_ops, |
696 | }, |
697 | }; |
698 | |
699 | static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = { |
700 | F(100000000, P_GPLL0, 8, 0, 0), |
701 | F(200000000, P_GPLL0, 4, 0, 0), |
702 | { } |
703 | }; |
704 | |
705 | static struct clk_rcg2 csi0_clk_src = { |
706 | .cmd_rcgr = 0x4e020, |
707 | .hid_width = 5, |
708 | .parent_map = gcc_xo_gpll0_map, |
709 | .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk, |
710 | .clkr.hw.init = &(struct clk_init_data){ |
711 | .name = "csi0_clk_src" , |
712 | .parent_data = gcc_xo_gpll0_parent_data, |
713 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
714 | .ops = &clk_rcg2_ops, |
715 | }, |
716 | }; |
717 | |
718 | static struct clk_rcg2 csi1_clk_src = { |
719 | .cmd_rcgr = 0x4f020, |
720 | .hid_width = 5, |
721 | .parent_map = gcc_xo_gpll0_map, |
722 | .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk, |
723 | .clkr.hw.init = &(struct clk_init_data){ |
724 | .name = "csi1_clk_src" , |
725 | .parent_data = gcc_xo_gpll0_parent_data, |
726 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
727 | .ops = &clk_rcg2_ops, |
728 | }, |
729 | }; |
730 | |
731 | static struct clk_rcg2 csi2_clk_src = { |
732 | .cmd_rcgr = 0x3c020, |
733 | .hid_width = 5, |
734 | .parent_map = gcc_xo_gpll0_map, |
735 | .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk, |
736 | .clkr.hw.init = &(struct clk_init_data){ |
737 | .name = "csi2_clk_src" , |
738 | .parent_data = gcc_xo_gpll0_parent_data, |
739 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
740 | .ops = &clk_rcg2_ops, |
741 | }, |
742 | }; |
743 | |
744 | static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { |
745 | F(19200000, P_XO, 1, 0, 0), |
746 | F(50000000, P_GPLL0, 16, 0, 0), |
747 | F(80000000, P_GPLL0, 10, 0, 0), |
748 | F(100000000, P_GPLL0, 8, 0, 0), |
749 | F(160000000, P_GPLL0, 5, 0, 0), |
750 | F(200000000, P_GPLL0, 4, 0, 0), |
751 | F(220000000, P_GPLL3, 5, 0, 0), |
752 | F(266670000, P_GPLL0, 3, 0, 0), |
753 | F(310000000, P_GPLL2_AUX, 3, 0, 0), |
754 | F(400000000, P_GPLL0, 2, 0, 0), |
755 | F(465000000, P_GPLL2_AUX, 2, 0, 0), |
756 | F(550000000, P_GPLL3, 2, 0, 0), |
757 | { } |
758 | }; |
759 | |
760 | static struct clk_rcg2 gfx3d_clk_src = { |
761 | .cmd_rcgr = 0x59000, |
762 | .hid_width = 5, |
763 | .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map, |
764 | .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, |
765 | .clkr.hw.init = &(struct clk_init_data){ |
766 | .name = "gfx3d_clk_src" , |
767 | .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data, |
768 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data), |
769 | .ops = &clk_rcg2_ops, |
770 | }, |
771 | }; |
772 | |
773 | static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { |
774 | F(50000000, P_GPLL0, 16, 0, 0), |
775 | F(80000000, P_GPLL0, 10, 0, 0), |
776 | F(100000000, P_GPLL0, 8, 0, 0), |
777 | F(160000000, P_GPLL0, 5, 0, 0), |
778 | F(177780000, P_GPLL0, 4.5, 0, 0), |
779 | F(200000000, P_GPLL0, 4, 0, 0), |
780 | F(266670000, P_GPLL0, 3, 0, 0), |
781 | F(320000000, P_GPLL0, 2.5, 0, 0), |
782 | F(400000000, P_GPLL0, 2, 0, 0), |
783 | F(465000000, P_GPLL2, 2, 0, 0), |
784 | F(480000000, P_GPLL4, 2.5, 0, 0), |
785 | F(600000000, P_GPLL4, 2, 0, 0), |
786 | { } |
787 | }; |
788 | |
789 | static struct clk_rcg2 vfe0_clk_src = { |
790 | .cmd_rcgr = 0x58000, |
791 | .hid_width = 5, |
792 | .parent_map = gcc_xo_gpll0_gpll2_gpll4_map, |
793 | .freq_tbl = ftbl_gcc_camss_vfe0_clk, |
794 | .clkr.hw.init = &(struct clk_init_data){ |
795 | .name = "vfe0_clk_src" , |
796 | .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data, |
797 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data), |
798 | .ops = &clk_rcg2_ops, |
799 | }, |
800 | }; |
801 | |
802 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { |
803 | F(19200000, P_XO, 1, 0, 0), |
804 | F(50000000, P_GPLL0, 16, 0, 0), |
805 | { } |
806 | }; |
807 | |
808 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { |
809 | .cmd_rcgr = 0x0200c, |
810 | .hid_width = 5, |
811 | .parent_map = gcc_xo_gpll0_map, |
812 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
813 | .clkr.hw.init = &(struct clk_init_data){ |
814 | .name = "blsp1_qup1_i2c_apps_clk_src" , |
815 | .parent_data = gcc_xo_gpll0_parent_data, |
816 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
817 | .ops = &clk_rcg2_ops, |
818 | }, |
819 | }; |
820 | |
821 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { |
822 | F(960000, P_XO, 10, 1, 2), |
823 | F(4800000, P_XO, 4, 0, 0), |
824 | F(9600000, P_XO, 2, 0, 0), |
825 | F(16000000, P_GPLL0, 10, 1, 5), |
826 | F(19200000, P_XO, 1, 0, 0), |
827 | F(25000000, P_GPLL0, 16, 1, 2), |
828 | F(50000000, P_GPLL0, 16, 0, 0), |
829 | { } |
830 | }; |
831 | |
832 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { |
833 | .cmd_rcgr = 0x02024, |
834 | .mnd_width = 8, |
835 | .hid_width = 5, |
836 | .parent_map = gcc_xo_gpll0_map, |
837 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
838 | .clkr.hw.init = &(struct clk_init_data){ |
839 | .name = "blsp1_qup1_spi_apps_clk_src" , |
840 | .parent_data = gcc_xo_gpll0_parent_data, |
841 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
842 | .ops = &clk_rcg2_ops, |
843 | }, |
844 | }; |
845 | |
846 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { |
847 | .cmd_rcgr = 0x03000, |
848 | .hid_width = 5, |
849 | .parent_map = gcc_xo_gpll0_map, |
850 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
851 | .clkr.hw.init = &(struct clk_init_data){ |
852 | .name = "blsp1_qup2_i2c_apps_clk_src" , |
853 | .parent_data = gcc_xo_gpll0_parent_data, |
854 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
855 | .ops = &clk_rcg2_ops, |
856 | }, |
857 | }; |
858 | |
859 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { |
860 | .cmd_rcgr = 0x03014, |
861 | .mnd_width = 8, |
862 | .hid_width = 5, |
863 | .parent_map = gcc_xo_gpll0_map, |
864 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
865 | .clkr.hw.init = &(struct clk_init_data){ |
866 | .name = "blsp1_qup2_spi_apps_clk_src" , |
867 | .parent_data = gcc_xo_gpll0_parent_data, |
868 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
869 | .ops = &clk_rcg2_ops, |
870 | }, |
871 | }; |
872 | |
873 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { |
874 | .cmd_rcgr = 0x04000, |
875 | .hid_width = 5, |
876 | .parent_map = gcc_xo_gpll0_map, |
877 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
878 | .clkr.hw.init = &(struct clk_init_data){ |
879 | .name = "blsp1_qup3_i2c_apps_clk_src" , |
880 | .parent_data = gcc_xo_gpll0_parent_data, |
881 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
882 | .ops = &clk_rcg2_ops, |
883 | }, |
884 | }; |
885 | |
886 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { |
887 | .cmd_rcgr = 0x04024, |
888 | .mnd_width = 8, |
889 | .hid_width = 5, |
890 | .parent_map = gcc_xo_gpll0_map, |
891 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
892 | .clkr.hw.init = &(struct clk_init_data){ |
893 | .name = "blsp1_qup3_spi_apps_clk_src" , |
894 | .parent_data = gcc_xo_gpll0_parent_data, |
895 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
896 | .ops = &clk_rcg2_ops, |
897 | }, |
898 | }; |
899 | |
900 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { |
901 | .cmd_rcgr = 0x05000, |
902 | .hid_width = 5, |
903 | .parent_map = gcc_xo_gpll0_map, |
904 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
905 | .clkr.hw.init = &(struct clk_init_data){ |
906 | .name = "blsp1_qup4_i2c_apps_clk_src" , |
907 | .parent_data = gcc_xo_gpll0_parent_data, |
908 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
909 | .ops = &clk_rcg2_ops, |
910 | }, |
911 | }; |
912 | |
913 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { |
914 | .cmd_rcgr = 0x05024, |
915 | .mnd_width = 8, |
916 | .hid_width = 5, |
917 | .parent_map = gcc_xo_gpll0_map, |
918 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
919 | .clkr.hw.init = &(struct clk_init_data){ |
920 | .name = "blsp1_qup4_spi_apps_clk_src" , |
921 | .parent_data = gcc_xo_gpll0_parent_data, |
922 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
923 | .ops = &clk_rcg2_ops, |
924 | }, |
925 | }; |
926 | |
927 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { |
928 | .cmd_rcgr = 0x06000, |
929 | .hid_width = 5, |
930 | .parent_map = gcc_xo_gpll0_map, |
931 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
932 | .clkr.hw.init = &(struct clk_init_data){ |
933 | .name = "blsp1_qup5_i2c_apps_clk_src" , |
934 | .parent_data = gcc_xo_gpll0_parent_data, |
935 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
936 | .ops = &clk_rcg2_ops, |
937 | }, |
938 | }; |
939 | |
940 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { |
941 | .cmd_rcgr = 0x06024, |
942 | .mnd_width = 8, |
943 | .hid_width = 5, |
944 | .parent_map = gcc_xo_gpll0_map, |
945 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
946 | .clkr.hw.init = &(struct clk_init_data){ |
947 | .name = "blsp1_qup5_spi_apps_clk_src" , |
948 | .parent_data = gcc_xo_gpll0_parent_data, |
949 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
950 | .ops = &clk_rcg2_ops, |
951 | }, |
952 | }; |
953 | |
954 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { |
955 | .cmd_rcgr = 0x07000, |
956 | .hid_width = 5, |
957 | .parent_map = gcc_xo_gpll0_map, |
958 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
959 | .clkr.hw.init = &(struct clk_init_data){ |
960 | .name = "blsp1_qup6_i2c_apps_clk_src" , |
961 | .parent_data = gcc_xo_gpll0_parent_data, |
962 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
963 | .ops = &clk_rcg2_ops, |
964 | }, |
965 | }; |
966 | |
967 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { |
968 | .cmd_rcgr = 0x07024, |
969 | .mnd_width = 8, |
970 | .hid_width = 5, |
971 | .parent_map = gcc_xo_gpll0_map, |
972 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
973 | .clkr.hw.init = &(struct clk_init_data){ |
974 | .name = "blsp1_qup6_spi_apps_clk_src" , |
975 | .parent_data = gcc_xo_gpll0_parent_data, |
976 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
977 | .ops = &clk_rcg2_ops, |
978 | }, |
979 | }; |
980 | |
981 | static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { |
982 | F(3686400, P_GPLL0, 1, 72, 15625), |
983 | F(7372800, P_GPLL0, 1, 144, 15625), |
984 | F(14745600, P_GPLL0, 1, 288, 15625), |
985 | F(16000000, P_GPLL0, 10, 1, 5), |
986 | F(19200000, P_XO, 1, 0, 0), |
987 | F(24000000, P_GPLL0, 1, 3, 100), |
988 | F(25000000, P_GPLL0, 16, 1, 2), |
989 | F(32000000, P_GPLL0, 1, 1, 25), |
990 | F(40000000, P_GPLL0, 1, 1, 20), |
991 | F(46400000, P_GPLL0, 1, 29, 500), |
992 | F(48000000, P_GPLL0, 1, 3, 50), |
993 | F(51200000, P_GPLL0, 1, 8, 125), |
994 | F(56000000, P_GPLL0, 1, 7, 100), |
995 | F(58982400, P_GPLL0, 1, 1152, 15625), |
996 | F(60000000, P_GPLL0, 1, 3, 40), |
997 | { } |
998 | }; |
999 | |
1000 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { |
1001 | .cmd_rcgr = 0x02044, |
1002 | .mnd_width = 16, |
1003 | .hid_width = 5, |
1004 | .parent_map = gcc_xo_gpll0_map, |
1005 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
1006 | .clkr.hw.init = &(struct clk_init_data){ |
1007 | .name = "blsp1_uart1_apps_clk_src" , |
1008 | .parent_data = gcc_xo_gpll0_parent_data, |
1009 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1010 | .ops = &clk_rcg2_ops, |
1011 | }, |
1012 | }; |
1013 | |
1014 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { |
1015 | .cmd_rcgr = 0x03034, |
1016 | .mnd_width = 16, |
1017 | .hid_width = 5, |
1018 | .parent_map = gcc_xo_gpll0_map, |
1019 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
1020 | .clkr.hw.init = &(struct clk_init_data){ |
1021 | .name = "blsp1_uart2_apps_clk_src" , |
1022 | .parent_data = gcc_xo_gpll0_parent_data, |
1023 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1024 | .ops = &clk_rcg2_ops, |
1025 | }, |
1026 | }; |
1027 | |
1028 | static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { |
1029 | F(19200000, P_XO, 1, 0, 0), |
1030 | F(37500000, P_GPLL0, 1, 3, 64), |
1031 | { } |
1032 | }; |
1033 | |
1034 | static struct clk_rcg2 cci_clk_src = { |
1035 | .cmd_rcgr = 0x51000, |
1036 | .mnd_width = 8, |
1037 | .hid_width = 5, |
1038 | .parent_map = gcc_xo_gpll0a_map, |
1039 | .freq_tbl = ftbl_gcc_camss_cci_clk, |
1040 | .clkr.hw.init = &(struct clk_init_data){ |
1041 | .name = "cci_clk_src" , |
1042 | .parent_data = gcc_xo_gpll0a_parent_data, |
1043 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data), |
1044 | .ops = &clk_rcg2_ops, |
1045 | }, |
1046 | }; |
1047 | |
1048 | /* |
1049 | * This is a frequency table for "General Purpose" clocks. |
1050 | * These clocks can be muxed to the SoC pins and may be used by |
1051 | * external devices. They're often used as PWM source. |
1052 | * |
1053 | * See comment at ftbl_gcc_gp1_3_clk. |
1054 | */ |
1055 | static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { |
1056 | F(10000, P_XO, 16, 1, 120), |
1057 | F(100000, P_XO, 16, 1, 12), |
1058 | F(500000, P_GPLL0, 16, 1, 100), |
1059 | F(1000000, P_GPLL0, 16, 1, 50), |
1060 | F(2500000, P_GPLL0, 16, 1, 20), |
1061 | F(5000000, P_GPLL0, 16, 1, 10), |
1062 | F(100000000, P_GPLL0, 8, 0, 0), |
1063 | F(200000000, P_GPLL0, 4, 0, 0), |
1064 | { } |
1065 | }; |
1066 | |
1067 | static struct clk_rcg2 camss_gp0_clk_src = { |
1068 | .cmd_rcgr = 0x54000, |
1069 | .mnd_width = 8, |
1070 | .hid_width = 5, |
1071 | .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, |
1072 | .freq_tbl = ftbl_gcc_camss_gp0_1_clk, |
1073 | .clkr.hw.init = &(struct clk_init_data){ |
1074 | .name = "camss_gp0_clk_src" , |
1075 | .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, |
1076 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data), |
1077 | .ops = &clk_rcg2_ops, |
1078 | }, |
1079 | }; |
1080 | |
1081 | static struct clk_rcg2 camss_gp1_clk_src = { |
1082 | .cmd_rcgr = 0x55000, |
1083 | .mnd_width = 8, |
1084 | .hid_width = 5, |
1085 | .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, |
1086 | .freq_tbl = ftbl_gcc_camss_gp0_1_clk, |
1087 | .clkr.hw.init = &(struct clk_init_data){ |
1088 | .name = "camss_gp1_clk_src" , |
1089 | .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, |
1090 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data), |
1091 | .ops = &clk_rcg2_ops, |
1092 | }, |
1093 | }; |
1094 | |
1095 | static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { |
1096 | F(133330000, P_GPLL0, 6, 0, 0), |
1097 | F(266670000, P_GPLL0, 3, 0, 0), |
1098 | F(320000000, P_GPLL0, 2.5, 0, 0), |
1099 | { } |
1100 | }; |
1101 | |
1102 | static struct clk_rcg2 jpeg0_clk_src = { |
1103 | .cmd_rcgr = 0x57000, |
1104 | .hid_width = 5, |
1105 | .parent_map = gcc_xo_gpll0_map, |
1106 | .freq_tbl = ftbl_gcc_camss_jpeg0_clk, |
1107 | .clkr.hw.init = &(struct clk_init_data){ |
1108 | .name = "jpeg0_clk_src" , |
1109 | .parent_data = gcc_xo_gpll0_parent_data, |
1110 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1111 | .ops = &clk_rcg2_ops, |
1112 | }, |
1113 | }; |
1114 | |
1115 | static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { |
1116 | F(24000000, P_GPLL0, 1, 1, 45), |
1117 | F(66670000, P_GPLL0, 12, 0, 0), |
1118 | { } |
1119 | }; |
1120 | |
1121 | static struct clk_rcg2 mclk0_clk_src = { |
1122 | .cmd_rcgr = 0x52000, |
1123 | .mnd_width = 8, |
1124 | .hid_width = 5, |
1125 | .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map, |
1126 | .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, |
1127 | .clkr.hw.init = &(struct clk_init_data){ |
1128 | .name = "mclk0_clk_src" , |
1129 | .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data, |
1130 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data), |
1131 | .ops = &clk_rcg2_ops, |
1132 | }, |
1133 | }; |
1134 | |
1135 | static struct clk_rcg2 mclk1_clk_src = { |
1136 | .cmd_rcgr = 0x53000, |
1137 | .mnd_width = 8, |
1138 | .hid_width = 5, |
1139 | .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map, |
1140 | .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, |
1141 | .clkr.hw.init = &(struct clk_init_data){ |
1142 | .name = "mclk1_clk_src" , |
1143 | .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data, |
1144 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data), |
1145 | .ops = &clk_rcg2_ops, |
1146 | }, |
1147 | }; |
1148 | |
1149 | static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { |
1150 | F(100000000, P_GPLL0, 8, 0, 0), |
1151 | F(200000000, P_GPLL0, 4, 0, 0), |
1152 | { } |
1153 | }; |
1154 | |
1155 | static struct clk_rcg2 csi0phytimer_clk_src = { |
1156 | .cmd_rcgr = 0x4e000, |
1157 | .hid_width = 5, |
1158 | .parent_map = gcc_xo_gpll0_gpll1a_map, |
1159 | .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, |
1160 | .clkr.hw.init = &(struct clk_init_data){ |
1161 | .name = "csi0phytimer_clk_src" , |
1162 | .parent_data = gcc_xo_gpll0_gpll1a_parent_data, |
1163 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data), |
1164 | .ops = &clk_rcg2_ops, |
1165 | }, |
1166 | }; |
1167 | |
1168 | static struct clk_rcg2 csi1phytimer_clk_src = { |
1169 | .cmd_rcgr = 0x4f000, |
1170 | .hid_width = 5, |
1171 | .parent_map = gcc_xo_gpll0_gpll1a_map, |
1172 | .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, |
1173 | .clkr.hw.init = &(struct clk_init_data){ |
1174 | .name = "csi1phytimer_clk_src" , |
1175 | .parent_data = gcc_xo_gpll0_gpll1a_parent_data, |
1176 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data), |
1177 | .ops = &clk_rcg2_ops, |
1178 | }, |
1179 | }; |
1180 | |
1181 | static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { |
1182 | F(160000000, P_GPLL0, 5, 0, 0), |
1183 | F(200000000, P_GPLL0, 4, 0, 0), |
1184 | F(228570000, P_GPLL0, 3.5, 0, 0), |
1185 | F(266670000, P_GPLL0, 3, 0, 0), |
1186 | F(320000000, P_GPLL0, 2.5, 0, 0), |
1187 | F(465000000, P_GPLL2, 2, 0, 0), |
1188 | { } |
1189 | }; |
1190 | |
1191 | static struct clk_rcg2 cpp_clk_src = { |
1192 | .cmd_rcgr = 0x58018, |
1193 | .hid_width = 5, |
1194 | .parent_map = gcc_xo_gpll0_gpll2_map, |
1195 | .freq_tbl = ftbl_gcc_camss_cpp_clk, |
1196 | .clkr.hw.init = &(struct clk_init_data){ |
1197 | .name = "cpp_clk_src" , |
1198 | .parent_data = gcc_xo_gpll0_gpll2_parent_data, |
1199 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data), |
1200 | .ops = &clk_rcg2_ops, |
1201 | }, |
1202 | }; |
1203 | |
1204 | static const struct freq_tbl ftbl_gcc_crypto_clk[] = { |
1205 | F(50000000, P_GPLL0, 16, 0, 0), |
1206 | F(80000000, P_GPLL0, 10, 0, 0), |
1207 | F(100000000, P_GPLL0, 8, 0, 0), |
1208 | F(160000000, P_GPLL0, 5, 0, 0), |
1209 | { } |
1210 | }; |
1211 | |
1212 | /* This is not in the documentation but is in the downstream driver */ |
1213 | static struct clk_rcg2 crypto_clk_src = { |
1214 | .cmd_rcgr = 0x16004, |
1215 | .hid_width = 5, |
1216 | .parent_map = gcc_xo_gpll0_map, |
1217 | .freq_tbl = ftbl_gcc_crypto_clk, |
1218 | .clkr.hw.init = &(struct clk_init_data){ |
1219 | .name = "crypto_clk_src" , |
1220 | .parent_data = gcc_xo_gpll0_parent_data, |
1221 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1222 | .ops = &clk_rcg2_ops, |
1223 | }, |
1224 | }; |
1225 | |
1226 | /* |
1227 | * This is a frequency table for "General Purpose" clocks. |
1228 | * These clocks can be muxed to the SoC pins and may be used by |
1229 | * external devices. They're often used as PWM source. |
1230 | * |
1231 | * Please note that MND divider must be enabled for duty-cycle |
1232 | * control to be possible. (M != N) Also since D register is configured |
1233 | * with a value multiplied by 2, and duty cycle is calculated as |
1234 | * (2 * D) % 2^W |
1235 | * DutyCycle = ---------------- |
1236 | * 2 * (N % 2^W) |
1237 | * (where W = .mnd_width) |
1238 | * N must be half or less than maximum value for the register. |
1239 | * Otherwise duty-cycle control would be limited. |
1240 | * (e.g. for 8-bit NMD N should be less than 128) |
1241 | */ |
1242 | static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { |
1243 | F(10000, P_XO, 16, 1, 120), |
1244 | F(100000, P_XO, 16, 1, 12), |
1245 | F(500000, P_GPLL0, 16, 1, 100), |
1246 | F(1000000, P_GPLL0, 16, 1, 50), |
1247 | F(2500000, P_GPLL0, 16, 1, 20), |
1248 | F(5000000, P_GPLL0, 16, 1, 10), |
1249 | F(19200000, P_XO, 1, 0, 0), |
1250 | { } |
1251 | }; |
1252 | |
1253 | static struct clk_rcg2 gp1_clk_src = { |
1254 | .cmd_rcgr = 0x08004, |
1255 | .mnd_width = 8, |
1256 | .hid_width = 5, |
1257 | .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, |
1258 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
1259 | .clkr.hw.init = &(struct clk_init_data){ |
1260 | .name = "gp1_clk_src" , |
1261 | .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, |
1262 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data), |
1263 | .ops = &clk_rcg2_ops, |
1264 | }, |
1265 | }; |
1266 | |
1267 | static struct clk_rcg2 gp2_clk_src = { |
1268 | .cmd_rcgr = 0x09004, |
1269 | .mnd_width = 8, |
1270 | .hid_width = 5, |
1271 | .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, |
1272 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
1273 | .clkr.hw.init = &(struct clk_init_data){ |
1274 | .name = "gp2_clk_src" , |
1275 | .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, |
1276 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data), |
1277 | .ops = &clk_rcg2_ops, |
1278 | }, |
1279 | }; |
1280 | |
1281 | static struct clk_rcg2 gp3_clk_src = { |
1282 | .cmd_rcgr = 0x0a004, |
1283 | .mnd_width = 8, |
1284 | .hid_width = 5, |
1285 | .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, |
1286 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
1287 | .clkr.hw.init = &(struct clk_init_data){ |
1288 | .name = "gp3_clk_src" , |
1289 | .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, |
1290 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data), |
1291 | .ops = &clk_rcg2_ops, |
1292 | }, |
1293 | }; |
1294 | |
1295 | static struct clk_rcg2 byte0_clk_src = { |
1296 | .cmd_rcgr = 0x4d044, |
1297 | .hid_width = 5, |
1298 | .parent_map = gcc_xo_gpll0a_dsibyte_map, |
1299 | .clkr.hw.init = &(struct clk_init_data){ |
1300 | .name = "byte0_clk_src" , |
1301 | .parent_data = gcc_xo_gpll0a_dsibyte_parent_data, |
1302 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data), |
1303 | .ops = &clk_byte2_ops, |
1304 | .flags = CLK_SET_RATE_PARENT, |
1305 | }, |
1306 | }; |
1307 | |
1308 | static struct clk_rcg2 byte1_clk_src = { |
1309 | .cmd_rcgr = 0x4d0b0, |
1310 | .hid_width = 5, |
1311 | .parent_map = gcc_xo_gpll0a_dsibyte_map, |
1312 | .clkr.hw.init = &(struct clk_init_data){ |
1313 | .name = "byte1_clk_src" , |
1314 | .parent_data = gcc_xo_gpll0a_dsibyte_parent_data, |
1315 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data), |
1316 | .ops = &clk_byte2_ops, |
1317 | .flags = CLK_SET_RATE_PARENT, |
1318 | }, |
1319 | }; |
1320 | |
1321 | static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = { |
1322 | F(19200000, P_XO, 1, 0, 0), |
1323 | { } |
1324 | }; |
1325 | |
1326 | static struct clk_rcg2 esc0_clk_src = { |
1327 | .cmd_rcgr = 0x4d060, |
1328 | .hid_width = 5, |
1329 | .parent_map = gcc_xo_dsibyte_map, |
1330 | .freq_tbl = ftbl_gcc_mdss_esc_clk, |
1331 | .clkr.hw.init = &(struct clk_init_data){ |
1332 | .name = "esc0_clk_src" , |
1333 | .parent_data = gcc_xo_dsibyte_parent_data, |
1334 | .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data), |
1335 | .ops = &clk_rcg2_ops, |
1336 | }, |
1337 | }; |
1338 | |
1339 | static struct clk_rcg2 esc1_clk_src = { |
1340 | .cmd_rcgr = 0x4d0a8, |
1341 | .hid_width = 5, |
1342 | .parent_map = gcc_xo_dsibyte_map, |
1343 | .freq_tbl = ftbl_gcc_mdss_esc_clk, |
1344 | .clkr.hw.init = &(struct clk_init_data){ |
1345 | .name = "esc1_clk_src" , |
1346 | .parent_data = gcc_xo_dsibyte_parent_data, |
1347 | .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data), |
1348 | .ops = &clk_rcg2_ops, |
1349 | }, |
1350 | }; |
1351 | |
1352 | static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { |
1353 | F(50000000, P_GPLL0_AUX, 16, 0, 0), |
1354 | F(80000000, P_GPLL0_AUX, 10, 0, 0), |
1355 | F(100000000, P_GPLL0_AUX, 8, 0, 0), |
1356 | F(145500000, P_GPLL0_AUX, 5.5, 0, 0), |
1357 | F(153600000, P_GPLL0, 4, 0, 0), |
1358 | F(160000000, P_GPLL0_AUX, 5, 0, 0), |
1359 | F(177780000, P_GPLL0_AUX, 4.5, 0, 0), |
1360 | F(200000000, P_GPLL0_AUX, 4, 0, 0), |
1361 | F(266670000, P_GPLL0_AUX, 3, 0, 0), |
1362 | F(307200000, P_GPLL1, 2, 0, 0), |
1363 | F(366670000, P_GPLL3_AUX, 3, 0, 0), |
1364 | { } |
1365 | }; |
1366 | |
1367 | static struct clk_rcg2 mdp_clk_src = { |
1368 | .cmd_rcgr = 0x4d014, |
1369 | .hid_width = 5, |
1370 | .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map, |
1371 | .freq_tbl = ftbl_gcc_mdss_mdp_clk, |
1372 | .clkr.hw.init = &(struct clk_init_data){ |
1373 | .name = "mdp_clk_src" , |
1374 | .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data, |
1375 | .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data), |
1376 | .ops = &clk_rcg2_ops, |
1377 | }, |
1378 | }; |
1379 | |
1380 | static struct clk_rcg2 pclk0_clk_src = { |
1381 | .cmd_rcgr = 0x4d000, |
1382 | .mnd_width = 8, |
1383 | .hid_width = 5, |
1384 | .parent_map = gcc_xo_gpll0a_dsiphy_map, |
1385 | .clkr.hw.init = &(struct clk_init_data){ |
1386 | .name = "pclk0_clk_src" , |
1387 | .parent_data = gcc_xo_gpll0a_dsiphy_parent_data, |
1388 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data), |
1389 | .ops = &clk_pixel_ops, |
1390 | .flags = CLK_SET_RATE_PARENT, |
1391 | }, |
1392 | }; |
1393 | |
1394 | static struct clk_rcg2 pclk1_clk_src = { |
1395 | .cmd_rcgr = 0x4d0b8, |
1396 | .mnd_width = 8, |
1397 | .hid_width = 5, |
1398 | .parent_map = gcc_xo_gpll0a_dsiphy_map, |
1399 | .clkr.hw.init = &(struct clk_init_data){ |
1400 | .name = "pclk1_clk_src" , |
1401 | .parent_data = gcc_xo_gpll0a_dsiphy_parent_data, |
1402 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data), |
1403 | .ops = &clk_pixel_ops, |
1404 | .flags = CLK_SET_RATE_PARENT, |
1405 | }, |
1406 | }; |
1407 | |
1408 | static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { |
1409 | F(19200000, P_XO, 1, 0, 0), |
1410 | { } |
1411 | }; |
1412 | |
1413 | static struct clk_rcg2 vsync_clk_src = { |
1414 | .cmd_rcgr = 0x4d02c, |
1415 | .hid_width = 5, |
1416 | .parent_map = gcc_xo_gpll0a_map, |
1417 | .freq_tbl = ftbl_gcc_mdss_vsync_clk, |
1418 | .clkr.hw.init = &(struct clk_init_data){ |
1419 | .name = "vsync_clk_src" , |
1420 | .parent_data = gcc_xo_gpll0a_parent_data, |
1421 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data), |
1422 | .ops = &clk_rcg2_ops, |
1423 | }, |
1424 | }; |
1425 | |
1426 | static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { |
1427 | F(64000000, P_GPLL0, 12.5, 0, 0), |
1428 | { } |
1429 | }; |
1430 | |
1431 | /* This is not in the documentation but is in the downstream driver */ |
1432 | static struct clk_rcg2 pdm2_clk_src = { |
1433 | .cmd_rcgr = 0x44010, |
1434 | .hid_width = 5, |
1435 | .parent_map = gcc_xo_gpll0_map, |
1436 | .freq_tbl = ftbl_gcc_pdm2_clk, |
1437 | .clkr.hw.init = &(struct clk_init_data){ |
1438 | .name = "pdm2_clk_src" , |
1439 | .parent_data = gcc_xo_gpll0_parent_data, |
1440 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1441 | .ops = &clk_rcg2_ops, |
1442 | }, |
1443 | }; |
1444 | |
1445 | static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = { |
1446 | F(144000, P_XO, 16, 3, 25), |
1447 | F(400000, P_XO, 12, 1, 4), |
1448 | F(20000000, P_GPLL0, 10, 1, 4), |
1449 | F(25000000, P_GPLL0, 16, 1, 2), |
1450 | F(50000000, P_GPLL0, 16, 0, 0), |
1451 | F(100000000, P_GPLL0, 8, 0, 0), |
1452 | F(177770000, P_GPLL0, 4.5, 0, 0), |
1453 | F(200000000, P_GPLL0, 4, 0, 0), |
1454 | { } |
1455 | }; |
1456 | |
1457 | static struct clk_rcg2 sdcc1_apps_clk_src = { |
1458 | .cmd_rcgr = 0x42004, |
1459 | .mnd_width = 8, |
1460 | .hid_width = 5, |
1461 | .parent_map = gcc_xo_gpll0_map, |
1462 | .freq_tbl = ftbl_gcc_sdcc_apps_clk, |
1463 | .clkr.hw.init = &(struct clk_init_data){ |
1464 | .name = "sdcc1_apps_clk_src" , |
1465 | .parent_data = gcc_xo_gpll0_parent_data, |
1466 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1467 | .ops = &clk_rcg2_floor_ops, |
1468 | }, |
1469 | }; |
1470 | |
1471 | static struct clk_rcg2 sdcc2_apps_clk_src = { |
1472 | .cmd_rcgr = 0x43004, |
1473 | .mnd_width = 8, |
1474 | .hid_width = 5, |
1475 | .parent_map = gcc_xo_gpll0_map, |
1476 | .freq_tbl = ftbl_gcc_sdcc_apps_clk, |
1477 | .clkr.hw.init = &(struct clk_init_data){ |
1478 | .name = "sdcc2_apps_clk_src" , |
1479 | .parent_data = gcc_xo_gpll0_parent_data, |
1480 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1481 | .ops = &clk_rcg2_floor_ops, |
1482 | }, |
1483 | }; |
1484 | |
1485 | static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { |
1486 | F(154285000, P_GPLL6, 7, 0, 0), |
1487 | F(320000000, P_GPLL0, 2.5, 0, 0), |
1488 | F(400000000, P_GPLL0, 2, 0, 0), |
1489 | { } |
1490 | }; |
1491 | |
1492 | static struct clk_rcg2 apss_tcu_clk_src = { |
1493 | .cmd_rcgr = 0x1207c, |
1494 | .hid_width = 5, |
1495 | .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map, |
1496 | .freq_tbl = ftbl_gcc_apss_tcu_clk, |
1497 | .clkr.hw.init = &(struct clk_init_data){ |
1498 | .name = "apss_tcu_clk_src" , |
1499 | .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data, |
1500 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data), |
1501 | .ops = &clk_rcg2_ops, |
1502 | }, |
1503 | }; |
1504 | |
1505 | static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { |
1506 | F(19200000, P_XO, 1, 0, 0), |
1507 | F(100000000, P_GPLL0, 8, 0, 0), |
1508 | F(200000000, P_GPLL0, 4, 0, 0), |
1509 | F(266500000, P_BIMC, 4, 0, 0), |
1510 | F(400000000, P_GPLL0, 2, 0, 0), |
1511 | F(533000000, P_BIMC, 2, 0, 0), |
1512 | { } |
1513 | }; |
1514 | |
1515 | static struct clk_rcg2 bimc_gpu_clk_src = { |
1516 | .cmd_rcgr = 0x31028, |
1517 | .hid_width = 5, |
1518 | .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map, |
1519 | .freq_tbl = ftbl_gcc_bimc_gpu_clk, |
1520 | .clkr.hw.init = &(struct clk_init_data){ |
1521 | .name = "bimc_gpu_clk_src" , |
1522 | .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data, |
1523 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data), |
1524 | .flags = CLK_GET_RATE_NOCACHE, |
1525 | .ops = &clk_rcg2_ops, |
1526 | }, |
1527 | }; |
1528 | |
1529 | static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
1530 | F(57140000, P_GPLL0, 14, 0, 0), |
1531 | F(80000000, P_GPLL0, 10, 0, 0), |
1532 | F(100000000, P_GPLL0, 8, 0, 0), |
1533 | { } |
1534 | }; |
1535 | |
1536 | static struct clk_rcg2 usb_hs_system_clk_src = { |
1537 | .cmd_rcgr = 0x41010, |
1538 | .hid_width = 5, |
1539 | .parent_map = gcc_xo_gpll0_map, |
1540 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
1541 | .clkr.hw.init = &(struct clk_init_data){ |
1542 | .name = "usb_hs_system_clk_src" , |
1543 | .parent_data = gcc_xo_gpll0_parent_data, |
1544 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1545 | .ops = &clk_rcg2_ops, |
1546 | }, |
1547 | }; |
1548 | |
1549 | static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = { |
1550 | F(64000000, P_GPLL0, 12.5, 0, 0), |
1551 | { } |
1552 | }; |
1553 | |
1554 | static struct clk_rcg2 usb_fs_system_clk_src = { |
1555 | .cmd_rcgr = 0x3f010, |
1556 | .hid_width = 5, |
1557 | .parent_map = gcc_xo_gpll0_map, |
1558 | .freq_tbl = ftbl_gcc_usb_fs_system_clk, |
1559 | .clkr.hw.init = &(struct clk_init_data){ |
1560 | .name = "usb_fs_system_clk_src" , |
1561 | .parent_data = gcc_xo_gpll6_gpll0_parent_data, |
1562 | .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data), |
1563 | .ops = &clk_rcg2_ops, |
1564 | }, |
1565 | }; |
1566 | |
1567 | static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = { |
1568 | F(60000000, P_GPLL6, 1, 1, 18), |
1569 | { } |
1570 | }; |
1571 | |
1572 | static struct clk_rcg2 usb_fs_ic_clk_src = { |
1573 | .cmd_rcgr = 0x3f034, |
1574 | .hid_width = 5, |
1575 | .parent_map = gcc_xo_gpll0_map, |
1576 | .freq_tbl = ftbl_gcc_usb_fs_ic_clk, |
1577 | .clkr.hw.init = &(struct clk_init_data){ |
1578 | .name = "usb_fs_ic_clk_src" , |
1579 | .parent_data = gcc_xo_gpll6_gpll0a_parent_data, |
1580 | .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data), |
1581 | .ops = &clk_rcg2_ops, |
1582 | }, |
1583 | }; |
1584 | |
1585 | static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { |
1586 | F(3200000, P_XO, 6, 0, 0), |
1587 | F(6400000, P_XO, 3, 0, 0), |
1588 | F(9600000, P_XO, 2, 0, 0), |
1589 | F(19200000, P_XO, 1, 0, 0), |
1590 | F(40000000, P_GPLL0, 10, 1, 2), |
1591 | F(66670000, P_GPLL0, 12, 0, 0), |
1592 | F(80000000, P_GPLL0, 10, 0, 0), |
1593 | F(100000000, P_GPLL0, 8, 0, 0), |
1594 | { } |
1595 | }; |
1596 | |
1597 | static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { |
1598 | .cmd_rcgr = 0x1c010, |
1599 | .hid_width = 5, |
1600 | .mnd_width = 8, |
1601 | .parent_map = gcc_xo_gpll0_gpll1_sleep_map, |
1602 | .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, |
1603 | .clkr.hw.init = &(struct clk_init_data){ |
1604 | .name = "ultaudio_ahbfabric_clk_src" , |
1605 | .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data, |
1606 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data), |
1607 | .ops = &clk_rcg2_ops, |
1608 | }, |
1609 | }; |
1610 | |
1611 | static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { |
1612 | .halt_reg = 0x1c028, |
1613 | .clkr = { |
1614 | .enable_reg = 0x1c028, |
1615 | .enable_mask = BIT(0), |
1616 | .hw.init = &(struct clk_init_data){ |
1617 | .name = "gcc_ultaudio_ahbfabric_ixfabric_clk" , |
1618 | .parent_hws = (const struct clk_hw*[]){ |
1619 | &ultaudio_ahbfabric_clk_src.clkr.hw, |
1620 | }, |
1621 | .num_parents = 1, |
1622 | .flags = CLK_SET_RATE_PARENT, |
1623 | .ops = &clk_branch2_ops, |
1624 | }, |
1625 | }, |
1626 | }; |
1627 | |
1628 | static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { |
1629 | .halt_reg = 0x1c024, |
1630 | .clkr = { |
1631 | .enable_reg = 0x1c024, |
1632 | .enable_mask = BIT(0), |
1633 | .hw.init = &(struct clk_init_data){ |
1634 | .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk" , |
1635 | .parent_hws = (const struct clk_hw*[]){ |
1636 | &ultaudio_ahbfabric_clk_src.clkr.hw, |
1637 | }, |
1638 | .num_parents = 1, |
1639 | .flags = CLK_SET_RATE_PARENT, |
1640 | .ops = &clk_branch2_ops, |
1641 | }, |
1642 | }, |
1643 | }; |
1644 | |
1645 | static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { |
1646 | F(128000, P_XO, 10, 1, 15), |
1647 | F(256000, P_XO, 5, 1, 15), |
1648 | F(384000, P_XO, 5, 1, 10), |
1649 | F(512000, P_XO, 5, 2, 15), |
1650 | F(576000, P_XO, 5, 3, 20), |
1651 | F(705600, P_GPLL1, 16, 1, 80), |
1652 | F(768000, P_XO, 5, 1, 5), |
1653 | F(800000, P_XO, 5, 5, 24), |
1654 | F(1024000, P_XO, 5, 4, 15), |
1655 | F(1152000, P_XO, 1, 3, 50), |
1656 | F(1411200, P_GPLL1, 16, 1, 40), |
1657 | F(1536000, P_XO, 1, 2, 25), |
1658 | F(1600000, P_XO, 12, 0, 0), |
1659 | F(1728000, P_XO, 5, 9, 20), |
1660 | F(2048000, P_XO, 5, 8, 15), |
1661 | F(2304000, P_XO, 5, 3, 5), |
1662 | F(2400000, P_XO, 8, 0, 0), |
1663 | F(2822400, P_GPLL1, 16, 1, 20), |
1664 | F(3072000, P_XO, 5, 4, 5), |
1665 | F(4096000, P_GPLL1, 9, 2, 49), |
1666 | F(4800000, P_XO, 4, 0, 0), |
1667 | F(5644800, P_GPLL1, 16, 1, 10), |
1668 | F(6144000, P_GPLL1, 7, 1, 21), |
1669 | F(8192000, P_GPLL1, 9, 4, 49), |
1670 | F(9600000, P_XO, 2, 0, 0), |
1671 | F(11289600, P_GPLL1, 16, 1, 5), |
1672 | F(12288000, P_GPLL1, 7, 2, 21), |
1673 | { } |
1674 | }; |
1675 | |
1676 | static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { |
1677 | .cmd_rcgr = 0x1c054, |
1678 | .hid_width = 5, |
1679 | .mnd_width = 8, |
1680 | .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, |
1681 | .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, |
1682 | .clkr.hw.init = &(struct clk_init_data){ |
1683 | .name = "ultaudio_lpaif_pri_i2s_clk_src" , |
1684 | .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data, |
1685 | .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data), |
1686 | .ops = &clk_rcg2_ops, |
1687 | }, |
1688 | }; |
1689 | |
1690 | static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { |
1691 | .halt_reg = 0x1c068, |
1692 | .clkr = { |
1693 | .enable_reg = 0x1c068, |
1694 | .enable_mask = BIT(0), |
1695 | .hw.init = &(struct clk_init_data){ |
1696 | .name = "gcc_ultaudio_lpaif_pri_i2s_clk" , |
1697 | .parent_hws = (const struct clk_hw*[]){ |
1698 | &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw, |
1699 | }, |
1700 | .num_parents = 1, |
1701 | .flags = CLK_SET_RATE_PARENT, |
1702 | .ops = &clk_branch2_ops, |
1703 | }, |
1704 | }, |
1705 | }; |
1706 | |
1707 | static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { |
1708 | .cmd_rcgr = 0x1c06c, |
1709 | .hid_width = 5, |
1710 | .mnd_width = 8, |
1711 | .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, |
1712 | .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, |
1713 | .clkr.hw.init = &(struct clk_init_data){ |
1714 | .name = "ultaudio_lpaif_sec_i2s_clk_src" , |
1715 | .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data, |
1716 | .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data), |
1717 | .ops = &clk_rcg2_ops, |
1718 | }, |
1719 | }; |
1720 | |
1721 | static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { |
1722 | .halt_reg = 0x1c080, |
1723 | .clkr = { |
1724 | .enable_reg = 0x1c080, |
1725 | .enable_mask = BIT(0), |
1726 | .hw.init = &(struct clk_init_data){ |
1727 | .name = "gcc_ultaudio_lpaif_sec_i2s_clk" , |
1728 | .parent_hws = (const struct clk_hw*[]){ |
1729 | &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw, |
1730 | }, |
1731 | .num_parents = 1, |
1732 | .flags = CLK_SET_RATE_PARENT, |
1733 | .ops = &clk_branch2_ops, |
1734 | }, |
1735 | }, |
1736 | }; |
1737 | |
1738 | static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { |
1739 | .cmd_rcgr = 0x1c084, |
1740 | .hid_width = 5, |
1741 | .mnd_width = 8, |
1742 | .parent_map = gcc_xo_gpll1_emclk_sleep_map, |
1743 | .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, |
1744 | .clkr.hw.init = &(struct clk_init_data){ |
1745 | .name = "ultaudio_lpaif_aux_i2s_clk_src" , |
1746 | .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data, |
1747 | .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data), |
1748 | .ops = &clk_rcg2_ops, |
1749 | }, |
1750 | }; |
1751 | |
1752 | static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { |
1753 | .halt_reg = 0x1c098, |
1754 | .clkr = { |
1755 | .enable_reg = 0x1c098, |
1756 | .enable_mask = BIT(0), |
1757 | .hw.init = &(struct clk_init_data){ |
1758 | .name = "gcc_ultaudio_lpaif_aux_i2s_clk" , |
1759 | .parent_hws = (const struct clk_hw*[]){ |
1760 | &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw, |
1761 | }, |
1762 | .num_parents = 1, |
1763 | .flags = CLK_SET_RATE_PARENT, |
1764 | .ops = &clk_branch2_ops, |
1765 | }, |
1766 | }, |
1767 | }; |
1768 | |
1769 | static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { |
1770 | F(19200000, P_XO, 1, 0, 0), |
1771 | { } |
1772 | }; |
1773 | |
1774 | static struct clk_rcg2 ultaudio_xo_clk_src = { |
1775 | .cmd_rcgr = 0x1c034, |
1776 | .hid_width = 5, |
1777 | .parent_map = gcc_xo_sleep_map, |
1778 | .freq_tbl = ftbl_gcc_ultaudio_xo_clk, |
1779 | .clkr.hw.init = &(struct clk_init_data){ |
1780 | .name = "ultaudio_xo_clk_src" , |
1781 | .parent_data = gcc_xo_sleep_parent_data, |
1782 | .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data), |
1783 | .ops = &clk_rcg2_ops, |
1784 | }, |
1785 | }; |
1786 | |
1787 | static struct clk_branch gcc_ultaudio_avsync_xo_clk = { |
1788 | .halt_reg = 0x1c04c, |
1789 | .clkr = { |
1790 | .enable_reg = 0x1c04c, |
1791 | .enable_mask = BIT(0), |
1792 | .hw.init = &(struct clk_init_data){ |
1793 | .name = "gcc_ultaudio_avsync_xo_clk" , |
1794 | .parent_hws = (const struct clk_hw*[]){ |
1795 | &ultaudio_xo_clk_src.clkr.hw, |
1796 | }, |
1797 | .num_parents = 1, |
1798 | .flags = CLK_SET_RATE_PARENT, |
1799 | .ops = &clk_branch2_ops, |
1800 | }, |
1801 | }, |
1802 | }; |
1803 | |
1804 | static struct clk_branch gcc_ultaudio_stc_xo_clk = { |
1805 | .halt_reg = 0x1c050, |
1806 | .clkr = { |
1807 | .enable_reg = 0x1c050, |
1808 | .enable_mask = BIT(0), |
1809 | .hw.init = &(struct clk_init_data){ |
1810 | .name = "gcc_ultaudio_stc_xo_clk" , |
1811 | .parent_hws = (const struct clk_hw*[]){ |
1812 | &ultaudio_xo_clk_src.clkr.hw, |
1813 | }, |
1814 | .num_parents = 1, |
1815 | .flags = CLK_SET_RATE_PARENT, |
1816 | .ops = &clk_branch2_ops, |
1817 | }, |
1818 | }, |
1819 | }; |
1820 | |
1821 | static const struct freq_tbl ftbl_codec_clk[] = { |
1822 | F(9600000, P_XO, 2, 0, 0), |
1823 | F(12288000, P_XO, 1, 16, 25), |
1824 | F(19200000, P_XO, 1, 0, 0), |
1825 | F(11289600, P_EXT_MCLK, 1, 0, 0), |
1826 | { } |
1827 | }; |
1828 | |
1829 | static struct clk_rcg2 codec_digcodec_clk_src = { |
1830 | .cmd_rcgr = 0x1c09c, |
1831 | .mnd_width = 8, |
1832 | .hid_width = 5, |
1833 | .parent_map = gcc_xo_gpll1_emclk_sleep_map, |
1834 | .freq_tbl = ftbl_codec_clk, |
1835 | .clkr.hw.init = &(struct clk_init_data){ |
1836 | .name = "codec_digcodec_clk_src" , |
1837 | .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data, |
1838 | .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data), |
1839 | .ops = &clk_rcg2_ops, |
1840 | }, |
1841 | }; |
1842 | |
1843 | static struct clk_branch gcc_codec_digcodec_clk = { |
1844 | .halt_reg = 0x1c0b0, |
1845 | .clkr = { |
1846 | .enable_reg = 0x1c0b0, |
1847 | .enable_mask = BIT(0), |
1848 | .hw.init = &(struct clk_init_data){ |
1849 | .name = "gcc_ultaudio_codec_digcodec_clk" , |
1850 | .parent_hws = (const struct clk_hw*[]){ |
1851 | &codec_digcodec_clk_src.clkr.hw, |
1852 | }, |
1853 | .num_parents = 1, |
1854 | .flags = CLK_SET_RATE_PARENT, |
1855 | .ops = &clk_branch2_ops, |
1856 | }, |
1857 | }, |
1858 | }; |
1859 | |
1860 | static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { |
1861 | .halt_reg = 0x1c000, |
1862 | .clkr = { |
1863 | .enable_reg = 0x1c000, |
1864 | .enable_mask = BIT(0), |
1865 | .hw.init = &(struct clk_init_data){ |
1866 | .name = "gcc_ultaudio_pcnoc_mport_clk" , |
1867 | .parent_hws = (const struct clk_hw*[]){ |
1868 | &pcnoc_bfdcd_clk_src.clkr.hw, |
1869 | }, |
1870 | .num_parents = 1, |
1871 | .ops = &clk_branch2_ops, |
1872 | }, |
1873 | }, |
1874 | }; |
1875 | |
1876 | static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { |
1877 | .halt_reg = 0x1c004, |
1878 | .clkr = { |
1879 | .enable_reg = 0x1c004, |
1880 | .enable_mask = BIT(0), |
1881 | .hw.init = &(struct clk_init_data){ |
1882 | .name = "gcc_ultaudio_pcnoc_sway_clk" , |
1883 | .parent_hws = (const struct clk_hw*[]){ |
1884 | &pcnoc_bfdcd_clk_src.clkr.hw, |
1885 | }, |
1886 | .num_parents = 1, |
1887 | .ops = &clk_branch2_ops, |
1888 | }, |
1889 | }, |
1890 | }; |
1891 | |
1892 | static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { |
1893 | F(133330000, P_GPLL0, 6, 0, 0), |
1894 | F(200000000, P_GPLL0, 4, 0, 0), |
1895 | F(266670000, P_GPLL0, 3, 0, 0), |
1896 | { } |
1897 | }; |
1898 | |
1899 | static struct clk_rcg2 vcodec0_clk_src = { |
1900 | .cmd_rcgr = 0x4C000, |
1901 | .mnd_width = 8, |
1902 | .hid_width = 5, |
1903 | .parent_map = gcc_xo_gpll0_map, |
1904 | .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, |
1905 | .clkr.hw.init = &(struct clk_init_data){ |
1906 | .name = "vcodec0_clk_src" , |
1907 | .parent_data = gcc_xo_gpll0_parent_data, |
1908 | .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data), |
1909 | .ops = &clk_rcg2_ops, |
1910 | }, |
1911 | }; |
1912 | |
1913 | static struct clk_branch gcc_blsp1_ahb_clk = { |
1914 | .halt_reg = 0x01008, |
1915 | .halt_check = BRANCH_HALT_VOTED, |
1916 | .clkr = { |
1917 | .enable_reg = 0x45004, |
1918 | .enable_mask = BIT(10), |
1919 | .hw.init = &(struct clk_init_data){ |
1920 | .name = "gcc_blsp1_ahb_clk" , |
1921 | .parent_hws = (const struct clk_hw*[]){ |
1922 | &pcnoc_bfdcd_clk_src.clkr.hw, |
1923 | }, |
1924 | .num_parents = 1, |
1925 | .ops = &clk_branch2_ops, |
1926 | }, |
1927 | }, |
1928 | }; |
1929 | |
1930 | static struct clk_branch gcc_blsp1_sleep_clk = { |
1931 | .halt_reg = 0x01004, |
1932 | .clkr = { |
1933 | .enable_reg = 0x01004, |
1934 | .enable_mask = BIT(0), |
1935 | .hw.init = &(struct clk_init_data){ |
1936 | .name = "gcc_blsp1_sleep_clk" , |
1937 | .ops = &clk_branch2_ops, |
1938 | }, |
1939 | }, |
1940 | }; |
1941 | |
1942 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
1943 | .halt_reg = 0x02008, |
1944 | .clkr = { |
1945 | .enable_reg = 0x02008, |
1946 | .enable_mask = BIT(0), |
1947 | .hw.init = &(struct clk_init_data){ |
1948 | .name = "gcc_blsp1_qup1_i2c_apps_clk" , |
1949 | .parent_hws = (const struct clk_hw*[]){ |
1950 | &blsp1_qup1_i2c_apps_clk_src.clkr.hw, |
1951 | }, |
1952 | .num_parents = 1, |
1953 | .flags = CLK_SET_RATE_PARENT, |
1954 | .ops = &clk_branch2_ops, |
1955 | }, |
1956 | }, |
1957 | }; |
1958 | |
1959 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
1960 | .halt_reg = 0x02004, |
1961 | .clkr = { |
1962 | .enable_reg = 0x02004, |
1963 | .enable_mask = BIT(0), |
1964 | .hw.init = &(struct clk_init_data){ |
1965 | .name = "gcc_blsp1_qup1_spi_apps_clk" , |
1966 | .parent_hws = (const struct clk_hw*[]){ |
1967 | &blsp1_qup1_spi_apps_clk_src.clkr.hw, |
1968 | }, |
1969 | .num_parents = 1, |
1970 | .flags = CLK_SET_RATE_PARENT, |
1971 | .ops = &clk_branch2_ops, |
1972 | }, |
1973 | }, |
1974 | }; |
1975 | |
1976 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
1977 | .halt_reg = 0x03010, |
1978 | .clkr = { |
1979 | .enable_reg = 0x03010, |
1980 | .enable_mask = BIT(0), |
1981 | .hw.init = &(struct clk_init_data){ |
1982 | .name = "gcc_blsp1_qup2_i2c_apps_clk" , |
1983 | .parent_hws = (const struct clk_hw*[]){ |
1984 | &blsp1_qup2_i2c_apps_clk_src.clkr.hw, |
1985 | }, |
1986 | .num_parents = 1, |
1987 | .flags = CLK_SET_RATE_PARENT, |
1988 | .ops = &clk_branch2_ops, |
1989 | }, |
1990 | }, |
1991 | }; |
1992 | |
1993 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
1994 | .halt_reg = 0x0300c, |
1995 | .clkr = { |
1996 | .enable_reg = 0x0300c, |
1997 | .enable_mask = BIT(0), |
1998 | .hw.init = &(struct clk_init_data){ |
1999 | .name = "gcc_blsp1_qup2_spi_apps_clk" , |
2000 | .parent_hws = (const struct clk_hw*[]){ |
2001 | &blsp1_qup2_spi_apps_clk_src.clkr.hw, |
2002 | }, |
2003 | .num_parents = 1, |
2004 | .flags = CLK_SET_RATE_PARENT, |
2005 | .ops = &clk_branch2_ops, |
2006 | }, |
2007 | }, |
2008 | }; |
2009 | |
2010 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
2011 | .halt_reg = 0x04020, |
2012 | .clkr = { |
2013 | .enable_reg = 0x04020, |
2014 | .enable_mask = BIT(0), |
2015 | .hw.init = &(struct clk_init_data){ |
2016 | .name = "gcc_blsp1_qup3_i2c_apps_clk" , |
2017 | .parent_hws = (const struct clk_hw*[]){ |
2018 | &blsp1_qup3_i2c_apps_clk_src.clkr.hw, |
2019 | }, |
2020 | .num_parents = 1, |
2021 | .flags = CLK_SET_RATE_PARENT, |
2022 | .ops = &clk_branch2_ops, |
2023 | }, |
2024 | }, |
2025 | }; |
2026 | |
2027 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
2028 | .halt_reg = 0x0401c, |
2029 | .clkr = { |
2030 | .enable_reg = 0x0401c, |
2031 | .enable_mask = BIT(0), |
2032 | .hw.init = &(struct clk_init_data){ |
2033 | .name = "gcc_blsp1_qup3_spi_apps_clk" , |
2034 | .parent_hws = (const struct clk_hw*[]){ |
2035 | &blsp1_qup3_spi_apps_clk_src.clkr.hw, |
2036 | }, |
2037 | .num_parents = 1, |
2038 | .flags = CLK_SET_RATE_PARENT, |
2039 | .ops = &clk_branch2_ops, |
2040 | }, |
2041 | }, |
2042 | }; |
2043 | |
2044 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
2045 | .halt_reg = 0x05020, |
2046 | .clkr = { |
2047 | .enable_reg = 0x05020, |
2048 | .enable_mask = BIT(0), |
2049 | .hw.init = &(struct clk_init_data){ |
2050 | .name = "gcc_blsp1_qup4_i2c_apps_clk" , |
2051 | .parent_hws = (const struct clk_hw*[]){ |
2052 | &blsp1_qup4_i2c_apps_clk_src.clkr.hw, |
2053 | }, |
2054 | .num_parents = 1, |
2055 | .flags = CLK_SET_RATE_PARENT, |
2056 | .ops = &clk_branch2_ops, |
2057 | }, |
2058 | }, |
2059 | }; |
2060 | |
2061 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
2062 | .halt_reg = 0x0501c, |
2063 | .clkr = { |
2064 | .enable_reg = 0x0501c, |
2065 | .enable_mask = BIT(0), |
2066 | .hw.init = &(struct clk_init_data){ |
2067 | .name = "gcc_blsp1_qup4_spi_apps_clk" , |
2068 | .parent_hws = (const struct clk_hw*[]){ |
2069 | &blsp1_qup4_spi_apps_clk_src.clkr.hw, |
2070 | }, |
2071 | .num_parents = 1, |
2072 | .flags = CLK_SET_RATE_PARENT, |
2073 | .ops = &clk_branch2_ops, |
2074 | }, |
2075 | }, |
2076 | }; |
2077 | |
2078 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { |
2079 | .halt_reg = 0x06020, |
2080 | .clkr = { |
2081 | .enable_reg = 0x06020, |
2082 | .enable_mask = BIT(0), |
2083 | .hw.init = &(struct clk_init_data){ |
2084 | .name = "gcc_blsp1_qup5_i2c_apps_clk" , |
2085 | .parent_hws = (const struct clk_hw*[]){ |
2086 | &blsp1_qup5_i2c_apps_clk_src.clkr.hw, |
2087 | }, |
2088 | .num_parents = 1, |
2089 | .flags = CLK_SET_RATE_PARENT, |
2090 | .ops = &clk_branch2_ops, |
2091 | }, |
2092 | }, |
2093 | }; |
2094 | |
2095 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { |
2096 | .halt_reg = 0x0601c, |
2097 | .clkr = { |
2098 | .enable_reg = 0x0601c, |
2099 | .enable_mask = BIT(0), |
2100 | .hw.init = &(struct clk_init_data){ |
2101 | .name = "gcc_blsp1_qup5_spi_apps_clk" , |
2102 | .parent_hws = (const struct clk_hw*[]){ |
2103 | &blsp1_qup5_spi_apps_clk_src.clkr.hw, |
2104 | }, |
2105 | .num_parents = 1, |
2106 | .flags = CLK_SET_RATE_PARENT, |
2107 | .ops = &clk_branch2_ops, |
2108 | }, |
2109 | }, |
2110 | }; |
2111 | |
2112 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { |
2113 | .halt_reg = 0x07020, |
2114 | .clkr = { |
2115 | .enable_reg = 0x07020, |
2116 | .enable_mask = BIT(0), |
2117 | .hw.init = &(struct clk_init_data){ |
2118 | .name = "gcc_blsp1_qup6_i2c_apps_clk" , |
2119 | .parent_hws = (const struct clk_hw*[]){ |
2120 | &blsp1_qup6_i2c_apps_clk_src.clkr.hw, |
2121 | }, |
2122 | .num_parents = 1, |
2123 | .flags = CLK_SET_RATE_PARENT, |
2124 | .ops = &clk_branch2_ops, |
2125 | }, |
2126 | }, |
2127 | }; |
2128 | |
2129 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { |
2130 | .halt_reg = 0x0701c, |
2131 | .clkr = { |
2132 | .enable_reg = 0x0701c, |
2133 | .enable_mask = BIT(0), |
2134 | .hw.init = &(struct clk_init_data){ |
2135 | .name = "gcc_blsp1_qup6_spi_apps_clk" , |
2136 | .parent_hws = (const struct clk_hw*[]){ |
2137 | &blsp1_qup6_spi_apps_clk_src.clkr.hw, |
2138 | }, |
2139 | .num_parents = 1, |
2140 | .flags = CLK_SET_RATE_PARENT, |
2141 | .ops = &clk_branch2_ops, |
2142 | }, |
2143 | }, |
2144 | }; |
2145 | |
2146 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
2147 | .halt_reg = 0x0203c, |
2148 | .clkr = { |
2149 | .enable_reg = 0x0203c, |
2150 | .enable_mask = BIT(0), |
2151 | .hw.init = &(struct clk_init_data){ |
2152 | .name = "gcc_blsp1_uart1_apps_clk" , |
2153 | .parent_hws = (const struct clk_hw*[]){ |
2154 | &blsp1_uart1_apps_clk_src.clkr.hw, |
2155 | }, |
2156 | .num_parents = 1, |
2157 | .flags = CLK_SET_RATE_PARENT, |
2158 | .ops = &clk_branch2_ops, |
2159 | }, |
2160 | }, |
2161 | }; |
2162 | |
2163 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
2164 | .halt_reg = 0x0302c, |
2165 | .clkr = { |
2166 | .enable_reg = 0x0302c, |
2167 | .enable_mask = BIT(0), |
2168 | .hw.init = &(struct clk_init_data){ |
2169 | .name = "gcc_blsp1_uart2_apps_clk" , |
2170 | .parent_hws = (const struct clk_hw*[]){ |
2171 | &blsp1_uart2_apps_clk_src.clkr.hw, |
2172 | }, |
2173 | .num_parents = 1, |
2174 | .flags = CLK_SET_RATE_PARENT, |
2175 | .ops = &clk_branch2_ops, |
2176 | }, |
2177 | }, |
2178 | }; |
2179 | |
2180 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
2181 | .halt_reg = 0x1300c, |
2182 | .halt_check = BRANCH_HALT_VOTED, |
2183 | .clkr = { |
2184 | .enable_reg = 0x45004, |
2185 | .enable_mask = BIT(7), |
2186 | .hw.init = &(struct clk_init_data){ |
2187 | .name = "gcc_boot_rom_ahb_clk" , |
2188 | .parent_hws = (const struct clk_hw*[]){ |
2189 | &pcnoc_bfdcd_clk_src.clkr.hw, |
2190 | }, |
2191 | .num_parents = 1, |
2192 | .ops = &clk_branch2_ops, |
2193 | }, |
2194 | }, |
2195 | }; |
2196 | |
2197 | static struct clk_branch gcc_camss_cci_ahb_clk = { |
2198 | .halt_reg = 0x5101c, |
2199 | .clkr = { |
2200 | .enable_reg = 0x5101c, |
2201 | .enable_mask = BIT(0), |
2202 | .hw.init = &(struct clk_init_data){ |
2203 | .name = "gcc_camss_cci_ahb_clk" , |
2204 | .parent_hws = (const struct clk_hw*[]){ |
2205 | &camss_ahb_clk_src.clkr.hw, |
2206 | }, |
2207 | .num_parents = 1, |
2208 | .flags = CLK_SET_RATE_PARENT, |
2209 | .ops = &clk_branch2_ops, |
2210 | }, |
2211 | }, |
2212 | }; |
2213 | |
2214 | static struct clk_branch gcc_camss_cci_clk = { |
2215 | .halt_reg = 0x51018, |
2216 | .clkr = { |
2217 | .enable_reg = 0x51018, |
2218 | .enable_mask = BIT(0), |
2219 | .hw.init = &(struct clk_init_data){ |
2220 | .name = "gcc_camss_cci_clk" , |
2221 | .parent_hws = (const struct clk_hw*[]){ |
2222 | &cci_clk_src.clkr.hw, |
2223 | }, |
2224 | .num_parents = 1, |
2225 | .flags = CLK_SET_RATE_PARENT, |
2226 | .ops = &clk_branch2_ops, |
2227 | }, |
2228 | }, |
2229 | }; |
2230 | |
2231 | static struct clk_branch gcc_camss_csi0_ahb_clk = { |
2232 | .halt_reg = 0x4e040, |
2233 | .clkr = { |
2234 | .enable_reg = 0x4e040, |
2235 | .enable_mask = BIT(0), |
2236 | .hw.init = &(struct clk_init_data){ |
2237 | .name = "gcc_camss_csi0_ahb_clk" , |
2238 | .parent_hws = (const struct clk_hw*[]){ |
2239 | &camss_ahb_clk_src.clkr.hw, |
2240 | }, |
2241 | .num_parents = 1, |
2242 | .flags = CLK_SET_RATE_PARENT, |
2243 | .ops = &clk_branch2_ops, |
2244 | }, |
2245 | }, |
2246 | }; |
2247 | |
2248 | static struct clk_branch gcc_camss_csi0_clk = { |
2249 | .halt_reg = 0x4e03c, |
2250 | .clkr = { |
2251 | .enable_reg = 0x4e03c, |
2252 | .enable_mask = BIT(0), |
2253 | .hw.init = &(struct clk_init_data){ |
2254 | .name = "gcc_camss_csi0_clk" , |
2255 | .parent_hws = (const struct clk_hw*[]){ |
2256 | &csi0_clk_src.clkr.hw, |
2257 | }, |
2258 | .num_parents = 1, |
2259 | .flags = CLK_SET_RATE_PARENT, |
2260 | .ops = &clk_branch2_ops, |
2261 | }, |
2262 | }, |
2263 | }; |
2264 | |
2265 | static struct clk_branch gcc_camss_csi0phy_clk = { |
2266 | .halt_reg = 0x4e048, |
2267 | .clkr = { |
2268 | .enable_reg = 0x4e048, |
2269 | .enable_mask = BIT(0), |
2270 | .hw.init = &(struct clk_init_data){ |
2271 | .name = "gcc_camss_csi0phy_clk" , |
2272 | .parent_hws = (const struct clk_hw*[]){ |
2273 | &csi0_clk_src.clkr.hw, |
2274 | }, |
2275 | .num_parents = 1, |
2276 | .flags = CLK_SET_RATE_PARENT, |
2277 | .ops = &clk_branch2_ops, |
2278 | }, |
2279 | }, |
2280 | }; |
2281 | |
2282 | static struct clk_branch gcc_camss_csi0pix_clk = { |
2283 | .halt_reg = 0x4e058, |
2284 | .clkr = { |
2285 | .enable_reg = 0x4e058, |
2286 | .enable_mask = BIT(0), |
2287 | .hw.init = &(struct clk_init_data){ |
2288 | .name = "gcc_camss_csi0pix_clk" , |
2289 | .parent_hws = (const struct clk_hw*[]){ |
2290 | &csi0_clk_src.clkr.hw, |
2291 | }, |
2292 | .num_parents = 1, |
2293 | .flags = CLK_SET_RATE_PARENT, |
2294 | .ops = &clk_branch2_ops, |
2295 | }, |
2296 | }, |
2297 | }; |
2298 | |
2299 | static struct clk_branch gcc_camss_csi0rdi_clk = { |
2300 | .halt_reg = 0x4e050, |
2301 | .clkr = { |
2302 | .enable_reg = 0x4e050, |
2303 | .enable_mask = BIT(0), |
2304 | .hw.init = &(struct clk_init_data){ |
2305 | .name = "gcc_camss_csi0rdi_clk" , |
2306 | .parent_hws = (const struct clk_hw*[]){ |
2307 | &csi0_clk_src.clkr.hw, |
2308 | }, |
2309 | .num_parents = 1, |
2310 | .flags = CLK_SET_RATE_PARENT, |
2311 | .ops = &clk_branch2_ops, |
2312 | }, |
2313 | }, |
2314 | }; |
2315 | |
2316 | static struct clk_branch gcc_camss_csi1_ahb_clk = { |
2317 | .halt_reg = 0x4f040, |
2318 | .clkr = { |
2319 | .enable_reg = 0x4f040, |
2320 | .enable_mask = BIT(0), |
2321 | .hw.init = &(struct clk_init_data){ |
2322 | .name = "gcc_camss_csi1_ahb_clk" , |
2323 | .parent_hws = (const struct clk_hw*[]){ |
2324 | &camss_ahb_clk_src.clkr.hw, |
2325 | }, |
2326 | .num_parents = 1, |
2327 | .flags = CLK_SET_RATE_PARENT, |
2328 | .ops = &clk_branch2_ops, |
2329 | }, |
2330 | }, |
2331 | }; |
2332 | |
2333 | static struct clk_branch gcc_camss_csi1_clk = { |
2334 | .halt_reg = 0x4f03c, |
2335 | .clkr = { |
2336 | .enable_reg = 0x4f03c, |
2337 | .enable_mask = BIT(0), |
2338 | .hw.init = &(struct clk_init_data){ |
2339 | .name = "gcc_camss_csi1_clk" , |
2340 | .parent_hws = (const struct clk_hw*[]){ |
2341 | &csi1_clk_src.clkr.hw, |
2342 | }, |
2343 | .num_parents = 1, |
2344 | .flags = CLK_SET_RATE_PARENT, |
2345 | .ops = &clk_branch2_ops, |
2346 | }, |
2347 | }, |
2348 | }; |
2349 | |
2350 | static struct clk_branch gcc_camss_csi1phy_clk = { |
2351 | .halt_reg = 0x4f048, |
2352 | .clkr = { |
2353 | .enable_reg = 0x4f048, |
2354 | .enable_mask = BIT(0), |
2355 | .hw.init = &(struct clk_init_data){ |
2356 | .name = "gcc_camss_csi1phy_clk" , |
2357 | .parent_hws = (const struct clk_hw*[]){ |
2358 | &csi1_clk_src.clkr.hw, |
2359 | }, |
2360 | .num_parents = 1, |
2361 | .flags = CLK_SET_RATE_PARENT, |
2362 | .ops = &clk_branch2_ops, |
2363 | }, |
2364 | }, |
2365 | }; |
2366 | |
2367 | static struct clk_branch gcc_camss_csi1pix_clk = { |
2368 | .halt_reg = 0x4f058, |
2369 | .clkr = { |
2370 | .enable_reg = 0x4f058, |
2371 | .enable_mask = BIT(0), |
2372 | .hw.init = &(struct clk_init_data){ |
2373 | .name = "gcc_camss_csi1pix_clk" , |
2374 | .parent_hws = (const struct clk_hw*[]){ |
2375 | &csi1_clk_src.clkr.hw, |
2376 | }, |
2377 | .num_parents = 1, |
2378 | .flags = CLK_SET_RATE_PARENT, |
2379 | .ops = &clk_branch2_ops, |
2380 | }, |
2381 | }, |
2382 | }; |
2383 | |
2384 | static struct clk_branch gcc_camss_csi1rdi_clk = { |
2385 | .halt_reg = 0x4f050, |
2386 | .clkr = { |
2387 | .enable_reg = 0x4f050, |
2388 | .enable_mask = BIT(0), |
2389 | .hw.init = &(struct clk_init_data){ |
2390 | .name = "gcc_camss_csi1rdi_clk" , |
2391 | .parent_hws = (const struct clk_hw*[]){ |
2392 | &csi1_clk_src.clkr.hw, |
2393 | }, |
2394 | .num_parents = 1, |
2395 | .flags = CLK_SET_RATE_PARENT, |
2396 | .ops = &clk_branch2_ops, |
2397 | }, |
2398 | }, |
2399 | }; |
2400 | |
2401 | static struct clk_branch gcc_camss_csi2_ahb_clk = { |
2402 | .halt_reg = 0x3c040, |
2403 | .clkr = { |
2404 | .enable_reg = 0x3c040, |
2405 | .enable_mask = BIT(0), |
2406 | .hw.init = &(struct clk_init_data){ |
2407 | .name = "gcc_camss_csi2_ahb_clk" , |
2408 | .parent_hws = (const struct clk_hw*[]){ |
2409 | &camss_ahb_clk_src.clkr.hw, |
2410 | }, |
2411 | .num_parents = 1, |
2412 | .flags = CLK_SET_RATE_PARENT, |
2413 | .ops = &clk_branch2_ops, |
2414 | }, |
2415 | }, |
2416 | }; |
2417 | |
2418 | static struct clk_branch gcc_camss_csi2_clk = { |
2419 | .halt_reg = 0x3c03c, |
2420 | .clkr = { |
2421 | .enable_reg = 0x3c03c, |
2422 | .enable_mask = BIT(0), |
2423 | .hw.init = &(struct clk_init_data){ |
2424 | .name = "gcc_camss_csi2_clk" , |
2425 | .parent_hws = (const struct clk_hw*[]){ |
2426 | &csi2_clk_src.clkr.hw, |
2427 | }, |
2428 | .num_parents = 1, |
2429 | .flags = CLK_SET_RATE_PARENT, |
2430 | .ops = &clk_branch2_ops, |
2431 | }, |
2432 | }, |
2433 | }; |
2434 | |
2435 | static struct clk_branch gcc_camss_csi2phy_clk = { |
2436 | .halt_reg = 0x3c048, |
2437 | .clkr = { |
2438 | .enable_reg = 0x3c048, |
2439 | .enable_mask = BIT(0), |
2440 | .hw.init = &(struct clk_init_data){ |
2441 | .name = "gcc_camss_csi2phy_clk" , |
2442 | .parent_hws = (const struct clk_hw*[]){ |
2443 | &csi2_clk_src.clkr.hw, |
2444 | }, |
2445 | .num_parents = 1, |
2446 | .flags = CLK_SET_RATE_PARENT, |
2447 | .ops = &clk_branch2_ops, |
2448 | }, |
2449 | }, |
2450 | }; |
2451 | |
2452 | static struct clk_branch gcc_camss_csi2pix_clk = { |
2453 | .halt_reg = 0x3c058, |
2454 | .clkr = { |
2455 | .enable_reg = 0x3c058, |
2456 | .enable_mask = BIT(0), |
2457 | .hw.init = &(struct clk_init_data){ |
2458 | .name = "gcc_camss_csi2pix_clk" , |
2459 | .parent_hws = (const struct clk_hw*[]){ |
2460 | &csi2_clk_src.clkr.hw, |
2461 | }, |
2462 | .num_parents = 1, |
2463 | .flags = CLK_SET_RATE_PARENT, |
2464 | .ops = &clk_branch2_ops, |
2465 | }, |
2466 | }, |
2467 | }; |
2468 | |
2469 | static struct clk_branch gcc_camss_csi2rdi_clk = { |
2470 | .halt_reg = 0x3c050, |
2471 | .clkr = { |
2472 | .enable_reg = 0x3c050, |
2473 | .enable_mask = BIT(0), |
2474 | .hw.init = &(struct clk_init_data){ |
2475 | .name = "gcc_camss_csi2rdi_clk" , |
2476 | .parent_hws = (const struct clk_hw*[]){ |
2477 | &csi2_clk_src.clkr.hw, |
2478 | }, |
2479 | .num_parents = 1, |
2480 | .flags = CLK_SET_RATE_PARENT, |
2481 | .ops = &clk_branch2_ops, |
2482 | }, |
2483 | }, |
2484 | }; |
2485 | |
2486 | static struct clk_branch gcc_camss_csi_vfe0_clk = { |
2487 | .halt_reg = 0x58050, |
2488 | .clkr = { |
2489 | .enable_reg = 0x58050, |
2490 | .enable_mask = BIT(0), |
2491 | .hw.init = &(struct clk_init_data){ |
2492 | .name = "gcc_camss_csi_vfe0_clk" , |
2493 | .parent_hws = (const struct clk_hw*[]){ |
2494 | &vfe0_clk_src.clkr.hw, |
2495 | }, |
2496 | .num_parents = 1, |
2497 | .flags = CLK_SET_RATE_PARENT, |
2498 | .ops = &clk_branch2_ops, |
2499 | }, |
2500 | }, |
2501 | }; |
2502 | |
2503 | static struct clk_branch gcc_camss_gp0_clk = { |
2504 | .halt_reg = 0x54018, |
2505 | .clkr = { |
2506 | .enable_reg = 0x54018, |
2507 | .enable_mask = BIT(0), |
2508 | .hw.init = &(struct clk_init_data){ |
2509 | .name = "gcc_camss_gp0_clk" , |
2510 | .parent_hws = (const struct clk_hw*[]){ |
2511 | &camss_gp0_clk_src.clkr.hw, |
2512 | }, |
2513 | .num_parents = 1, |
2514 | .flags = CLK_SET_RATE_PARENT, |
2515 | .ops = &clk_branch2_ops, |
2516 | }, |
2517 | }, |
2518 | }; |
2519 | |
2520 | static struct clk_branch gcc_camss_gp1_clk = { |
2521 | .halt_reg = 0x55018, |
2522 | .clkr = { |
2523 | .enable_reg = 0x55018, |
2524 | .enable_mask = BIT(0), |
2525 | .hw.init = &(struct clk_init_data){ |
2526 | .name = "gcc_camss_gp1_clk" , |
2527 | .parent_hws = (const struct clk_hw*[]){ |
2528 | &camss_gp1_clk_src.clkr.hw, |
2529 | }, |
2530 | .num_parents = 1, |
2531 | .flags = CLK_SET_RATE_PARENT, |
2532 | .ops = &clk_branch2_ops, |
2533 | }, |
2534 | }, |
2535 | }; |
2536 | |
2537 | static struct clk_branch gcc_camss_ispif_ahb_clk = { |
2538 | .halt_reg = 0x50004, |
2539 | .clkr = { |
2540 | .enable_reg = 0x50004, |
2541 | .enable_mask = BIT(0), |
2542 | .hw.init = &(struct clk_init_data){ |
2543 | .name = "gcc_camss_ispif_ahb_clk" , |
2544 | .parent_hws = (const struct clk_hw*[]){ |
2545 | &camss_ahb_clk_src.clkr.hw, |
2546 | }, |
2547 | .num_parents = 1, |
2548 | .flags = CLK_SET_RATE_PARENT, |
2549 | .ops = &clk_branch2_ops, |
2550 | }, |
2551 | }, |
2552 | }; |
2553 | |
2554 | static struct clk_branch gcc_camss_jpeg0_clk = { |
2555 | .halt_reg = 0x57020, |
2556 | .clkr = { |
2557 | .enable_reg = 0x57020, |
2558 | .enable_mask = BIT(0), |
2559 | .hw.init = &(struct clk_init_data){ |
2560 | .name = "gcc_camss_jpeg0_clk" , |
2561 | .parent_hws = (const struct clk_hw*[]){ |
2562 | &jpeg0_clk_src.clkr.hw, |
2563 | }, |
2564 | .num_parents = 1, |
2565 | .flags = CLK_SET_RATE_PARENT, |
2566 | .ops = &clk_branch2_ops, |
2567 | }, |
2568 | }, |
2569 | }; |
2570 | |
2571 | static struct clk_branch gcc_camss_jpeg_ahb_clk = { |
2572 | .halt_reg = 0x57024, |
2573 | .clkr = { |
2574 | .enable_reg = 0x57024, |
2575 | .enable_mask = BIT(0), |
2576 | .hw.init = &(struct clk_init_data){ |
2577 | .name = "gcc_camss_jpeg_ahb_clk" , |
2578 | .parent_hws = (const struct clk_hw*[]){ |
2579 | &camss_ahb_clk_src.clkr.hw, |
2580 | }, |
2581 | .num_parents = 1, |
2582 | .flags = CLK_SET_RATE_PARENT, |
2583 | .ops = &clk_branch2_ops, |
2584 | }, |
2585 | }, |
2586 | }; |
2587 | |
2588 | static struct clk_branch gcc_camss_jpeg_axi_clk = { |
2589 | .halt_reg = 0x57028, |
2590 | .clkr = { |
2591 | .enable_reg = 0x57028, |
2592 | .enable_mask = BIT(0), |
2593 | .hw.init = &(struct clk_init_data){ |
2594 | .name = "gcc_camss_jpeg_axi_clk" , |
2595 | .parent_hws = (const struct clk_hw*[]){ |
2596 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
2597 | }, |
2598 | .num_parents = 1, |
2599 | .flags = CLK_SET_RATE_PARENT, |
2600 | .ops = &clk_branch2_ops, |
2601 | }, |
2602 | }, |
2603 | }; |
2604 | |
2605 | static struct clk_branch gcc_camss_mclk0_clk = { |
2606 | .halt_reg = 0x52018, |
2607 | .clkr = { |
2608 | .enable_reg = 0x52018, |
2609 | .enable_mask = BIT(0), |
2610 | .hw.init = &(struct clk_init_data){ |
2611 | .name = "gcc_camss_mclk0_clk" , |
2612 | .parent_hws = (const struct clk_hw*[]){ |
2613 | &mclk0_clk_src.clkr.hw, |
2614 | }, |
2615 | .num_parents = 1, |
2616 | .flags = CLK_SET_RATE_PARENT, |
2617 | .ops = &clk_branch2_ops, |
2618 | }, |
2619 | }, |
2620 | }; |
2621 | |
2622 | static struct clk_branch gcc_camss_mclk1_clk = { |
2623 | .halt_reg = 0x53018, |
2624 | .clkr = { |
2625 | .enable_reg = 0x53018, |
2626 | .enable_mask = BIT(0), |
2627 | .hw.init = &(struct clk_init_data){ |
2628 | .name = "gcc_camss_mclk1_clk" , |
2629 | .parent_hws = (const struct clk_hw*[]){ |
2630 | &mclk1_clk_src.clkr.hw, |
2631 | }, |
2632 | .num_parents = 1, |
2633 | .flags = CLK_SET_RATE_PARENT, |
2634 | .ops = &clk_branch2_ops, |
2635 | }, |
2636 | }, |
2637 | }; |
2638 | |
2639 | static struct clk_branch gcc_camss_micro_ahb_clk = { |
2640 | .halt_reg = 0x5600c, |
2641 | .clkr = { |
2642 | .enable_reg = 0x5600c, |
2643 | .enable_mask = BIT(0), |
2644 | .hw.init = &(struct clk_init_data){ |
2645 | .name = "gcc_camss_micro_ahb_clk" , |
2646 | .parent_hws = (const struct clk_hw*[]){ |
2647 | &camss_ahb_clk_src.clkr.hw, |
2648 | }, |
2649 | .num_parents = 1, |
2650 | .flags = CLK_SET_RATE_PARENT, |
2651 | .ops = &clk_branch2_ops, |
2652 | }, |
2653 | }, |
2654 | }; |
2655 | |
2656 | static struct clk_branch gcc_camss_csi0phytimer_clk = { |
2657 | .halt_reg = 0x4e01c, |
2658 | .clkr = { |
2659 | .enable_reg = 0x4e01c, |
2660 | .enable_mask = BIT(0), |
2661 | .hw.init = &(struct clk_init_data){ |
2662 | .name = "gcc_camss_csi0phytimer_clk" , |
2663 | .parent_hws = (const struct clk_hw*[]){ |
2664 | &csi0phytimer_clk_src.clkr.hw, |
2665 | }, |
2666 | .num_parents = 1, |
2667 | .flags = CLK_SET_RATE_PARENT, |
2668 | .ops = &clk_branch2_ops, |
2669 | }, |
2670 | }, |
2671 | }; |
2672 | |
2673 | static struct clk_branch gcc_camss_csi1phytimer_clk = { |
2674 | .halt_reg = 0x4f01c, |
2675 | .clkr = { |
2676 | .enable_reg = 0x4f01c, |
2677 | .enable_mask = BIT(0), |
2678 | .hw.init = &(struct clk_init_data){ |
2679 | .name = "gcc_camss_csi1phytimer_clk" , |
2680 | .parent_hws = (const struct clk_hw*[]){ |
2681 | &csi1phytimer_clk_src.clkr.hw, |
2682 | }, |
2683 | .num_parents = 1, |
2684 | .flags = CLK_SET_RATE_PARENT, |
2685 | .ops = &clk_branch2_ops, |
2686 | }, |
2687 | }, |
2688 | }; |
2689 | |
2690 | static struct clk_branch gcc_camss_ahb_clk = { |
2691 | .halt_reg = 0x5a014, |
2692 | .clkr = { |
2693 | .enable_reg = 0x5a014, |
2694 | .enable_mask = BIT(0), |
2695 | .hw.init = &(struct clk_init_data){ |
2696 | .name = "gcc_camss_ahb_clk" , |
2697 | .parent_hws = (const struct clk_hw*[]){ |
2698 | &camss_ahb_clk_src.clkr.hw, |
2699 | }, |
2700 | .num_parents = 1, |
2701 | .flags = CLK_SET_RATE_PARENT, |
2702 | .ops = &clk_branch2_ops, |
2703 | }, |
2704 | }, |
2705 | }; |
2706 | |
2707 | static struct clk_branch gcc_camss_top_ahb_clk = { |
2708 | .halt_reg = 0x56004, |
2709 | .clkr = { |
2710 | .enable_reg = 0x56004, |
2711 | .enable_mask = BIT(0), |
2712 | .hw.init = &(struct clk_init_data){ |
2713 | .name = "gcc_camss_top_ahb_clk" , |
2714 | .parent_hws = (const struct clk_hw*[]){ |
2715 | &pcnoc_bfdcd_clk_src.clkr.hw, |
2716 | }, |
2717 | .num_parents = 1, |
2718 | .flags = CLK_SET_RATE_PARENT, |
2719 | .ops = &clk_branch2_ops, |
2720 | }, |
2721 | }, |
2722 | }; |
2723 | |
2724 | static struct clk_branch gcc_camss_cpp_ahb_clk = { |
2725 | .halt_reg = 0x58040, |
2726 | .clkr = { |
2727 | .enable_reg = 0x58040, |
2728 | .enable_mask = BIT(0), |
2729 | .hw.init = &(struct clk_init_data){ |
2730 | .name = "gcc_camss_cpp_ahb_clk" , |
2731 | .parent_hws = (const struct clk_hw*[]){ |
2732 | &camss_ahb_clk_src.clkr.hw, |
2733 | }, |
2734 | .num_parents = 1, |
2735 | .flags = CLK_SET_RATE_PARENT, |
2736 | .ops = &clk_branch2_ops, |
2737 | }, |
2738 | }, |
2739 | }; |
2740 | |
2741 | static struct clk_branch gcc_camss_cpp_clk = { |
2742 | .halt_reg = 0x5803c, |
2743 | .clkr = { |
2744 | .enable_reg = 0x5803c, |
2745 | .enable_mask = BIT(0), |
2746 | .hw.init = &(struct clk_init_data){ |
2747 | .name = "gcc_camss_cpp_clk" , |
2748 | .parent_hws = (const struct clk_hw*[]){ |
2749 | &cpp_clk_src.clkr.hw, |
2750 | }, |
2751 | .num_parents = 1, |
2752 | .flags = CLK_SET_RATE_PARENT, |
2753 | .ops = &clk_branch2_ops, |
2754 | }, |
2755 | }, |
2756 | }; |
2757 | |
2758 | static struct clk_branch gcc_camss_vfe0_clk = { |
2759 | .halt_reg = 0x58038, |
2760 | .clkr = { |
2761 | .enable_reg = 0x58038, |
2762 | .enable_mask = BIT(0), |
2763 | .hw.init = &(struct clk_init_data){ |
2764 | .name = "gcc_camss_vfe0_clk" , |
2765 | .parent_hws = (const struct clk_hw*[]){ |
2766 | &vfe0_clk_src.clkr.hw, |
2767 | }, |
2768 | .num_parents = 1, |
2769 | .flags = CLK_SET_RATE_PARENT, |
2770 | .ops = &clk_branch2_ops, |
2771 | }, |
2772 | }, |
2773 | }; |
2774 | |
2775 | static struct clk_branch gcc_camss_vfe_ahb_clk = { |
2776 | .halt_reg = 0x58044, |
2777 | .clkr = { |
2778 | .enable_reg = 0x58044, |
2779 | .enable_mask = BIT(0), |
2780 | .hw.init = &(struct clk_init_data){ |
2781 | .name = "gcc_camss_vfe_ahb_clk" , |
2782 | .parent_hws = (const struct clk_hw*[]){ |
2783 | &camss_ahb_clk_src.clkr.hw, |
2784 | }, |
2785 | .num_parents = 1, |
2786 | .flags = CLK_SET_RATE_PARENT, |
2787 | .ops = &clk_branch2_ops, |
2788 | }, |
2789 | }, |
2790 | }; |
2791 | |
2792 | static struct clk_branch gcc_camss_vfe_axi_clk = { |
2793 | .halt_reg = 0x58048, |
2794 | .clkr = { |
2795 | .enable_reg = 0x58048, |
2796 | .enable_mask = BIT(0), |
2797 | .hw.init = &(struct clk_init_data){ |
2798 | .name = "gcc_camss_vfe_axi_clk" , |
2799 | .parent_hws = (const struct clk_hw*[]){ |
2800 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
2801 | }, |
2802 | .num_parents = 1, |
2803 | .flags = CLK_SET_RATE_PARENT, |
2804 | .ops = &clk_branch2_ops, |
2805 | }, |
2806 | }, |
2807 | }; |
2808 | |
2809 | static struct clk_branch gcc_crypto_ahb_clk = { |
2810 | .halt_reg = 0x16024, |
2811 | .halt_check = BRANCH_HALT_VOTED, |
2812 | .clkr = { |
2813 | .enable_reg = 0x45004, |
2814 | .enable_mask = BIT(0), |
2815 | .hw.init = &(struct clk_init_data){ |
2816 | .name = "gcc_crypto_ahb_clk" , |
2817 | .parent_hws = (const struct clk_hw*[]){ |
2818 | &pcnoc_bfdcd_clk_src.clkr.hw, |
2819 | }, |
2820 | .num_parents = 1, |
2821 | .flags = CLK_SET_RATE_PARENT, |
2822 | .ops = &clk_branch2_ops, |
2823 | }, |
2824 | }, |
2825 | }; |
2826 | |
2827 | static struct clk_branch gcc_crypto_axi_clk = { |
2828 | .halt_reg = 0x16020, |
2829 | .halt_check = BRANCH_HALT_VOTED, |
2830 | .clkr = { |
2831 | .enable_reg = 0x45004, |
2832 | .enable_mask = BIT(1), |
2833 | .hw.init = &(struct clk_init_data){ |
2834 | .name = "gcc_crypto_axi_clk" , |
2835 | .parent_hws = (const struct clk_hw*[]){ |
2836 | &pcnoc_bfdcd_clk_src.clkr.hw, |
2837 | }, |
2838 | .num_parents = 1, |
2839 | .flags = CLK_SET_RATE_PARENT, |
2840 | .ops = &clk_branch2_ops, |
2841 | }, |
2842 | }, |
2843 | }; |
2844 | |
2845 | static struct clk_branch gcc_crypto_clk = { |
2846 | .halt_reg = 0x1601c, |
2847 | .halt_check = BRANCH_HALT_VOTED, |
2848 | .clkr = { |
2849 | .enable_reg = 0x45004, |
2850 | .enable_mask = BIT(2), |
2851 | .hw.init = &(struct clk_init_data){ |
2852 | .name = "gcc_crypto_clk" , |
2853 | .parent_hws = (const struct clk_hw*[]){ |
2854 | &crypto_clk_src.clkr.hw, |
2855 | }, |
2856 | .num_parents = 1, |
2857 | .flags = CLK_SET_RATE_PARENT, |
2858 | .ops = &clk_branch2_ops, |
2859 | }, |
2860 | }, |
2861 | }; |
2862 | |
2863 | static struct clk_branch gcc_oxili_gmem_clk = { |
2864 | .halt_reg = 0x59024, |
2865 | .clkr = { |
2866 | .enable_reg = 0x59024, |
2867 | .enable_mask = BIT(0), |
2868 | .hw.init = &(struct clk_init_data){ |
2869 | .name = "gcc_oxili_gmem_clk" , |
2870 | .parent_hws = (const struct clk_hw*[]){ |
2871 | &gfx3d_clk_src.clkr.hw, |
2872 | }, |
2873 | .num_parents = 1, |
2874 | .flags = CLK_SET_RATE_PARENT, |
2875 | .ops = &clk_branch2_ops, |
2876 | }, |
2877 | }, |
2878 | }; |
2879 | |
2880 | static struct clk_branch gcc_gp1_clk = { |
2881 | .halt_reg = 0x08000, |
2882 | .clkr = { |
2883 | .enable_reg = 0x08000, |
2884 | .enable_mask = BIT(0), |
2885 | .hw.init = &(struct clk_init_data){ |
2886 | .name = "gcc_gp1_clk" , |
2887 | .parent_hws = (const struct clk_hw*[]){ |
2888 | &gp1_clk_src.clkr.hw, |
2889 | }, |
2890 | .num_parents = 1, |
2891 | .flags = CLK_SET_RATE_PARENT, |
2892 | .ops = &clk_branch2_ops, |
2893 | }, |
2894 | }, |
2895 | }; |
2896 | |
2897 | static struct clk_branch gcc_gp2_clk = { |
2898 | .halt_reg = 0x09000, |
2899 | .clkr = { |
2900 | .enable_reg = 0x09000, |
2901 | .enable_mask = BIT(0), |
2902 | .hw.init = &(struct clk_init_data){ |
2903 | .name = "gcc_gp2_clk" , |
2904 | .parent_hws = (const struct clk_hw*[]){ |
2905 | &gp2_clk_src.clkr.hw, |
2906 | }, |
2907 | .num_parents = 1, |
2908 | .flags = CLK_SET_RATE_PARENT, |
2909 | .ops = &clk_branch2_ops, |
2910 | }, |
2911 | }, |
2912 | }; |
2913 | |
2914 | static struct clk_branch gcc_gp3_clk = { |
2915 | .halt_reg = 0x0a000, |
2916 | .clkr = { |
2917 | .enable_reg = 0x0a000, |
2918 | .enable_mask = BIT(0), |
2919 | .hw.init = &(struct clk_init_data){ |
2920 | .name = "gcc_gp3_clk" , |
2921 | .parent_hws = (const struct clk_hw*[]){ |
2922 | &gp3_clk_src.clkr.hw, |
2923 | }, |
2924 | .num_parents = 1, |
2925 | .flags = CLK_SET_RATE_PARENT, |
2926 | .ops = &clk_branch2_ops, |
2927 | }, |
2928 | }, |
2929 | }; |
2930 | |
2931 | static struct clk_branch gcc_mdss_ahb_clk = { |
2932 | .halt_reg = 0x4d07c, |
2933 | .clkr = { |
2934 | .enable_reg = 0x4d07c, |
2935 | .enable_mask = BIT(0), |
2936 | .hw.init = &(struct clk_init_data){ |
2937 | .name = "gcc_mdss_ahb_clk" , |
2938 | .parent_hws = (const struct clk_hw*[]){ |
2939 | &pcnoc_bfdcd_clk_src.clkr.hw, |
2940 | }, |
2941 | .num_parents = 1, |
2942 | .flags = CLK_SET_RATE_PARENT, |
2943 | .ops = &clk_branch2_ops, |
2944 | }, |
2945 | }, |
2946 | }; |
2947 | |
2948 | static struct clk_branch gcc_mdss_axi_clk = { |
2949 | .halt_reg = 0x4d080, |
2950 | .clkr = { |
2951 | .enable_reg = 0x4d080, |
2952 | .enable_mask = BIT(0), |
2953 | .hw.init = &(struct clk_init_data){ |
2954 | .name = "gcc_mdss_axi_clk" , |
2955 | .parent_hws = (const struct clk_hw*[]){ |
2956 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
2957 | }, |
2958 | .num_parents = 1, |
2959 | .flags = CLK_SET_RATE_PARENT, |
2960 | .ops = &clk_branch2_ops, |
2961 | }, |
2962 | }, |
2963 | }; |
2964 | |
2965 | static struct clk_branch gcc_mdss_byte0_clk = { |
2966 | .halt_reg = 0x4d094, |
2967 | .clkr = { |
2968 | .enable_reg = 0x4d094, |
2969 | .enable_mask = BIT(0), |
2970 | .hw.init = &(struct clk_init_data){ |
2971 | .name = "gcc_mdss_byte0_clk" , |
2972 | .parent_hws = (const struct clk_hw*[]){ |
2973 | &byte0_clk_src.clkr.hw, |
2974 | }, |
2975 | .num_parents = 1, |
2976 | .flags = CLK_SET_RATE_PARENT, |
2977 | .ops = &clk_branch2_ops, |
2978 | }, |
2979 | }, |
2980 | }; |
2981 | |
2982 | static struct clk_branch gcc_mdss_byte1_clk = { |
2983 | .halt_reg = 0x4d0a0, |
2984 | .clkr = { |
2985 | .enable_reg = 0x4d0a0, |
2986 | .enable_mask = BIT(0), |
2987 | .hw.init = &(struct clk_init_data){ |
2988 | .name = "gcc_mdss_byte1_clk" , |
2989 | .parent_hws = (const struct clk_hw*[]){ |
2990 | &byte1_clk_src.clkr.hw, |
2991 | }, |
2992 | .num_parents = 1, |
2993 | .flags = CLK_SET_RATE_PARENT, |
2994 | .ops = &clk_branch2_ops, |
2995 | }, |
2996 | }, |
2997 | }; |
2998 | |
2999 | static struct clk_branch gcc_mdss_esc0_clk = { |
3000 | .halt_reg = 0x4d098, |
3001 | .clkr = { |
3002 | .enable_reg = 0x4d098, |
3003 | .enable_mask = BIT(0), |
3004 | .hw.init = &(struct clk_init_data){ |
3005 | .name = "gcc_mdss_esc0_clk" , |
3006 | .parent_hws = (const struct clk_hw*[]){ |
3007 | &esc0_clk_src.clkr.hw, |
3008 | }, |
3009 | .num_parents = 1, |
3010 | .flags = CLK_SET_RATE_PARENT, |
3011 | .ops = &clk_branch2_ops, |
3012 | }, |
3013 | }, |
3014 | }; |
3015 | |
3016 | static struct clk_branch gcc_mdss_esc1_clk = { |
3017 | .halt_reg = 0x4d09c, |
3018 | .clkr = { |
3019 | .enable_reg = 0x4d09c, |
3020 | .enable_mask = BIT(0), |
3021 | .hw.init = &(struct clk_init_data){ |
3022 | .name = "gcc_mdss_esc1_clk" , |
3023 | .parent_hws = (const struct clk_hw*[]){ |
3024 | &esc1_clk_src.clkr.hw, |
3025 | }, |
3026 | .num_parents = 1, |
3027 | .flags = CLK_SET_RATE_PARENT, |
3028 | .ops = &clk_branch2_ops, |
3029 | }, |
3030 | }, |
3031 | }; |
3032 | |
3033 | static struct clk_branch gcc_mdss_mdp_clk = { |
3034 | .halt_reg = 0x4D088, |
3035 | .clkr = { |
3036 | .enable_reg = 0x4D088, |
3037 | .enable_mask = BIT(0), |
3038 | .hw.init = &(struct clk_init_data){ |
3039 | .name = "gcc_mdss_mdp_clk" , |
3040 | .parent_hws = (const struct clk_hw*[]){ |
3041 | &mdp_clk_src.clkr.hw, |
3042 | }, |
3043 | .num_parents = 1, |
3044 | .flags = CLK_SET_RATE_PARENT, |
3045 | .ops = &clk_branch2_ops, |
3046 | }, |
3047 | }, |
3048 | }; |
3049 | |
3050 | static struct clk_branch gcc_mdss_pclk0_clk = { |
3051 | .halt_reg = 0x4d084, |
3052 | .clkr = { |
3053 | .enable_reg = 0x4d084, |
3054 | .enable_mask = BIT(0), |
3055 | .hw.init = &(struct clk_init_data){ |
3056 | .name = "gcc_mdss_pclk0_clk" , |
3057 | .parent_hws = (const struct clk_hw*[]){ |
3058 | &pclk0_clk_src.clkr.hw, |
3059 | }, |
3060 | .num_parents = 1, |
3061 | .flags = CLK_SET_RATE_PARENT, |
3062 | .ops = &clk_branch2_ops, |
3063 | }, |
3064 | }, |
3065 | }; |
3066 | |
3067 | static struct clk_branch gcc_mdss_pclk1_clk = { |
3068 | .halt_reg = 0x4d0a4, |
3069 | .clkr = { |
3070 | .enable_reg = 0x4d0a4, |
3071 | .enable_mask = BIT(0), |
3072 | .hw.init = &(struct clk_init_data){ |
3073 | .name = "gcc_mdss_pclk1_clk" , |
3074 | .parent_hws = (const struct clk_hw*[]){ |
3075 | &pclk1_clk_src.clkr.hw, |
3076 | }, |
3077 | .num_parents = 1, |
3078 | .flags = CLK_SET_RATE_PARENT, |
3079 | .ops = &clk_branch2_ops, |
3080 | }, |
3081 | }, |
3082 | }; |
3083 | |
3084 | static struct clk_branch gcc_mdss_vsync_clk = { |
3085 | .halt_reg = 0x4d090, |
3086 | .clkr = { |
3087 | .enable_reg = 0x4d090, |
3088 | .enable_mask = BIT(0), |
3089 | .hw.init = &(struct clk_init_data){ |
3090 | .name = "gcc_mdss_vsync_clk" , |
3091 | .parent_hws = (const struct clk_hw*[]){ |
3092 | &vsync_clk_src.clkr.hw, |
3093 | }, |
3094 | .num_parents = 1, |
3095 | .flags = CLK_SET_RATE_PARENT, |
3096 | .ops = &clk_branch2_ops, |
3097 | }, |
3098 | }, |
3099 | }; |
3100 | |
3101 | static struct clk_branch gcc_mss_cfg_ahb_clk = { |
3102 | .halt_reg = 0x49000, |
3103 | .clkr = { |
3104 | .enable_reg = 0x49000, |
3105 | .enable_mask = BIT(0), |
3106 | .hw.init = &(struct clk_init_data){ |
3107 | .name = "gcc_mss_cfg_ahb_clk" , |
3108 | .parent_hws = (const struct clk_hw*[]){ |
3109 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3110 | }, |
3111 | .num_parents = 1, |
3112 | .flags = CLK_SET_RATE_PARENT, |
3113 | .ops = &clk_branch2_ops, |
3114 | }, |
3115 | }, |
3116 | }; |
3117 | |
3118 | static struct clk_branch gcc_mss_q6_bimc_axi_clk = { |
3119 | .halt_reg = 0x49004, |
3120 | .clkr = { |
3121 | .enable_reg = 0x49004, |
3122 | .enable_mask = BIT(0), |
3123 | .hw.init = &(struct clk_init_data){ |
3124 | .name = "gcc_mss_q6_bimc_axi_clk" , |
3125 | .parent_hws = (const struct clk_hw*[]){ |
3126 | &bimc_ddr_clk_src.clkr.hw, |
3127 | }, |
3128 | .num_parents = 1, |
3129 | .flags = CLK_SET_RATE_PARENT, |
3130 | .ops = &clk_branch2_ops, |
3131 | }, |
3132 | }, |
3133 | }; |
3134 | |
3135 | static struct clk_branch gcc_oxili_ahb_clk = { |
3136 | .halt_reg = 0x59028, |
3137 | .clkr = { |
3138 | .enable_reg = 0x59028, |
3139 | .enable_mask = BIT(0), |
3140 | .hw.init = &(struct clk_init_data){ |
3141 | .name = "gcc_oxili_ahb_clk" , |
3142 | .parent_hws = (const struct clk_hw*[]){ |
3143 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3144 | }, |
3145 | .num_parents = 1, |
3146 | .flags = CLK_SET_RATE_PARENT, |
3147 | .ops = &clk_branch2_ops, |
3148 | }, |
3149 | }, |
3150 | }; |
3151 | |
3152 | static struct clk_branch gcc_oxili_gfx3d_clk = { |
3153 | .halt_reg = 0x59020, |
3154 | .clkr = { |
3155 | .enable_reg = 0x59020, |
3156 | .enable_mask = BIT(0), |
3157 | .hw.init = &(struct clk_init_data){ |
3158 | .name = "gcc_oxili_gfx3d_clk" , |
3159 | .parent_hws = (const struct clk_hw*[]){ |
3160 | &gfx3d_clk_src.clkr.hw, |
3161 | }, |
3162 | .num_parents = 1, |
3163 | .flags = CLK_SET_RATE_PARENT, |
3164 | .ops = &clk_branch2_ops, |
3165 | }, |
3166 | }, |
3167 | }; |
3168 | |
3169 | static struct clk_branch gcc_pdm2_clk = { |
3170 | .halt_reg = 0x4400c, |
3171 | .clkr = { |
3172 | .enable_reg = 0x4400c, |
3173 | .enable_mask = BIT(0), |
3174 | .hw.init = &(struct clk_init_data){ |
3175 | .name = "gcc_pdm2_clk" , |
3176 | .parent_hws = (const struct clk_hw*[]){ |
3177 | &pdm2_clk_src.clkr.hw, |
3178 | }, |
3179 | .num_parents = 1, |
3180 | .flags = CLK_SET_RATE_PARENT, |
3181 | .ops = &clk_branch2_ops, |
3182 | }, |
3183 | }, |
3184 | }; |
3185 | |
3186 | static struct clk_branch gcc_pdm_ahb_clk = { |
3187 | .halt_reg = 0x44004, |
3188 | .clkr = { |
3189 | .enable_reg = 0x44004, |
3190 | .enable_mask = BIT(0), |
3191 | .hw.init = &(struct clk_init_data){ |
3192 | .name = "gcc_pdm_ahb_clk" , |
3193 | .parent_hws = (const struct clk_hw*[]){ |
3194 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3195 | }, |
3196 | .num_parents = 1, |
3197 | .flags = CLK_SET_RATE_PARENT, |
3198 | .ops = &clk_branch2_ops, |
3199 | }, |
3200 | }, |
3201 | }; |
3202 | |
3203 | static struct clk_branch gcc_prng_ahb_clk = { |
3204 | .halt_reg = 0x13004, |
3205 | .halt_check = BRANCH_HALT_VOTED, |
3206 | .clkr = { |
3207 | .enable_reg = 0x45004, |
3208 | .enable_mask = BIT(8), |
3209 | .hw.init = &(struct clk_init_data){ |
3210 | .name = "gcc_prng_ahb_clk" , |
3211 | .parent_hws = (const struct clk_hw*[]){ |
3212 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3213 | }, |
3214 | .num_parents = 1, |
3215 | .ops = &clk_branch2_ops, |
3216 | }, |
3217 | }, |
3218 | }; |
3219 | |
3220 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
3221 | .halt_reg = 0x4201c, |
3222 | .clkr = { |
3223 | .enable_reg = 0x4201c, |
3224 | .enable_mask = BIT(0), |
3225 | .hw.init = &(struct clk_init_data){ |
3226 | .name = "gcc_sdcc1_ahb_clk" , |
3227 | .parent_hws = (const struct clk_hw*[]){ |
3228 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3229 | }, |
3230 | .num_parents = 1, |
3231 | .flags = CLK_SET_RATE_PARENT, |
3232 | .ops = &clk_branch2_ops, |
3233 | }, |
3234 | }, |
3235 | }; |
3236 | |
3237 | static struct clk_branch gcc_sdcc1_apps_clk = { |
3238 | .halt_reg = 0x42018, |
3239 | .clkr = { |
3240 | .enable_reg = 0x42018, |
3241 | .enable_mask = BIT(0), |
3242 | .hw.init = &(struct clk_init_data){ |
3243 | .name = "gcc_sdcc1_apps_clk" , |
3244 | .parent_hws = (const struct clk_hw*[]){ |
3245 | &sdcc1_apps_clk_src.clkr.hw, |
3246 | }, |
3247 | .num_parents = 1, |
3248 | .flags = CLK_SET_RATE_PARENT, |
3249 | .ops = &clk_branch2_ops, |
3250 | }, |
3251 | }, |
3252 | }; |
3253 | |
3254 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
3255 | .halt_reg = 0x4301c, |
3256 | .clkr = { |
3257 | .enable_reg = 0x4301c, |
3258 | .enable_mask = BIT(0), |
3259 | .hw.init = &(struct clk_init_data){ |
3260 | .name = "gcc_sdcc2_ahb_clk" , |
3261 | .parent_hws = (const struct clk_hw*[]){ |
3262 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3263 | }, |
3264 | .num_parents = 1, |
3265 | .flags = CLK_SET_RATE_PARENT, |
3266 | .ops = &clk_branch2_ops, |
3267 | }, |
3268 | }, |
3269 | }; |
3270 | |
3271 | static struct clk_branch gcc_sdcc2_apps_clk = { |
3272 | .halt_reg = 0x43018, |
3273 | .clkr = { |
3274 | .enable_reg = 0x43018, |
3275 | .enable_mask = BIT(0), |
3276 | .hw.init = &(struct clk_init_data){ |
3277 | .name = "gcc_sdcc2_apps_clk" , |
3278 | .parent_hws = (const struct clk_hw*[]){ |
3279 | &sdcc2_apps_clk_src.clkr.hw, |
3280 | }, |
3281 | .num_parents = 1, |
3282 | .flags = CLK_SET_RATE_PARENT, |
3283 | .ops = &clk_branch2_ops, |
3284 | }, |
3285 | }, |
3286 | }; |
3287 | |
3288 | static struct clk_branch gcc_apss_tcu_clk = { |
3289 | .halt_reg = 0x12018, |
3290 | .halt_check = BRANCH_HALT_VOTED, |
3291 | .clkr = { |
3292 | .enable_reg = 0x4500c, |
3293 | .enable_mask = BIT(1), |
3294 | .hw.init = &(struct clk_init_data){ |
3295 | .name = "gcc_apss_tcu_clk" , |
3296 | .parent_hws = (const struct clk_hw*[]){ |
3297 | &bimc_ddr_clk_src.clkr.hw, |
3298 | }, |
3299 | .num_parents = 1, |
3300 | .ops = &clk_branch2_ops, |
3301 | }, |
3302 | }, |
3303 | }; |
3304 | |
3305 | static struct clk_branch gcc_gfx_tcu_clk = { |
3306 | .halt_reg = 0x12020, |
3307 | .halt_check = BRANCH_HALT_VOTED, |
3308 | .clkr = { |
3309 | .enable_reg = 0x4500c, |
3310 | .enable_mask = BIT(2), |
3311 | .hw.init = &(struct clk_init_data){ |
3312 | .name = "gcc_gfx_tcu_clk" , |
3313 | .parent_hws = (const struct clk_hw*[]){ |
3314 | &bimc_ddr_clk_src.clkr.hw, |
3315 | }, |
3316 | .num_parents = 1, |
3317 | .ops = &clk_branch2_ops, |
3318 | }, |
3319 | }, |
3320 | }; |
3321 | |
3322 | static struct clk_branch gcc_gfx_tbu_clk = { |
3323 | .halt_reg = 0x12010, |
3324 | .halt_check = BRANCH_HALT_VOTED, |
3325 | .clkr = { |
3326 | .enable_reg = 0x4500c, |
3327 | .enable_mask = BIT(3), |
3328 | .hw.init = &(struct clk_init_data){ |
3329 | .name = "gcc_gfx_tbu_clk" , |
3330 | .parent_hws = (const struct clk_hw*[]){ |
3331 | &bimc_ddr_clk_src.clkr.hw, |
3332 | }, |
3333 | .num_parents = 1, |
3334 | .ops = &clk_branch2_ops, |
3335 | }, |
3336 | }, |
3337 | }; |
3338 | |
3339 | static struct clk_branch gcc_mdp_tbu_clk = { |
3340 | .halt_reg = 0x1201c, |
3341 | .halt_check = BRANCH_HALT_VOTED, |
3342 | .clkr = { |
3343 | .enable_reg = 0x4500c, |
3344 | .enable_mask = BIT(4), |
3345 | .hw.init = &(struct clk_init_data){ |
3346 | .name = "gcc_mdp_tbu_clk" , |
3347 | .parent_hws = (const struct clk_hw*[]){ |
3348 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
3349 | }, |
3350 | .num_parents = 1, |
3351 | .flags = CLK_SET_RATE_PARENT, |
3352 | .ops = &clk_branch2_ops, |
3353 | }, |
3354 | }, |
3355 | }; |
3356 | |
3357 | static struct clk_branch gcc_venus_tbu_clk = { |
3358 | .halt_reg = 0x12014, |
3359 | .halt_check = BRANCH_HALT_VOTED, |
3360 | .clkr = { |
3361 | .enable_reg = 0x4500c, |
3362 | .enable_mask = BIT(5), |
3363 | .hw.init = &(struct clk_init_data){ |
3364 | .name = "gcc_venus_tbu_clk" , |
3365 | .parent_hws = (const struct clk_hw*[]){ |
3366 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
3367 | }, |
3368 | .num_parents = 1, |
3369 | .flags = CLK_SET_RATE_PARENT, |
3370 | .ops = &clk_branch2_ops, |
3371 | }, |
3372 | }, |
3373 | }; |
3374 | |
3375 | static struct clk_branch gcc_vfe_tbu_clk = { |
3376 | .halt_reg = 0x1203c, |
3377 | .halt_check = BRANCH_HALT_VOTED, |
3378 | .clkr = { |
3379 | .enable_reg = 0x4500c, |
3380 | .enable_mask = BIT(9), |
3381 | .hw.init = &(struct clk_init_data){ |
3382 | .name = "gcc_vfe_tbu_clk" , |
3383 | .parent_hws = (const struct clk_hw*[]){ |
3384 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
3385 | }, |
3386 | .num_parents = 1, |
3387 | .flags = CLK_SET_RATE_PARENT, |
3388 | .ops = &clk_branch2_ops, |
3389 | }, |
3390 | }, |
3391 | }; |
3392 | |
3393 | static struct clk_branch gcc_jpeg_tbu_clk = { |
3394 | .halt_reg = 0x12034, |
3395 | .halt_check = BRANCH_HALT_VOTED, |
3396 | .clkr = { |
3397 | .enable_reg = 0x4500c, |
3398 | .enable_mask = BIT(10), |
3399 | .hw.init = &(struct clk_init_data){ |
3400 | .name = "gcc_jpeg_tbu_clk" , |
3401 | .parent_hws = (const struct clk_hw*[]){ |
3402 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
3403 | }, |
3404 | .num_parents = 1, |
3405 | .flags = CLK_SET_RATE_PARENT, |
3406 | .ops = &clk_branch2_ops, |
3407 | }, |
3408 | }, |
3409 | }; |
3410 | |
3411 | static struct clk_branch gcc_smmu_cfg_clk = { |
3412 | .halt_reg = 0x12038, |
3413 | .halt_check = BRANCH_HALT_VOTED, |
3414 | .clkr = { |
3415 | .enable_reg = 0x4500c, |
3416 | .enable_mask = BIT(12), |
3417 | .hw.init = &(struct clk_init_data){ |
3418 | .name = "gcc_smmu_cfg_clk" , |
3419 | .parent_hws = (const struct clk_hw*[]){ |
3420 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3421 | }, |
3422 | .num_parents = 1, |
3423 | .flags = CLK_SET_RATE_PARENT, |
3424 | .ops = &clk_branch2_ops, |
3425 | }, |
3426 | }, |
3427 | }; |
3428 | |
3429 | static struct clk_branch gcc_gtcu_ahb_clk = { |
3430 | .halt_reg = 0x12044, |
3431 | .halt_check = BRANCH_HALT_VOTED, |
3432 | .clkr = { |
3433 | .enable_reg = 0x4500c, |
3434 | .enable_mask = BIT(13), |
3435 | .hw.init = &(struct clk_init_data){ |
3436 | .name = "gcc_gtcu_ahb_clk" , |
3437 | .parent_hws = (const struct clk_hw*[]){ |
3438 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3439 | }, |
3440 | .num_parents = 1, |
3441 | .flags = CLK_SET_RATE_PARENT, |
3442 | .ops = &clk_branch2_ops, |
3443 | }, |
3444 | }, |
3445 | }; |
3446 | |
3447 | static struct clk_branch gcc_cpp_tbu_clk = { |
3448 | .halt_reg = 0x12040, |
3449 | .halt_check = BRANCH_HALT_VOTED, |
3450 | .clkr = { |
3451 | .enable_reg = 0x4500c, |
3452 | .enable_mask = BIT(14), |
3453 | .hw.init = &(struct clk_init_data){ |
3454 | .name = "gcc_cpp_tbu_clk" , |
3455 | .parent_hws = (const struct clk_hw*[]){ |
3456 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3457 | }, |
3458 | .num_parents = 1, |
3459 | .flags = CLK_SET_RATE_PARENT, |
3460 | .ops = &clk_branch2_ops, |
3461 | }, |
3462 | }, |
3463 | }; |
3464 | |
3465 | static struct clk_branch gcc_mdp_rt_tbu_clk = { |
3466 | .halt_reg = 0x1201c, |
3467 | .halt_check = BRANCH_HALT_VOTED, |
3468 | .clkr = { |
3469 | .enable_reg = 0x4500c, |
3470 | .enable_mask = BIT(15), |
3471 | .hw.init = &(struct clk_init_data){ |
3472 | .name = "gcc_mdp_rt_tbu_clk" , |
3473 | .parent_hws = (const struct clk_hw*[]){ |
3474 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3475 | }, |
3476 | .num_parents = 1, |
3477 | .flags = CLK_SET_RATE_PARENT, |
3478 | .ops = &clk_branch2_ops, |
3479 | }, |
3480 | }, |
3481 | }; |
3482 | |
3483 | static struct clk_branch gcc_bimc_gfx_clk = { |
3484 | .halt_reg = 0x31024, |
3485 | .clkr = { |
3486 | .enable_reg = 0x31024, |
3487 | .enable_mask = BIT(0), |
3488 | .hw.init = &(struct clk_init_data){ |
3489 | .name = "gcc_bimc_gfx_clk" , |
3490 | .parent_hws = (const struct clk_hw*[]){ |
3491 | &bimc_gpu_clk_src.clkr.hw, |
3492 | }, |
3493 | .num_parents = 1, |
3494 | .flags = CLK_SET_RATE_PARENT, |
3495 | .ops = &clk_branch2_ops, |
3496 | }, |
3497 | }, |
3498 | }; |
3499 | |
3500 | static struct clk_branch gcc_bimc_gpu_clk = { |
3501 | .halt_reg = 0x31040, |
3502 | .clkr = { |
3503 | .enable_reg = 0x31040, |
3504 | .enable_mask = BIT(0), |
3505 | .hw.init = &(struct clk_init_data){ |
3506 | .name = "gcc_bimc_gpu_clk" , |
3507 | .parent_hws = (const struct clk_hw*[]){ |
3508 | &bimc_gpu_clk_src.clkr.hw, |
3509 | }, |
3510 | .num_parents = 1, |
3511 | .flags = CLK_SET_RATE_PARENT, |
3512 | .ops = &clk_branch2_ops, |
3513 | }, |
3514 | }, |
3515 | }; |
3516 | |
3517 | static struct clk_branch gcc_usb2a_phy_sleep_clk = { |
3518 | .halt_reg = 0x4102c, |
3519 | .clkr = { |
3520 | .enable_reg = 0x4102c, |
3521 | .enable_mask = BIT(0), |
3522 | .hw.init = &(struct clk_init_data){ |
3523 | .name = "gcc_usb2a_phy_sleep_clk" , |
3524 | .ops = &clk_branch2_ops, |
3525 | }, |
3526 | }, |
3527 | }; |
3528 | |
3529 | static struct clk_branch gcc_usb_fs_ahb_clk = { |
3530 | .halt_reg = 0x3f008, |
3531 | .clkr = { |
3532 | .enable_reg = 0x3f008, |
3533 | .enable_mask = BIT(0), |
3534 | .hw.init = &(struct clk_init_data){ |
3535 | .name = "gcc_usb_fs_ahb_clk" , |
3536 | .parent_hws = (const struct clk_hw*[]){ |
3537 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3538 | }, |
3539 | .num_parents = 1, |
3540 | .flags = CLK_SET_RATE_PARENT, |
3541 | .ops = &clk_branch2_ops, |
3542 | }, |
3543 | }, |
3544 | }; |
3545 | |
3546 | static struct clk_branch gcc_usb_fs_ic_clk = { |
3547 | .halt_reg = 0x3f030, |
3548 | .clkr = { |
3549 | .enable_reg = 0x3f030, |
3550 | .enable_mask = BIT(0), |
3551 | .hw.init = &(struct clk_init_data){ |
3552 | .name = "gcc_usb_fs_ic_clk" , |
3553 | .parent_hws = (const struct clk_hw*[]){ |
3554 | &usb_fs_ic_clk_src.clkr.hw, |
3555 | }, |
3556 | .num_parents = 1, |
3557 | .flags = CLK_SET_RATE_PARENT, |
3558 | .ops = &clk_branch2_ops, |
3559 | }, |
3560 | }, |
3561 | }; |
3562 | |
3563 | static struct clk_branch gcc_usb_fs_system_clk = { |
3564 | .halt_reg = 0x3f004, |
3565 | .clkr = { |
3566 | .enable_reg = 0x3f004, |
3567 | .enable_mask = BIT(0), |
3568 | .hw.init = &(struct clk_init_data){ |
3569 | .name = "gcc_usb_fs_system_clk" , |
3570 | .parent_hws = (const struct clk_hw*[]){ |
3571 | &usb_fs_system_clk_src.clkr.hw, |
3572 | }, |
3573 | .num_parents = 1, |
3574 | .flags = CLK_SET_RATE_PARENT, |
3575 | .ops = &clk_branch2_ops, |
3576 | }, |
3577 | }, |
3578 | }; |
3579 | |
3580 | static struct clk_branch gcc_usb_hs_ahb_clk = { |
3581 | .halt_reg = 0x41008, |
3582 | .clkr = { |
3583 | .enable_reg = 0x41008, |
3584 | .enable_mask = BIT(0), |
3585 | .hw.init = &(struct clk_init_data){ |
3586 | .name = "gcc_usb_hs_ahb_clk" , |
3587 | .parent_hws = (const struct clk_hw*[]){ |
3588 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3589 | }, |
3590 | .num_parents = 1, |
3591 | .flags = CLK_SET_RATE_PARENT, |
3592 | .ops = &clk_branch2_ops, |
3593 | }, |
3594 | }, |
3595 | }; |
3596 | |
3597 | static struct clk_branch gcc_usb_hs_system_clk = { |
3598 | .halt_reg = 0x41004, |
3599 | .clkr = { |
3600 | .enable_reg = 0x41004, |
3601 | .enable_mask = BIT(0), |
3602 | .hw.init = &(struct clk_init_data){ |
3603 | .name = "gcc_usb_hs_system_clk" , |
3604 | .parent_hws = (const struct clk_hw*[]){ |
3605 | &usb_hs_system_clk_src.clkr.hw, |
3606 | }, |
3607 | .num_parents = 1, |
3608 | .flags = CLK_SET_RATE_PARENT, |
3609 | .ops = &clk_branch2_ops, |
3610 | }, |
3611 | }, |
3612 | }; |
3613 | |
3614 | static struct clk_branch gcc_venus0_ahb_clk = { |
3615 | .halt_reg = 0x4c020, |
3616 | .clkr = { |
3617 | .enable_reg = 0x4c020, |
3618 | .enable_mask = BIT(0), |
3619 | .hw.init = &(struct clk_init_data){ |
3620 | .name = "gcc_venus0_ahb_clk" , |
3621 | .parent_hws = (const struct clk_hw*[]){ |
3622 | &pcnoc_bfdcd_clk_src.clkr.hw, |
3623 | }, |
3624 | .num_parents = 1, |
3625 | .flags = CLK_SET_RATE_PARENT, |
3626 | .ops = &clk_branch2_ops, |
3627 | }, |
3628 | }, |
3629 | }; |
3630 | |
3631 | static struct clk_branch gcc_venus0_axi_clk = { |
3632 | .halt_reg = 0x4c024, |
3633 | .clkr = { |
3634 | .enable_reg = 0x4c024, |
3635 | .enable_mask = BIT(0), |
3636 | .hw.init = &(struct clk_init_data){ |
3637 | .name = "gcc_venus0_axi_clk" , |
3638 | .parent_hws = (const struct clk_hw*[]){ |
3639 | &system_mm_noc_bfdcd_clk_src.clkr.hw, |
3640 | }, |
3641 | .num_parents = 1, |
3642 | .flags = CLK_SET_RATE_PARENT, |
3643 | .ops = &clk_branch2_ops, |
3644 | }, |
3645 | }, |
3646 | }; |
3647 | |
3648 | static struct clk_branch gcc_venus0_vcodec0_clk = { |
3649 | .halt_reg = 0x4c01c, |
3650 | .clkr = { |
3651 | .enable_reg = 0x4c01c, |
3652 | .enable_mask = BIT(0), |
3653 | .hw.init = &(struct clk_init_data){ |
3654 | .name = "gcc_venus0_vcodec0_clk" , |
3655 | .parent_hws = (const struct clk_hw*[]){ |
3656 | &vcodec0_clk_src.clkr.hw, |
3657 | }, |
3658 | .num_parents = 1, |
3659 | .flags = CLK_SET_RATE_PARENT, |
3660 | .ops = &clk_branch2_ops, |
3661 | }, |
3662 | }, |
3663 | }; |
3664 | |
3665 | static struct clk_branch gcc_venus0_core0_vcodec0_clk = { |
3666 | .halt_reg = 0x4c02c, |
3667 | .clkr = { |
3668 | .enable_reg = 0x4c02c, |
3669 | .enable_mask = BIT(0), |
3670 | .hw.init = &(struct clk_init_data){ |
3671 | .name = "gcc_venus0_core0_vcodec0_clk" , |
3672 | .parent_hws = (const struct clk_hw*[]){ |
3673 | &vcodec0_clk_src.clkr.hw, |
3674 | }, |
3675 | .num_parents = 1, |
3676 | .flags = CLK_SET_RATE_PARENT, |
3677 | .ops = &clk_branch2_ops, |
3678 | }, |
3679 | }, |
3680 | }; |
3681 | |
3682 | static struct clk_branch gcc_venus0_core1_vcodec0_clk = { |
3683 | .halt_reg = 0x4c034, |
3684 | .clkr = { |
3685 | .enable_reg = 0x4c034, |
3686 | .enable_mask = BIT(0), |
3687 | .hw.init = &(struct clk_init_data){ |
3688 | .name = "gcc_venus0_core1_vcodec0_clk" , |
3689 | .parent_hws = (const struct clk_hw*[]){ |
3690 | &vcodec0_clk_src.clkr.hw, |
3691 | }, |
3692 | .num_parents = 1, |
3693 | .flags = CLK_SET_RATE_PARENT, |
3694 | .ops = &clk_branch2_ops, |
3695 | }, |
3696 | }, |
3697 | }; |
3698 | |
3699 | static struct clk_branch gcc_oxili_timer_clk = { |
3700 | .halt_reg = 0x59040, |
3701 | .clkr = { |
3702 | .enable_reg = 0x59040, |
3703 | .enable_mask = BIT(0), |
3704 | .hw.init = &(struct clk_init_data){ |
3705 | .name = "gcc_oxili_timer_clk" , |
3706 | .ops = &clk_branch2_ops, |
3707 | }, |
3708 | }, |
3709 | }; |
3710 | |
3711 | static struct gdsc venus_gdsc = { |
3712 | .gdscr = 0x4c018, |
3713 | .pd = { |
3714 | .name = "venus" , |
3715 | }, |
3716 | .pwrsts = PWRSTS_OFF_ON, |
3717 | }; |
3718 | |
3719 | static struct gdsc mdss_gdsc = { |
3720 | .gdscr = 0x4d078, |
3721 | .pd = { |
3722 | .name = "mdss" , |
3723 | }, |
3724 | .pwrsts = PWRSTS_OFF_ON, |
3725 | }; |
3726 | |
3727 | static struct gdsc jpeg_gdsc = { |
3728 | .gdscr = 0x5701c, |
3729 | .pd = { |
3730 | .name = "jpeg" , |
3731 | }, |
3732 | .pwrsts = PWRSTS_OFF_ON, |
3733 | }; |
3734 | |
3735 | static struct gdsc vfe_gdsc = { |
3736 | .gdscr = 0x58034, |
3737 | .pd = { |
3738 | .name = "vfe" , |
3739 | }, |
3740 | .pwrsts = PWRSTS_OFF_ON, |
3741 | }; |
3742 | |
3743 | static struct gdsc oxili_gdsc = { |
3744 | .gdscr = 0x5901c, |
3745 | .pd = { |
3746 | .name = "oxili" , |
3747 | }, |
3748 | .pwrsts = PWRSTS_OFF_ON, |
3749 | }; |
3750 | |
3751 | static struct gdsc venus_core0_gdsc = { |
3752 | .gdscr = 0x4c028, |
3753 | .pd = { |
3754 | .name = "venus_core0" , |
3755 | }, |
3756 | .pwrsts = PWRSTS_OFF_ON, |
3757 | }; |
3758 | |
3759 | static struct gdsc venus_core1_gdsc = { |
3760 | .gdscr = 0x4c030, |
3761 | .pd = { |
3762 | .name = "venus_core1" , |
3763 | }, |
3764 | .pwrsts = PWRSTS_OFF_ON, |
3765 | }; |
3766 | |
3767 | static struct clk_regmap *gcc_msm8939_clocks[] = { |
3768 | [GPLL0] = &gpll0.clkr, |
3769 | [GPLL0_VOTE] = &gpll0_vote, |
3770 | [BIMC_PLL] = &bimc_pll.clkr, |
3771 | [BIMC_PLL_VOTE] = &bimc_pll_vote, |
3772 | [GPLL1] = &gpll1.clkr, |
3773 | [GPLL1_VOTE] = &gpll1_vote, |
3774 | [GPLL2] = &gpll2.clkr, |
3775 | [GPLL2_VOTE] = &gpll2_vote, |
3776 | [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, |
3777 | [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, |
3778 | [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr, |
3779 | [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, |
3780 | [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, |
3781 | [CSI0_CLK_SRC] = &csi0_clk_src.clkr, |
3782 | [CSI1_CLK_SRC] = &csi1_clk_src.clkr, |
3783 | [CSI2_CLK_SRC] = &csi2_clk_src.clkr, |
3784 | [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, |
3785 | [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, |
3786 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, |
3787 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, |
3788 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, |
3789 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, |
3790 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, |
3791 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, |
3792 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, |
3793 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, |
3794 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, |
3795 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, |
3796 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, |
3797 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, |
3798 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, |
3799 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, |
3800 | [CCI_CLK_SRC] = &cci_clk_src.clkr, |
3801 | [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, |
3802 | [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, |
3803 | [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, |
3804 | [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, |
3805 | [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, |
3806 | [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, |
3807 | [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, |
3808 | [CPP_CLK_SRC] = &cpp_clk_src.clkr, |
3809 | [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, |
3810 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, |
3811 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, |
3812 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, |
3813 | [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, |
3814 | [ESC0_CLK_SRC] = &esc0_clk_src.clkr, |
3815 | [MDP_CLK_SRC] = &mdp_clk_src.clkr, |
3816 | [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, |
3817 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, |
3818 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, |
3819 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, |
3820 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, |
3821 | [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, |
3822 | [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, |
3823 | [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, |
3824 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, |
3825 | [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, |
3826 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, |
3827 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, |
3828 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, |
3829 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, |
3830 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, |
3831 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, |
3832 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, |
3833 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, |
3834 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, |
3835 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, |
3836 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, |
3837 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, |
3838 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, |
3839 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, |
3840 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
3841 | [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, |
3842 | [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, |
3843 | [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, |
3844 | [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, |
3845 | [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, |
3846 | [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, |
3847 | [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, |
3848 | [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, |
3849 | [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, |
3850 | [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, |
3851 | [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, |
3852 | [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, |
3853 | [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, |
3854 | [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, |
3855 | [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr, |
3856 | [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, |
3857 | [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, |
3858 | [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, |
3859 | [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, |
3860 | [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, |
3861 | [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, |
3862 | [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, |
3863 | [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, |
3864 | [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, |
3865 | [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, |
3866 | [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, |
3867 | [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, |
3868 | [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, |
3869 | [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, |
3870 | [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, |
3871 | [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, |
3872 | [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, |
3873 | [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, |
3874 | [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, |
3875 | [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, |
3876 | [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, |
3877 | [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, |
3878 | [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, |
3879 | [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, |
3880 | [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, |
3881 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
3882 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
3883 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
3884 | [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, |
3885 | [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, |
3886 | [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, |
3887 | [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, |
3888 | [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, |
3889 | [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, |
3890 | [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, |
3891 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, |
3892 | [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, |
3893 | [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, |
3894 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
3895 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
3896 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
3897 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
3898 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, |
3899 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, |
3900 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, |
3901 | [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, |
3902 | [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, |
3903 | [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, |
3904 | [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, |
3905 | [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, |
3906 | [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, |
3907 | [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, |
3908 | [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, |
3909 | [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, |
3910 | [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, |
3911 | [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, |
3912 | [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, |
3913 | [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, |
3914 | [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, |
3915 | [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, |
3916 | [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, |
3917 | [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, |
3918 | [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, |
3919 | [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, |
3920 | [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, |
3921 | [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, |
3922 | [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, |
3923 | [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, |
3924 | [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, |
3925 | [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, |
3926 | [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, |
3927 | [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, |
3928 | [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, |
3929 | [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, |
3930 | [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, |
3931 | [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, |
3932 | [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, |
3933 | [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, |
3934 | [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, |
3935 | [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, |
3936 | [GPLL3] = &gpll3.clkr, |
3937 | [GPLL3_VOTE] = &gpll3_vote, |
3938 | [GPLL4] = &gpll4.clkr, |
3939 | [GPLL4_VOTE] = &gpll4_vote, |
3940 | [GPLL5] = &gpll5.clkr, |
3941 | [GPLL5_VOTE] = &gpll5_vote, |
3942 | [GPLL6] = &gpll6.clkr, |
3943 | [GPLL6_VOTE] = &gpll6_vote, |
3944 | [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, |
3945 | [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr, |
3946 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, |
3947 | [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr, |
3948 | [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, |
3949 | [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr, |
3950 | [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr, |
3951 | [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr, |
3952 | [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr, |
3953 | [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr, |
3954 | [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr, |
3955 | [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr, |
3956 | [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr, |
3957 | [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr, |
3958 | [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr, |
3959 | [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr, |
3960 | [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr, |
3961 | }; |
3962 | |
3963 | static struct gdsc *gcc_msm8939_gdscs[] = { |
3964 | [VENUS_GDSC] = &venus_gdsc, |
3965 | [MDSS_GDSC] = &mdss_gdsc, |
3966 | [JPEG_GDSC] = &jpeg_gdsc, |
3967 | [VFE_GDSC] = &vfe_gdsc, |
3968 | [OXILI_GDSC] = &oxili_gdsc, |
3969 | [VENUS_CORE0_GDSC] = &venus_core0_gdsc, |
3970 | [VENUS_CORE1_GDSC] = &venus_core1_gdsc, |
3971 | }; |
3972 | |
3973 | static const struct qcom_reset_map gcc_msm8939_resets[] = { |
3974 | [GCC_BLSP1_BCR] = { 0x01000 }, |
3975 | [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, |
3976 | [GCC_BLSP1_UART1_BCR] = { 0x02038 }, |
3977 | [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, |
3978 | [GCC_BLSP1_UART2_BCR] = { 0x03028 }, |
3979 | [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, |
3980 | [GCC_BLSP1_UART3_BCR] = { 0x04038 }, |
3981 | [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, |
3982 | [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, |
3983 | [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, |
3984 | [GCC_IMEM_BCR] = { 0x0e000 }, |
3985 | [GCC_SMMU_BCR] = { 0x12000 }, |
3986 | [GCC_APSS_TCU_BCR] = { 0x12050 }, |
3987 | [GCC_SMMU_XPU_BCR] = { 0x12054 }, |
3988 | [GCC_PCNOC_TBU_BCR] = { 0x12058 }, |
3989 | [GCC_PRNG_BCR] = { 0x13000 }, |
3990 | [GCC_BOOT_ROM_BCR] = { 0x13008 }, |
3991 | [GCC_CRYPTO_BCR] = { 0x16000 }, |
3992 | [GCC_SEC_CTRL_BCR] = { 0x1a000 }, |
3993 | [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, |
3994 | [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, |
3995 | [GCC_DEHR_BCR] = { 0x1f000 }, |
3996 | [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, |
3997 | [GCC_PCNOC_BCR] = { 0x27018 }, |
3998 | [GCC_TCSR_BCR] = { 0x28000 }, |
3999 | [GCC_QDSS_BCR] = { 0x29000 }, |
4000 | [GCC_DCD_BCR] = { 0x2a000 }, |
4001 | [GCC_MSG_RAM_BCR] = { 0x2b000 }, |
4002 | [GCC_MPM_BCR] = { 0x2c000 }, |
4003 | [GCC_SPMI_BCR] = { 0x2e000 }, |
4004 | [GCC_SPDM_BCR] = { 0x2f000 }, |
4005 | [GCC_MM_SPDM_BCR] = { 0x2f024 }, |
4006 | [GCC_BIMC_BCR] = { 0x31000 }, |
4007 | [GCC_RBCPR_BCR] = { 0x33000 }, |
4008 | [GCC_TLMM_BCR] = { 0x34000 }, |
4009 | [GCC_CAMSS_CSI2_BCR] = { 0x3c038 }, |
4010 | [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 }, |
4011 | [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c }, |
4012 | [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 }, |
4013 | [GCC_USB_FS_BCR] = { 0x3f000 }, |
4014 | [GCC_USB_HS_BCR] = { 0x41000 }, |
4015 | [GCC_USB2A_PHY_BCR] = { 0x41028 }, |
4016 | [GCC_SDCC1_BCR] = { 0x42000 }, |
4017 | [GCC_SDCC2_BCR] = { 0x43000 }, |
4018 | [GCC_PDM_BCR] = { 0x44000 }, |
4019 | [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, |
4020 | [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, |
4021 | [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, |
4022 | [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, |
4023 | [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, |
4024 | [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, |
4025 | [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, |
4026 | [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, |
4027 | [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, |
4028 | [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, |
4029 | [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, |
4030 | [GCC_MMSS_BCR] = { 0x4b000 }, |
4031 | [GCC_VENUS0_BCR] = { 0x4c014 }, |
4032 | [GCC_MDSS_BCR] = { 0x4d074 }, |
4033 | [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, |
4034 | [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, |
4035 | [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, |
4036 | [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, |
4037 | [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, |
4038 | [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, |
4039 | [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, |
4040 | [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, |
4041 | [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, |
4042 | [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, |
4043 | [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, |
4044 | [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c }, |
4045 | [GCC_CAMSS_CCI_BCR] = { 0x51014 }, |
4046 | [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, |
4047 | [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, |
4048 | [GCC_CAMSS_GP0_BCR] = { 0x54014 }, |
4049 | [GCC_CAMSS_GP1_BCR] = { 0x55014 }, |
4050 | [GCC_CAMSS_TOP_BCR] = { 0x56000 }, |
4051 | [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, |
4052 | [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, |
4053 | [GCC_CAMSS_VFE_BCR] = { 0x58030 }, |
4054 | [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, |
4055 | [GCC_OXILI_BCR] = { 0x59018 }, |
4056 | [GCC_GMEM_BCR] = { 0x5902c }, |
4057 | [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, |
4058 | [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 }, |
4059 | [GCC_MDP_TBU_BCR] = { 0x62000 }, |
4060 | [GCC_GFX_TBU_BCR] = { 0x63000 }, |
4061 | [GCC_GFX_TCU_BCR] = { 0x64000 }, |
4062 | [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, |
4063 | [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, |
4064 | [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, |
4065 | [GCC_GTCU_AHB_BCR] = { 0x68000 }, |
4066 | [GCC_SMMU_CFG_BCR] = { 0x69000 }, |
4067 | [GCC_VFE_TBU_BCR] = { 0x6a000 }, |
4068 | [GCC_VENUS_TBU_BCR] = { 0x6b000 }, |
4069 | [GCC_JPEG_TBU_BCR] = { 0x6c000 }, |
4070 | [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, |
4071 | [GCC_CPP_TBU_BCR] = { 0x6e000 }, |
4072 | [GCC_MDP_RT_TBU_BCR] = { 0x6f000 }, |
4073 | [GCC_SMMU_CATS_BCR] = { 0x7c000 }, |
4074 | }; |
4075 | |
4076 | static const struct regmap_config gcc_msm8939_regmap_config = { |
4077 | .reg_bits = 32, |
4078 | .reg_stride = 4, |
4079 | .val_bits = 32, |
4080 | .max_register = 0x80000, |
4081 | .fast_io = true, |
4082 | }; |
4083 | |
4084 | static const struct qcom_cc_desc gcc_msm8939_desc = { |
4085 | .config = &gcc_msm8939_regmap_config, |
4086 | .clks = gcc_msm8939_clocks, |
4087 | .num_clks = ARRAY_SIZE(gcc_msm8939_clocks), |
4088 | .resets = gcc_msm8939_resets, |
4089 | .num_resets = ARRAY_SIZE(gcc_msm8939_resets), |
4090 | .gdscs = gcc_msm8939_gdscs, |
4091 | .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs), |
4092 | }; |
4093 | |
4094 | static const struct of_device_id gcc_msm8939_match_table[] = { |
4095 | { .compatible = "qcom,gcc-msm8939" }, |
4096 | { } |
4097 | }; |
4098 | MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table); |
4099 | |
4100 | static int gcc_msm8939_probe(struct platform_device *pdev) |
4101 | { |
4102 | struct regmap *regmap; |
4103 | |
4104 | regmap = qcom_cc_map(pdev, desc: &gcc_msm8939_desc); |
4105 | if (IS_ERR(ptr: regmap)) |
4106 | return PTR_ERR(ptr: regmap); |
4107 | |
4108 | clk_pll_configure_sr_hpm_lp(pll: &gpll3, regmap, config: &gpll3_config, fsm_mode: true); |
4109 | clk_pll_configure_sr_hpm_lp(pll: &gpll4, regmap, config: &gpll4_config, fsm_mode: true); |
4110 | |
4111 | return qcom_cc_really_probe(pdev, desc: &gcc_msm8939_desc, regmap); |
4112 | } |
4113 | |
4114 | static struct platform_driver gcc_msm8939_driver = { |
4115 | .probe = gcc_msm8939_probe, |
4116 | .driver = { |
4117 | .name = "gcc-msm8939" , |
4118 | .of_match_table = gcc_msm8939_match_table, |
4119 | }, |
4120 | }; |
4121 | |
4122 | static int __init gcc_msm8939_init(void) |
4123 | { |
4124 | return platform_driver_register(&gcc_msm8939_driver); |
4125 | } |
4126 | core_initcall(gcc_msm8939_init); |
4127 | |
4128 | static void __exit gcc_msm8939_exit(void) |
4129 | { |
4130 | platform_driver_unregister(&gcc_msm8939_driver); |
4131 | } |
4132 | module_exit(gcc_msm8939_exit); |
4133 | |
4134 | MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver" ); |
4135 | MODULE_LICENSE("GPL v2" ); |
4136 | |