1	// SPDX-License-Identifier: GPL-2.0-only
2	/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3	*/
4
5	#include <linux/clk-provider.h>
6	#include <linux/kernel.h>
7	#include <linux/init.h>
8	#include <linux/err.h>
9	#include <linux/ctype.h>
10	#include <linux/io.h>
11	#include <linux/of.h>
12	#include <linux/platform_device.h>
13	#include <linux/module.h>
14	#include <linux/regmap.h>
15
16	#include <dt-bindings/clock/qcom,gcc-msm8994.h>
17
18	#include "common.h"
19	#include "clk-regmap.h"
20	#include "clk-alpha-pll.h"
21	#include "clk-rcg.h"
22	#include "clk-branch.h"
23	#include "reset.h"
24	#include "gdsc.h"
25
26	enum {
27	P_XO,
28	P_GPLL0,
29	P_GPLL4,
30	};
31
32	static struct clk_alpha_pll gpll0_early = {
33	.offset = 0,
34	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
35	.clkr = {
36	.enable_reg = 0x1480,
37	.enable_mask = BIT(0),
38	.hw.init = &(struct clk_init_data){
39	.name = "gpll0_early",
40	.parent_data = &(const struct clk_parent_data){
41	.fw_name = "xo",
42	},
43	.num_parents = 1,
44	.ops = &clk_alpha_pll_ops,
45	},
46	},
47	};
48
49	static struct clk_alpha_pll_postdiv gpll0 = {
50	.offset = 0,
51	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
52	.clkr.hw.init = &(struct clk_init_data){
53	.name = "gpll0",
54	.parent_hws = (const struct clk_hw*[]){
55	&gpll0_early.clkr.hw
56	},
57	.num_parents = 1,
58	.ops = &clk_alpha_pll_postdiv_ops,
59	},
60	};
61
62	static struct clk_alpha_pll gpll4_early = {
63	.offset = 0x1dc0,
64	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
65	.clkr = {
66	.enable_reg = 0x1480,
67	.enable_mask = BIT(4),
68	.hw.init = &(struct clk_init_data){
69	.name = "gpll4_early",
70	.parent_data = &(const struct clk_parent_data){
71	.fw_name = "xo",
72	},
73	.num_parents = 1,
74	.ops = &clk_alpha_pll_ops,
75	},
76	},
77	};
78
79	static struct clk_alpha_pll_postdiv gpll4 = {
80	.offset = 0x1dc0,
81	.width = 4,
82	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
83	.clkr.hw.init = &(struct clk_init_data){
84	.name = "gpll4",
85	.parent_hws = (const struct clk_hw*[]){
86	&gpll4_early.clkr.hw
87	},
88	.num_parents = 1,
89	.ops = &clk_alpha_pll_postdiv_ops,
90	},
91	};
92
93	static const struct parent_map gcc_xo_gpll0_map[] = {
94	{ P_XO, 0 },
95	{ P_GPLL0, 1 },
96	};
97
98	static const struct clk_parent_data gcc_xo_gpll0[] = {
99	{ .fw_name = "xo" },
100	{ .hw = &gpll0.clkr.hw },
101	};
102
103	static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
104	{ P_XO, 0 },
105	{ P_GPLL0, 1 },
106	{ P_GPLL4, 5 },
107	};
108
109	static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
110	{ .fw_name = "xo" },
111	{ .hw = &gpll0.clkr.hw },
112	{ .hw = &gpll4.clkr.hw },
113	};
114
115	static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
116	F(50000000, P_GPLL0, 12, 0, 0),
117	F(100000000, P_GPLL0, 6, 0, 0),
118	F(150000000, P_GPLL0, 4, 0, 0),
119	F(171430000, P_GPLL0, 3.5, 0, 0),
120	F(200000000, P_GPLL0, 3, 0, 0),
121	F(240000000, P_GPLL0, 2.5, 0, 0),
122	{ }
123	};
124
125	static struct clk_rcg2 ufs_axi_clk_src = {
126	.cmd_rcgr = 0x1d68,
127	.mnd_width = 8,
128	.hid_width = 5,
129	.parent_map = gcc_xo_gpll0_map,
130	.freq_tbl = ftbl_ufs_axi_clk_src,
131	.clkr.hw.init = &(struct clk_init_data){
132	.name = "ufs_axi_clk_src",
133	.parent_data = gcc_xo_gpll0,
134	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
135	.ops = &clk_rcg2_ops,
136	},
137	};
138
139	static struct freq_tbl ftbl_usb30_master_clk_src[] = {
140	F(19200000, P_XO, 1, 0, 0),
141	F(125000000, P_GPLL0, 1, 5, 24),
142	{ }
143	};
144
145	static struct clk_rcg2 usb30_master_clk_src = {
146	.cmd_rcgr = 0x03d4,
147	.mnd_width = 8,
148	.hid_width = 5,
149	.parent_map = gcc_xo_gpll0_map,
150	.freq_tbl = ftbl_usb30_master_clk_src,
151	.clkr.hw.init = &(struct clk_init_data){
152	.name = "usb30_master_clk_src",
153	.parent_data = gcc_xo_gpll0,
154	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
155	.ops = &clk_rcg2_ops,
156	},
157	};
158
159	static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
160	F(19200000, P_XO, 1, 0, 0),
161	F(50000000, P_GPLL0, 12, 0, 0),
162	{ }
163	};
164
165	static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
166	.cmd_rcgr = 0x0660,
167	.hid_width = 5,
168	.parent_map = gcc_xo_gpll0_map,
169	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
170	.clkr.hw.init = &(struct clk_init_data){
171	.name = "blsp1_qup1_i2c_apps_clk_src",
172	.parent_data = gcc_xo_gpll0,
173	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
174	.ops = &clk_rcg2_ops,
175	},
176	};
177
178	static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
179	F(960000, P_XO, 10, 1, 2),
180	F(4800000, P_XO, 4, 0, 0),
181	F(9600000, P_XO, 2, 0, 0),
182	F(15000000, P_GPLL0, 10, 1, 4),
183	F(19200000, P_XO, 1, 0, 0),
184	F(24000000, P_GPLL0, 12.5, 1, 2),
185	F(25000000, P_GPLL0, 12, 1, 2),
186	F(48000000, P_GPLL0, 12.5, 0, 0),
187	F(50000000, P_GPLL0, 12, 0, 0),
188	{ }
189	};
190
191	static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
192	F(960000, P_XO, 10, 1, 2),
193	F(4800000, P_XO, 4, 0, 0),
194	F(9600000, P_XO, 2, 0, 0),
195	F(15000000, P_GPLL0, 10, 1, 4),
196	F(19200000, P_XO, 1, 0, 0),
197	F(25000000, P_GPLL0, 12, 1, 2),
198	F(50000000, P_GPLL0, 12, 0, 0),
199	{ }
200	};
201
202	static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
203	.cmd_rcgr = 0x064c,
204	.mnd_width = 8,
205	.hid_width = 5,
206	.parent_map = gcc_xo_gpll0_map,
207	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
208	.clkr.hw.init = &(struct clk_init_data){
209	.name = "blsp1_qup1_spi_apps_clk_src",
210	.parent_data = gcc_xo_gpll0,
211	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
212	.ops = &clk_rcg2_ops,
213	},
214	};
215
216	static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
217	.cmd_rcgr = 0x06e0,
218	.hid_width = 5,
219	.parent_map = gcc_xo_gpll0_map,
220	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
221	.clkr.hw.init = &(struct clk_init_data){
222	.name = "blsp1_qup2_i2c_apps_clk_src",
223	.parent_data = gcc_xo_gpll0,
224	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
225	.ops = &clk_rcg2_ops,
226	},
227	};
228
229	static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
230	F(960000, P_XO, 10, 1, 2),
231	F(4800000, P_XO, 4, 0, 0),
232	F(9600000, P_XO, 2, 0, 0),
233	F(15000000, P_GPLL0, 10, 1, 4),
234	F(19200000, P_XO, 1, 0, 0),
235	F(24000000, P_GPLL0, 12.5, 1, 2),
236	F(25000000, P_GPLL0, 12, 1, 2),
237	F(42860000, P_GPLL0, 14, 0, 0),
238	F(46150000, P_GPLL0, 13, 0, 0),
239	{ }
240	};
241
242	static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
243	.cmd_rcgr = 0x06cc,
244	.mnd_width = 8,
245	.hid_width = 5,
246	.parent_map = gcc_xo_gpll0_map,
247	.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
248	.clkr.hw.init = &(struct clk_init_data){
249	.name = "blsp1_qup2_spi_apps_clk_src",
250	.parent_data = gcc_xo_gpll0,
251	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
252	.ops = &clk_rcg2_ops,
253	},
254	};
255
256	static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
257	.cmd_rcgr = 0x0760,
258	.hid_width = 5,
259	.parent_map = gcc_xo_gpll0_map,
260	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
261	.clkr.hw.init = &(struct clk_init_data){
262	.name = "blsp1_qup3_i2c_apps_clk_src",
263	.parent_data = gcc_xo_gpll0,
264	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
265	.ops = &clk_rcg2_ops,
266	},
267	};
268
269	static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
270	F(960000, P_XO, 10, 1, 2),
271	F(4800000, P_XO, 4, 0, 0),
272	F(9600000, P_XO, 2, 0, 0),
273	F(15000000, P_GPLL0, 10, 1, 4),
274	F(19200000, P_XO, 1, 0, 0),
275	F(24000000, P_GPLL0, 12.5, 1, 2),
276	F(25000000, P_GPLL0, 12, 1, 2),
277	F(42860000, P_GPLL0, 14, 0, 0),
278	F(44440000, P_GPLL0, 13.5, 0, 0),
279	{ }
280	};
281
282	static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
283	.cmd_rcgr = 0x074c,
284	.mnd_width = 8,
285	.hid_width = 5,
286	.parent_map = gcc_xo_gpll0_map,
287	.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
288	.clkr.hw.init = &(struct clk_init_data){
289	.name = "blsp1_qup3_spi_apps_clk_src",
290	.parent_data = gcc_xo_gpll0,
291	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
292	.ops = &clk_rcg2_ops,
293	},
294	};
295
296	static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
297	.cmd_rcgr = 0x07e0,
298	.hid_width = 5,
299	.parent_map = gcc_xo_gpll0_map,
300	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
301	.clkr.hw.init = &(struct clk_init_data){
302	.name = "blsp1_qup4_i2c_apps_clk_src",
303	.parent_data = gcc_xo_gpll0,
304	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
305	.ops = &clk_rcg2_ops,
306	},
307	};
308
309	static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
310	.cmd_rcgr = 0x07cc,
311	.mnd_width = 8,
312	.hid_width = 5,
313	.parent_map = gcc_xo_gpll0_map,
314	.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
315	.clkr.hw.init = &(struct clk_init_data){
316	.name = "blsp1_qup4_spi_apps_clk_src",
317	.parent_data = gcc_xo_gpll0,
318	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
319	.ops = &clk_rcg2_ops,
320	},
321	};
322
323	static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
324	.cmd_rcgr = 0x0860,
325	.hid_width = 5,
326	.parent_map = gcc_xo_gpll0_map,
327	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
328	.clkr.hw.init = &(struct clk_init_data){
329	.name = "blsp1_qup5_i2c_apps_clk_src",
330	.parent_data = gcc_xo_gpll0,
331	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
332	.ops = &clk_rcg2_ops,
333	},
334	};
335
336	static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
337	F(960000, P_XO, 10, 1, 2),
338	F(4800000, P_XO, 4, 0, 0),
339	F(9600000, P_XO, 2, 0, 0),
340	F(15000000, P_GPLL0, 10, 1, 4),
341	F(19200000, P_XO, 1, 0, 0),
342	F(24000000, P_GPLL0, 12.5, 1, 2),
343	F(25000000, P_GPLL0, 12, 1, 2),
344	F(40000000, P_GPLL0, 15, 0, 0),
345	F(42860000, P_GPLL0, 14, 0, 0),
346	{ }
347	};
348
349	static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
350	.cmd_rcgr = 0x084c,
351	.mnd_width = 8,
352	.hid_width = 5,
353	.parent_map = gcc_xo_gpll0_map,
354	.freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
355	.clkr.hw.init = &(struct clk_init_data){
356	.name = "blsp1_qup5_spi_apps_clk_src",
357	.parent_data = gcc_xo_gpll0,
358	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
359	.ops = &clk_rcg2_ops,
360	},
361	};
362
363	static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
364	.cmd_rcgr = 0x08e0,
365	.hid_width = 5,
366	.parent_map = gcc_xo_gpll0_map,
367	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
368	.clkr.hw.init = &(struct clk_init_data){
369	.name = "blsp1_qup6_i2c_apps_clk_src",
370	.parent_data = gcc_xo_gpll0,
371	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
372	.ops = &clk_rcg2_ops,
373	},
374	};
375
376	static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
377	F(960000, P_XO, 10, 1, 2),
378	F(4800000, P_XO, 4, 0, 0),
379	F(9600000, P_XO, 2, 0, 0),
380	F(15000000, P_GPLL0, 10, 1, 4),
381	F(19200000, P_XO, 1, 0, 0),
382	F(24000000, P_GPLL0, 12.5, 1, 2),
383	F(27906976, P_GPLL0, 1, 2, 43),
384	F(41380000, P_GPLL0, 15, 0, 0),
385	F(42860000, P_GPLL0, 14, 0, 0),
386	{ }
387	};
388
389	static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
390	.cmd_rcgr = 0x08cc,
391	.mnd_width = 8,
392	.hid_width = 5,
393	.parent_map = gcc_xo_gpll0_map,
394	.freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
395	.clkr.hw.init = &(struct clk_init_data){
396	.name = "blsp1_qup6_spi_apps_clk_src",
397	.parent_data = gcc_xo_gpll0,
398	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
399	.ops = &clk_rcg2_ops,
400	},
401	};
402
403	static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
404	F(3686400, P_GPLL0, 1, 96, 15625),
405	F(7372800, P_GPLL0, 1, 192, 15625),
406	F(14745600, P_GPLL0, 1, 384, 15625),
407	F(16000000, P_GPLL0, 5, 2, 15),
408	F(19200000, P_XO, 1, 0, 0),
409	F(24000000, P_GPLL0, 5, 1, 5),
410	F(32000000, P_GPLL0, 1, 4, 75),
411	F(40000000, P_GPLL0, 15, 0, 0),
412	F(46400000, P_GPLL0, 1, 29, 375),
413	F(48000000, P_GPLL0, 12.5, 0, 0),
414	F(51200000, P_GPLL0, 1, 32, 375),
415	F(56000000, P_GPLL0, 1, 7, 75),
416	F(58982400, P_GPLL0, 1, 1536, 15625),
417	F(60000000, P_GPLL0, 10, 0, 0),
418	F(63160000, P_GPLL0, 9.5, 0, 0),
419	{ }
420	};
421
422	static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
423	.cmd_rcgr = 0x068c,
424	.mnd_width = 16,
425	.hid_width = 5,
426	.parent_map = gcc_xo_gpll0_map,
427	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
428	.clkr.hw.init = &(struct clk_init_data){
429	.name = "blsp1_uart1_apps_clk_src",
430	.parent_data = gcc_xo_gpll0,
431	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
432	.ops = &clk_rcg2_ops,
433	},
434	};
435
436	static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
437	.cmd_rcgr = 0x070c,
438	.mnd_width = 16,
439	.hid_width = 5,
440	.parent_map = gcc_xo_gpll0_map,
441	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
442	.clkr.hw.init = &(struct clk_init_data){
443	.name = "blsp1_uart2_apps_clk_src",
444	.parent_data = gcc_xo_gpll0,
445	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
446	.ops = &clk_rcg2_ops,
447	},
448	};
449
450	static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
451	.cmd_rcgr = 0x078c,
452	.mnd_width = 16,
453	.hid_width = 5,
454	.parent_map = gcc_xo_gpll0_map,
455	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
456	.clkr.hw.init = &(struct clk_init_data){
457	.name = "blsp1_uart3_apps_clk_src",
458	.parent_data = gcc_xo_gpll0,
459	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
460	.ops = &clk_rcg2_ops,
461	},
462	};
463
464	static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
465	.cmd_rcgr = 0x080c,
466	.mnd_width = 16,
467	.hid_width = 5,
468	.parent_map = gcc_xo_gpll0_map,
469	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
470	.clkr.hw.init = &(struct clk_init_data){
471	.name = "blsp1_uart4_apps_clk_src",
472	.parent_data = gcc_xo_gpll0,
473	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
474	.ops = &clk_rcg2_ops,
475	},
476	};
477
478	static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
479	.cmd_rcgr = 0x088c,
480	.mnd_width = 16,
481	.hid_width = 5,
482	.parent_map = gcc_xo_gpll0_map,
483	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
484	.clkr.hw.init = &(struct clk_init_data){
485	.name = "blsp1_uart5_apps_clk_src",
486	.parent_data = gcc_xo_gpll0,
487	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
488	.ops = &clk_rcg2_ops,
489	},
490	};
491
492	static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
493	.cmd_rcgr = 0x090c,
494	.mnd_width = 16,
495	.hid_width = 5,
496	.parent_map = gcc_xo_gpll0_map,
497	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
498	.clkr.hw.init = &(struct clk_init_data){
499	.name = "blsp1_uart6_apps_clk_src",
500	.parent_data = gcc_xo_gpll0,
501	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
502	.ops = &clk_rcg2_ops,
503	},
504	};
505
506	static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
507	.cmd_rcgr = 0x09a0,
508	.hid_width = 5,
509	.parent_map = gcc_xo_gpll0_map,
510	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
511	.clkr.hw.init = &(struct clk_init_data){
512	.name = "blsp2_qup1_i2c_apps_clk_src",
513	.parent_data = gcc_xo_gpll0,
514	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
515	.ops = &clk_rcg2_ops,
516	},
517	};
518
519	static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
520	F(960000, P_XO, 10, 1, 2),
521	F(4800000, P_XO, 4, 0, 0),
522	F(9600000, P_XO, 2, 0, 0),
523	F(15000000, P_GPLL0, 10, 1, 4),
524	F(19200000, P_XO, 1, 0, 0),
525	F(24000000, P_GPLL0, 12.5, 1, 2),
526	F(25000000, P_GPLL0, 12, 1, 2),
527	F(42860000, P_GPLL0, 14, 0, 0),
528	F(44440000, P_GPLL0, 13.5, 0, 0),
529	{ }
530	};
531
532	static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
533	.cmd_rcgr = 0x098c,
534	.mnd_width = 8,
535	.hid_width = 5,
536	.parent_map = gcc_xo_gpll0_map,
537	.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
538	.clkr.hw.init = &(struct clk_init_data){
539	.name = "blsp2_qup1_spi_apps_clk_src",
540	.parent_data = gcc_xo_gpll0,
541	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
542	.ops = &clk_rcg2_ops,
543	},
544	};
545
546	static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
547	.cmd_rcgr = 0x0a20,
548	.hid_width = 5,
549	.parent_map = gcc_xo_gpll0_map,
550	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
551	.clkr.hw.init = &(struct clk_init_data){
552	.name = "blsp2_qup2_i2c_apps_clk_src",
553	.parent_data = gcc_xo_gpll0,
554	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
555	.ops = &clk_rcg2_ops,
556	},
557	};
558
559	static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
560	.cmd_rcgr = 0x0a0c,
561	.mnd_width = 8,
562	.hid_width = 5,
563	.parent_map = gcc_xo_gpll0_map,
564	.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
565	.clkr.hw.init = &(struct clk_init_data){
566	.name = "blsp2_qup2_spi_apps_clk_src",
567	.parent_data = gcc_xo_gpll0,
568	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
569	.ops = &clk_rcg2_ops,
570	},
571	};
572
573	static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
574	F(960000, P_XO, 10, 1, 2),
575	F(4800000, P_XO, 4, 0, 0),
576	F(9600000, P_XO, 2, 0, 0),
577	F(15000000, P_GPLL0, 10, 1, 4),
578	F(19200000, P_XO, 1, 0, 0),
579	F(24000000, P_GPLL0, 12.5, 1, 2),
580	F(25000000, P_GPLL0, 12, 1, 2),
581	F(42860000, P_GPLL0, 14, 0, 0),
582	F(48000000, P_GPLL0, 12.5, 0, 0),
583	{ }
584	};
585
586	static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
587	.cmd_rcgr = 0x0aa0,
588	.hid_width = 5,
589	.parent_map = gcc_xo_gpll0_map,
590	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
591	.clkr.hw.init = &(struct clk_init_data){
592	.name = "blsp2_qup3_i2c_apps_clk_src",
593	.parent_data = gcc_xo_gpll0,
594	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
595	.ops = &clk_rcg2_ops,
596	},
597	};
598
599	static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
600	.cmd_rcgr = 0x0a8c,
601	.mnd_width = 8,
602	.hid_width = 5,
603	.parent_map = gcc_xo_gpll0_map,
604	.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
605	.clkr.hw.init = &(struct clk_init_data){
606	.name = "blsp2_qup3_spi_apps_clk_src",
607	.parent_data = gcc_xo_gpll0,
608	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
609	.ops = &clk_rcg2_ops,
610	},
611	};
612
613	static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
614	.cmd_rcgr = 0x0b20,
615	.hid_width = 5,
616	.parent_map = gcc_xo_gpll0_map,
617	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
618	.clkr.hw.init = &(struct clk_init_data){
619	.name = "blsp2_qup4_i2c_apps_clk_src",
620	.parent_data = gcc_xo_gpll0,
621	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
622	.ops = &clk_rcg2_ops,
623	},
624	};
625
626	static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
627	.cmd_rcgr = 0x0b0c,
628	.mnd_width = 8,
629	.hid_width = 5,
630	.parent_map = gcc_xo_gpll0_map,
631	.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
632	.clkr.hw.init = &(struct clk_init_data){
633	.name = "blsp2_qup4_spi_apps_clk_src",
634	.parent_data = gcc_xo_gpll0,
635	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
636	.ops = &clk_rcg2_ops,
637	},
638	};
639
640	static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
641	.cmd_rcgr = 0x0ba0,
642	.hid_width = 5,
643	.parent_map = gcc_xo_gpll0_map,
644	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
645	.clkr.hw.init = &(struct clk_init_data){
646	.name = "blsp2_qup5_i2c_apps_clk_src",
647	.parent_data = gcc_xo_gpll0,
648	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
649	.ops = &clk_rcg2_ops,
650	},
651	};
652
653	static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
654	.cmd_rcgr = 0x0b8c,
655	.mnd_width = 8,
656	.hid_width = 5,
657	.parent_map = gcc_xo_gpll0_map,
658	/* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
659	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
660	.clkr.hw.init = &(struct clk_init_data){
661	.name = "blsp2_qup5_spi_apps_clk_src",
662	.parent_data = gcc_xo_gpll0,
663	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
664	.ops = &clk_rcg2_ops,
665	},
666	};
667
668	static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
669	.cmd_rcgr = 0x0c20,
670	.hid_width = 5,
671	.parent_map = gcc_xo_gpll0_map,
672	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
673	.clkr.hw.init = &(struct clk_init_data){
674	.name = "blsp2_qup6_i2c_apps_clk_src",
675	.parent_data = gcc_xo_gpll0,
676	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
677	.ops = &clk_rcg2_ops,
678	},
679	};
680
681	static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
682	F(960000, P_XO, 10, 1, 2),
683	F(4800000, P_XO, 4, 0, 0),
684	F(9600000, P_XO, 2, 0, 0),
685	F(15000000, P_GPLL0, 10, 1, 4),
686	F(19200000, P_XO, 1, 0, 0),
687	F(24000000, P_GPLL0, 12.5, 1, 2),
688	F(25000000, P_GPLL0, 12, 1, 2),
689	F(44440000, P_GPLL0, 13.5, 0, 0),
690	F(48000000, P_GPLL0, 12.5, 0, 0),
691	{ }
692	};
693
694	static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
695	.cmd_rcgr = 0x0c0c,
696	.mnd_width = 8,
697	.hid_width = 5,
698	.parent_map = gcc_xo_gpll0_map,
699	.freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
700	.clkr.hw.init = &(struct clk_init_data){
701	.name = "blsp2_qup6_spi_apps_clk_src",
702	.parent_data = gcc_xo_gpll0,
703	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
704	.ops = &clk_rcg2_ops,
705	},
706	};
707
708	static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
709	.cmd_rcgr = 0x09cc,
710	.mnd_width = 16,
711	.hid_width = 5,
712	.parent_map = gcc_xo_gpll0_map,
713	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
714	.clkr.hw.init = &(struct clk_init_data){
715	.name = "blsp2_uart1_apps_clk_src",
716	.parent_data = gcc_xo_gpll0,
717	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
718	.ops = &clk_rcg2_ops,
719	},
720	};
721
722	static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
723	.cmd_rcgr = 0x0a4c,
724	.mnd_width = 16,
725	.hid_width = 5,
726	.parent_map = gcc_xo_gpll0_map,
727	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
728	.clkr.hw.init = &(struct clk_init_data){
729	.name = "blsp2_uart2_apps_clk_src",
730	.parent_data = gcc_xo_gpll0,
731	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
732	.ops = &clk_rcg2_ops,
733	},
734	};
735
736	static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
737	.cmd_rcgr = 0x0acc,
738	.mnd_width = 16,
739	.hid_width = 5,
740	.parent_map = gcc_xo_gpll0_map,
741	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
742	.clkr.hw.init = &(struct clk_init_data){
743	.name = "blsp2_uart3_apps_clk_src",
744	.parent_data = gcc_xo_gpll0,
745	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
746	.ops = &clk_rcg2_ops,
747	},
748	};
749
750	static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
751	.cmd_rcgr = 0x0b4c,
752	.mnd_width = 16,
753	.hid_width = 5,
754	.parent_map = gcc_xo_gpll0_map,
755	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
756	.clkr.hw.init = &(struct clk_init_data){
757	.name = "blsp2_uart4_apps_clk_src",
758	.parent_data = gcc_xo_gpll0,
759	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
760	.ops = &clk_rcg2_ops,
761	},
762	};
763
764	static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
765	.cmd_rcgr = 0x0bcc,
766	.mnd_width = 16,
767	.hid_width = 5,
768	.parent_map = gcc_xo_gpll0_map,
769	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
770	.clkr.hw.init = &(struct clk_init_data){
771	.name = "blsp2_uart5_apps_clk_src",
772	.parent_data = gcc_xo_gpll0,
773	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
774	.ops = &clk_rcg2_ops,
775	},
776	};
777
778	static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
779	.cmd_rcgr = 0x0c4c,
780	.mnd_width = 16,
781	.hid_width = 5,
782	.parent_map = gcc_xo_gpll0_map,
783	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
784	.clkr.hw.init = &(struct clk_init_data){
785	.name = "blsp2_uart6_apps_clk_src",
786	.parent_data = gcc_xo_gpll0,
787	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
788	.ops = &clk_rcg2_ops,
789	},
790	};
791
792	static struct freq_tbl ftbl_gp1_clk_src[] = {
793	F(19200000, P_XO, 1, 0, 0),
794	F(100000000, P_GPLL0, 6, 0, 0),
795	F(200000000, P_GPLL0, 3, 0, 0),
796	{ }
797	};
798
799	static struct clk_rcg2 gp1_clk_src = {
800	.cmd_rcgr = 0x1904,
801	.mnd_width = 8,
802	.hid_width = 5,
803	.parent_map = gcc_xo_gpll0_map,
804	.freq_tbl = ftbl_gp1_clk_src,
805	.clkr.hw.init = &(struct clk_init_data){
806	.name = "gp1_clk_src",
807	.parent_data = gcc_xo_gpll0,
808	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
809	.ops = &clk_rcg2_ops,
810	},
811	};
812
813	static struct freq_tbl ftbl_gp2_clk_src[] = {
814	F(19200000, P_XO, 1, 0, 0),
815	F(100000000, P_GPLL0, 6, 0, 0),
816	F(200000000, P_GPLL0, 3, 0, 0),
817	{ }
818	};
819
820	static struct clk_rcg2 gp2_clk_src = {
821	.cmd_rcgr = 0x1944,
822	.mnd_width = 8,
823	.hid_width = 5,
824	.parent_map = gcc_xo_gpll0_map,
825	.freq_tbl = ftbl_gp2_clk_src,
826	.clkr.hw.init = &(struct clk_init_data){
827	.name = "gp2_clk_src",
828	.parent_data = gcc_xo_gpll0,
829	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
830	.ops = &clk_rcg2_ops,
831	},
832	};
833
834	static struct freq_tbl ftbl_gp3_clk_src[] = {
835	F(19200000, P_XO, 1, 0, 0),
836	F(100000000, P_GPLL0, 6, 0, 0),
837	F(200000000, P_GPLL0, 3, 0, 0),
838	{ }
839	};
840
841	static struct clk_rcg2 gp3_clk_src = {
842	.cmd_rcgr = 0x1984,
843	.mnd_width = 8,
844	.hid_width = 5,
845	.parent_map = gcc_xo_gpll0_map,
846	.freq_tbl = ftbl_gp3_clk_src,
847	.clkr.hw.init = &(struct clk_init_data){
848	.name = "gp3_clk_src",
849	.parent_data = gcc_xo_gpll0,
850	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
851	.ops = &clk_rcg2_ops,
852	},
853	};
854
855	static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
856	F(1011000, P_XO, 1, 1, 19),
857	{ }
858	};
859
860	static struct clk_rcg2 pcie_0_aux_clk_src = {
861	.cmd_rcgr = 0x1b00,
862	.mnd_width = 8,
863	.hid_width = 5,
864	.freq_tbl = ftbl_pcie_0_aux_clk_src,
865	.clkr.hw.init = &(struct clk_init_data){
866	.name = "pcie_0_aux_clk_src",
867	.parent_data = &(const struct clk_parent_data){
868	.fw_name = "xo",
869	},
870	.num_parents = 1,
871	.ops = &clk_rcg2_ops,
872	},
873	};
874
875	static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
876	F(125000000, P_XO, 1, 0, 0),
877	{ }
878	};
879
880	static struct clk_rcg2 pcie_0_pipe_clk_src = {
881	.cmd_rcgr = 0x1adc,
882	.hid_width = 5,
883	.freq_tbl = ftbl_pcie_pipe_clk_src,
884	.clkr.hw.init = &(struct clk_init_data){
885	.name = "pcie_0_pipe_clk_src",
886	.parent_data = &(const struct clk_parent_data){
887	.fw_name = "xo",
888	},
889	.num_parents = 1,
890	.ops = &clk_rcg2_ops,
891	},
892	};
893
894	static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
895	F(1011000, P_XO, 1, 1, 19),
896	{ }
897	};
898
899	static struct clk_rcg2 pcie_1_aux_clk_src = {
900	.cmd_rcgr = 0x1b80,
901	.mnd_width = 8,
902	.hid_width = 5,
903	.freq_tbl = ftbl_pcie_1_aux_clk_src,
904	.clkr.hw.init = &(struct clk_init_data){
905	.name = "pcie_1_aux_clk_src",
906	.parent_data = &(const struct clk_parent_data){
907	.fw_name = "xo",
908	},
909	.num_parents = 1,
910	.ops = &clk_rcg2_ops,
911	},
912	};
913
914	static struct clk_rcg2 pcie_1_pipe_clk_src = {
915	.cmd_rcgr = 0x1b5c,
916	.hid_width = 5,
917	.freq_tbl = ftbl_pcie_pipe_clk_src,
918	.clkr.hw.init = &(struct clk_init_data){
919	.name = "pcie_1_pipe_clk_src",
920	.parent_data = &(const struct clk_parent_data){
921	.fw_name = "xo",
922	},
923	.num_parents = 1,
924	.ops = &clk_rcg2_ops,
925	},
926	};
927
928	static struct freq_tbl ftbl_pdm2_clk_src[] = {
929	F(60000000, P_GPLL0, 10, 0, 0),
930	{ }
931	};
932
933	static struct clk_rcg2 pdm2_clk_src = {
934	.cmd_rcgr = 0x0cd0,
935	.hid_width = 5,
936	.parent_map = gcc_xo_gpll0_map,
937	.freq_tbl = ftbl_pdm2_clk_src,
938	.clkr.hw.init = &(struct clk_init_data){
939	.name = "pdm2_clk_src",
940	.parent_data = gcc_xo_gpll0,
941	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
942	.ops = &clk_rcg2_ops,
943	},
944	};
945
946	static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
947	F(144000, P_XO, 16, 3, 25),
948	F(400000, P_XO, 12, 1, 4),
949	F(20000000, P_GPLL0, 15, 1, 2),
950	F(25000000, P_GPLL0, 12, 1, 2),
951	F(50000000, P_GPLL0, 12, 0, 0),
952	F(100000000, P_GPLL0, 6, 0, 0),
953	F(192000000, P_GPLL4, 2, 0, 0),
954	F(384000000, P_GPLL4, 1, 0, 0),
955	{ }
956	};
957
958	static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
959	F(144000, P_XO, 16, 3, 25),
960	F(400000, P_XO, 12, 1, 4),
961	F(20000000, P_GPLL0, 15, 1, 2),
962	F(25000000, P_GPLL0, 12, 1, 2),
963	F(50000000, P_GPLL0, 12, 0, 0),
964	F(100000000, P_GPLL0, 6, 0, 0),
965	F(172000000, P_GPLL4, 2, 0, 0),
966	F(344000000, P_GPLL4, 1, 0, 0),
967	{ }
968	};
969
970	static struct clk_rcg2 sdcc1_apps_clk_src = {
971	.cmd_rcgr = 0x04d0,
972	.mnd_width = 8,
973	.hid_width = 5,
974	.parent_map = gcc_xo_gpll0_gpll4_map,
975	.freq_tbl = ftbl_sdcc1_apps_clk_src,
976	.clkr.hw.init = &(struct clk_init_data){
977	.name = "sdcc1_apps_clk_src",
978	.parent_data = gcc_xo_gpll0_gpll4,
979	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
980	.ops = &clk_rcg2_floor_ops,
981	},
982	};
983
984	static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
985	F(144000, P_XO, 16, 3, 25),
986	F(400000, P_XO, 12, 1, 4),
987	F(20000000, P_GPLL0, 15, 1, 2),
988	F(25000000, P_GPLL0, 12, 1, 2),
989	F(50000000, P_GPLL0, 12, 0, 0),
990	F(100000000, P_GPLL0, 6, 0, 0),
991	F(200000000, P_GPLL0, 3, 0, 0),
992	{ }
993	};
994
995	static struct clk_rcg2 sdcc2_apps_clk_src = {
996	.cmd_rcgr = 0x0510,
997	.mnd_width = 8,
998	.hid_width = 5,
999	.parent_map = gcc_xo_gpll0_map,
1000	.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1001	.clkr.hw.init = &(struct clk_init_data){
1002	.name = "sdcc2_apps_clk_src",
1003	.parent_data = gcc_xo_gpll0,
1004	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1005	.ops = &clk_rcg2_floor_ops,
1006	},
1007	};
1008
1009	static struct clk_rcg2 sdcc3_apps_clk_src = {
1010	.cmd_rcgr = 0x0550,
1011	.mnd_width = 8,
1012	.hid_width = 5,
1013	.parent_map = gcc_xo_gpll0_map,
1014	.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1015	.clkr.hw.init = &(struct clk_init_data){
1016	.name = "sdcc3_apps_clk_src",
1017	.parent_data = gcc_xo_gpll0,
1018	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1019	.ops = &clk_rcg2_floor_ops,
1020	},
1021	};
1022
1023	static struct clk_rcg2 sdcc4_apps_clk_src = {
1024	.cmd_rcgr = 0x0590,
1025	.mnd_width = 8,
1026	.hid_width = 5,
1027	.parent_map = gcc_xo_gpll0_map,
1028	.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1029	.clkr.hw.init = &(struct clk_init_data){
1030	.name = "sdcc4_apps_clk_src",
1031	.parent_data = gcc_xo_gpll0,
1032	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1033	.ops = &clk_rcg2_floor_ops,
1034	},
1035	};
1036
1037	static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1038	F(105500, P_XO, 1, 1, 182),
1039	{ }
1040	};
1041
1042	static struct clk_rcg2 tsif_ref_clk_src = {
1043	.cmd_rcgr = 0x0d90,
1044	.mnd_width = 8,
1045	.hid_width = 5,
1046	.freq_tbl = ftbl_tsif_ref_clk_src,
1047	.clkr.hw.init = &(struct clk_init_data){
1048	.name = "tsif_ref_clk_src",
1049	.parent_data = &(const struct clk_parent_data){
1050	.fw_name = "xo",
1051	},
1052	.num_parents = 1,
1053	.ops = &clk_rcg2_ops,
1054	},
1055	};
1056
1057	static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1058	F(19200000, P_XO, 1, 0, 0),
1059	F(60000000, P_GPLL0, 10, 0, 0),
1060	{ }
1061	};
1062
1063	static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1064	.cmd_rcgr = 0x03e8,
1065	.hid_width = 5,
1066	.parent_map = gcc_xo_gpll0_map,
1067	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1068	.clkr.hw.init = &(struct clk_init_data){
1069	.name = "usb30_mock_utmi_clk_src",
1070	.parent_data = gcc_xo_gpll0,
1071	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1072	.ops = &clk_rcg2_ops,
1073	},
1074	};
1075
1076	static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1077	F(1200000, P_XO, 16, 0, 0),
1078	{ }
1079	};
1080
1081	static struct clk_rcg2 usb3_phy_aux_clk_src = {
1082	.cmd_rcgr = 0x1414,
1083	.hid_width = 5,
1084	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
1085	.clkr.hw.init = &(struct clk_init_data){
1086	.name = "usb3_phy_aux_clk_src",
1087	.parent_data = &(const struct clk_parent_data){
1088	.fw_name = "xo",
1089	},
1090	.num_parents = 1,
1091	.ops = &clk_rcg2_ops,
1092	},
1093	};
1094
1095	static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1096	F(75000000, P_GPLL0, 8, 0, 0),
1097	{ }
1098	};
1099
1100	static struct clk_rcg2 usb_hs_system_clk_src = {
1101	.cmd_rcgr = 0x0490,
1102	.hid_width = 5,
1103	.parent_map = gcc_xo_gpll0_map,
1104	.freq_tbl = ftbl_usb_hs_system_clk_src,
1105	.clkr.hw.init = &(struct clk_init_data){
1106	.name = "usb_hs_system_clk_src",
1107	.parent_data = gcc_xo_gpll0,
1108	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1109	.ops = &clk_rcg2_ops,
1110	},
1111	};
1112
1113	static struct clk_branch gcc_blsp1_ahb_clk = {
1114	.halt_reg = 0x05c4,
1115	.halt_check = BRANCH_HALT_VOTED,
1116	.clkr = {
1117	.enable_reg = 0x1484,
1118	.enable_mask = BIT(17),
1119	.hw.init = &(struct clk_init_data){
1120	.name = "gcc_blsp1_ahb_clk",
1121	.ops = &clk_branch2_ops,
1122	},
1123	},
1124	};
1125
1126	static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1127	.halt_reg = 0x0648,
1128	.clkr = {
1129	.enable_reg = 0x0648,
1130	.enable_mask = BIT(0),
1131	.hw.init = &(struct clk_init_data){
1132	.name = "gcc_blsp1_qup1_i2c_apps_clk",
1133	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1134	.num_parents = 1,
1135	.flags = CLK_SET_RATE_PARENT,
1136	.ops = &clk_branch2_ops,
1137	},
1138	},
1139	};
1140
1141	static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1142	.halt_reg = 0x0644,
1143	.clkr = {
1144	.enable_reg = 0x0644,
1145	.enable_mask = BIT(0),
1146	.hw.init = &(struct clk_init_data){
1147	.name = "gcc_blsp1_qup1_spi_apps_clk",
1148	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1149	.num_parents = 1,
1150	.flags = CLK_SET_RATE_PARENT,
1151	.ops = &clk_branch2_ops,
1152	},
1153	},
1154	};
1155
1156	static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1157	.halt_reg = 0x06c8,
1158	.clkr = {
1159	.enable_reg = 0x06c8,
1160	.enable_mask = BIT(0),
1161	.hw.init = &(struct clk_init_data){
1162	.name = "gcc_blsp1_qup2_i2c_apps_clk",
1163	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1164	.num_parents = 1,
1165	.flags = CLK_SET_RATE_PARENT,
1166	.ops = &clk_branch2_ops,
1167	},
1168	},
1169	};
1170
1171	static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1172	.halt_reg = 0x06c4,
1173	.clkr = {
1174	.enable_reg = 0x06c4,
1175	.enable_mask = BIT(0),
1176	.hw.init = &(struct clk_init_data){
1177	.name = "gcc_blsp1_qup2_spi_apps_clk",
1178	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1179	.num_parents = 1,
1180	.flags = CLK_SET_RATE_PARENT,
1181	.ops = &clk_branch2_ops,
1182	},
1183	},
1184	};
1185
1186	static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1187	.halt_reg = 0x0748,
1188	.clkr = {
1189	.enable_reg = 0x0748,
1190	.enable_mask = BIT(0),
1191	.hw.init = &(struct clk_init_data){
1192	.name = "gcc_blsp1_qup3_i2c_apps_clk",
1193	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1194	.num_parents = 1,
1195	.flags = CLK_SET_RATE_PARENT,
1196	.ops = &clk_branch2_ops,
1197	},
1198	},
1199	};
1200
1201	static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1202	.halt_reg = 0x0744,
1203	.clkr = {
1204	.enable_reg = 0x0744,
1205	.enable_mask = BIT(0),
1206	.hw.init = &(struct clk_init_data){
1207	.name = "gcc_blsp1_qup3_spi_apps_clk",
1208	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1209	.num_parents = 1,
1210	.flags = CLK_SET_RATE_PARENT,
1211	.ops = &clk_branch2_ops,
1212	},
1213	},
1214	};
1215
1216	static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1217	.halt_reg = 0x07c8,
1218	.clkr = {
1219	.enable_reg = 0x07c8,
1220	.enable_mask = BIT(0),
1221	.hw.init = &(struct clk_init_data){
1222	.name = "gcc_blsp1_qup4_i2c_apps_clk",
1223	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1224	.num_parents = 1,
1225	.flags = CLK_SET_RATE_PARENT,
1226	.ops = &clk_branch2_ops,
1227	},
1228	},
1229	};
1230
1231	static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1232	.halt_reg = 0x07c4,
1233	.clkr = {
1234	.enable_reg = 0x07c4,
1235	.enable_mask = BIT(0),
1236	.hw.init = &(struct clk_init_data){
1237	.name = "gcc_blsp1_qup4_spi_apps_clk",
1238	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1239	.num_parents = 1,
1240	.flags = CLK_SET_RATE_PARENT,
1241	.ops = &clk_branch2_ops,
1242	},
1243	},
1244	};
1245
1246	static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1247	.halt_reg = 0x0848,
1248	.clkr = {
1249	.enable_reg = 0x0848,
1250	.enable_mask = BIT(0),
1251	.hw.init = &(struct clk_init_data){
1252	.name = "gcc_blsp1_qup5_i2c_apps_clk",
1253	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1254	.num_parents = 1,
1255	.flags = CLK_SET_RATE_PARENT,
1256	.ops = &clk_branch2_ops,
1257	},
1258	},
1259	};
1260
1261	static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1262	.halt_reg = 0x0844,
1263	.clkr = {
1264	.enable_reg = 0x0844,
1265	.enable_mask = BIT(0),
1266	.hw.init = &(struct clk_init_data){
1267	.name = "gcc_blsp1_qup5_spi_apps_clk",
1268	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1269	.num_parents = 1,
1270	.flags = CLK_SET_RATE_PARENT,
1271	.ops = &clk_branch2_ops,
1272	},
1273	},
1274	};
1275
1276	static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1277	.halt_reg = 0x08c8,
1278	.clkr = {
1279	.enable_reg = 0x08c8,
1280	.enable_mask = BIT(0),
1281	.hw.init = &(struct clk_init_data){
1282	.name = "gcc_blsp1_qup6_i2c_apps_clk",
1283	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1284	.num_parents = 1,
1285	.flags = CLK_SET_RATE_PARENT,
1286	.ops = &clk_branch2_ops,
1287	},
1288	},
1289	};
1290
1291	static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1292	.halt_reg = 0x08c4,
1293	.clkr = {
1294	.enable_reg = 0x08c4,
1295	.enable_mask = BIT(0),
1296	.hw.init = &(struct clk_init_data){
1297	.name = "gcc_blsp1_qup6_spi_apps_clk",
1298	.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1299	.num_parents = 1,
1300	.flags = CLK_SET_RATE_PARENT,
1301	.ops = &clk_branch2_ops,
1302	},
1303	},
1304	};
1305
1306	static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1307	.halt_reg = 0x0684,
1308	.clkr = {
1309	.enable_reg = 0x0684,
1310	.enable_mask = BIT(0),
1311	.hw.init = &(struct clk_init_data){
1312	.name = "gcc_blsp1_uart1_apps_clk",
1313	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1314	.num_parents = 1,
1315	.flags = CLK_SET_RATE_PARENT,
1316	.ops = &clk_branch2_ops,
1317	},
1318	},
1319	};
1320
1321	static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1322	.halt_reg = 0x0704,
1323	.clkr = {
1324	.enable_reg = 0x0704,
1325	.enable_mask = BIT(0),
1326	.hw.init = &(struct clk_init_data){
1327	.name = "gcc_blsp1_uart2_apps_clk",
1328	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1329	.num_parents = 1,
1330	.flags = CLK_SET_RATE_PARENT,
1331	.ops = &clk_branch2_ops,
1332	},
1333	},
1334	};
1335
1336	static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1337	.halt_reg = 0x0784,
1338	.clkr = {
1339	.enable_reg = 0x0784,
1340	.enable_mask = BIT(0),
1341	.hw.init = &(struct clk_init_data){
1342	.name = "gcc_blsp1_uart3_apps_clk",
1343	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1344	.num_parents = 1,
1345	.flags = CLK_SET_RATE_PARENT,
1346	.ops = &clk_branch2_ops,
1347	},
1348	},
1349	};
1350
1351	static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1352	.halt_reg = 0x0804,
1353	.clkr = {
1354	.enable_reg = 0x0804,
1355	.enable_mask = BIT(0),
1356	.hw.init = &(struct clk_init_data){
1357	.name = "gcc_blsp1_uart4_apps_clk",
1358	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1359	.num_parents = 1,
1360	.flags = CLK_SET_RATE_PARENT,
1361	.ops = &clk_branch2_ops,
1362	},
1363	},
1364	};
1365
1366	static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1367	.halt_reg = 0x0884,
1368	.clkr = {
1369	.enable_reg = 0x0884,
1370	.enable_mask = BIT(0),
1371	.hw.init = &(struct clk_init_data){
1372	.name = "gcc_blsp1_uart5_apps_clk",
1373	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1374	.num_parents = 1,
1375	.flags = CLK_SET_RATE_PARENT,
1376	.ops = &clk_branch2_ops,
1377	},
1378	},
1379	};
1380
1381	static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1382	.halt_reg = 0x0904,
1383	.clkr = {
1384	.enable_reg = 0x0904,
1385	.enable_mask = BIT(0),
1386	.hw.init = &(struct clk_init_data){
1387	.name = "gcc_blsp1_uart6_apps_clk",
1388	.parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1389	.num_parents = 1,
1390	.flags = CLK_SET_RATE_PARENT,
1391	.ops = &clk_branch2_ops,
1392	},
1393	},
1394	};
1395
1396	static struct clk_branch gcc_blsp2_ahb_clk = {
1397	.halt_reg = 0x0944,
1398	.halt_check = BRANCH_HALT_VOTED,
1399	.clkr = {
1400	.enable_reg = 0x1484,
1401	.enable_mask = BIT(15),
1402	.hw.init = &(struct clk_init_data){
1403	.name = "gcc_blsp2_ahb_clk",
1404	.ops = &clk_branch2_ops,
1405	},
1406	},
1407	};
1408
1409	static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1410	.halt_reg = 0x0988,
1411	.clkr = {
1412	.enable_reg = 0x0988,
1413	.enable_mask = BIT(0),
1414	.hw.init = &(struct clk_init_data){
1415	.name = "gcc_blsp2_qup1_i2c_apps_clk",
1416	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1417	.num_parents = 1,
1418	.flags = CLK_SET_RATE_PARENT,
1419	.ops = &clk_branch2_ops,
1420	},
1421	},
1422	};
1423
1424	static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1425	.halt_reg = 0x0984,
1426	.clkr = {
1427	.enable_reg = 0x0984,
1428	.enable_mask = BIT(0),
1429	.hw.init = &(struct clk_init_data){
1430	.name = "gcc_blsp2_qup1_spi_apps_clk",
1431	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1432	.num_parents = 1,
1433	.flags = CLK_SET_RATE_PARENT,
1434	.ops = &clk_branch2_ops,
1435	},
1436	},
1437	};
1438
1439	static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1440	.halt_reg = 0x0a08,
1441	.clkr = {
1442	.enable_reg = 0x0a08,
1443	.enable_mask = BIT(0),
1444	.hw.init = &(struct clk_init_data){
1445	.name = "gcc_blsp2_qup2_i2c_apps_clk",
1446	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1447	.num_parents = 1,
1448	.flags = CLK_SET_RATE_PARENT,
1449	.ops = &clk_branch2_ops,
1450	},
1451	},
1452	};
1453
1454	static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1455	.halt_reg = 0x0a04,
1456	.clkr = {
1457	.enable_reg = 0x0a04,
1458	.enable_mask = BIT(0),
1459	.hw.init = &(struct clk_init_data){
1460	.name = "gcc_blsp2_qup2_spi_apps_clk",
1461	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1462	.num_parents = 1,
1463	.flags = CLK_SET_RATE_PARENT,
1464	.ops = &clk_branch2_ops,
1465	},
1466	},
1467	};
1468
1469	static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1470	.halt_reg = 0x0a88,
1471	.clkr = {
1472	.enable_reg = 0x0a88,
1473	.enable_mask = BIT(0),
1474	.hw.init = &(struct clk_init_data){
1475	.name = "gcc_blsp2_qup3_i2c_apps_clk",
1476	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1477	.num_parents = 1,
1478	.flags = CLK_SET_RATE_PARENT,
1479	.ops = &clk_branch2_ops,
1480	},
1481	},
1482	};
1483
1484	static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1485	.halt_reg = 0x0a84,
1486	.clkr = {
1487	.enable_reg = 0x0a84,
1488	.enable_mask = BIT(0),
1489	.hw.init = &(struct clk_init_data){
1490	.name = "gcc_blsp2_qup3_spi_apps_clk",
1491	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1492	.num_parents = 1,
1493	.flags = CLK_SET_RATE_PARENT,
1494	.ops = &clk_branch2_ops,
1495	},
1496	},
1497	};
1498
1499	static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1500	.halt_reg = 0x0b08,
1501	.clkr = {
1502	.enable_reg = 0x0b08,
1503	.enable_mask = BIT(0),
1504	.hw.init = &(struct clk_init_data){
1505	.name = "gcc_blsp2_qup4_i2c_apps_clk",
1506	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1507	.num_parents = 1,
1508	.flags = CLK_SET_RATE_PARENT,
1509	.ops = &clk_branch2_ops,
1510	},
1511	},
1512	};
1513
1514	static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1515	.halt_reg = 0x0b04,
1516	.clkr = {
1517	.enable_reg = 0x0b04,
1518	.enable_mask = BIT(0),
1519	.hw.init = &(struct clk_init_data){
1520	.name = "gcc_blsp2_qup4_spi_apps_clk",
1521	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1522	.num_parents = 1,
1523	.flags = CLK_SET_RATE_PARENT,
1524	.ops = &clk_branch2_ops,
1525	},
1526	},
1527	};
1528
1529	static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1530	.halt_reg = 0x0b88,
1531	.clkr = {
1532	.enable_reg = 0x0b88,
1533	.enable_mask = BIT(0),
1534	.hw.init = &(struct clk_init_data){
1535	.name = "gcc_blsp2_qup5_i2c_apps_clk",
1536	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1537	.num_parents = 1,
1538	.flags = CLK_SET_RATE_PARENT,
1539	.ops = &clk_branch2_ops,
1540	},
1541	},
1542	};
1543
1544	static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1545	.halt_reg = 0x0b84,
1546	.clkr = {
1547	.enable_reg = 0x0b84,
1548	.enable_mask = BIT(0),
1549	.hw.init = &(struct clk_init_data){
1550	.name = "gcc_blsp2_qup5_spi_apps_clk",
1551	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1552	.num_parents = 1,
1553	.flags = CLK_SET_RATE_PARENT,
1554	.ops = &clk_branch2_ops,
1555	},
1556	},
1557	};
1558
1559	static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1560	.halt_reg = 0x0c08,
1561	.clkr = {
1562	.enable_reg = 0x0c08,
1563	.enable_mask = BIT(0),
1564	.hw.init = &(struct clk_init_data){
1565	.name = "gcc_blsp2_qup6_i2c_apps_clk",
1566	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1567	.num_parents = 1,
1568	.flags = CLK_SET_RATE_PARENT,
1569	.ops = &clk_branch2_ops,
1570	},
1571	},
1572	};
1573
1574	static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1575	.halt_reg = 0x0c04,
1576	.clkr = {
1577	.enable_reg = 0x0c04,
1578	.enable_mask = BIT(0),
1579	.hw.init = &(struct clk_init_data){
1580	.name = "gcc_blsp2_qup6_spi_apps_clk",
1581	.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1582	.num_parents = 1,
1583	.flags = CLK_SET_RATE_PARENT,
1584	.ops = &clk_branch2_ops,
1585	},
1586	},
1587	};
1588
1589	static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1590	.halt_reg = 0x09c4,
1591	.clkr = {
1592	.enable_reg = 0x09c4,
1593	.enable_mask = BIT(0),
1594	.hw.init = &(struct clk_init_data){
1595	.name = "gcc_blsp2_uart1_apps_clk",
1596	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1597	.num_parents = 1,
1598	.flags = CLK_SET_RATE_PARENT,
1599	.ops = &clk_branch2_ops,
1600	},
1601	},
1602	};
1603
1604	static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1605	.halt_reg = 0x0a44,
1606	.clkr = {
1607	.enable_reg = 0x0a44,
1608	.enable_mask = BIT(0),
1609	.hw.init = &(struct clk_init_data){
1610	.name = "gcc_blsp2_uart2_apps_clk",
1611	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1612	.num_parents = 1,
1613	.flags = CLK_SET_RATE_PARENT,
1614	.ops = &clk_branch2_ops,
1615	},
1616	},
1617	};
1618
1619	static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1620	.halt_reg = 0x0ac4,
1621	.clkr = {
1622	.enable_reg = 0x0ac4,
1623	.enable_mask = BIT(0),
1624	.hw.init = &(struct clk_init_data){
1625	.name = "gcc_blsp2_uart3_apps_clk",
1626	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1627	.num_parents = 1,
1628	.flags = CLK_SET_RATE_PARENT,
1629	.ops = &clk_branch2_ops,
1630	},
1631	},
1632	};
1633
1634	static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1635	.halt_reg = 0x0b44,
1636	.clkr = {
1637	.enable_reg = 0x0b44,
1638	.enable_mask = BIT(0),
1639	.hw.init = &(struct clk_init_data){
1640	.name = "gcc_blsp2_uart4_apps_clk",
1641	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1642	.num_parents = 1,
1643	.flags = CLK_SET_RATE_PARENT,
1644	.ops = &clk_branch2_ops,
1645	},
1646	},
1647	};
1648
1649	static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1650	.halt_reg = 0x0bc4,
1651	.clkr = {
1652	.enable_reg = 0x0bc4,
1653	.enable_mask = BIT(0),
1654	.hw.init = &(struct clk_init_data){
1655	.name = "gcc_blsp2_uart5_apps_clk",
1656	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1657	.num_parents = 1,
1658	.flags = CLK_SET_RATE_PARENT,
1659	.ops = &clk_branch2_ops,
1660	},
1661	},
1662	};
1663
1664	static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1665	.halt_reg = 0x0c44,
1666	.clkr = {
1667	.enable_reg = 0x0c44,
1668	.enable_mask = BIT(0),
1669	.hw.init = &(struct clk_init_data){
1670	.name = "gcc_blsp2_uart6_apps_clk",
1671	.parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1672	.num_parents = 1,
1673	.flags = CLK_SET_RATE_PARENT,
1674	.ops = &clk_branch2_ops,
1675	},
1676	},
1677	};
1678
1679	static struct clk_branch gcc_gp1_clk = {
1680	.halt_reg = 0x1900,
1681	.clkr = {
1682	.enable_reg = 0x1900,
1683	.enable_mask = BIT(0),
1684	.hw.init = &(struct clk_init_data){
1685	.name = "gcc_gp1_clk",
1686	.parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1687	.num_parents = 1,
1688	.flags = CLK_SET_RATE_PARENT,
1689	.ops = &clk_branch2_ops,
1690	},
1691	},
1692	};
1693
1694	static struct clk_branch gcc_gp2_clk = {
1695	.halt_reg = 0x1940,
1696	.clkr = {
1697	.enable_reg = 0x1940,
1698	.enable_mask = BIT(0),
1699	.hw.init = &(struct clk_init_data){
1700	.name = "gcc_gp2_clk",
1701	.parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1702	.num_parents = 1,
1703	.flags = CLK_SET_RATE_PARENT,
1704	.ops = &clk_branch2_ops,
1705	},
1706	},
1707	};
1708
1709	static struct clk_branch gcc_gp3_clk = {
1710	.halt_reg = 0x1980,
1711	.clkr = {
1712	.enable_reg = 0x1980,
1713	.enable_mask = BIT(0),
1714	.hw.init = &(struct clk_init_data){
1715	.name = "gcc_gp3_clk",
1716	.parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1717	.num_parents = 1,
1718	.flags = CLK_SET_RATE_PARENT,
1719	.ops = &clk_branch2_ops,
1720	},
1721	},
1722	};
1723
1724	static struct clk_branch gcc_lpass_q6_axi_clk = {
1725	.halt_reg = 0x0280,
1726	.clkr = {
1727	.enable_reg = 0x0280,
1728	.enable_mask = BIT(0),
1729	.hw.init = &(struct clk_init_data){
1730	.name = "gcc_lpass_q6_axi_clk",
1731	.ops = &clk_branch2_ops,
1732	},
1733	},
1734	};
1735
1736	static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1737	.halt_reg = 0x0284,
1738	.clkr = {
1739	.enable_reg = 0x0284,
1740	.enable_mask = BIT(0),
1741	.hw.init = &(struct clk_init_data){
1742	.name = "gcc_mss_q6_bimc_axi_clk",
1743	.ops = &clk_branch2_ops,
1744	},
1745	},
1746	};
1747
1748	static struct clk_branch gcc_pcie_0_aux_clk = {
1749	.halt_reg = 0x1ad4,
1750	.clkr = {
1751	.enable_reg = 0x1ad4,
1752	.enable_mask = BIT(0),
1753	.hw.init = &(struct clk_init_data){
1754	.name = "gcc_pcie_0_aux_clk",
1755	.parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1756	.num_parents = 1,
1757	.flags = CLK_SET_RATE_PARENT,
1758	.ops = &clk_branch2_ops,
1759	},
1760	},
1761	};
1762
1763	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1764	.halt_reg = 0x1ad0,
1765	.clkr = {
1766	.enable_reg = 0x1ad0,
1767	.enable_mask = BIT(0),
1768	.hw.init = &(struct clk_init_data){
1769	.name = "gcc_pcie_0_cfg_ahb_clk",
1770	.ops = &clk_branch2_ops,
1771	},
1772	},
1773	};
1774
1775	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1776	.halt_reg = 0x1acc,
1777	.clkr = {
1778	.enable_reg = 0x1acc,
1779	.enable_mask = BIT(0),
1780	.hw.init = &(struct clk_init_data){
1781	.name = "gcc_pcie_0_mstr_axi_clk",
1782	.ops = &clk_branch2_ops,
1783	},
1784	},
1785	};
1786
1787	static struct clk_branch gcc_pcie_0_pipe_clk = {
1788	.halt_reg = 0x1ad8,
1789	.halt_check = BRANCH_HALT_DELAY,
1790	.clkr = {
1791	.enable_reg = 0x1ad8,
1792	.enable_mask = BIT(0),
1793	.hw.init = &(struct clk_init_data){
1794	.name = "gcc_pcie_0_pipe_clk",
1795	.parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1796	.num_parents = 1,
1797	.flags = CLK_SET_RATE_PARENT,
1798	.ops = &clk_branch2_ops,
1799	},
1800	},
1801	};
1802
1803	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1804	.halt_reg = 0x1ac8,
1805	.halt_check = BRANCH_HALT_DELAY,
1806	.clkr = {
1807	.enable_reg = 0x1ac8,
1808	.enable_mask = BIT(0),
1809	.hw.init = &(struct clk_init_data){
1810	.name = "gcc_pcie_0_slv_axi_clk",
1811	.ops = &clk_branch2_ops,
1812	},
1813	},
1814	};
1815
1816	static struct clk_branch gcc_pcie_1_aux_clk = {
1817	.halt_reg = 0x1b54,
1818	.clkr = {
1819	.enable_reg = 0x1b54,
1820	.enable_mask = BIT(0),
1821	.hw.init = &(struct clk_init_data){
1822	.name = "gcc_pcie_1_aux_clk",
1823	.parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1824	.num_parents = 1,
1825	.flags = CLK_SET_RATE_PARENT,
1826	.ops = &clk_branch2_ops,
1827	},
1828	},
1829	};
1830
1831	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1832	.halt_reg = 0x1b54,
1833	.clkr = {
1834	.enable_reg = 0x1b54,
1835	.enable_mask = BIT(0),
1836	.hw.init = &(struct clk_init_data){
1837	.name = "gcc_pcie_1_cfg_ahb_clk",
1838	.ops = &clk_branch2_ops,
1839	},
1840	},
1841	};
1842
1843	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1844	.halt_reg = 0x1b50,
1845	.clkr = {
1846	.enable_reg = 0x1b50,
1847	.enable_mask = BIT(0),
1848	.hw.init = &(struct clk_init_data){
1849	.name = "gcc_pcie_1_mstr_axi_clk",
1850	.ops = &clk_branch2_ops,
1851	},
1852	},
1853	};
1854
1855	static struct clk_branch gcc_pcie_1_pipe_clk = {
1856	.halt_reg = 0x1b58,
1857	.halt_check = BRANCH_HALT_DELAY,
1858	.clkr = {
1859	.enable_reg = 0x1b58,
1860	.enable_mask = BIT(0),
1861	.hw.init = &(struct clk_init_data){
1862	.name = "gcc_pcie_1_pipe_clk",
1863	.parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1864	.num_parents = 1,
1865	.flags = CLK_SET_RATE_PARENT,
1866	.ops = &clk_branch2_ops,
1867	},
1868	},
1869	};
1870
1871	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1872	.halt_reg = 0x1b48,
1873	.clkr = {
1874	.enable_reg = 0x1b48,
1875	.enable_mask = BIT(0),
1876	.hw.init = &(struct clk_init_data){
1877	.name = "gcc_pcie_1_slv_axi_clk",
1878	.ops = &clk_branch2_ops,
1879	},
1880	},
1881	};
1882
1883	static struct clk_branch gcc_pdm2_clk = {
1884	.halt_reg = 0x0ccc,
1885	.clkr = {
1886	.enable_reg = 0x0ccc,
1887	.enable_mask = BIT(0),
1888	.hw.init = &(struct clk_init_data){
1889	.name = "gcc_pdm2_clk",
1890	.parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1891	.num_parents = 1,
1892	.flags = CLK_SET_RATE_PARENT,
1893	.ops = &clk_branch2_ops,
1894	},
1895	},
1896	};
1897
1898	static struct clk_branch gcc_pdm_ahb_clk = {
1899	.halt_reg = 0x0cc4,
1900	.clkr = {
1901	.enable_reg = 0x0cc4,
1902	.enable_mask = BIT(0),
1903	.hw.init = &(struct clk_init_data){
1904	.name = "gcc_pdm_ahb_clk",
1905	.ops = &clk_branch2_ops,
1906	},
1907	},
1908	};
1909
1910	static struct clk_branch gcc_sdcc1_apps_clk = {
1911	.halt_reg = 0x04c4,
1912	.clkr = {
1913	.enable_reg = 0x04c4,
1914	.enable_mask = BIT(0),
1915	.hw.init = &(struct clk_init_data){
1916	.name = "gcc_sdcc1_apps_clk",
1917	.parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1918	.num_parents = 1,
1919	.flags = CLK_SET_RATE_PARENT,
1920	.ops = &clk_branch2_ops,
1921	},
1922	},
1923	};
1924
1925	static struct clk_branch gcc_sdcc1_ahb_clk = {
1926	.halt_reg = 0x04c8,
1927	.clkr = {
1928	.enable_reg = 0x04c8,
1929	.enable_mask = BIT(0),
1930	.hw.init = &(struct clk_init_data){
1931	.name = "gcc_sdcc1_ahb_clk",
1932	.ops = &clk_branch2_ops,
1933	},
1934	},
1935	};
1936
1937	static struct clk_branch gcc_sdcc2_ahb_clk = {
1938	.halt_reg = 0x0508,
1939	.clkr = {
1940	.enable_reg = 0x0508,
1941	.enable_mask = BIT(0),
1942	.hw.init = &(struct clk_init_data){
1943	.name = "gcc_sdcc2_ahb_clk",
1944	.ops = &clk_branch2_ops,
1945	},
1946	},
1947	};
1948
1949	static struct clk_branch gcc_sdcc2_apps_clk = {
1950	.halt_reg = 0x0504,
1951	.clkr = {
1952	.enable_reg = 0x0504,
1953	.enable_mask = BIT(0),
1954	.hw.init = &(struct clk_init_data){
1955	.name = "gcc_sdcc2_apps_clk",
1956	.parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1957	.num_parents = 1,
1958	.flags = CLK_SET_RATE_PARENT,
1959	.ops = &clk_branch2_ops,
1960	},
1961	},
1962	};
1963
1964	static struct clk_branch gcc_sdcc3_ahb_clk = {
1965	.halt_reg = 0x0548,
1966	.clkr = {
1967	.enable_reg = 0x0548,
1968	.enable_mask = BIT(0),
1969	.hw.init = &(struct clk_init_data){
1970	.name = "gcc_sdcc3_ahb_clk",
1971	.ops = &clk_branch2_ops,
1972	},
1973	},
1974	};
1975
1976	static struct clk_branch gcc_sdcc3_apps_clk = {
1977	.halt_reg = 0x0544,
1978	.clkr = {
1979	.enable_reg = 0x0544,
1980	.enable_mask = BIT(0),
1981	.hw.init = &(struct clk_init_data){
1982	.name = "gcc_sdcc3_apps_clk",
1983	.parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
1984	.num_parents = 1,
1985	.flags = CLK_SET_RATE_PARENT,
1986	.ops = &clk_branch2_ops,
1987	},
1988	},
1989	};
1990
1991	static struct clk_branch gcc_sdcc4_ahb_clk = {
1992	.halt_reg = 0x0588,
1993	.clkr = {
1994	.enable_reg = 0x0588,
1995	.enable_mask = BIT(0),
1996	.hw.init = &(struct clk_init_data){
1997	.name = "gcc_sdcc4_ahb_clk",
1998	.ops = &clk_branch2_ops,
1999	},
2000	},
2001	};
2002
2003	static struct clk_branch gcc_sdcc4_apps_clk = {
2004	.halt_reg = 0x0584,
2005	.clkr = {
2006	.enable_reg = 0x0584,
2007	.enable_mask = BIT(0),
2008	.hw.init = &(struct clk_init_data){
2009	.name = "gcc_sdcc4_apps_clk",
2010	.parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2011	.num_parents = 1,
2012	.flags = CLK_SET_RATE_PARENT,
2013	.ops = &clk_branch2_ops,
2014	},
2015	},
2016	};
2017
2018	static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2019	.halt_reg = 0x1d7c,
2020	.clkr = {
2021	.enable_reg = 0x1d7c,
2022	.enable_mask = BIT(0),
2023	.hw.init = &(struct clk_init_data){
2024	.name = "gcc_sys_noc_ufs_axi_clk",
2025	.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2026	.num_parents = 1,
2027	.flags = CLK_SET_RATE_PARENT,
2028	.ops = &clk_branch2_ops,
2029	},
2030	},
2031	};
2032
2033	static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2034	.halt_reg = 0x03fc,
2035	.clkr = {
2036	.enable_reg = 0x03fc,
2037	.enable_mask = BIT(0),
2038	.hw.init = &(struct clk_init_data){
2039	.name = "gcc_sys_noc_usb3_axi_clk",
2040	.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2041	.num_parents = 1,
2042	.flags = CLK_SET_RATE_PARENT,
2043	.ops = &clk_branch2_ops,
2044	},
2045	},
2046	};
2047
2048	static struct clk_branch gcc_tsif_ahb_clk = {
2049	.halt_reg = 0x0d84,
2050	.clkr = {
2051	.enable_reg = 0x0d84,
2052	.enable_mask = BIT(0),
2053	.hw.init = &(struct clk_init_data){
2054	.name = "gcc_tsif_ahb_clk",
2055	.ops = &clk_branch2_ops,
2056	},
2057	},
2058	};
2059
2060	static struct clk_branch gcc_tsif_ref_clk = {
2061	.halt_reg = 0x0d88,
2062	.clkr = {
2063	.enable_reg = 0x0d88,
2064	.enable_mask = BIT(0),
2065	.hw.init = &(struct clk_init_data){
2066	.name = "gcc_tsif_ref_clk",
2067	.parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2068	.num_parents = 1,
2069	.flags = CLK_SET_RATE_PARENT,
2070	.ops = &clk_branch2_ops,
2071	},
2072	},
2073	};
2074
2075	static struct clk_branch gcc_ufs_ahb_clk = {
2076	.halt_reg = 0x1d4c,
2077	.clkr = {
2078	.enable_reg = 0x1d4c,
2079	.enable_mask = BIT(0),
2080	.hw.init = &(struct clk_init_data){
2081	.name = "gcc_ufs_ahb_clk",
2082	.ops = &clk_branch2_ops,
2083	},
2084	},
2085	};
2086
2087	static struct clk_branch gcc_ufs_axi_clk = {
2088	.halt_reg = 0x1d48,
2089	.clkr = {
2090	.enable_reg = 0x1d48,
2091	.enable_mask = BIT(0),
2092	.hw.init = &(struct clk_init_data){
2093	.name = "gcc_ufs_axi_clk",
2094	.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2095	.num_parents = 1,
2096	.flags = CLK_SET_RATE_PARENT,
2097	.ops = &clk_branch2_ops,
2098	},
2099	},
2100	};
2101
2102	static struct clk_branch gcc_ufs_rx_cfg_clk = {
2103	.halt_reg = 0x1d54,
2104	.clkr = {
2105	.enable_reg = 0x1d54,
2106	.enable_mask = BIT(0),
2107	.hw.init = &(struct clk_init_data){
2108	.name = "gcc_ufs_rx_cfg_clk",
2109	.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2110	.num_parents = 1,
2111	.flags = CLK_SET_RATE_PARENT,
2112	.ops = &clk_branch2_ops,
2113	},
2114	},
2115	};
2116
2117	static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2118	.halt_reg = 0x1d60,
2119	.halt_check = BRANCH_HALT_DELAY,
2120	.clkr = {
2121	.enable_reg = 0x1d60,
2122	.enable_mask = BIT(0),
2123	.hw.init = &(struct clk_init_data){
2124	.name = "gcc_ufs_rx_symbol_0_clk",
2125	.ops = &clk_branch2_ops,
2126	},
2127	},
2128	};
2129
2130	static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2131	.halt_reg = 0x1d64,
2132	.halt_check = BRANCH_HALT_DELAY,
2133	.clkr = {
2134	.enable_reg = 0x1d64,
2135	.enable_mask = BIT(0),
2136	.hw.init = &(struct clk_init_data){
2137	.name = "gcc_ufs_rx_symbol_1_clk",
2138	.ops = &clk_branch2_ops,
2139	},
2140	},
2141	};
2142
2143	static struct clk_branch gcc_ufs_tx_cfg_clk = {
2144	.halt_reg = 0x1d50,
2145	.clkr = {
2146	.enable_reg = 0x1d50,
2147	.enable_mask = BIT(0),
2148	.hw.init = &(struct clk_init_data){
2149	.name = "gcc_ufs_tx_cfg_clk",
2150	.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2151	.num_parents = 1,
2152	.flags = CLK_SET_RATE_PARENT,
2153	.ops = &clk_branch2_ops,
2154	},
2155	},
2156	};
2157
2158	static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2159	.halt_reg = 0x1d58,
2160	.halt_check = BRANCH_HALT_DELAY,
2161	.clkr = {
2162	.enable_reg = 0x1d58,
2163	.enable_mask = BIT(0),
2164	.hw.init = &(struct clk_init_data){
2165	.name = "gcc_ufs_tx_symbol_0_clk",
2166	.ops = &clk_branch2_ops,
2167	},
2168	},
2169	};
2170
2171	static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2172	.halt_reg = 0x1d5c,
2173	.halt_check = BRANCH_HALT_DELAY,
2174	.clkr = {
2175	.enable_reg = 0x1d5c,
2176	.enable_mask = BIT(0),
2177	.hw.init = &(struct clk_init_data){
2178	.name = "gcc_ufs_tx_symbol_1_clk",
2179	.ops = &clk_branch2_ops,
2180	},
2181	},
2182	};
2183
2184	static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2185	.halt_reg = 0x04ac,
2186	.clkr = {
2187	.enable_reg = 0x04ac,
2188	.enable_mask = BIT(0),
2189	.hw.init = &(struct clk_init_data){
2190	.name = "gcc_usb2_hs_phy_sleep_clk",
2191	.parent_data = &(const struct clk_parent_data){
2192	.fw_name = "sleep",
2193	.name = "sleep"
2194	},
2195	.num_parents = 1,
2196	.ops = &clk_branch2_ops,
2197	},
2198	},
2199	};
2200
2201	static struct clk_branch gcc_usb30_master_clk = {
2202	.halt_reg = 0x03c8,
2203	.clkr = {
2204	.enable_reg = 0x03c8,
2205	.enable_mask = BIT(0),
2206	.hw.init = &(struct clk_init_data){
2207	.name = "gcc_usb30_master_clk",
2208	.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2209	.num_parents = 1,
2210	.flags = CLK_SET_RATE_PARENT,
2211	.ops = &clk_branch2_ops,
2212	},
2213	},
2214	};
2215
2216	static struct clk_branch gcc_usb30_mock_utmi_clk = {
2217	.halt_reg = 0x03d0,
2218	.clkr = {
2219	.enable_reg = 0x03d0,
2220	.enable_mask = BIT(0),
2221	.hw.init = &(struct clk_init_data){
2222	.name = "gcc_usb30_mock_utmi_clk",
2223	.parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2224	.num_parents = 1,
2225	.flags = CLK_SET_RATE_PARENT,
2226	.ops = &clk_branch2_ops,
2227	},
2228	},
2229	};
2230
2231	static struct clk_branch gcc_usb30_sleep_clk = {
2232	.halt_reg = 0x03cc,
2233	.clkr = {
2234	.enable_reg = 0x03cc,
2235	.enable_mask = BIT(0),
2236	.hw.init = &(struct clk_init_data){
2237	.name = "gcc_usb30_sleep_clk",
2238	.parent_data = &(const struct clk_parent_data){
2239	.fw_name = "sleep",
2240	.name = "sleep"
2241	},
2242	.num_parents = 1,
2243	.ops = &clk_branch2_ops,
2244	},
2245	},
2246	};
2247
2248	static struct clk_branch gcc_usb3_phy_aux_clk = {
2249	.halt_reg = 0x1408,
2250	.clkr = {
2251	.enable_reg = 0x1408,
2252	.enable_mask = BIT(0),
2253	.hw.init = &(struct clk_init_data){
2254	.name = "gcc_usb3_phy_aux_clk",
2255	.parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2256	.num_parents = 1,
2257	.flags = CLK_SET_RATE_PARENT,
2258	.ops = &clk_branch2_ops,
2259	},
2260	},
2261	};
2262
2263	static struct clk_branch gcc_usb3_phy_pipe_clk = {
2264	.halt_reg = 0x140c,
2265	.halt_check = BRANCH_HALT_SKIP,
2266	.clkr = {
2267	.enable_reg = 0x140c,
2268	.enable_mask = BIT(0),
2269	.hw.init = &(struct clk_init_data){
2270	.name = "gcc_usb3_phy_pipe_clk",
2271	.ops = &clk_branch2_ops,
2272	},
2273	},
2274	};
2275
2276	static struct clk_branch gcc_usb_hs_ahb_clk = {
2277	.halt_reg = 0x0488,
2278	.clkr = {
2279	.enable_reg = 0x0488,
2280	.enable_mask = BIT(0),
2281	.hw.init = &(struct clk_init_data){
2282	.name = "gcc_usb_hs_ahb_clk",
2283	.ops = &clk_branch2_ops,
2284	},
2285	},
2286	};
2287
2288	static struct clk_branch gcc_usb_hs_system_clk = {
2289	.halt_reg = 0x0484,
2290	.clkr = {
2291	.enable_reg = 0x0484,
2292	.enable_mask = BIT(0),
2293	.hw.init = &(struct clk_init_data){
2294	.name = "gcc_usb_hs_system_clk",
2295	.parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2296	.num_parents = 1,
2297	.flags = CLK_SET_RATE_PARENT,
2298	.ops = &clk_branch2_ops,
2299	},
2300	},
2301	};
2302
2303	static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2304	.halt_reg = 0x1a84,
2305	.clkr = {
2306	.enable_reg = 0x1a84,
2307	.enable_mask = BIT(0),
2308	.hw.init = &(struct clk_init_data){
2309	.name = "gcc_usb_phy_cfg_ahb2phy_clk",
2310	.ops = &clk_branch2_ops,
2311	},
2312	},
2313	};
2314
2315	static struct clk_branch gpll0_out_mmsscc = {
2316	.halt_check = BRANCH_HALT_DELAY,
2317	.clkr = {
2318	.enable_reg = 0x1484,
2319	.enable_mask = BIT(26),
2320	.hw.init = &(struct clk_init_data){
2321	.name = "gpll0_out_mmsscc",
2322	.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2323	.num_parents = 1,
2324	.ops = &clk_branch2_ops,
2325	},
2326	},
2327	};
2328
2329	static struct clk_branch gpll0_out_msscc = {
2330	.halt_check = BRANCH_HALT_DELAY,
2331	.clkr = {
2332	.enable_reg = 0x1484,
2333	.enable_mask = BIT(27),
2334	.hw.init = &(struct clk_init_data){
2335	.name = "gpll0_out_msscc",
2336	.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2337	.num_parents = 1,
2338	.ops = &clk_branch2_ops,
2339	},
2340	},
2341	};
2342
2343	static struct clk_branch pcie_0_phy_ldo = {
2344	.halt_reg = 0x1e00,
2345	.halt_check = BRANCH_HALT_SKIP,
2346	.clkr = {
2347	.enable_reg = 0x1E00,
2348	.enable_mask = BIT(0),
2349	.hw.init = &(struct clk_init_data){
2350	.name = "pcie_0_phy_ldo",
2351	.ops = &clk_branch2_ops,
2352	},
2353	},
2354	};
2355
2356	static struct clk_branch pcie_1_phy_ldo = {
2357	.halt_reg = 0x1e04,
2358	.halt_check = BRANCH_HALT_SKIP,
2359	.clkr = {
2360	.enable_reg = 0x1E04,
2361	.enable_mask = BIT(0),
2362	.hw.init = &(struct clk_init_data){
2363	.name = "pcie_1_phy_ldo",
2364	.ops = &clk_branch2_ops,
2365	},
2366	},
2367	};
2368
2369	static struct clk_branch ufs_phy_ldo = {
2370	.halt_reg = 0x1e0c,
2371	.halt_check = BRANCH_HALT_SKIP,
2372	.clkr = {
2373	.enable_reg = 0x1E0C,
2374	.enable_mask = BIT(0),
2375	.hw.init = &(struct clk_init_data){
2376	.name = "ufs_phy_ldo",
2377	.ops = &clk_branch2_ops,
2378	},
2379	},
2380	};
2381
2382	static struct clk_branch usb_ss_phy_ldo = {
2383	.halt_reg = 0x1e08,
2384	.halt_check = BRANCH_HALT_SKIP,
2385	.clkr = {
2386	.enable_reg = 0x1E08,
2387	.enable_mask = BIT(0),
2388	.hw.init = &(struct clk_init_data){
2389	.name = "usb_ss_phy_ldo",
2390	.ops = &clk_branch2_ops,
2391	},
2392	},
2393	};
2394
2395	static struct clk_branch gcc_boot_rom_ahb_clk = {
2396	.halt_reg = 0x0e04,
2397	.halt_check = BRANCH_HALT_VOTED,
2398	.hwcg_reg = 0x0e04,
2399	.hwcg_bit = 1,
2400	.clkr = {
2401	.enable_reg = 0x1484,
2402	.enable_mask = BIT(10),
2403	.hw.init = &(struct clk_init_data){
2404	.name = "gcc_boot_rom_ahb_clk",
2405	.ops = &clk_branch2_ops,
2406	},
2407	},
2408	};
2409
2410	static struct clk_branch gcc_prng_ahb_clk = {
2411	.halt_reg = 0x0d04,
2412	.halt_check = BRANCH_HALT_VOTED,
2413	.clkr = {
2414	.enable_reg = 0x1484,
2415	.enable_mask = BIT(13),
2416	.hw.init = &(struct clk_init_data){
2417	.name = "gcc_prng_ahb_clk",
2418	.ops = &clk_branch2_ops,
2419	},
2420	},
2421	};
2422
2423	static struct gdsc pcie_0_gdsc = {
2424	.gdscr = 0x1ac4,
2425	.pd = {
2426	.name = "pcie_0",
2427	},
2428	.pwrsts = PWRSTS_OFF_ON,
2429	};
2430
2431	static struct gdsc pcie_1_gdsc = {
2432	.gdscr = 0x1b44,
2433	.pd = {
2434	.name = "pcie_1",
2435	},
2436	.pwrsts = PWRSTS_OFF_ON,
2437	};
2438
2439	static struct gdsc usb30_gdsc = {
2440	.gdscr = 0x3c4,
2441	.pd = {
2442	.name = "usb30",
2443	},
2444	.pwrsts = PWRSTS_OFF_ON,
2445	};
2446
2447	static struct gdsc ufs_gdsc = {
2448	.gdscr = 0x1d44,
2449	.pd = {
2450	.name = "ufs",
2451	},
2452	.pwrsts = PWRSTS_OFF_ON,
2453	};
2454
2455	static struct clk_regmap *gcc_msm8994_clocks[] = {
2456	[GPLL0_EARLY] = &gpll0_early.clkr,
2457	[GPLL0] = &gpll0.clkr,
2458	[GPLL4_EARLY] = &gpll4_early.clkr,
2459	[GPLL4] = &gpll4.clkr,
2460	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2461	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2462	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2463	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2464	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2465	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2466	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2467	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2468	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2469	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2470	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2471	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2472	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2473	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2474	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2475	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2476	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2477	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2478	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2479	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2480	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2481	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2482	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2483	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2484	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2485	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2486	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2487	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2488	[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2489	[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2490	[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2491	[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2492	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2493	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2494	[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2495	[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2496	[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2497	[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2498	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
2499	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
2500	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
2501	[PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2502	[PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2503	[PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2504	[PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2505	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2506	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2507	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2508	[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2509	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2510	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2511	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2512	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2513	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2514	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2515	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2516	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2517	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2518	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2519	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2520	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2521	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2522	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2523	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2524	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2525	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2526	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2527	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2528	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2529	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2530	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2531	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2532	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2533	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2534	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2535	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2536	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2537	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2538	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2539	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2540	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2541	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2542	[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2543	[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2544	[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2545	[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2546	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2547	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2548	[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2549	[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2550	[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2551	[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2552	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2553	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2554	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2555	[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2556	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2557	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2558	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2559	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2560	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2561	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2562	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2563	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2564	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2565	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2566	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2567	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2568	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2569	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2570	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2571	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2572	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2573	[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2574	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2575	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2576	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2577	[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2578	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2579	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2580	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2581	[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2582	[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2583	[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2584	[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2585	[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2586	[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2587	[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2588	[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2589	[GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2590	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2591	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2592	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2593	[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2594	[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2595	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2596	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2597	[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2598	[GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2599	[GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2600	[PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2601	[PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2602	[UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2603	[USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2604	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2605	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2606
2607	/*
2608	* The following clocks should NOT be managed by this driver, but they once were
2609	* mistakengly added. Now they are only here to indicate that they are not defined
2610	* on purpose, even though the names will stay in the header file (for ABI sanity).
2611	*/
2612	[CONFIG_NOC_CLK_SRC] = NULL,
2613	[PERIPH_NOC_CLK_SRC] = NULL,
2614	[SYSTEM_NOC_CLK_SRC] = NULL,
2615	};
2616
2617	static struct gdsc *gcc_msm8994_gdscs[] = {
2618	/* This GDSC does not exist, but ABI has to remain intact */
2619	[PCIE_GDSC] = NULL,
2620	[PCIE_0_GDSC] = &pcie_0_gdsc,
2621	[PCIE_1_GDSC] = &pcie_1_gdsc,
2622	[USB30_GDSC] = &usb30_gdsc,
2623	[UFS_GDSC] = &ufs_gdsc,
2624	};
2625
2626	static const struct qcom_reset_map gcc_msm8994_resets[] = {
2627	[USB3_PHY_RESET] = { 0x1400 },
2628	[USB3PHY_PHY_RESET] = { 0x1404 },
2629	[MSS_RESET] = { 0x1680 },
2630	[PCIE_PHY_0_RESET] = { 0x1b18 },
2631	[PCIE_PHY_1_RESET] = { 0x1b98 },
2632	[QUSB2_PHY_RESET] = { 0x04b8 },
2633	};
2634
2635	static const struct regmap_config gcc_msm8994_regmap_config = {
2636	.reg_bits = 32,
2637	.reg_stride = 4,
2638	.val_bits = 32,
2639	.max_register = 0x2000,
2640	.fast_io = true,
2641	};
2642
2643	static const struct qcom_cc_desc gcc_msm8994_desc = {
2644	.config = &gcc_msm8994_regmap_config,
2645	.clks = gcc_msm8994_clocks,
2646	.num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2647	.resets = gcc_msm8994_resets,
2648	.num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2649	.gdscs = gcc_msm8994_gdscs,
2650	.num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2651	};
2652
2653	static const struct of_device_id gcc_msm8994_match_table[] = {
2654	{ .compatible = "qcom,gcc-msm8992" },
2655	{ .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2656	{}
2657	};
2658	MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2659
2660	static int gcc_msm8994_probe(struct platform_device *pdev)
2661	{
2662	if (of_device_is_compatible(device: pdev->dev.of_node, "qcom,gcc-msm8992")) {
2663	/* MSM8992 features less clocks and some have different freq tables */
2664	gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2665	gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2666	gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2667	gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2668	gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2669	gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2670	gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2671	gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2672	gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2673	gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2674	gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2675
2676	sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2677	blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2678	blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2679	blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2680	blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2681	blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2682	blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2683	blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2684	blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2685	blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2686	blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2687	blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2688	blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2689
2690	/*
2691	* Some 8992 boards might *possibly* use
2692	* PCIe1 clocks and controller, but it's not
2693	* standard and they should be disabled otherwise.
2694	*/
2695	gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2696	gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2697	gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2698	gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2699	gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2700	gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2701	gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2702	gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2703	gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2704	}
2705
2706	return qcom_cc_probe(pdev, desc: &gcc_msm8994_desc);
2707	}
2708
2709	static struct platform_driver gcc_msm8994_driver = {
2710	.probe = gcc_msm8994_probe,
2711	.driver = {
2712	.name = "gcc-msm8994",
2713	.of_match_table = gcc_msm8994_match_table,
2714	},
2715	};
2716
2717	static int __init gcc_msm8994_init(void)
2718	{
2719	return platform_driver_register(&gcc_msm8994_driver);
2720	}
2721	core_initcall(gcc_msm8994_init);
2722
2723	static void __exit gcc_msm8994_exit(void)
2724	{
2725	platform_driver_unregister(&gcc_msm8994_driver);
2726	}
2727	module_exit(gcc_msm8994_exit);
2728
2729	MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2730	MODULE_LICENSE("GPL v2");
2731	MODULE_ALIAS("platform:gcc-msm8994");
2732