1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2020-2021, Linaro Ltd.
5	*/
6
7	#include <linux/bitops.h>
8	#include <linux/clk-provider.h>
9	#include <linux/err.h>
10	#include <linux/kernel.h>
11	#include <linux/module.h>
12	#include <linux/of.h>
13	#include <linux/platform_device.h>
14	#include <linux/regmap.h>
15	#include <linux/reset-controller.h>
16
17	#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
18
19	#include "common.h"
20	#include "clk-alpha-pll.h"
21	#include "clk-branch.h"
22	#include "clk-pll.h"
23	#include "clk-rcg.h"
24	#include "clk-regmap.h"
25	#include "gdsc.h"
26	#include "reset.h"
27
28	enum {
29	P_AUD_REF_CLK,
30	P_BI_TCXO,
31	P_GPLL0_OUT_EVEN,
32	P_GPLL0_OUT_MAIN,
33	P_GPLL1_OUT_MAIN,
34	P_GPLL2_OUT_MAIN,
35	P_GPLL4_OUT_MAIN,
36	P_GPLL5_OUT_MAIN,
37	P_GPLL7_OUT_MAIN,
38	P_GPLL9_OUT_MAIN,
39	P_SLEEP_CLK,
40	};
41
42	static struct pll_vco trion_vco[] = {
43	{ 249600000, 2000000000, 0 },
44	};
45
46	static struct clk_alpha_pll gpll0 = {
47	.offset = 0x0,
48	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
49	.vco_table = trion_vco,
50	.num_vco = ARRAY_SIZE(trion_vco),
51	.clkr = {
52	.enable_reg = 0x52000,
53	.enable_mask = BIT(0),
54	.hw.init = &(struct clk_init_data){
55	.name = "gpll0",
56	.parent_data = &(const struct clk_parent_data){
57	.fw_name = "bi_tcxo",
58	},
59	.num_parents = 1,
60	.ops = &clk_alpha_pll_fixed_trion_ops,
61	},
62	},
63	};
64
65	static const struct clk_div_table post_div_table_trion_even[] = {
66	{ 0x0, 1 },
67	{ 0x1, 2 },
68	{ 0x3, 4 },
69	{ 0x7, 8 },
70	{ }
71	};
72
73	static struct clk_alpha_pll_postdiv gpll0_out_even = {
74	.offset = 0x0,
75	.post_div_shift = 8,
76	.post_div_table = post_div_table_trion_even,
77	.num_post_div = ARRAY_SIZE(post_div_table_trion_even),
78	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
79	.width = 4,
80	.clkr.hw.init = &(struct clk_init_data){
81	.name = "gpll0_out_even",
82	.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
83	.num_parents = 1,
84	.ops = &clk_alpha_pll_postdiv_trion_ops,
85	},
86	};
87
88	static struct clk_alpha_pll gpll1 = {
89	.offset = 0x1000,
90	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
91	.vco_table = trion_vco,
92	.num_vco = ARRAY_SIZE(trion_vco),
93	.clkr = {
94	.enable_reg = 0x52000,
95	.enable_mask = BIT(1),
96	.hw.init = &(struct clk_init_data){
97	.name = "gpll1",
98	.parent_data = &(const struct clk_parent_data){
99	.fw_name = "bi_tcxo",
100	},
101	.num_parents = 1,
102	.ops = &clk_alpha_pll_fixed_trion_ops,
103	},
104	},
105	};
106
107	static struct clk_alpha_pll gpll4 = {
108	.offset = 0x76000,
109	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
110	.vco_table = trion_vco,
111	.num_vco = ARRAY_SIZE(trion_vco),
112	.clkr = {
113	.enable_reg = 0x52000,
114	.enable_mask = BIT(4),
115	.hw.init = &(struct clk_init_data){
116	.name = "gpll4",
117	.parent_data = &(const struct clk_parent_data){
118	.fw_name = "bi_tcxo",
119	},
120	.num_parents = 1,
121	.ops = &clk_alpha_pll_fixed_trion_ops,
122	},
123	},
124	};
125
126	static struct clk_alpha_pll gpll7 = {
127	.offset = 0x1a000,
128	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
129	.vco_table = trion_vco,
130	.num_vco = ARRAY_SIZE(trion_vco),
131	.clkr = {
132	.enable_reg = 0x52000,
133	.enable_mask = BIT(7),
134	.hw.init = &(struct clk_init_data){
135	.name = "gpll7",
136	.parent_data = &(const struct clk_parent_data){
137	.fw_name = "bi_tcxo",
138	},
139	.num_parents = 1,
140	.ops = &clk_alpha_pll_fixed_trion_ops,
141	},
142	},
143	};
144
145	static const struct parent_map gcc_parent_map_0[] = {
146	{ P_BI_TCXO, 0 },
147	{ P_GPLL0_OUT_MAIN, 1 },
148	{ P_GPLL0_OUT_EVEN, 6 },
149	};
150
151	static const struct clk_parent_data gcc_parents_0[] = {
152	{ .fw_name = "bi_tcxo" },
153	{ .hw = &gpll0.clkr.hw },
154	{ .hw = &gpll0_out_even.clkr.hw },
155	};
156
157	static const struct parent_map gcc_parent_map_1[] = {
158	{ P_BI_TCXO, 0 },
159	{ P_GPLL0_OUT_MAIN, 1 },
160	{ P_SLEEP_CLK, 5 },
161	{ P_GPLL0_OUT_EVEN, 6 },
162	};
163
164	static const struct clk_parent_data gcc_parents_1[] = {
165	{ .fw_name = "bi_tcxo", },
166	{ .hw = &gpll0.clkr.hw },
167	{ .fw_name = "sleep_clk", },
168	{ .hw = &gpll0_out_even.clkr.hw },
169	};
170
171	static const struct parent_map gcc_parent_map_2[] = {
172	{ P_BI_TCXO, 0 },
173	{ P_SLEEP_CLK, 5 },
174	};
175
176	static const struct clk_parent_data gcc_parents_2[] = {
177	{ .fw_name = "bi_tcxo", },
178	{ .fw_name = "sleep_clk", },
179	};
180
181	static const struct parent_map gcc_parent_map_3[] = {
182	{ P_BI_TCXO, 0 },
183	{ P_GPLL0_OUT_MAIN, 1 },
184	{ P_GPLL2_OUT_MAIN, 2 },
185	{ P_GPLL5_OUT_MAIN, 3 },
186	{ P_GPLL1_OUT_MAIN, 4 },
187	{ P_GPLL4_OUT_MAIN, 5 },
188	{ P_GPLL0_OUT_EVEN, 6 },
189	};
190
191	static const struct clk_parent_data gcc_parents_3[] = {
192	{ .fw_name = "bi_tcxo", },
193	{ .hw = &gpll0.clkr.hw },
194	{ .name = "gpll2" },
195	{ .name = "gpll5" },
196	{ .hw = &gpll1.clkr.hw },
197	{ .hw = &gpll4.clkr.hw },
198	{ .hw = &gpll0_out_even.clkr.hw },
199	};
200
201	static const struct parent_map gcc_parent_map_4[] = {
202	{ P_BI_TCXO, 0 },
203	};
204
205	static const struct clk_parent_data gcc_parents_4[] = {
206	{ .fw_name = "bi_tcxo", },
207	};
208
209	static const struct parent_map gcc_parent_map_5[] = {
210	{ P_BI_TCXO, 0 },
211	{ P_GPLL0_OUT_MAIN, 1 },
212	};
213
214	static const struct clk_parent_data gcc_parents_5[] = {
215	{ .fw_name = "bi_tcxo", },
216	{ .hw = &gpll0.clkr.hw },
217	};
218
219	static const struct parent_map gcc_parent_map_6[] = {
220	{ P_BI_TCXO, 0 },
221	{ P_GPLL0_OUT_MAIN, 1 },
222	{ P_GPLL7_OUT_MAIN, 3 },
223	{ P_GPLL0_OUT_EVEN, 6 },
224	};
225
226	static const struct clk_parent_data gcc_parents_6[] = {
227	{ .fw_name = "bi_tcxo", },
228	{ .hw = &gpll0.clkr.hw },
229	{ .hw = &gpll7.clkr.hw },
230	{ .hw = &gpll0_out_even.clkr.hw },
231	};
232
233	static const struct parent_map gcc_parent_map_7[] = {
234	{ P_BI_TCXO, 0 },
235	{ P_GPLL0_OUT_MAIN, 1 },
236	{ P_GPLL9_OUT_MAIN, 2 },
237	{ P_GPLL4_OUT_MAIN, 5 },
238	{ P_GPLL0_OUT_EVEN, 6 },
239	};
240
241	static const struct clk_parent_data gcc_parents_7[] = {
242	{ .fw_name = "bi_tcxo", },
243	{ .hw = &gpll0.clkr.hw },
244	{ .name = "gppl9" },
245	{ .hw = &gpll4.clkr.hw },
246	{ .hw = &gpll0_out_even.clkr.hw },
247	};
248
249	static const struct parent_map gcc_parent_map_8[] = {
250	{ P_BI_TCXO, 0 },
251	{ P_GPLL0_OUT_MAIN, 1 },
252	{ P_AUD_REF_CLK, 2 },
253	{ P_GPLL0_OUT_EVEN, 6 },
254	};
255
256	static const struct clk_parent_data gcc_parents_8[] = {
257	{ .fw_name = "bi_tcxo", },
258	{ .hw = &gpll0.clkr.hw },
259	{ .name = "aud_ref_clk" },
260	{ .hw = &gpll0_out_even.clkr.hw },
261	};
262
263	static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
264	F(19200000, P_BI_TCXO, 1, 0, 0),
265	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
266	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
267	{ }
268	};
269
270	static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
271	.cmd_rcgr = 0x48014,
272	.mnd_width = 0,
273	.hid_width = 5,
274	.parent_map = gcc_parent_map_0,
275	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
276	.clkr.hw.init = &(struct clk_init_data){
277	.name = "gcc_cpuss_ahb_clk_src",
278	.parent_data = gcc_parents_0,
279	.num_parents = ARRAY_SIZE(gcc_parents_0),
280	.flags = CLK_SET_RATE_PARENT,
281	.ops = &clk_rcg2_ops,
282	},
283	};
284
285	static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
286	F(19200000, P_BI_TCXO, 1, 0, 0),
287	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
288	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
289	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
290	{ }
291	};
292
293	static struct clk_rcg2 gcc_emac_ptp_clk_src = {
294	.cmd_rcgr = 0x6038,
295	.mnd_width = 0,
296	.hid_width = 5,
297	.parent_map = gcc_parent_map_6,
298	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
299	.clkr.hw.init = &(struct clk_init_data){
300	.name = "gcc_emac_ptp_clk_src",
301	.parent_data = gcc_parents_6,
302	.num_parents = ARRAY_SIZE(gcc_parents_6),
303	.flags = CLK_SET_RATE_PARENT,
304	.ops = &clk_rcg2_ops,
305	},
306	};
307
308	static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
309	F(2500000, P_BI_TCXO, 1, 25, 192),
310	F(5000000, P_BI_TCXO, 1, 25, 96),
311	F(19200000, P_BI_TCXO, 1, 0, 0),
312	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
313	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
314	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
315	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
316	{ }
317	};
318
319	static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
320	.cmd_rcgr = 0x601c,
321	.mnd_width = 8,
322	.hid_width = 5,
323	.parent_map = gcc_parent_map_6,
324	.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
325	.clkr.hw.init = &(struct clk_init_data){
326	.name = "gcc_emac_rgmii_clk_src",
327	.parent_data = gcc_parents_6,
328	.num_parents = ARRAY_SIZE(gcc_parents_6),
329	.flags = CLK_SET_RATE_PARENT,
330	.ops = &clk_rcg2_ops,
331	},
332	};
333
334	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
335	F(19200000, P_BI_TCXO, 1, 0, 0),
336	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
337	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
338	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
339	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
340	{ }
341	};
342
343	static struct clk_rcg2 gcc_gp1_clk_src = {
344	.cmd_rcgr = 0x64004,
345	.mnd_width = 8,
346	.hid_width = 5,
347	.parent_map = gcc_parent_map_1,
348	.freq_tbl = ftbl_gcc_gp1_clk_src,
349	.clkr.hw.init = &(struct clk_init_data){
350	.name = "gcc_gp1_clk_src",
351	.parent_data = gcc_parents_1,
352	.num_parents = ARRAY_SIZE(gcc_parents_1),
353	.flags = CLK_SET_RATE_PARENT,
354	.ops = &clk_rcg2_ops,
355	},
356	};
357
358	static struct clk_rcg2 gcc_gp2_clk_src = {
359	.cmd_rcgr = 0x65004,
360	.mnd_width = 8,
361	.hid_width = 5,
362	.parent_map = gcc_parent_map_1,
363	.freq_tbl = ftbl_gcc_gp1_clk_src,
364	.clkr.hw.init = &(struct clk_init_data){
365	.name = "gcc_gp2_clk_src",
366	.parent_data = gcc_parents_1,
367	.num_parents = ARRAY_SIZE(gcc_parents_1),
368	.flags = CLK_SET_RATE_PARENT,
369	.ops = &clk_rcg2_ops,
370	},
371	};
372
373	static struct clk_rcg2 gcc_gp3_clk_src = {
374	.cmd_rcgr = 0x66004,
375	.mnd_width = 8,
376	.hid_width = 5,
377	.parent_map = gcc_parent_map_1,
378	.freq_tbl = ftbl_gcc_gp1_clk_src,
379	.clkr.hw.init = &(struct clk_init_data){
380	.name = "gcc_gp3_clk_src",
381	.parent_data = gcc_parents_1,
382	.num_parents = ARRAY_SIZE(gcc_parents_1),
383	.flags = CLK_SET_RATE_PARENT,
384	.ops = &clk_rcg2_ops,
385	},
386	};
387
388	static struct clk_rcg2 gcc_gp4_clk_src = {
389	.cmd_rcgr = 0xbe004,
390	.mnd_width = 8,
391	.hid_width = 5,
392	.parent_map = gcc_parent_map_1,
393	.freq_tbl = ftbl_gcc_gp1_clk_src,
394	.clkr.hw.init = &(struct clk_init_data){
395	.name = "gcc_gp4_clk_src",
396	.parent_data = gcc_parents_1,
397	.num_parents = ARRAY_SIZE(gcc_parents_1),
398	.flags = CLK_SET_RATE_PARENT,
399	.ops = &clk_rcg2_ops,
400	},
401	};
402
403	static struct clk_rcg2 gcc_gp5_clk_src = {
404	.cmd_rcgr = 0xbf004,
405	.mnd_width = 8,
406	.hid_width = 5,
407	.parent_map = gcc_parent_map_1,
408	.freq_tbl = ftbl_gcc_gp1_clk_src,
409	.clkr.hw.init = &(struct clk_init_data){
410	.name = "gcc_gp5_clk_src",
411	.parent_data = gcc_parents_1,
412	.num_parents = ARRAY_SIZE(gcc_parents_1),
413	.flags = CLK_SET_RATE_PARENT,
414	.ops = &clk_rcg2_ops,
415	},
416	};
417
418	static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {
419	F(19200000, P_BI_TCXO, 1, 0, 0),
420	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
421	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
422	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
423	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
424	F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
425	F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
426	{ }
427	};
428
429	static struct clk_rcg2 gcc_npu_axi_clk_src = {
430	.cmd_rcgr = 0x4d014,
431	.mnd_width = 0,
432	.hid_width = 5,
433	.parent_map = gcc_parent_map_3,
434	.freq_tbl = ftbl_gcc_npu_axi_clk_src,
435	.clkr.hw.init = &(struct clk_init_data){
436	.name = "gcc_npu_axi_clk_src",
437	.parent_data = gcc_parents_3,
438	.num_parents = ARRAY_SIZE(gcc_parents_3),
439	.flags = CLK_SET_RATE_PARENT,
440	.ops = &clk_rcg2_ops,
441	},
442	};
443
444	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
445	F(9600000, P_BI_TCXO, 2, 0, 0),
446	F(19200000, P_BI_TCXO, 1, 0, 0),
447	{ }
448	};
449
450	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
451	.cmd_rcgr = 0x6b02c,
452	.mnd_width = 16,
453	.hid_width = 5,
454	.parent_map = gcc_parent_map_2,
455	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
456	.clkr.hw.init = &(struct clk_init_data){
457	.name = "gcc_pcie_0_aux_clk_src",
458	.parent_data = gcc_parents_2,
459	.num_parents = ARRAY_SIZE(gcc_parents_2),
460	.flags = CLK_SET_RATE_PARENT,
461	.ops = &clk_rcg2_ops,
462	},
463	};
464
465	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
466	.cmd_rcgr = 0x8d02c,
467	.mnd_width = 16,
468	.hid_width = 5,
469	.parent_map = gcc_parent_map_2,
470	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
471	.clkr.hw.init = &(struct clk_init_data){
472	.name = "gcc_pcie_1_aux_clk_src",
473	.parent_data = gcc_parents_2,
474	.num_parents = ARRAY_SIZE(gcc_parents_2),
475	.flags = CLK_SET_RATE_PARENT,
476	.ops = &clk_rcg2_ops,
477	},
478	};
479
480	static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
481	.cmd_rcgr = 0x9d02c,
482	.mnd_width = 16,
483	.hid_width = 5,
484	.parent_map = gcc_parent_map_2,
485	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
486	.clkr.hw.init = &(struct clk_init_data){
487	.name = "gcc_pcie_2_aux_clk_src",
488	.parent_data = gcc_parents_2,
489	.num_parents = ARRAY_SIZE(gcc_parents_2),
490	.flags = CLK_SET_RATE_PARENT,
491	.ops = &clk_rcg2_ops,
492	},
493	};
494
495	static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
496	.cmd_rcgr = 0xa302c,
497	.mnd_width = 16,
498	.hid_width = 5,
499	.parent_map = gcc_parent_map_2,
500	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
501	.clkr.hw.init = &(struct clk_init_data){
502	.name = "gcc_pcie_3_aux_clk_src",
503	.parent_data = gcc_parents_2,
504	.num_parents = ARRAY_SIZE(gcc_parents_2),
505	.flags = CLK_SET_RATE_PARENT,
506	.ops = &clk_rcg2_ops,
507	},
508	};
509
510	static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
511	F(19200000, P_BI_TCXO, 1, 0, 0),
512	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
513	{ }
514	};
515
516	static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
517	.cmd_rcgr = 0x6f014,
518	.mnd_width = 0,
519	.hid_width = 5,
520	.parent_map = gcc_parent_map_0,
521	.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
522	.clkr.hw.init = &(struct clk_init_data){
523	.name = "gcc_pcie_phy_refgen_clk_src",
524	.parent_data = gcc_parents_0,
525	.num_parents = ARRAY_SIZE(gcc_parents_0),
526	.flags = CLK_SET_RATE_PARENT,
527	.ops = &clk_rcg2_ops,
528	},
529	};
530
531	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
532	F(9600000, P_BI_TCXO, 2, 0, 0),
533	F(19200000, P_BI_TCXO, 1, 0, 0),
534	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
535	{ }
536	};
537
538	static struct clk_rcg2 gcc_pdm2_clk_src = {
539	.cmd_rcgr = 0x33010,
540	.mnd_width = 0,
541	.hid_width = 5,
542	.parent_map = gcc_parent_map_0,
543	.freq_tbl = ftbl_gcc_pdm2_clk_src,
544	.clkr.hw.init = &(struct clk_init_data){
545	.name = "gcc_pdm2_clk_src",
546	.parent_data = gcc_parents_0,
547	.num_parents = ARRAY_SIZE(gcc_parents_0),
548	.flags = CLK_SET_RATE_PARENT,
549	.ops = &clk_rcg2_ops,
550	},
551	};
552
553	static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = {
554	F(19200000, P_BI_TCXO, 1, 0, 0),
555	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
556	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
557	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
558	{ }
559	};
560
561	static struct clk_rcg2 gcc_qspi_1_core_clk_src = {
562	.cmd_rcgr = 0x4a00c,
563	.mnd_width = 0,
564	.hid_width = 5,
565	.parent_map = gcc_parent_map_0,
566	.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
567	.clkr.hw.init = &(struct clk_init_data){
568	.name = "gcc_qspi_1_core_clk_src",
569	.parent_data = gcc_parents_0,
570	.num_parents = ARRAY_SIZE(gcc_parents_0),
571	.flags = CLK_SET_RATE_PARENT,
572	.ops = &clk_rcg2_ops,
573	},
574	};
575
576	static struct clk_rcg2 gcc_qspi_core_clk_src = {
577	.cmd_rcgr = 0x4b008,
578	.mnd_width = 0,
579	.hid_width = 5,
580	.parent_map = gcc_parent_map_0,
581	.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
582	.clkr.hw.init = &(struct clk_init_data){
583	.name = "gcc_qspi_core_clk_src",
584	.parent_data = gcc_parents_0,
585	.num_parents = ARRAY_SIZE(gcc_parents_0),
586	.flags = CLK_SET_RATE_PARENT,
587	.ops = &clk_rcg2_ops,
588	},
589	};
590
591	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
592	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
593	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
594	F(19200000, P_BI_TCXO, 1, 0, 0),
595	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
596	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
597	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
598	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
599	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
600	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
601	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
602	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
603	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
604	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
605	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
606	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
607	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
608	F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
609	{ }
610	};
611
612	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
613	.cmd_rcgr = 0x17148,
614	.mnd_width = 16,
615	.hid_width = 5,
616	.parent_map = gcc_parent_map_0,
617	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
618	.clkr.hw.init = &(struct clk_init_data){
619	.name = "gcc_qupv3_wrap0_s0_clk_src",
620	.parent_data = gcc_parents_0,
621	.num_parents = ARRAY_SIZE(gcc_parents_0),
622	.flags = CLK_SET_RATE_PARENT,
623	.ops = &clk_rcg2_ops,
624	},
625	};
626
627	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
628	.cmd_rcgr = 0x17278,
629	.mnd_width = 16,
630	.hid_width = 5,
631	.parent_map = gcc_parent_map_0,
632	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
633	.clkr.hw.init = &(struct clk_init_data){
634	.name = "gcc_qupv3_wrap0_s1_clk_src",
635	.parent_data = gcc_parents_0,
636	.num_parents = ARRAY_SIZE(gcc_parents_0),
637	.flags = CLK_SET_RATE_PARENT,
638	.ops = &clk_rcg2_ops,
639	},
640	};
641
642	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
643	.cmd_rcgr = 0x173a8,
644	.mnd_width = 16,
645	.hid_width = 5,
646	.parent_map = gcc_parent_map_0,
647	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
648	.clkr.hw.init = &(struct clk_init_data){
649	.name = "gcc_qupv3_wrap0_s2_clk_src",
650	.parent_data = gcc_parents_0,
651	.num_parents = ARRAY_SIZE(gcc_parents_0),
652	.flags = CLK_SET_RATE_PARENT,
653	.ops = &clk_rcg2_ops,
654	},
655	};
656
657	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
658	.cmd_rcgr = 0x174d8,
659	.mnd_width = 16,
660	.hid_width = 5,
661	.parent_map = gcc_parent_map_0,
662	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
663	.clkr.hw.init = &(struct clk_init_data){
664	.name = "gcc_qupv3_wrap0_s3_clk_src",
665	.parent_data = gcc_parents_0,
666	.num_parents = ARRAY_SIZE(gcc_parents_0),
667	.flags = CLK_SET_RATE_PARENT,
668	.ops = &clk_rcg2_ops,
669	},
670	};
671
672	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
673	.cmd_rcgr = 0x17608,
674	.mnd_width = 16,
675	.hid_width = 5,
676	.parent_map = gcc_parent_map_0,
677	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
678	.clkr.hw.init = &(struct clk_init_data){
679	.name = "gcc_qupv3_wrap0_s4_clk_src",
680	.parent_data = gcc_parents_0,
681	.num_parents = ARRAY_SIZE(gcc_parents_0),
682	.flags = CLK_SET_RATE_PARENT,
683	.ops = &clk_rcg2_ops,
684	},
685	};
686
687	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
688	.cmd_rcgr = 0x17738,
689	.mnd_width = 16,
690	.hid_width = 5,
691	.parent_map = gcc_parent_map_0,
692	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
693	.clkr.hw.init = &(struct clk_init_data){
694	.name = "gcc_qupv3_wrap0_s5_clk_src",
695	.parent_data = gcc_parents_0,
696	.num_parents = ARRAY_SIZE(gcc_parents_0),
697	.flags = CLK_SET_RATE_PARENT,
698	.ops = &clk_rcg2_ops,
699	},
700	};
701
702	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
703	.cmd_rcgr = 0x17868,
704	.mnd_width = 16,
705	.hid_width = 5,
706	.parent_map = gcc_parent_map_0,
707	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
708	.clkr.hw.init = &(struct clk_init_data){
709	.name = "gcc_qupv3_wrap0_s6_clk_src",
710	.parent_data = gcc_parents_0,
711	.num_parents = ARRAY_SIZE(gcc_parents_0),
712	.flags = CLK_SET_RATE_PARENT,
713	.ops = &clk_rcg2_ops,
714	},
715	};
716
717	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
718	.cmd_rcgr = 0x17998,
719	.mnd_width = 16,
720	.hid_width = 5,
721	.parent_map = gcc_parent_map_0,
722	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
723	.clkr.hw.init = &(struct clk_init_data){
724	.name = "gcc_qupv3_wrap0_s7_clk_src",
725	.parent_data = gcc_parents_0,
726	.num_parents = ARRAY_SIZE(gcc_parents_0),
727	.flags = CLK_SET_RATE_PARENT,
728	.ops = &clk_rcg2_ops,
729	},
730	};
731
732	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
733	.cmd_rcgr = 0x18148,
734	.mnd_width = 16,
735	.hid_width = 5,
736	.parent_map = gcc_parent_map_0,
737	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
738	.clkr.hw.init = &(struct clk_init_data){
739	.name = "gcc_qupv3_wrap1_s0_clk_src",
740	.parent_data = gcc_parents_0,
741	.num_parents = ARRAY_SIZE(gcc_parents_0),
742	.flags = CLK_SET_RATE_PARENT,
743	.ops = &clk_rcg2_ops,
744	},
745	};
746
747	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
748	.cmd_rcgr = 0x18278,
749	.mnd_width = 16,
750	.hid_width = 5,
751	.parent_map = gcc_parent_map_0,
752	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
753	.clkr.hw.init = &(struct clk_init_data){
754	.name = "gcc_qupv3_wrap1_s1_clk_src",
755	.parent_data = gcc_parents_0,
756	.num_parents = ARRAY_SIZE(gcc_parents_0),
757	.flags = CLK_SET_RATE_PARENT,
758	.ops = &clk_rcg2_ops,
759	},
760	};
761
762	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
763	.cmd_rcgr = 0x183a8,
764	.mnd_width = 16,
765	.hid_width = 5,
766	.parent_map = gcc_parent_map_0,
767	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
768	.clkr.hw.init = &(struct clk_init_data){
769	.name = "gcc_qupv3_wrap1_s2_clk_src",
770	.parent_data = gcc_parents_0,
771	.num_parents = ARRAY_SIZE(gcc_parents_0),
772	.flags = CLK_SET_RATE_PARENT,
773	.ops = &clk_rcg2_ops,
774	},
775	};
776
777	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
778	.cmd_rcgr = 0x184d8,
779	.mnd_width = 16,
780	.hid_width = 5,
781	.parent_map = gcc_parent_map_0,
782	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
783	.clkr.hw.init = &(struct clk_init_data){
784	.name = "gcc_qupv3_wrap1_s3_clk_src",
785	.parent_data = gcc_parents_0,
786	.num_parents = ARRAY_SIZE(gcc_parents_0),
787	.flags = CLK_SET_RATE_PARENT,
788	.ops = &clk_rcg2_ops,
789	},
790	};
791
792	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
793	.cmd_rcgr = 0x18608,
794	.mnd_width = 16,
795	.hid_width = 5,
796	.parent_map = gcc_parent_map_0,
797	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
798	.clkr.hw.init = &(struct clk_init_data){
799	.name = "gcc_qupv3_wrap1_s4_clk_src",
800	.parent_data = gcc_parents_0,
801	.num_parents = ARRAY_SIZE(gcc_parents_0),
802	.flags = CLK_SET_RATE_PARENT,
803	.ops = &clk_rcg2_ops,
804	},
805	};
806
807	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
808	.cmd_rcgr = 0x18738,
809	.mnd_width = 16,
810	.hid_width = 5,
811	.parent_map = gcc_parent_map_0,
812	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
813	.clkr.hw.init = &(struct clk_init_data){
814	.name = "gcc_qupv3_wrap1_s5_clk_src",
815	.parent_data = gcc_parents_0,
816	.num_parents = ARRAY_SIZE(gcc_parents_0),
817	.flags = CLK_SET_RATE_PARENT,
818	.ops = &clk_rcg2_ops,
819	},
820	};
821
822	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
823	.cmd_rcgr = 0x1e148,
824	.mnd_width = 16,
825	.hid_width = 5,
826	.parent_map = gcc_parent_map_0,
827	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
828	.clkr.hw.init = &(struct clk_init_data){
829	.name = "gcc_qupv3_wrap2_s0_clk_src",
830	.parent_data = gcc_parents_0,
831	.num_parents = ARRAY_SIZE(gcc_parents_0),
832	.flags = CLK_SET_RATE_PARENT,
833	.ops = &clk_rcg2_ops,
834	},
835	};
836
837	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
838	.cmd_rcgr = 0x1e278,
839	.mnd_width = 16,
840	.hid_width = 5,
841	.parent_map = gcc_parent_map_0,
842	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
843	.clkr.hw.init = &(struct clk_init_data){
844	.name = "gcc_qupv3_wrap2_s1_clk_src",
845	.parent_data = gcc_parents_0,
846	.num_parents = ARRAY_SIZE(gcc_parents_0),
847	.flags = CLK_SET_RATE_PARENT,
848	.ops = &clk_rcg2_ops,
849	},
850	};
851
852	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
853	.cmd_rcgr = 0x1e3a8,
854	.mnd_width = 16,
855	.hid_width = 5,
856	.parent_map = gcc_parent_map_0,
857	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
858	.clkr.hw.init = &(struct clk_init_data){
859	.name = "gcc_qupv3_wrap2_s2_clk_src",
860	.parent_data = gcc_parents_0,
861	.num_parents = ARRAY_SIZE(gcc_parents_0),
862	.flags = CLK_SET_RATE_PARENT,
863	.ops = &clk_rcg2_ops,
864	},
865	};
866
867	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
868	.cmd_rcgr = 0x1e4d8,
869	.mnd_width = 16,
870	.hid_width = 5,
871	.parent_map = gcc_parent_map_0,
872	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
873	.clkr.hw.init = &(struct clk_init_data){
874	.name = "gcc_qupv3_wrap2_s3_clk_src",
875	.parent_data = gcc_parents_0,
876	.num_parents = ARRAY_SIZE(gcc_parents_0),
877	.flags = CLK_SET_RATE_PARENT,
878	.ops = &clk_rcg2_ops,
879	},
880	};
881
882	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
883	.cmd_rcgr = 0x1e608,
884	.mnd_width = 16,
885	.hid_width = 5,
886	.parent_map = gcc_parent_map_0,
887	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
888	.clkr.hw.init = &(struct clk_init_data){
889	.name = "gcc_qupv3_wrap2_s4_clk_src",
890	.parent_data = gcc_parents_0,
891	.num_parents = ARRAY_SIZE(gcc_parents_0),
892	.flags = CLK_SET_RATE_PARENT,
893	.ops = &clk_rcg2_ops,
894	},
895	};
896
897	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
898	.cmd_rcgr = 0x1e738,
899	.mnd_width = 16,
900	.hid_width = 5,
901	.parent_map = gcc_parent_map_0,
902	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
903	.clkr.hw.init = &(struct clk_init_data){
904	.name = "gcc_qupv3_wrap2_s5_clk_src",
905	.parent_data = gcc_parents_0,
906	.num_parents = ARRAY_SIZE(gcc_parents_0),
907	.flags = CLK_SET_RATE_PARENT,
908	.ops = &clk_rcg2_ops,
909	},
910	};
911
912	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
913	F(400000, P_BI_TCXO, 12, 1, 4),
914	F(9600000, P_BI_TCXO, 2, 0, 0),
915	F(19200000, P_BI_TCXO, 1, 0, 0),
916	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
917	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
918	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
919	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
920	{ }
921	};
922
923	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
924	.cmd_rcgr = 0x1400c,
925	.mnd_width = 8,
926	.hid_width = 5,
927	.parent_map = gcc_parent_map_7,
928	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
929	.clkr.hw.init = &(struct clk_init_data){
930	.name = "gcc_sdcc2_apps_clk_src",
931	.parent_data = gcc_parents_7,
932	.num_parents = ARRAY_SIZE(gcc_parents_7),
933	.flags = CLK_SET_RATE_PARENT,
934	.ops = &clk_rcg2_floor_ops,
935	},
936	};
937
938	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
939	F(400000, P_BI_TCXO, 12, 1, 4),
940	F(9600000, P_BI_TCXO, 2, 0, 0),
941	F(19200000, P_BI_TCXO, 1, 0, 0),
942	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
943	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
944	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
945	{ }
946	};
947
948	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
949	.cmd_rcgr = 0x1600c,
950	.mnd_width = 8,
951	.hid_width = 5,
952	.parent_map = gcc_parent_map_5,
953	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
954	.clkr.hw.init = &(struct clk_init_data){
955	.name = "gcc_sdcc4_apps_clk_src",
956	.parent_data = gcc_parents_5,
957	.num_parents = ARRAY_SIZE(gcc_parents_5),
958	.flags = CLK_SET_RATE_PARENT,
959	.ops = &clk_rcg2_floor_ops,
960	},
961	};
962
963	static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
964	F(105495, P_BI_TCXO, 2, 1, 91),
965	{ }
966	};
967
968	static struct clk_rcg2 gcc_tsif_ref_clk_src = {
969	.cmd_rcgr = 0x36010,
970	.mnd_width = 8,
971	.hid_width = 5,
972	.parent_map = gcc_parent_map_8,
973	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
974	.clkr.hw.init = &(struct clk_init_data){
975	.name = "gcc_tsif_ref_clk_src",
976	.parent_data = gcc_parents_8,
977	.num_parents = ARRAY_SIZE(gcc_parents_8),
978	.flags = CLK_SET_RATE_PARENT,
979	.ops = &clk_rcg2_ops,
980	},
981	};
982
983	static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = {
984	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
985	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
986	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
987	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
988	{ }
989	};
990
991	static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = {
992	.cmd_rcgr = 0xa2020,
993	.mnd_width = 8,
994	.hid_width = 5,
995	.parent_map = gcc_parent_map_0,
996	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
997	.clkr.hw.init = &(struct clk_init_data){
998	.name = "gcc_ufs_card_2_axi_clk_src",
999	.parent_data = gcc_parents_0,
1000	.num_parents = ARRAY_SIZE(gcc_parents_0),
1001	.flags = CLK_SET_RATE_PARENT,
1002	.ops = &clk_rcg2_ops,
1003	},
1004	};
1005
1006	static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = {
1007	.cmd_rcgr = 0xa2060,
1008	.mnd_width = 0,
1009	.hid_width = 5,
1010	.parent_map = gcc_parent_map_0,
1011	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1012	.clkr.hw.init = &(struct clk_init_data){
1013	.name = "gcc_ufs_card_2_ice_core_clk_src",
1014	.parent_data = gcc_parents_0,
1015	.num_parents = ARRAY_SIZE(gcc_parents_0),
1016	.flags = CLK_SET_RATE_PARENT,
1017	.ops = &clk_rcg2_ops,
1018	},
1019	};
1020
1021	static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = {
1022	F(19200000, P_BI_TCXO, 1, 0, 0),
1023	{ }
1024	};
1025
1026	static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = {
1027	.cmd_rcgr = 0xa2094,
1028	.mnd_width = 0,
1029	.hid_width = 5,
1030	.parent_map = gcc_parent_map_4,
1031	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1032	.clkr.hw.init = &(struct clk_init_data){
1033	.name = "gcc_ufs_card_2_phy_aux_clk_src",
1034	.parent_data = gcc_parents_4,
1035	.num_parents = ARRAY_SIZE(gcc_parents_4),
1036	.flags = CLK_SET_RATE_PARENT,
1037	.ops = &clk_rcg2_ops,
1038	},
1039	};
1040
1041	static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = {
1042	.cmd_rcgr = 0xa2078,
1043	.mnd_width = 0,
1044	.hid_width = 5,
1045	.parent_map = gcc_parent_map_0,
1046	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1047	.clkr.hw.init = &(struct clk_init_data){
1048	.name = "gcc_ufs_card_2_unipro_core_clk_src",
1049	.parent_data = gcc_parents_0,
1050	.num_parents = ARRAY_SIZE(gcc_parents_0),
1051	.flags = CLK_SET_RATE_PARENT,
1052	.ops = &clk_rcg2_ops,
1053	},
1054	};
1055
1056	static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1057	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1058	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1059	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1060	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1061	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1062	{ }
1063	};
1064
1065	static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1066	.cmd_rcgr = 0x75020,
1067	.mnd_width = 8,
1068	.hid_width = 5,
1069	.parent_map = gcc_parent_map_0,
1070	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1071	.clkr.hw.init = &(struct clk_init_data){
1072	.name = "gcc_ufs_card_axi_clk_src",
1073	.parent_data = gcc_parents_0,
1074	.num_parents = ARRAY_SIZE(gcc_parents_0),
1075	.flags = CLK_SET_RATE_PARENT,
1076	.ops = &clk_rcg2_ops,
1077	},
1078	};
1079
1080	static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1081	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1082	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1083	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1084	{ }
1085	};
1086
1087	static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1088	.cmd_rcgr = 0x75060,
1089	.mnd_width = 0,
1090	.hid_width = 5,
1091	.parent_map = gcc_parent_map_0,
1092	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1093	.clkr.hw.init = &(struct clk_init_data){
1094	.name = "gcc_ufs_card_ice_core_clk_src",
1095	.parent_data = gcc_parents_0,
1096	.num_parents = ARRAY_SIZE(gcc_parents_0),
1097	.flags = CLK_SET_RATE_PARENT,
1098	.ops = &clk_rcg2_ops,
1099	},
1100	};
1101
1102	static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1103	.cmd_rcgr = 0x75094,
1104	.mnd_width = 0,
1105	.hid_width = 5,
1106	.parent_map = gcc_parent_map_4,
1107	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1108	.clkr.hw.init = &(struct clk_init_data){
1109	.name = "gcc_ufs_card_phy_aux_clk_src",
1110	.parent_data = gcc_parents_4,
1111	.num_parents = ARRAY_SIZE(gcc_parents_4),
1112	.flags = CLK_SET_RATE_PARENT,
1113	.ops = &clk_rcg2_ops,
1114	},
1115	};
1116
1117	static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
1118	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1119	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1120	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1121	{ }
1122	};
1123
1124	static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1125	.cmd_rcgr = 0x75078,
1126	.mnd_width = 0,
1127	.hid_width = 5,
1128	.parent_map = gcc_parent_map_0,
1129	.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
1130	.clkr.hw.init = &(struct clk_init_data){
1131	.name = "gcc_ufs_card_unipro_core_clk_src",
1132	.parent_data = gcc_parents_0,
1133	.num_parents = ARRAY_SIZE(gcc_parents_0),
1134	.flags = CLK_SET_RATE_PARENT,
1135	.ops = &clk_rcg2_ops,
1136	},
1137	};
1138
1139	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1140	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1141	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1142	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1143	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1144	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1145	{ }
1146	};
1147
1148	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1149	.cmd_rcgr = 0x77020,
1150	.mnd_width = 8,
1151	.hid_width = 5,
1152	.parent_map = gcc_parent_map_0,
1153	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1154	.clkr.hw.init = &(struct clk_init_data){
1155	.name = "gcc_ufs_phy_axi_clk_src",
1156	.parent_data = gcc_parents_0,
1157	.num_parents = ARRAY_SIZE(gcc_parents_0),
1158	.flags = CLK_SET_RATE_PARENT,
1159	.ops = &clk_rcg2_ops,
1160	},
1161	};
1162
1163	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1164	.cmd_rcgr = 0x77060,
1165	.mnd_width = 0,
1166	.hid_width = 5,
1167	.parent_map = gcc_parent_map_0,
1168	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1169	.clkr.hw.init = &(struct clk_init_data){
1170	.name = "gcc_ufs_phy_ice_core_clk_src",
1171	.parent_data = gcc_parents_0,
1172	.num_parents = ARRAY_SIZE(gcc_parents_0),
1173	.flags = CLK_SET_RATE_PARENT,
1174	.ops = &clk_rcg2_ops,
1175	},
1176	};
1177
1178	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1179	.cmd_rcgr = 0x77094,
1180	.mnd_width = 0,
1181	.hid_width = 5,
1182	.parent_map = gcc_parent_map_4,
1183	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1184	.clkr.hw.init = &(struct clk_init_data){
1185	.name = "gcc_ufs_phy_phy_aux_clk_src",
1186	.parent_data = gcc_parents_4,
1187	.num_parents = ARRAY_SIZE(gcc_parents_4),
1188	.flags = CLK_SET_RATE_PARENT,
1189	.ops = &clk_rcg2_ops,
1190	},
1191	};
1192
1193	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1194	.cmd_rcgr = 0x77078,
1195	.mnd_width = 0,
1196	.hid_width = 5,
1197	.parent_map = gcc_parent_map_0,
1198	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1199	.clkr.hw.init = &(struct clk_init_data){
1200	.name = "gcc_ufs_phy_unipro_core_clk_src",
1201	.parent_data = gcc_parents_0,
1202	.num_parents = ARRAY_SIZE(gcc_parents_0),
1203	.flags = CLK_SET_RATE_PARENT,
1204	.ops = &clk_rcg2_ops,
1205	},
1206	};
1207
1208	static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1209	F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1210	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1211	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1212	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1213	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1214	{ }
1215	};
1216
1217	static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1218	.cmd_rcgr = 0xa601c,
1219	.mnd_width = 8,
1220	.hid_width = 5,
1221	.parent_map = gcc_parent_map_0,
1222	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1223	.clkr.hw.init = &(struct clk_init_data){
1224	.name = "gcc_usb30_mp_master_clk_src",
1225	.parent_data = gcc_parents_0,
1226	.num_parents = ARRAY_SIZE(gcc_parents_0),
1227	.flags = CLK_SET_RATE_PARENT,
1228	.ops = &clk_rcg2_ops,
1229	},
1230	};
1231
1232	static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = {
1233	F(19200000, P_BI_TCXO, 1, 0, 0),
1234	F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1235	F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1236	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1237	{ }
1238	};
1239
1240	static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1241	.cmd_rcgr = 0xa6034,
1242	.mnd_width = 0,
1243	.hid_width = 5,
1244	.parent_map = gcc_parent_map_0,
1245	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1246	.clkr.hw.init = &(struct clk_init_data){
1247	.name = "gcc_usb30_mp_mock_utmi_clk_src",
1248	.parent_data = gcc_parents_0,
1249	.num_parents = ARRAY_SIZE(gcc_parents_0),
1250	.flags = CLK_SET_RATE_PARENT,
1251	.ops = &clk_rcg2_ops,
1252	},
1253	};
1254
1255	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1256	.cmd_rcgr = 0xf01c,
1257	.mnd_width = 8,
1258	.hid_width = 5,
1259	.parent_map = gcc_parent_map_0,
1260	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1261	.clkr.hw.init = &(struct clk_init_data){
1262	.name = "gcc_usb30_prim_master_clk_src",
1263	.parent_data = gcc_parents_0,
1264	.num_parents = ARRAY_SIZE(gcc_parents_0),
1265	.flags = CLK_SET_RATE_PARENT,
1266	.ops = &clk_rcg2_ops,
1267	},
1268	};
1269
1270	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1271	.cmd_rcgr = 0xf034,
1272	.mnd_width = 0,
1273	.hid_width = 5,
1274	.parent_map = gcc_parent_map_0,
1275	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1276	.clkr.hw.init = &(struct clk_init_data){
1277	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1278	.parent_data = gcc_parents_0,
1279	.num_parents = ARRAY_SIZE(gcc_parents_0),
1280	.flags = CLK_SET_RATE_PARENT,
1281	.ops = &clk_rcg2_ops,
1282	},
1283	};
1284
1285	static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1286	.cmd_rcgr = 0x1001c,
1287	.mnd_width = 8,
1288	.hid_width = 5,
1289	.parent_map = gcc_parent_map_0,
1290	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1291	.clkr.hw.init = &(struct clk_init_data){
1292	.name = "gcc_usb30_sec_master_clk_src",
1293	.parent_data = gcc_parents_0,
1294	.num_parents = ARRAY_SIZE(gcc_parents_0),
1295	.flags = CLK_SET_RATE_PARENT,
1296	.ops = &clk_rcg2_ops,
1297	},
1298	};
1299
1300	static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1301	.cmd_rcgr = 0x10034,
1302	.mnd_width = 0,
1303	.hid_width = 5,
1304	.parent_map = gcc_parent_map_0,
1305	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1306	.clkr.hw.init = &(struct clk_init_data){
1307	.name = "gcc_usb30_sec_mock_utmi_clk_src",
1308	.parent_data = gcc_parents_0,
1309	.num_parents = ARRAY_SIZE(gcc_parents_0),
1310	.flags = CLK_SET_RATE_PARENT,
1311	.ops = &clk_rcg2_ops,
1312	},
1313	};
1314
1315	static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1316	.cmd_rcgr = 0xa6068,
1317	.mnd_width = 0,
1318	.hid_width = 5,
1319	.parent_map = gcc_parent_map_2,
1320	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1321	.clkr.hw.init = &(struct clk_init_data){
1322	.name = "gcc_usb3_mp_phy_aux_clk_src",
1323	.parent_data = gcc_parents_2,
1324	.num_parents = ARRAY_SIZE(gcc_parents_2),
1325	.flags = CLK_SET_RATE_PARENT,
1326	.ops = &clk_rcg2_ops,
1327	},
1328	};
1329
1330	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1331	.cmd_rcgr = 0xf060,
1332	.mnd_width = 0,
1333	.hid_width = 5,
1334	.parent_map = gcc_parent_map_2,
1335	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1336	.clkr.hw.init = &(struct clk_init_data){
1337	.name = "gcc_usb3_prim_phy_aux_clk_src",
1338	.parent_data = gcc_parents_2,
1339	.num_parents = ARRAY_SIZE(gcc_parents_2),
1340	.flags = CLK_SET_RATE_PARENT,
1341	.ops = &clk_rcg2_ops,
1342	},
1343	};
1344
1345	static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1346	.cmd_rcgr = 0x10060,
1347	.mnd_width = 0,
1348	.hid_width = 5,
1349	.parent_map = gcc_parent_map_2,
1350	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1351	.clkr.hw.init = &(struct clk_init_data){
1352	.name = "gcc_usb3_sec_phy_aux_clk_src",
1353	.parent_data = gcc_parents_2,
1354	.num_parents = ARRAY_SIZE(gcc_parents_2),
1355	.flags = CLK_SET_RATE_PARENT,
1356	.ops = &clk_rcg2_ops,
1357	},
1358	};
1359
1360	static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1361	.halt_reg = 0x90018,
1362	.halt_check = BRANCH_HALT,
1363	.clkr = {
1364	.enable_reg = 0x90018,
1365	.enable_mask = BIT(0),
1366	.hw.init = &(struct clk_init_data){
1367	.name = "gcc_aggre_noc_pcie_tbu_clk",
1368	.ops = &clk_branch2_ops,
1369	},
1370	},
1371	};
1372
1373	static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1374	.halt_reg = 0x750c0,
1375	.halt_check = BRANCH_HALT,
1376	.hwcg_reg = 0x750c0,
1377	.hwcg_bit = 1,
1378	.clkr = {
1379	.enable_reg = 0x750c0,
1380	.enable_mask = BIT(0),
1381	.hw.init = &(struct clk_init_data){
1382	.name = "gcc_aggre_ufs_card_axi_clk",
1383	.parent_hws = (const struct clk_hw *[]){
1384	&gcc_ufs_card_axi_clk_src.clkr.hw
1385	},
1386	.num_parents = 1,
1387	.flags = CLK_SET_RATE_PARENT,
1388	.ops = &clk_branch2_ops,
1389	},
1390	},
1391	};
1392
1393	static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1394	.halt_reg = 0x750c0,
1395	.halt_check = BRANCH_HALT,
1396	.hwcg_reg = 0x750c0,
1397	.hwcg_bit = 1,
1398	.clkr = {
1399	.enable_reg = 0x750c0,
1400	.enable_mask = BIT(1),
1401	.hw.init = &(struct clk_init_data){
1402	.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1403	.parent_hws = (const struct clk_hw *[]){
1404	&gcc_aggre_ufs_card_axi_clk.clkr.hw
1405	},
1406	.num_parents = 1,
1407	.flags = CLK_SET_RATE_PARENT,
1408	.ops = &clk_branch_simple_ops,
1409	},
1410	},
1411	};
1412
1413	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1414	.halt_reg = 0x770c0,
1415	.halt_check = BRANCH_HALT,
1416	.hwcg_reg = 0x770c0,
1417	.hwcg_bit = 1,
1418	.clkr = {
1419	.enable_reg = 0x770c0,
1420	.enable_mask = BIT(0),
1421	.hw.init = &(struct clk_init_data){
1422	.name = "gcc_aggre_ufs_phy_axi_clk",
1423	.parent_hws = (const struct clk_hw *[]){
1424	&gcc_ufs_phy_axi_clk_src.clkr.hw
1425	},
1426	.num_parents = 1,
1427	.flags = CLK_SET_RATE_PARENT,
1428	.ops = &clk_branch2_ops,
1429	},
1430	},
1431	};
1432
1433	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1434	.halt_reg = 0x770c0,
1435	.halt_check = BRANCH_HALT,
1436	.hwcg_reg = 0x770c0,
1437	.hwcg_bit = 1,
1438	.clkr = {
1439	.enable_reg = 0x770c0,
1440	.enable_mask = BIT(1),
1441	.hw.init = &(struct clk_init_data){
1442	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1443	.parent_hws = (const struct clk_hw *[]){
1444	&gcc_aggre_ufs_phy_axi_clk.clkr.hw
1445	},
1446	.num_parents = 1,
1447	.flags = CLK_SET_RATE_PARENT,
1448	.ops = &clk_branch_simple_ops,
1449	},
1450	},
1451	};
1452
1453	static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
1454	.halt_reg = 0xa6084,
1455	.halt_check = BRANCH_HALT,
1456	.clkr = {
1457	.enable_reg = 0xa6084,
1458	.enable_mask = BIT(0),
1459	.hw.init = &(struct clk_init_data){
1460	.name = "gcc_aggre_usb3_mp_axi_clk",
1461	.parent_hws = (const struct clk_hw *[]){
1462	&gcc_usb30_mp_master_clk_src.clkr.hw
1463	},
1464	.num_parents = 1,
1465	.flags = CLK_SET_RATE_PARENT,
1466	.ops = &clk_branch2_ops,
1467	},
1468	},
1469	};
1470
1471	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1472	.halt_reg = 0xf07c,
1473	.halt_check = BRANCH_HALT,
1474	.clkr = {
1475	.enable_reg = 0xf07c,
1476	.enable_mask = BIT(0),
1477	.hw.init = &(struct clk_init_data){
1478	.name = "gcc_aggre_usb3_prim_axi_clk",
1479	.parent_hws = (const struct clk_hw *[]){
1480	&gcc_usb30_prim_master_clk_src.clkr.hw
1481	},
1482	.num_parents = 1,
1483	.flags = CLK_SET_RATE_PARENT,
1484	.ops = &clk_branch2_ops,
1485	},
1486	},
1487	};
1488
1489	static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1490	.halt_reg = 0x1007c,
1491	.halt_check = BRANCH_HALT,
1492	.clkr = {
1493	.enable_reg = 0x1007c,
1494	.enable_mask = BIT(0),
1495	.hw.init = &(struct clk_init_data){
1496	.name = "gcc_aggre_usb3_sec_axi_clk",
1497	.parent_hws = (const struct clk_hw *[]){
1498	&gcc_usb30_sec_master_clk_src.clkr.hw
1499	},
1500	.num_parents = 1,
1501	.flags = CLK_SET_RATE_PARENT,
1502	.ops = &clk_branch2_ops,
1503	},
1504	},
1505	};
1506
1507	static struct clk_branch gcc_boot_rom_ahb_clk = {
1508	.halt_reg = 0x38004,
1509	.halt_check = BRANCH_HALT_VOTED,
1510	.hwcg_reg = 0x38004,
1511	.hwcg_bit = 1,
1512	.clkr = {
1513	.enable_reg = 0x52004,
1514	.enable_mask = BIT(10),
1515	.hw.init = &(struct clk_init_data){
1516	.name = "gcc_boot_rom_ahb_clk",
1517	.ops = &clk_branch2_ops,
1518	},
1519	},
1520	};
1521
1522	static struct clk_branch gcc_camera_hf_axi_clk = {
1523	.halt_reg = 0xb030,
1524	.halt_check = BRANCH_HALT,
1525	.clkr = {
1526	.enable_reg = 0xb030,
1527	.enable_mask = BIT(0),
1528	.hw.init = &(struct clk_init_data){
1529	.name = "gcc_camera_hf_axi_clk",
1530	.ops = &clk_branch2_ops,
1531	},
1532	},
1533	};
1534
1535	static struct clk_branch gcc_camera_sf_axi_clk = {
1536	.halt_reg = 0xb034,
1537	.halt_check = BRANCH_HALT,
1538	.clkr = {
1539	.enable_reg = 0xb034,
1540	.enable_mask = BIT(0),
1541	.hw.init = &(struct clk_init_data){
1542	.name = "gcc_camera_sf_axi_clk",
1543	.ops = &clk_branch2_ops,
1544	},
1545	},
1546	};
1547
1548	static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
1549	.halt_reg = 0xa609c,
1550	.halt_check = BRANCH_HALT,
1551	.clkr = {
1552	.enable_reg = 0xa609c,
1553	.enable_mask = BIT(0),
1554	.hw.init = &(struct clk_init_data){
1555	.name = "gcc_cfg_noc_usb3_mp_axi_clk",
1556	.parent_hws = (const struct clk_hw *[]){
1557	&gcc_usb30_mp_master_clk_src.clkr.hw
1558	},
1559	.num_parents = 1,
1560	.flags = CLK_SET_RATE_PARENT,
1561	.ops = &clk_branch2_ops,
1562	},
1563	},
1564	};
1565
1566	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1567	.halt_reg = 0xf078,
1568	.halt_check = BRANCH_HALT,
1569	.clkr = {
1570	.enable_reg = 0xf078,
1571	.enable_mask = BIT(0),
1572	.hw.init = &(struct clk_init_data){
1573	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1574	.parent_hws = (const struct clk_hw *[]){
1575	&gcc_usb30_prim_master_clk_src.clkr.hw
1576	},
1577	.num_parents = 1,
1578	.flags = CLK_SET_RATE_PARENT,
1579	.ops = &clk_branch2_ops,
1580	},
1581	},
1582	};
1583
1584	static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1585	.halt_reg = 0x10078,
1586	.halt_check = BRANCH_HALT,
1587	.clkr = {
1588	.enable_reg = 0x10078,
1589	.enable_mask = BIT(0),
1590	.hw.init = &(struct clk_init_data){
1591	.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1592	.parent_hws = (const struct clk_hw *[]){
1593	&gcc_usb30_sec_master_clk_src.clkr.hw
1594	},
1595	.num_parents = 1,
1596	.flags = CLK_SET_RATE_PARENT,
1597	.ops = &clk_branch2_ops,
1598	},
1599	},
1600	};
1601
1602	/* For CPUSS functionality the AHB clock needs to be left enabled */
1603	static struct clk_branch gcc_cpuss_ahb_clk = {
1604	.halt_reg = 0x48000,
1605	.halt_check = BRANCH_HALT_VOTED,
1606	.clkr = {
1607	.enable_reg = 0x52004,
1608	.enable_mask = BIT(21),
1609	.hw.init = &(struct clk_init_data){
1610	.name = "gcc_cpuss_ahb_clk",
1611	.parent_hws = (const struct clk_hw *[]){
1612	&gcc_cpuss_ahb_clk_src.clkr.hw
1613	},
1614	.num_parents = 1,
1615	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1616	.ops = &clk_branch2_ops,
1617	},
1618	},
1619	};
1620
1621	static struct clk_branch gcc_cpuss_rbcpr_clk = {
1622	.halt_reg = 0x48008,
1623	.halt_check = BRANCH_HALT,
1624	.clkr = {
1625	.enable_reg = 0x48008,
1626	.enable_mask = BIT(0),
1627	.hw.init = &(struct clk_init_data){
1628	.name = "gcc_cpuss_rbcpr_clk",
1629	.ops = &clk_branch2_ops,
1630	},
1631	},
1632	};
1633
1634	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1635	.halt_reg = 0x71154,
1636	.halt_check = BRANCH_VOTED,
1637	.clkr = {
1638	.enable_reg = 0x71154,
1639	.enable_mask = BIT(0),
1640	.hw.init = &(struct clk_init_data){
1641	.name = "gcc_ddrss_gpu_axi_clk",
1642	.ops = &clk_branch2_ops,
1643	},
1644	},
1645	};
1646
1647	static struct clk_branch gcc_disp_hf_axi_clk = {
1648	.halt_reg = 0xb038,
1649	.halt_check = BRANCH_HALT,
1650	.clkr = {
1651	.enable_reg = 0xb038,
1652	.enable_mask = BIT(0),
1653	.hw.init = &(struct clk_init_data){
1654	.name = "gcc_disp_hf_axi_clk",
1655	.ops = &clk_branch2_ops,
1656	},
1657	},
1658	};
1659
1660	static struct clk_branch gcc_disp_sf_axi_clk = {
1661	.halt_reg = 0xb03c,
1662	.halt_check = BRANCH_HALT,
1663	.clkr = {
1664	.enable_reg = 0xb03c,
1665	.enable_mask = BIT(0),
1666	.hw.init = &(struct clk_init_data){
1667	.name = "gcc_disp_sf_axi_clk",
1668	.ops = &clk_branch2_ops,
1669	},
1670	},
1671	};
1672
1673	static struct clk_branch gcc_emac_axi_clk = {
1674	.halt_reg = 0x6010,
1675	.halt_check = BRANCH_HALT,
1676	.clkr = {
1677	.enable_reg = 0x6010,
1678	.enable_mask = BIT(0),
1679	.hw.init = &(struct clk_init_data){
1680	.name = "gcc_emac_axi_clk",
1681	.ops = &clk_branch2_ops,
1682	},
1683	},
1684	};
1685
1686	static struct clk_branch gcc_emac_ptp_clk = {
1687	.halt_reg = 0x6034,
1688	.halt_check = BRANCH_HALT,
1689	.clkr = {
1690	.enable_reg = 0x6034,
1691	.enable_mask = BIT(0),
1692	.hw.init = &(struct clk_init_data){
1693	.name = "gcc_emac_ptp_clk",
1694	.parent_hws = (const struct clk_hw *[]){
1695	&gcc_emac_ptp_clk_src.clkr.hw
1696	},
1697	.num_parents = 1,
1698	.flags = CLK_SET_RATE_PARENT,
1699	.ops = &clk_branch2_ops,
1700	},
1701	},
1702	};
1703
1704	static struct clk_branch gcc_emac_rgmii_clk = {
1705	.halt_reg = 0x6018,
1706	.halt_check = BRANCH_HALT,
1707	.clkr = {
1708	.enable_reg = 0x6018,
1709	.enable_mask = BIT(0),
1710	.hw.init = &(struct clk_init_data){
1711	.name = "gcc_emac_rgmii_clk",
1712	.parent_hws = (const struct clk_hw *[]){
1713	&gcc_emac_rgmii_clk_src.clkr.hw
1714	},
1715	.num_parents = 1,
1716	.flags = CLK_SET_RATE_PARENT,
1717	.ops = &clk_branch2_ops,
1718	},
1719	},
1720	};
1721
1722	static struct clk_branch gcc_emac_slv_ahb_clk = {
1723	.halt_reg = 0x6014,
1724	.halt_check = BRANCH_HALT,
1725	.hwcg_reg = 0x6014,
1726	.hwcg_bit = 1,
1727	.clkr = {
1728	.enable_reg = 0x6014,
1729	.enable_mask = BIT(0),
1730	.hw.init = &(struct clk_init_data){
1731	.name = "gcc_emac_slv_ahb_clk",
1732	.ops = &clk_branch2_ops,
1733	},
1734	},
1735	};
1736
1737	static struct clk_branch gcc_gp1_clk = {
1738	.halt_reg = 0x64000,
1739	.halt_check = BRANCH_HALT,
1740	.clkr = {
1741	.enable_reg = 0x64000,
1742	.enable_mask = BIT(0),
1743	.hw.init = &(struct clk_init_data){
1744	.name = "gcc_gp1_clk",
1745	.parent_hws = (const struct clk_hw *[]){
1746	&gcc_gp1_clk_src.clkr.hw
1747	},
1748	.num_parents = 1,
1749	.flags = CLK_SET_RATE_PARENT,
1750	.ops = &clk_branch2_ops,
1751	},
1752	},
1753	};
1754
1755	static struct clk_branch gcc_gp2_clk = {
1756	.halt_reg = 0x65000,
1757	.halt_check = BRANCH_HALT,
1758	.clkr = {
1759	.enable_reg = 0x65000,
1760	.enable_mask = BIT(0),
1761	.hw.init = &(struct clk_init_data){
1762	.name = "gcc_gp2_clk",
1763	.parent_hws = (const struct clk_hw *[]){
1764	&gcc_gp2_clk_src.clkr.hw
1765	},
1766	.num_parents = 1,
1767	.flags = CLK_SET_RATE_PARENT,
1768	.ops = &clk_branch2_ops,
1769	},
1770	},
1771	};
1772
1773	static struct clk_branch gcc_gp3_clk = {
1774	.halt_reg = 0x66000,
1775	.halt_check = BRANCH_HALT,
1776	.clkr = {
1777	.enable_reg = 0x66000,
1778	.enable_mask = BIT(0),
1779	.hw.init = &(struct clk_init_data){
1780	.name = "gcc_gp3_clk",
1781	.parent_hws = (const struct clk_hw *[]){
1782	&gcc_gp3_clk_src.clkr.hw
1783	},
1784	.num_parents = 1,
1785	.flags = CLK_SET_RATE_PARENT,
1786	.ops = &clk_branch2_ops,
1787	},
1788	},
1789	};
1790
1791	static struct clk_branch gcc_gp4_clk = {
1792	.halt_reg = 0xbe000,
1793	.halt_check = BRANCH_HALT,
1794	.clkr = {
1795	.enable_reg = 0xbe000,
1796	.enable_mask = BIT(0),
1797	.hw.init = &(struct clk_init_data){
1798	.name = "gcc_gp4_clk",
1799	.parent_hws = (const struct clk_hw *[]){
1800	&gcc_gp4_clk_src.clkr.hw
1801	},
1802	.num_parents = 1,
1803	.flags = CLK_SET_RATE_PARENT,
1804	.ops = &clk_branch2_ops,
1805	},
1806	},
1807	};
1808
1809	static struct clk_branch gcc_gp5_clk = {
1810	.halt_reg = 0xbf000,
1811	.halt_check = BRANCH_HALT,
1812	.clkr = {
1813	.enable_reg = 0xbf000,
1814	.enable_mask = BIT(0),
1815	.hw.init = &(struct clk_init_data){
1816	.name = "gcc_gp5_clk",
1817	.parent_hws = (const struct clk_hw *[]){
1818	&gcc_gp5_clk_src.clkr.hw
1819	},
1820	.num_parents = 1,
1821	.flags = CLK_SET_RATE_PARENT,
1822	.ops = &clk_branch2_ops,
1823	},
1824	},
1825	};
1826
1827	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1828	.halt_check = BRANCH_HALT_DELAY,
1829	.clkr = {
1830	.enable_reg = 0x52004,
1831	.enable_mask = BIT(15),
1832	.hw.init = &(struct clk_init_data){
1833	.name = "gcc_gpu_gpll0_clk_src",
1834	.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1835	.num_parents = 1,
1836	.flags = CLK_SET_RATE_PARENT,
1837	.ops = &clk_branch2_ops,
1838	},
1839	},
1840	};
1841
1842	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1843	.halt_check = BRANCH_HALT_DELAY,
1844	.clkr = {
1845	.enable_reg = 0x52004,
1846	.enable_mask = BIT(16),
1847	.hw.init = &(struct clk_init_data){
1848	.name = "gcc_gpu_gpll0_div_clk_src",
1849	.parent_hws = (const struct clk_hw *[]){
1850	&gpll0_out_even.clkr.hw
1851	},
1852	.num_parents = 1,
1853	.flags = CLK_SET_RATE_PARENT,
1854	.ops = &clk_branch2_ops,
1855	},
1856	},
1857	};
1858
1859	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1860	.halt_reg = 0x7100c,
1861	.halt_check = BRANCH_VOTED,
1862	.clkr = {
1863	.enable_reg = 0x7100c,
1864	.enable_mask = BIT(0),
1865	.hw.init = &(struct clk_init_data){
1866	.name = "gcc_gpu_memnoc_gfx_clk",
1867	.ops = &clk_branch2_ops,
1868	},
1869	},
1870	};
1871
1872	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1873	.halt_reg = 0x71018,
1874	.halt_check = BRANCH_HALT,
1875	.clkr = {
1876	.enable_reg = 0x71018,
1877	.enable_mask = BIT(0),
1878	.hw.init = &(struct clk_init_data){
1879	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1880	.ops = &clk_branch2_ops,
1881	},
1882	},
1883	};
1884
1885	static struct clk_branch gcc_npu_at_clk = {
1886	.halt_reg = 0x4d010,
1887	.halt_check = BRANCH_VOTED,
1888	.clkr = {
1889	.enable_reg = 0x4d010,
1890	.enable_mask = BIT(0),
1891	.hw.init = &(struct clk_init_data){
1892	.name = "gcc_npu_at_clk",
1893	.ops = &clk_branch2_ops,
1894	},
1895	},
1896	};
1897
1898	static struct clk_branch gcc_npu_axi_clk = {
1899	.halt_reg = 0x4d008,
1900	.halt_check = BRANCH_VOTED,
1901	.clkr = {
1902	.enable_reg = 0x4d008,
1903	.enable_mask = BIT(0),
1904	.hw.init = &(struct clk_init_data){
1905	.name = "gcc_npu_axi_clk",
1906	.parent_hws = (const struct clk_hw *[]){
1907	&gcc_npu_axi_clk_src.clkr.hw
1908	},
1909	.num_parents = 1,
1910	.flags = CLK_SET_RATE_PARENT,
1911	.ops = &clk_branch2_ops,
1912	},
1913	},
1914	};
1915
1916	static struct clk_branch gcc_npu_gpll0_clk_src = {
1917	.halt_check = BRANCH_HALT_DELAY,
1918	.clkr = {
1919	.enable_reg = 0x52004,
1920	.enable_mask = BIT(18),
1921	.hw.init = &(struct clk_init_data){
1922	.name = "gcc_npu_gpll0_clk_src",
1923	.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1924	.num_parents = 1,
1925	.flags = CLK_SET_RATE_PARENT,
1926	.ops = &clk_branch2_ops,
1927	},
1928	},
1929	};
1930
1931	static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1932	.halt_check = BRANCH_HALT_DELAY,
1933	.clkr = {
1934	.enable_reg = 0x52004,
1935	.enable_mask = BIT(19),
1936	.hw.init = &(struct clk_init_data){
1937	.name = "gcc_npu_gpll0_div_clk_src",
1938	.parent_hws = (const struct clk_hw *[]){
1939	&gpll0_out_even.clkr.hw
1940	},
1941	.num_parents = 1,
1942	.flags = CLK_SET_RATE_PARENT,
1943	.ops = &clk_branch2_ops,
1944	},
1945	},
1946	};
1947
1948	static struct clk_branch gcc_npu_trig_clk = {
1949	.halt_reg = 0x4d00c,
1950	.halt_check = BRANCH_VOTED,
1951	.clkr = {
1952	.enable_reg = 0x4d00c,
1953	.enable_mask = BIT(0),
1954	.hw.init = &(struct clk_init_data){
1955	.name = "gcc_npu_trig_clk",
1956	.ops = &clk_branch2_ops,
1957	},
1958	},
1959	};
1960
1961	static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1962	.halt_reg = 0x6f02c,
1963	.halt_check = BRANCH_HALT,
1964	.clkr = {
1965	.enable_reg = 0x6f02c,
1966	.enable_mask = BIT(0),
1967	.hw.init = &(struct clk_init_data){
1968	.name = "gcc_pcie0_phy_refgen_clk",
1969	.parent_hws = (const struct clk_hw *[]){
1970	&gcc_pcie_phy_refgen_clk_src.clkr.hw
1971	},
1972	.num_parents = 1,
1973	.flags = CLK_SET_RATE_PARENT,
1974	.ops = &clk_branch2_ops,
1975	},
1976	},
1977	};
1978
1979	static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1980	.halt_reg = 0x6f030,
1981	.halt_check = BRANCH_HALT,
1982	.clkr = {
1983	.enable_reg = 0x6f030,
1984	.enable_mask = BIT(0),
1985	.hw.init = &(struct clk_init_data){
1986	.name = "gcc_pcie1_phy_refgen_clk",
1987	.parent_hws = (const struct clk_hw *[]){
1988	&gcc_pcie_phy_refgen_clk_src.clkr.hw
1989	},
1990	.num_parents = 1,
1991	.flags = CLK_SET_RATE_PARENT,
1992	.ops = &clk_branch2_ops,
1993	},
1994	},
1995	};
1996
1997	static struct clk_branch gcc_pcie2_phy_refgen_clk = {
1998	.halt_reg = 0x6f034,
1999	.halt_check = BRANCH_HALT,
2000	.clkr = {
2001	.enable_reg = 0x6f034,
2002	.enable_mask = BIT(0),
2003	.hw.init = &(struct clk_init_data){
2004	.name = "gcc_pcie2_phy_refgen_clk",
2005	.parent_hws = (const struct clk_hw *[]){
2006	&gcc_pcie_phy_refgen_clk_src.clkr.hw
2007	},
2008	.num_parents = 1,
2009	.flags = CLK_SET_RATE_PARENT,
2010	.ops = &clk_branch2_ops,
2011	},
2012	},
2013	};
2014
2015	static struct clk_branch gcc_pcie3_phy_refgen_clk = {
2016	.halt_reg = 0x6f038,
2017	.halt_check = BRANCH_HALT,
2018	.clkr = {
2019	.enable_reg = 0x6f038,
2020	.enable_mask = BIT(0),
2021	.hw.init = &(struct clk_init_data){
2022	.name = "gcc_pcie3_phy_refgen_clk",
2023	.parent_hws = (const struct clk_hw *[]){
2024	&gcc_pcie_phy_refgen_clk_src.clkr.hw
2025	},
2026	.num_parents = 1,
2027	.flags = CLK_SET_RATE_PARENT,
2028	.ops = &clk_branch2_ops,
2029	},
2030	},
2031	};
2032
2033	static struct clk_branch gcc_pcie_0_aux_clk = {
2034	.halt_reg = 0x6b020,
2035	.halt_check = BRANCH_HALT_VOTED,
2036	.clkr = {
2037	.enable_reg = 0x5200c,
2038	.enable_mask = BIT(3),
2039	.hw.init = &(struct clk_init_data){
2040	.name = "gcc_pcie_0_aux_clk",
2041	.parent_hws = (const struct clk_hw *[]){
2042	&gcc_pcie_0_aux_clk_src.clkr.hw
2043	},
2044	.num_parents = 1,
2045	.flags = CLK_SET_RATE_PARENT,
2046	.ops = &clk_branch2_ops,
2047	},
2048	},
2049	};
2050
2051	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2052	.halt_reg = 0x6b01c,
2053	.halt_check = BRANCH_HALT_VOTED,
2054	.hwcg_reg = 0x6b01c,
2055	.hwcg_bit = 1,
2056	.clkr = {
2057	.enable_reg = 0x5200c,
2058	.enable_mask = BIT(2),
2059	.hw.init = &(struct clk_init_data){
2060	.name = "gcc_pcie_0_cfg_ahb_clk",
2061	.ops = &clk_branch2_ops,
2062	},
2063	},
2064	};
2065
2066	static struct clk_branch gcc_pcie_0_clkref_clk = {
2067	.halt_reg = 0x8c00c,
2068	.halt_check = BRANCH_HALT,
2069	.clkr = {
2070	.enable_reg = 0x8c00c,
2071	.enable_mask = BIT(0),
2072	.hw.init = &(struct clk_init_data){
2073	.name = "gcc_pcie_0_clkref_clk",
2074	.ops = &clk_branch2_ops,
2075	},
2076	},
2077	};
2078
2079	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2080	.halt_reg = 0x6b018,
2081	.halt_check = BRANCH_HALT_VOTED,
2082	.clkr = {
2083	.enable_reg = 0x5200c,
2084	.enable_mask = BIT(1),
2085	.hw.init = &(struct clk_init_data){
2086	.name = "gcc_pcie_0_mstr_axi_clk",
2087	.ops = &clk_branch2_ops,
2088	},
2089	},
2090	};
2091
2092	static struct clk_branch gcc_pcie_0_pipe_clk = {
2093	.halt_reg = 0x6b024,
2094	.halt_check = BRANCH_HALT_SKIP,
2095	.clkr = {
2096	.enable_reg = 0x5200c,
2097	.enable_mask = BIT(4),
2098	.hw.init = &(struct clk_init_data){
2099	.name = "gcc_pcie_0_pipe_clk",
2100	.ops = &clk_branch2_ops,
2101	},
2102	},
2103	};
2104
2105	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2106	.halt_reg = 0x6b014,
2107	.halt_check = BRANCH_HALT_VOTED,
2108	.hwcg_reg = 0x6b014,
2109	.hwcg_bit = 1,
2110	.clkr = {
2111	.enable_reg = 0x5200c,
2112	.enable_mask = BIT(0),
2113	.hw.init = &(struct clk_init_data){
2114	.name = "gcc_pcie_0_slv_axi_clk",
2115	.ops = &clk_branch2_ops,
2116	},
2117	},
2118	};
2119
2120	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2121	.halt_reg = 0x6b010,
2122	.halt_check = BRANCH_HALT_VOTED,
2123	.clkr = {
2124	.enable_reg = 0x5200c,
2125	.enable_mask = BIT(5),
2126	.hw.init = &(struct clk_init_data){
2127	.name = "gcc_pcie_0_slv_q2a_axi_clk",
2128	.ops = &clk_branch2_ops,
2129	},
2130	},
2131	};
2132
2133	static struct clk_branch gcc_pcie_1_aux_clk = {
2134	.halt_reg = 0x8d020,
2135	.halt_check = BRANCH_HALT_VOTED,
2136	.clkr = {
2137	.enable_reg = 0x52004,
2138	.enable_mask = BIT(29),
2139	.hw.init = &(struct clk_init_data){
2140	.name = "gcc_pcie_1_aux_clk",
2141	.parent_hws = (const struct clk_hw *[]){
2142	&gcc_pcie_1_aux_clk_src.clkr.hw
2143	},
2144	.num_parents = 1,
2145	.flags = CLK_SET_RATE_PARENT,
2146	.ops = &clk_branch2_ops,
2147	},
2148	},
2149	};
2150
2151	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2152	.halt_reg = 0x8d01c,
2153	.halt_check = BRANCH_HALT_VOTED,
2154	.hwcg_reg = 0x8d01c,
2155	.hwcg_bit = 1,
2156	.clkr = {
2157	.enable_reg = 0x52004,
2158	.enable_mask = BIT(28),
2159	.hw.init = &(struct clk_init_data){
2160	.name = "gcc_pcie_1_cfg_ahb_clk",
2161	.ops = &clk_branch2_ops,
2162	},
2163	},
2164	};
2165
2166	static struct clk_branch gcc_pcie_1_clkref_clk = {
2167	.halt_reg = 0x8c02c,
2168	.halt_check = BRANCH_HALT,
2169	.clkr = {
2170	.enable_reg = 0x8c02c,
2171	.enable_mask = BIT(0),
2172	.hw.init = &(struct clk_init_data){
2173	.name = "gcc_pcie_1_clkref_clk",
2174	.ops = &clk_branch2_ops,
2175	},
2176	},
2177	};
2178
2179	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2180	.halt_reg = 0x8d018,
2181	.halt_check = BRANCH_HALT_VOTED,
2182	.clkr = {
2183	.enable_reg = 0x52004,
2184	.enable_mask = BIT(27),
2185	.hw.init = &(struct clk_init_data){
2186	.name = "gcc_pcie_1_mstr_axi_clk",
2187	.ops = &clk_branch2_ops,
2188	},
2189	},
2190	};
2191
2192	static struct clk_branch gcc_pcie_1_pipe_clk = {
2193	.halt_reg = 0x8d024,
2194	.halt_check = BRANCH_HALT_SKIP,
2195	.clkr = {
2196	.enable_reg = 0x52004,
2197	.enable_mask = BIT(30),
2198	.hw.init = &(struct clk_init_data){
2199	.name = "gcc_pcie_1_pipe_clk",
2200	.ops = &clk_branch2_ops,
2201	},
2202	},
2203	};
2204
2205	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2206	.halt_reg = 0x8d014,
2207	.halt_check = BRANCH_HALT_VOTED,
2208	.hwcg_reg = 0x8d014,
2209	.hwcg_bit = 1,
2210	.clkr = {
2211	.enable_reg = 0x52004,
2212	.enable_mask = BIT(26),
2213	.hw.init = &(struct clk_init_data){
2214	.name = "gcc_pcie_1_slv_axi_clk",
2215	.ops = &clk_branch2_ops,
2216	},
2217	},
2218	};
2219
2220	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2221	.halt_reg = 0x8d010,
2222	.halt_check = BRANCH_HALT_VOTED,
2223	.clkr = {
2224	.enable_reg = 0x52004,
2225	.enable_mask = BIT(25),
2226	.hw.init = &(struct clk_init_data){
2227	.name = "gcc_pcie_1_slv_q2a_axi_clk",
2228	.ops = &clk_branch2_ops,
2229	},
2230	},
2231	};
2232
2233	static struct clk_branch gcc_pcie_2_aux_clk = {
2234	.halt_reg = 0x9d020,
2235	.halt_check = BRANCH_HALT_VOTED,
2236	.clkr = {
2237	.enable_reg = 0x52014,
2238	.enable_mask = BIT(14),
2239	.hw.init = &(struct clk_init_data){
2240	.name = "gcc_pcie_2_aux_clk",
2241	.parent_hws = (const struct clk_hw *[]){
2242	&gcc_pcie_2_aux_clk_src.clkr.hw
2243	},
2244	.num_parents = 1,
2245	.flags = CLK_SET_RATE_PARENT,
2246	.ops = &clk_branch2_ops,
2247	},
2248	},
2249	};
2250
2251	static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2252	.halt_reg = 0x9d01c,
2253	.halt_check = BRANCH_HALT_VOTED,
2254	.hwcg_reg = 0x9d01c,
2255	.hwcg_bit = 1,
2256	.clkr = {
2257	.enable_reg = 0x52014,
2258	.enable_mask = BIT(13),
2259	.hw.init = &(struct clk_init_data){
2260	.name = "gcc_pcie_2_cfg_ahb_clk",
2261	.ops = &clk_branch2_ops,
2262	},
2263	},
2264	};
2265
2266	static struct clk_branch gcc_pcie_2_clkref_clk = {
2267	.halt_reg = 0x8c014,
2268	.halt_check = BRANCH_HALT,
2269	.clkr = {
2270	.enable_reg = 0x8c014,
2271	.enable_mask = BIT(0),
2272	.hw.init = &(struct clk_init_data){
2273	.name = "gcc_pcie_2_clkref_clk",
2274	.ops = &clk_branch2_ops,
2275	},
2276	},
2277	};
2278
2279	static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2280	.halt_reg = 0x9d018,
2281	.halt_check = BRANCH_HALT_VOTED,
2282	.clkr = {
2283	.enable_reg = 0x52014,
2284	.enable_mask = BIT(12),
2285	.hw.init = &(struct clk_init_data){
2286	.name = "gcc_pcie_2_mstr_axi_clk",
2287	.ops = &clk_branch2_ops,
2288	},
2289	},
2290	};
2291
2292	static struct clk_branch gcc_pcie_2_pipe_clk = {
2293	.halt_reg = 0x9d024,
2294	.halt_check = BRANCH_HALT_SKIP,
2295	.clkr = {
2296	.enable_reg = 0x52014,
2297	.enable_mask = BIT(15),
2298	.hw.init = &(struct clk_init_data){
2299	.name = "gcc_pcie_2_pipe_clk",
2300	.ops = &clk_branch2_ops,
2301	},
2302	},
2303	};
2304
2305	static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2306	.halt_reg = 0x9d014,
2307	.halt_check = BRANCH_HALT_VOTED,
2308	.hwcg_reg = 0x9d014,
2309	.hwcg_bit = 1,
2310	.clkr = {
2311	.enable_reg = 0x52014,
2312	.enable_mask = BIT(11),
2313	.hw.init = &(struct clk_init_data){
2314	.name = "gcc_pcie_2_slv_axi_clk",
2315	.ops = &clk_branch2_ops,
2316	},
2317	},
2318	};
2319
2320	static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
2321	.halt_reg = 0x9d010,
2322	.halt_check = BRANCH_HALT_VOTED,
2323	.clkr = {
2324	.enable_reg = 0x52014,
2325	.enable_mask = BIT(10),
2326	.hw.init = &(struct clk_init_data){
2327	.name = "gcc_pcie_2_slv_q2a_axi_clk",
2328	.ops = &clk_branch2_ops,
2329	},
2330	},
2331	};
2332
2333	static struct clk_branch gcc_pcie_3_aux_clk = {
2334	.halt_reg = 0xa3020,
2335	.halt_check = BRANCH_HALT_VOTED,
2336	.clkr = {
2337	.enable_reg = 0x52014,
2338	.enable_mask = BIT(20),
2339	.hw.init = &(struct clk_init_data){
2340	.name = "gcc_pcie_3_aux_clk",
2341	.parent_hws = (const struct clk_hw *[]){
2342	&gcc_pcie_3_aux_clk_src.clkr.hw
2343	},
2344	.num_parents = 1,
2345	.flags = CLK_SET_RATE_PARENT,
2346	.ops = &clk_branch2_ops,
2347	},
2348	},
2349	};
2350
2351	static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
2352	.halt_reg = 0xa301c,
2353	.halt_check = BRANCH_HALT_VOTED,
2354	.hwcg_reg = 0xa301c,
2355	.hwcg_bit = 1,
2356	.clkr = {
2357	.enable_reg = 0x52014,
2358	.enable_mask = BIT(19),
2359	.hw.init = &(struct clk_init_data){
2360	.name = "gcc_pcie_3_cfg_ahb_clk",
2361	.ops = &clk_branch2_ops,
2362	},
2363	},
2364	};
2365
2366	static struct clk_branch gcc_pcie_3_clkref_clk = {
2367	.halt_reg = 0x8c018,
2368	.halt_check = BRANCH_HALT,
2369	.clkr = {
2370	.enable_reg = 0x8c018,
2371	.enable_mask = BIT(0),
2372	.hw.init = &(struct clk_init_data){
2373	.name = "gcc_pcie_3_clkref_clk",
2374	.ops = &clk_branch2_ops,
2375	},
2376	},
2377	};
2378
2379	static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
2380	.halt_reg = 0xa3018,
2381	.halt_check = BRANCH_HALT_VOTED,
2382	.clkr = {
2383	.enable_reg = 0x52014,
2384	.enable_mask = BIT(18),
2385	.hw.init = &(struct clk_init_data){
2386	.name = "gcc_pcie_3_mstr_axi_clk",
2387	.ops = &clk_branch2_ops,
2388	},
2389	},
2390	};
2391
2392	static struct clk_branch gcc_pcie_3_pipe_clk = {
2393	.halt_reg = 0xa3024,
2394	.halt_check = BRANCH_HALT_SKIP,
2395	.clkr = {
2396	.enable_reg = 0x52014,
2397	.enable_mask = BIT(21),
2398	.hw.init = &(struct clk_init_data){
2399	.name = "gcc_pcie_3_pipe_clk",
2400	.ops = &clk_branch2_ops,
2401	},
2402	},
2403	};
2404
2405	static struct clk_branch gcc_pcie_3_slv_axi_clk = {
2406	.halt_reg = 0xa3014,
2407	.halt_check = BRANCH_HALT_VOTED,
2408	.hwcg_reg = 0xa3014,
2409	.hwcg_bit = 1,
2410	.clkr = {
2411	.enable_reg = 0x52014,
2412	.enable_mask = BIT(17),
2413	.hw.init = &(struct clk_init_data){
2414	.name = "gcc_pcie_3_slv_axi_clk",
2415	.ops = &clk_branch2_ops,
2416	},
2417	},
2418	};
2419
2420	static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
2421	.halt_reg = 0xa3010,
2422	.halt_check = BRANCH_HALT_VOTED,
2423	.clkr = {
2424	.enable_reg = 0x52014,
2425	.enable_mask = BIT(16),
2426	.hw.init = &(struct clk_init_data){
2427	.name = "gcc_pcie_3_slv_q2a_axi_clk",
2428	.ops = &clk_branch2_ops,
2429	},
2430	},
2431	};
2432
2433	static struct clk_branch gcc_pcie_phy_aux_clk = {
2434	.halt_reg = 0x6f004,
2435	.halt_check = BRANCH_HALT,
2436	.clkr = {
2437	.enable_reg = 0x6f004,
2438	.enable_mask = BIT(0),
2439	.hw.init = &(struct clk_init_data){
2440	.name = "gcc_pcie_phy_aux_clk",
2441	.parent_hws = (const struct clk_hw *[]){
2442	&gcc_pcie_0_aux_clk_src.clkr.hw
2443	},
2444	.num_parents = 1,
2445	.flags = CLK_SET_RATE_PARENT,
2446	.ops = &clk_branch2_ops,
2447	},
2448	},
2449	};
2450
2451	static struct clk_branch gcc_pdm2_clk = {
2452	.halt_reg = 0x3300c,
2453	.halt_check = BRANCH_HALT,
2454	.clkr = {
2455	.enable_reg = 0x3300c,
2456	.enable_mask = BIT(0),
2457	.hw.init = &(struct clk_init_data){
2458	.name = "gcc_pdm2_clk",
2459	.parent_hws = (const struct clk_hw *[]){
2460	&gcc_pdm2_clk_src.clkr.hw
2461	},
2462	.num_parents = 1,
2463	.flags = CLK_SET_RATE_PARENT,
2464	.ops = &clk_branch2_ops,
2465	},
2466	},
2467	};
2468
2469	static struct clk_branch gcc_pdm_ahb_clk = {
2470	.halt_reg = 0x33004,
2471	.halt_check = BRANCH_HALT,
2472	.hwcg_reg = 0x33004,
2473	.hwcg_bit = 1,
2474	.clkr = {
2475	.enable_reg = 0x33004,
2476	.enable_mask = BIT(0),
2477	.hw.init = &(struct clk_init_data){
2478	.name = "gcc_pdm_ahb_clk",
2479	.ops = &clk_branch2_ops,
2480	},
2481	},
2482	};
2483
2484	static struct clk_branch gcc_pdm_xo4_clk = {
2485	.halt_reg = 0x33008,
2486	.halt_check = BRANCH_HALT,
2487	.clkr = {
2488	.enable_reg = 0x33008,
2489	.enable_mask = BIT(0),
2490	.hw.init = &(struct clk_init_data){
2491	.name = "gcc_pdm_xo4_clk",
2492	.ops = &clk_branch2_ops,
2493	},
2494	},
2495	};
2496
2497	static struct clk_branch gcc_prng_ahb_clk = {
2498	.halt_reg = 0x34004,
2499	.halt_check = BRANCH_HALT_VOTED,
2500	.clkr = {
2501	.enable_reg = 0x52004,
2502	.enable_mask = BIT(13),
2503	.hw.init = &(struct clk_init_data){
2504	.name = "gcc_prng_ahb_clk",
2505	.ops = &clk_branch2_ops,
2506	},
2507	},
2508	};
2509
2510	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2511	.halt_reg = 0xb018,
2512	.halt_check = BRANCH_HALT,
2513	.hwcg_reg = 0xb018,
2514	.hwcg_bit = 1,
2515	.clkr = {
2516	.enable_reg = 0xb018,
2517	.enable_mask = BIT(0),
2518	.hw.init = &(struct clk_init_data){
2519	.name = "gcc_qmip_camera_nrt_ahb_clk",
2520	.ops = &clk_branch2_ops,
2521	},
2522	},
2523	};
2524
2525	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2526	.halt_reg = 0xb01c,
2527	.halt_check = BRANCH_HALT,
2528	.hwcg_reg = 0xb01c,
2529	.hwcg_bit = 1,
2530	.clkr = {
2531	.enable_reg = 0xb01c,
2532	.enable_mask = BIT(0),
2533	.hw.init = &(struct clk_init_data){
2534	.name = "gcc_qmip_camera_rt_ahb_clk",
2535	.ops = &clk_branch2_ops,
2536	},
2537	},
2538	};
2539
2540	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2541	.halt_reg = 0xb020,
2542	.halt_check = BRANCH_HALT,
2543	.hwcg_reg = 0xb020,
2544	.hwcg_bit = 1,
2545	.clkr = {
2546	.enable_reg = 0xb020,
2547	.enable_mask = BIT(0),
2548	.hw.init = &(struct clk_init_data){
2549	.name = "gcc_qmip_disp_ahb_clk",
2550	.ops = &clk_branch2_ops,
2551	},
2552	},
2553	};
2554
2555	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2556	.halt_reg = 0xb010,
2557	.halt_check = BRANCH_HALT,
2558	.hwcg_reg = 0xb010,
2559	.hwcg_bit = 1,
2560	.clkr = {
2561	.enable_reg = 0xb010,
2562	.enable_mask = BIT(0),
2563	.hw.init = &(struct clk_init_data){
2564	.name = "gcc_qmip_video_cvp_ahb_clk",
2565	.ops = &clk_branch2_ops,
2566	},
2567	},
2568	};
2569
2570	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2571	.halt_reg = 0xb014,
2572	.halt_check = BRANCH_HALT,
2573	.hwcg_reg = 0xb014,
2574	.hwcg_bit = 1,
2575	.clkr = {
2576	.enable_reg = 0xb014,
2577	.enable_mask = BIT(0),
2578	.hw.init = &(struct clk_init_data){
2579	.name = "gcc_qmip_video_vcodec_ahb_clk",
2580	.ops = &clk_branch2_ops,
2581	},
2582	},
2583	};
2584
2585	static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = {
2586	.halt_reg = 0x4a004,
2587	.halt_check = BRANCH_HALT,
2588	.clkr = {
2589	.enable_reg = 0x4a004,
2590	.enable_mask = BIT(0),
2591	.hw.init = &(struct clk_init_data){
2592	.name = "gcc_qspi_1_cnoc_periph_ahb_clk",
2593	.ops = &clk_branch2_ops,
2594	},
2595	},
2596	};
2597
2598	static struct clk_branch gcc_qspi_1_core_clk = {
2599	.halt_reg = 0x4a008,
2600	.halt_check = BRANCH_HALT,
2601	.clkr = {
2602	.enable_reg = 0x4a008,
2603	.enable_mask = BIT(0),
2604	.hw.init = &(struct clk_init_data){
2605	.name = "gcc_qspi_1_core_clk",
2606	.parent_hws = (const struct clk_hw *[]){
2607	&gcc_qspi_1_core_clk_src.clkr.hw
2608	},
2609	.num_parents = 1,
2610	.flags = CLK_SET_RATE_PARENT,
2611	.ops = &clk_branch2_ops,
2612	},
2613	},
2614	};
2615
2616	static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2617	.halt_reg = 0x4b000,
2618	.halt_check = BRANCH_HALT,
2619	.clkr = {
2620	.enable_reg = 0x4b000,
2621	.enable_mask = BIT(0),
2622	.hw.init = &(struct clk_init_data){
2623	.name = "gcc_qspi_cnoc_periph_ahb_clk",
2624	.ops = &clk_branch2_ops,
2625	},
2626	},
2627	};
2628
2629	static struct clk_branch gcc_qspi_core_clk = {
2630	.halt_reg = 0x4b004,
2631	.halt_check = BRANCH_HALT,
2632	.clkr = {
2633	.enable_reg = 0x4b004,
2634	.enable_mask = BIT(0),
2635	.hw.init = &(struct clk_init_data){
2636	.name = "gcc_qspi_core_clk",
2637	.parent_hws = (const struct clk_hw *[]){
2638	&gcc_qspi_core_clk_src.clkr.hw
2639	},
2640	.num_parents = 1,
2641	.flags = CLK_SET_RATE_PARENT,
2642	.ops = &clk_branch2_ops,
2643	},
2644	},
2645	};
2646
2647	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2648	.halt_reg = 0x17144,
2649	.halt_check = BRANCH_HALT_VOTED,
2650	.clkr = {
2651	.enable_reg = 0x5200c,
2652	.enable_mask = BIT(10),
2653	.hw.init = &(struct clk_init_data){
2654	.name = "gcc_qupv3_wrap0_s0_clk",
2655	.parent_hws = (const struct clk_hw *[]){
2656	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw
2657	},
2658	.num_parents = 1,
2659	.flags = CLK_SET_RATE_PARENT,
2660	.ops = &clk_branch2_ops,
2661	},
2662	},
2663	};
2664
2665	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2666	.halt_reg = 0x17274,
2667	.halt_check = BRANCH_HALT_VOTED,
2668	.clkr = {
2669	.enable_reg = 0x5200c,
2670	.enable_mask = BIT(11),
2671	.hw.init = &(struct clk_init_data){
2672	.name = "gcc_qupv3_wrap0_s1_clk",
2673	.parent_hws = (const struct clk_hw *[]){
2674	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw
2675	},
2676	.num_parents = 1,
2677	.flags = CLK_SET_RATE_PARENT,
2678	.ops = &clk_branch2_ops,
2679	},
2680	},
2681	};
2682
2683	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2684	.halt_reg = 0x173a4,
2685	.halt_check = BRANCH_HALT_VOTED,
2686	.clkr = {
2687	.enable_reg = 0x5200c,
2688	.enable_mask = BIT(12),
2689	.hw.init = &(struct clk_init_data){
2690	.name = "gcc_qupv3_wrap0_s2_clk",
2691	.parent_hws = (const struct clk_hw *[]){
2692	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw
2693	},
2694	.num_parents = 1,
2695	.flags = CLK_SET_RATE_PARENT,
2696	.ops = &clk_branch2_ops,
2697	},
2698	},
2699	};
2700
2701	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2702	.halt_reg = 0x174d4,
2703	.halt_check = BRANCH_HALT_VOTED,
2704	.clkr = {
2705	.enable_reg = 0x5200c,
2706	.enable_mask = BIT(13),
2707	.hw.init = &(struct clk_init_data){
2708	.name = "gcc_qupv3_wrap0_s3_clk",
2709	.parent_hws = (const struct clk_hw *[]){
2710	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw
2711	},
2712	.num_parents = 1,
2713	.flags = CLK_SET_RATE_PARENT,
2714	.ops = &clk_branch2_ops,
2715	},
2716	},
2717	};
2718
2719	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2720	.halt_reg = 0x17604,
2721	.halt_check = BRANCH_HALT_VOTED,
2722	.clkr = {
2723	.enable_reg = 0x5200c,
2724	.enable_mask = BIT(14),
2725	.hw.init = &(struct clk_init_data){
2726	.name = "gcc_qupv3_wrap0_s4_clk",
2727	.parent_hws = (const struct clk_hw *[]){
2728	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw
2729	},
2730	.num_parents = 1,
2731	.flags = CLK_SET_RATE_PARENT,
2732	.ops = &clk_branch2_ops,
2733	},
2734	},
2735	};
2736
2737	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2738	.halt_reg = 0x17734,
2739	.halt_check = BRANCH_HALT_VOTED,
2740	.clkr = {
2741	.enable_reg = 0x5200c,
2742	.enable_mask = BIT(15),
2743	.hw.init = &(struct clk_init_data){
2744	.name = "gcc_qupv3_wrap0_s5_clk",
2745	.parent_hws = (const struct clk_hw *[]){
2746	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw
2747	},
2748	.num_parents = 1,
2749	.flags = CLK_SET_RATE_PARENT,
2750	.ops = &clk_branch2_ops,
2751	},
2752	},
2753	};
2754
2755	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2756	.halt_reg = 0x17864,
2757	.halt_check = BRANCH_HALT_VOTED,
2758	.clkr = {
2759	.enable_reg = 0x5200c,
2760	.enable_mask = BIT(16),
2761	.hw.init = &(struct clk_init_data){
2762	.name = "gcc_qupv3_wrap0_s6_clk",
2763	.parent_hws = (const struct clk_hw *[]){
2764	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw
2765	},
2766	.num_parents = 1,
2767	.flags = CLK_SET_RATE_PARENT,
2768	.ops = &clk_branch2_ops,
2769	},
2770	},
2771	};
2772
2773	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2774	.halt_reg = 0x17994,
2775	.halt_check = BRANCH_HALT_VOTED,
2776	.clkr = {
2777	.enable_reg = 0x5200c,
2778	.enable_mask = BIT(17),
2779	.hw.init = &(struct clk_init_data){
2780	.name = "gcc_qupv3_wrap0_s7_clk",
2781	.parent_hws = (const struct clk_hw *[]){
2782	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw
2783	},
2784	.num_parents = 1,
2785	.flags = CLK_SET_RATE_PARENT,
2786	.ops = &clk_branch2_ops,
2787	},
2788	},
2789	};
2790
2791	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2792	.halt_reg = 0x18144,
2793	.halt_check = BRANCH_HALT_VOTED,
2794	.clkr = {
2795	.enable_reg = 0x5200c,
2796	.enable_mask = BIT(22),
2797	.hw.init = &(struct clk_init_data){
2798	.name = "gcc_qupv3_wrap1_s0_clk",
2799	.parent_hws = (const struct clk_hw *[]){
2800	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw
2801	},
2802	.num_parents = 1,
2803	.flags = CLK_SET_RATE_PARENT,
2804	.ops = &clk_branch2_ops,
2805	},
2806	},
2807	};
2808
2809	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2810	.halt_reg = 0x18274,
2811	.halt_check = BRANCH_HALT_VOTED,
2812	.clkr = {
2813	.enable_reg = 0x5200c,
2814	.enable_mask = BIT(23),
2815	.hw.init = &(struct clk_init_data){
2816	.name = "gcc_qupv3_wrap1_s1_clk",
2817	.parent_hws = (const struct clk_hw *[]){
2818	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw
2819	},
2820	.num_parents = 1,
2821	.flags = CLK_SET_RATE_PARENT,
2822	.ops = &clk_branch2_ops,
2823	},
2824	},
2825	};
2826
2827	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2828	.halt_reg = 0x183a4,
2829	.halt_check = BRANCH_HALT_VOTED,
2830	.clkr = {
2831	.enable_reg = 0x5200c,
2832	.enable_mask = BIT(24),
2833	.hw.init = &(struct clk_init_data){
2834	.name = "gcc_qupv3_wrap1_s2_clk",
2835	.parent_hws = (const struct clk_hw *[]){
2836	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw
2837	},
2838	.num_parents = 1,
2839	.flags = CLK_SET_RATE_PARENT,
2840	.ops = &clk_branch2_ops,
2841	},
2842	},
2843	};
2844
2845	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2846	.halt_reg = 0x184d4,
2847	.halt_check = BRANCH_HALT_VOTED,
2848	.clkr = {
2849	.enable_reg = 0x5200c,
2850	.enable_mask = BIT(25),
2851	.hw.init = &(struct clk_init_data){
2852	.name = "gcc_qupv3_wrap1_s3_clk",
2853	.parent_hws = (const struct clk_hw *[]){
2854	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw
2855	},
2856	.num_parents = 1,
2857	.flags = CLK_SET_RATE_PARENT,
2858	.ops = &clk_branch2_ops,
2859	},
2860	},
2861	};
2862
2863	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2864	.halt_reg = 0x18604,
2865	.halt_check = BRANCH_HALT_VOTED,
2866	.clkr = {
2867	.enable_reg = 0x5200c,
2868	.enable_mask = BIT(26),
2869	.hw.init = &(struct clk_init_data){
2870	.name = "gcc_qupv3_wrap1_s4_clk",
2871	.parent_hws = (const struct clk_hw *[]){
2872	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw
2873	},
2874	.num_parents = 1,
2875	.flags = CLK_SET_RATE_PARENT,
2876	.ops = &clk_branch2_ops,
2877	},
2878	},
2879	};
2880
2881	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2882	.halt_reg = 0x18734,
2883	.halt_check = BRANCH_HALT_VOTED,
2884	.clkr = {
2885	.enable_reg = 0x5200c,
2886	.enable_mask = BIT(27),
2887	.hw.init = &(struct clk_init_data){
2888	.name = "gcc_qupv3_wrap1_s5_clk",
2889	.parent_hws = (const struct clk_hw *[]){
2890	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw
2891	},
2892	.num_parents = 1,
2893	.flags = CLK_SET_RATE_PARENT,
2894	.ops = &clk_branch2_ops,
2895	},
2896	},
2897	};
2898
2899	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2900	.halt_reg = 0x1e144,
2901	.halt_check = BRANCH_HALT_VOTED,
2902	.clkr = {
2903	.enable_reg = 0x52014,
2904	.enable_mask = BIT(4),
2905	.hw.init = &(struct clk_init_data){
2906	.name = "gcc_qupv3_wrap2_s0_clk",
2907	.parent_hws = (const struct clk_hw *[]){
2908	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw
2909	},
2910	.num_parents = 1,
2911	.flags = CLK_SET_RATE_PARENT,
2912	.ops = &clk_branch2_ops,
2913	},
2914	},
2915	};
2916
2917	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2918	.halt_reg = 0x1e274,
2919	.halt_check = BRANCH_HALT_VOTED,
2920	.clkr = {
2921	.enable_reg = 0x52014,
2922	.enable_mask = BIT(5),
2923	.hw.init = &(struct clk_init_data){
2924	.name = "gcc_qupv3_wrap2_s1_clk",
2925	.parent_hws = (const struct clk_hw *[]){
2926	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw
2927	},
2928	.num_parents = 1,
2929	.flags = CLK_SET_RATE_PARENT,
2930	.ops = &clk_branch2_ops,
2931	},
2932	},
2933	};
2934
2935	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2936	.halt_reg = 0x1e3a4,
2937	.halt_check = BRANCH_HALT_VOTED,
2938	.clkr = {
2939	.enable_reg = 0x52014,
2940	.enable_mask = BIT(6),
2941	.hw.init = &(struct clk_init_data){
2942	.name = "gcc_qupv3_wrap2_s2_clk",
2943	.parent_hws = (const struct clk_hw *[]){
2944	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw
2945	},
2946	.num_parents = 1,
2947	.flags = CLK_SET_RATE_PARENT,
2948	.ops = &clk_branch2_ops,
2949	},
2950	},
2951	};
2952
2953	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2954	.halt_reg = 0x1e4d4,
2955	.halt_check = BRANCH_HALT_VOTED,
2956	.clkr = {
2957	.enable_reg = 0x52014,
2958	.enable_mask = BIT(7),
2959	.hw.init = &(struct clk_init_data){
2960	.name = "gcc_qupv3_wrap2_s3_clk",
2961	.parent_hws = (const struct clk_hw *[]){
2962	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw
2963	},
2964	.num_parents = 1,
2965	.flags = CLK_SET_RATE_PARENT,
2966	.ops = &clk_branch2_ops,
2967	},
2968	},
2969	};
2970
2971	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2972	.halt_reg = 0x1e604,
2973	.halt_check = BRANCH_HALT_VOTED,
2974	.clkr = {
2975	.enable_reg = 0x52014,
2976	.enable_mask = BIT(8),
2977	.hw.init = &(struct clk_init_data){
2978	.name = "gcc_qupv3_wrap2_s4_clk",
2979	.parent_hws = (const struct clk_hw *[]){
2980	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw
2981	},
2982	.num_parents = 1,
2983	.flags = CLK_SET_RATE_PARENT,
2984	.ops = &clk_branch2_ops,
2985	},
2986	},
2987	};
2988
2989	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2990	.halt_reg = 0x1e734,
2991	.halt_check = BRANCH_HALT_VOTED,
2992	.clkr = {
2993	.enable_reg = 0x52014,
2994	.enable_mask = BIT(9),
2995	.hw.init = &(struct clk_init_data){
2996	.name = "gcc_qupv3_wrap2_s5_clk",
2997	.parent_hws = (const struct clk_hw *[]){
2998	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw
2999	},
3000	.num_parents = 1,
3001	.flags = CLK_SET_RATE_PARENT,
3002	.ops = &clk_branch2_ops,
3003	},
3004	},
3005	};
3006
3007	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3008	.halt_reg = 0x17004,
3009	.halt_check = BRANCH_HALT_VOTED,
3010	.clkr = {
3011	.enable_reg = 0x5200c,
3012	.enable_mask = BIT(6),
3013	.hw.init = &(struct clk_init_data){
3014	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
3015	.ops = &clk_branch2_ops,
3016	},
3017	},
3018	};
3019
3020	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3021	.halt_reg = 0x17008,
3022	.halt_check = BRANCH_HALT_VOTED,
3023	.hwcg_reg = 0x17008,
3024	.hwcg_bit = 1,
3025	.clkr = {
3026	.enable_reg = 0x5200c,
3027	.enable_mask = BIT(7),
3028	.hw.init = &(struct clk_init_data){
3029	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
3030	.ops = &clk_branch2_ops,
3031	},
3032	},
3033	};
3034
3035	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3036	.halt_reg = 0x18004,
3037	.halt_check = BRANCH_HALT_VOTED,
3038	.clkr = {
3039	.enable_reg = 0x5200c,
3040	.enable_mask = BIT(20),
3041	.hw.init = &(struct clk_init_data){
3042	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
3043	.ops = &clk_branch2_ops,
3044	},
3045	},
3046	};
3047
3048	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3049	.halt_reg = 0x18008,
3050	.halt_check = BRANCH_HALT_VOTED,
3051	.hwcg_reg = 0x18008,
3052	.hwcg_bit = 1,
3053	.clkr = {
3054	.enable_reg = 0x5200c,
3055	.enable_mask = BIT(21),
3056	.hw.init = &(struct clk_init_data){
3057	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
3058	.ops = &clk_branch2_ops,
3059	},
3060	},
3061	};
3062
3063	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
3064	.halt_reg = 0x1e004,
3065	.halt_check = BRANCH_HALT_VOTED,
3066	.clkr = {
3067	.enable_reg = 0x52014,
3068	.enable_mask = BIT(2),
3069	.hw.init = &(struct clk_init_data){
3070	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
3071	.ops = &clk_branch2_ops,
3072	},
3073	},
3074	};
3075
3076	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
3077	.halt_reg = 0x1e008,
3078	.halt_check = BRANCH_HALT_VOTED,
3079	.hwcg_reg = 0x1e008,
3080	.hwcg_bit = 1,
3081	.clkr = {
3082	.enable_reg = 0x52014,
3083	.enable_mask = BIT(1),
3084	.hw.init = &(struct clk_init_data){
3085	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
3086	.ops = &clk_branch2_ops,
3087	},
3088	},
3089	};
3090
3091	static struct clk_branch gcc_sdcc2_ahb_clk = {
3092	.halt_reg = 0x14008,
3093	.halt_check = BRANCH_HALT,
3094	.clkr = {
3095	.enable_reg = 0x14008,
3096	.enable_mask = BIT(0),
3097	.hw.init = &(struct clk_init_data){
3098	.name = "gcc_sdcc2_ahb_clk",
3099	.ops = &clk_branch2_ops,
3100	},
3101	},
3102	};
3103
3104	static struct clk_branch gcc_sdcc2_apps_clk = {
3105	.halt_reg = 0x14004,
3106	.halt_check = BRANCH_HALT,
3107	.clkr = {
3108	.enable_reg = 0x14004,
3109	.enable_mask = BIT(0),
3110	.hw.init = &(struct clk_init_data){
3111	.name = "gcc_sdcc2_apps_clk",
3112	.parent_hws = (const struct clk_hw *[]){
3113	&gcc_sdcc2_apps_clk_src.clkr.hw
3114	},
3115	.num_parents = 1,
3116	.flags = CLK_SET_RATE_PARENT,
3117	.ops = &clk_branch2_ops,
3118	},
3119	},
3120	};
3121
3122	static struct clk_branch gcc_sdcc4_ahb_clk = {
3123	.halt_reg = 0x16008,
3124	.halt_check = BRANCH_HALT,
3125	.clkr = {
3126	.enable_reg = 0x16008,
3127	.enable_mask = BIT(0),
3128	.hw.init = &(struct clk_init_data){
3129	.name = "gcc_sdcc4_ahb_clk",
3130	.ops = &clk_branch2_ops,
3131	},
3132	},
3133	};
3134
3135	static struct clk_branch gcc_sdcc4_apps_clk = {
3136	.halt_reg = 0x16004,
3137	.halt_check = BRANCH_HALT,
3138	.clkr = {
3139	.enable_reg = 0x16004,
3140	.enable_mask = BIT(0),
3141	.hw.init = &(struct clk_init_data){
3142	.name = "gcc_sdcc4_apps_clk",
3143	.parent_hws = (const struct clk_hw *[]){
3144	&gcc_sdcc4_apps_clk_src.clkr.hw
3145	},
3146	.num_parents = 1,
3147	.flags = CLK_SET_RATE_PARENT,
3148	.ops = &clk_branch2_ops,
3149	},
3150	},
3151	};
3152
3153	/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
3154	static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3155	.halt_reg = 0x4819c,
3156	.halt_check = BRANCH_HALT_VOTED,
3157	.clkr = {
3158	.enable_reg = 0x52004,
3159	.enable_mask = BIT(0),
3160	.hw.init = &(struct clk_init_data){
3161	.name = "gcc_sys_noc_cpuss_ahb_clk",
3162	.parent_hws = (const struct clk_hw *[]){
3163	&gcc_cpuss_ahb_clk_src.clkr.hw
3164	},
3165	.num_parents = 1,
3166	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
3167	.ops = &clk_branch2_ops,
3168	},
3169	},
3170	};
3171
3172	static struct clk_branch gcc_tsif_ahb_clk = {
3173	.halt_reg = 0x36004,
3174	.halt_check = BRANCH_HALT,
3175	.clkr = {
3176	.enable_reg = 0x36004,
3177	.enable_mask = BIT(0),
3178	.hw.init = &(struct clk_init_data){
3179	.name = "gcc_tsif_ahb_clk",
3180	.ops = &clk_branch2_ops,
3181	},
3182	},
3183	};
3184
3185	static struct clk_branch gcc_tsif_inactivity_timers_clk = {
3186	.halt_reg = 0x3600c,
3187	.halt_check = BRANCH_HALT,
3188	.clkr = {
3189	.enable_reg = 0x3600c,
3190	.enable_mask = BIT(0),
3191	.hw.init = &(struct clk_init_data){
3192	.name = "gcc_tsif_inactivity_timers_clk",
3193	.ops = &clk_branch2_ops,
3194	},
3195	},
3196	};
3197
3198	static struct clk_branch gcc_tsif_ref_clk = {
3199	.halt_reg = 0x36008,
3200	.halt_check = BRANCH_HALT,
3201	.clkr = {
3202	.enable_reg = 0x36008,
3203	.enable_mask = BIT(0),
3204	.hw.init = &(struct clk_init_data){
3205	.name = "gcc_tsif_ref_clk",
3206	.parent_hws = (const struct clk_hw *[]){
3207	&gcc_tsif_ref_clk_src.clkr.hw
3208	},
3209	.num_parents = 1,
3210	.flags = CLK_SET_RATE_PARENT,
3211	.ops = &clk_branch2_ops,
3212	},
3213	},
3214	};
3215
3216	static struct clk_branch gcc_ufs_card_2_ahb_clk = {
3217	.halt_reg = 0xa2014,
3218	.halt_check = BRANCH_HALT,
3219	.hwcg_reg = 0xa2014,
3220	.hwcg_bit = 1,
3221	.clkr = {
3222	.enable_reg = 0xa2014,
3223	.enable_mask = BIT(0),
3224	.hw.init = &(struct clk_init_data){
3225	.name = "gcc_ufs_card_2_ahb_clk",
3226	.ops = &clk_branch2_ops,
3227	},
3228	},
3229	};
3230
3231	static struct clk_branch gcc_ufs_card_2_axi_clk = {
3232	.halt_reg = 0xa2010,
3233	.halt_check = BRANCH_HALT,
3234	.hwcg_reg = 0xa2010,
3235	.hwcg_bit = 1,
3236	.clkr = {
3237	.enable_reg = 0xa2010,
3238	.enable_mask = BIT(0),
3239	.hw.init = &(struct clk_init_data){
3240	.name = "gcc_ufs_card_2_axi_clk",
3241	.parent_hws = (const struct clk_hw *[]){
3242	&gcc_ufs_card_2_axi_clk_src.clkr.hw
3243	},
3244	.num_parents = 1,
3245	.flags = CLK_SET_RATE_PARENT,
3246	.ops = &clk_branch2_ops,
3247	},
3248	},
3249	};
3250
3251	static struct clk_branch gcc_ufs_card_2_ice_core_clk = {
3252	.halt_reg = 0xa205c,
3253	.halt_check = BRANCH_HALT,
3254	.hwcg_reg = 0xa205c,
3255	.hwcg_bit = 1,
3256	.clkr = {
3257	.enable_reg = 0xa205c,
3258	.enable_mask = BIT(0),
3259	.hw.init = &(struct clk_init_data){
3260	.name = "gcc_ufs_card_2_ice_core_clk",
3261	.parent_hws = (const struct clk_hw *[]){
3262	&gcc_ufs_card_2_ice_core_clk_src.clkr.hw
3263	},
3264	.num_parents = 1,
3265	.flags = CLK_SET_RATE_PARENT,
3266	.ops = &clk_branch2_ops,
3267	},
3268	},
3269	};
3270
3271	static struct clk_branch gcc_ufs_card_2_phy_aux_clk = {
3272	.halt_reg = 0xa2090,
3273	.halt_check = BRANCH_HALT,
3274	.hwcg_reg = 0xa2090,
3275	.hwcg_bit = 1,
3276	.clkr = {
3277	.enable_reg = 0xa2090,
3278	.enable_mask = BIT(0),
3279	.hw.init = &(struct clk_init_data){
3280	.name = "gcc_ufs_card_2_phy_aux_clk",
3281	.parent_hws = (const struct clk_hw *[]){
3282	&gcc_ufs_card_2_phy_aux_clk_src.clkr.hw
3283	},
3284	.num_parents = 1,
3285	.flags = CLK_SET_RATE_PARENT,
3286	.ops = &clk_branch2_ops,
3287	},
3288	},
3289	};
3290
3291	static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = {
3292	.halt_reg = 0xa201c,
3293	.halt_check = BRANCH_HALT,
3294	.clkr = {
3295	.enable_reg = 0xa201c,
3296	.enable_mask = BIT(0),
3297	.hw.init = &(struct clk_init_data){
3298	.name = "gcc_ufs_card_2_rx_symbol_0_clk",
3299	.ops = &clk_branch2_ops,
3300	},
3301	},
3302	};
3303
3304	static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = {
3305	.halt_reg = 0xa20ac,
3306	.halt_check = BRANCH_HALT,
3307	.clkr = {
3308	.enable_reg = 0xa20ac,
3309	.enable_mask = BIT(0),
3310	.hw.init = &(struct clk_init_data){
3311	.name = "gcc_ufs_card_2_rx_symbol_1_clk",
3312	.ops = &clk_branch2_ops,
3313	},
3314	},
3315	};
3316
3317	static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = {
3318	.halt_reg = 0xa2018,
3319	.halt_check = BRANCH_HALT,
3320	.clkr = {
3321	.enable_reg = 0xa2018,
3322	.enable_mask = BIT(0),
3323	.hw.init = &(struct clk_init_data){
3324	.name = "gcc_ufs_card_2_tx_symbol_0_clk",
3325	.ops = &clk_branch2_ops,
3326	},
3327	},
3328	};
3329
3330	static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
3331	.halt_reg = 0xa2058,
3332	.halt_check = BRANCH_HALT,
3333	.hwcg_reg = 0xa2058,
3334	.hwcg_bit = 1,
3335	.clkr = {
3336	.enable_reg = 0xa2058,
3337	.enable_mask = BIT(0),
3338	.hw.init = &(struct clk_init_data){
3339	.name = "gcc_ufs_card_2_unipro_core_clk",
3340	.parent_hws = (const struct clk_hw *[]){
3341	&gcc_ufs_card_2_unipro_core_clk_src.clkr.hw
3342	},
3343	.num_parents = 1,
3344	.flags = CLK_SET_RATE_PARENT,
3345	.ops = &clk_branch2_ops,
3346	},
3347	},
3348	};
3349
3350	static struct clk_branch gcc_ufs_card_clkref_en = {
3351	.halt_reg = 0x8c004,
3352	.halt_check = BRANCH_HALT,
3353	.clkr = {
3354	.enable_reg = 0x8c004,
3355	.enable_mask = BIT(0),
3356	.hw.init = &(const struct clk_init_data) {
3357	.name = "gcc_ufs_card_clkref_en",
3358	.ops = &clk_branch2_ops,
3359	},
3360	},
3361	};
3362
3363	static struct clk_branch gcc_ufs_card_ahb_clk = {
3364	.halt_reg = 0x75014,
3365	.halt_check = BRANCH_HALT,
3366	.hwcg_reg = 0x75014,
3367	.hwcg_bit = 1,
3368	.clkr = {
3369	.enable_reg = 0x75014,
3370	.enable_mask = BIT(0),
3371	.hw.init = &(struct clk_init_data){
3372	.name = "gcc_ufs_card_ahb_clk",
3373	.ops = &clk_branch2_ops,
3374	},
3375	},
3376	};
3377
3378	static struct clk_branch gcc_ufs_card_axi_clk = {
3379	.halt_reg = 0x75010,
3380	.halt_check = BRANCH_HALT,
3381	.hwcg_reg = 0x75010,
3382	.hwcg_bit = 1,
3383	.clkr = {
3384	.enable_reg = 0x75010,
3385	.enable_mask = BIT(0),
3386	.hw.init = &(struct clk_init_data){
3387	.name = "gcc_ufs_card_axi_clk",
3388	.parent_hws = (const struct clk_hw *[]){
3389	&gcc_ufs_card_axi_clk_src.clkr.hw
3390	},
3391	.num_parents = 1,
3392	.flags = CLK_SET_RATE_PARENT,
3393	.ops = &clk_branch2_ops,
3394	},
3395	},
3396	};
3397
3398	static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
3399	.halt_reg = 0x75010,
3400	.halt_check = BRANCH_HALT,
3401	.hwcg_reg = 0x75010,
3402	.hwcg_bit = 1,
3403	.clkr = {
3404	.enable_reg = 0x75010,
3405	.enable_mask = BIT(1),
3406	.hw.init = &(struct clk_init_data){
3407	.name = "gcc_ufs_card_axi_hw_ctl_clk",
3408	.parent_hws = (const struct clk_hw *[]){
3409	&gcc_ufs_card_axi_clk.clkr.hw
3410	},
3411	.num_parents = 1,
3412	.flags = CLK_SET_RATE_PARENT,
3413	.ops = &clk_branch_simple_ops,
3414	},
3415	},
3416	};
3417
3418	static struct clk_branch gcc_ufs_card_ice_core_clk = {
3419	.halt_reg = 0x7505c,
3420	.halt_check = BRANCH_HALT,
3421	.hwcg_reg = 0x7505c,
3422	.hwcg_bit = 1,
3423	.clkr = {
3424	.enable_reg = 0x7505c,
3425	.enable_mask = BIT(0),
3426	.hw.init = &(struct clk_init_data){
3427	.name = "gcc_ufs_card_ice_core_clk",
3428	.parent_hws = (const struct clk_hw *[]){
3429	&gcc_ufs_card_ice_core_clk_src.clkr.hw
3430	},
3431	.num_parents = 1,
3432	.flags = CLK_SET_RATE_PARENT,
3433	.ops = &clk_branch2_ops,
3434	},
3435	},
3436	};
3437
3438	static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
3439	.halt_reg = 0x7505c,
3440	.halt_check = BRANCH_HALT,
3441	.hwcg_reg = 0x7505c,
3442	.hwcg_bit = 1,
3443	.clkr = {
3444	.enable_reg = 0x7505c,
3445	.enable_mask = BIT(1),
3446	.hw.init = &(struct clk_init_data){
3447	.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
3448	.parent_hws = (const struct clk_hw *[]){
3449	&gcc_ufs_card_ice_core_clk.clkr.hw
3450	},
3451	.num_parents = 1,
3452	.flags = CLK_SET_RATE_PARENT,
3453	.ops = &clk_branch_simple_ops,
3454	},
3455	},
3456	};
3457
3458	static struct clk_branch gcc_ufs_card_phy_aux_clk = {
3459	.halt_reg = 0x75090,
3460	.halt_check = BRANCH_HALT,
3461	.hwcg_reg = 0x75090,
3462	.hwcg_bit = 1,
3463	.clkr = {
3464	.enable_reg = 0x75090,
3465	.enable_mask = BIT(0),
3466	.hw.init = &(struct clk_init_data){
3467	.name = "gcc_ufs_card_phy_aux_clk",
3468	.parent_hws = (const struct clk_hw *[]){
3469	&gcc_ufs_card_phy_aux_clk_src.clkr.hw
3470	},
3471	.num_parents = 1,
3472	.flags = CLK_SET_RATE_PARENT,
3473	.ops = &clk_branch2_ops,
3474	},
3475	},
3476	};
3477
3478	static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
3479	.halt_reg = 0x75090,
3480	.halt_check = BRANCH_HALT,
3481	.hwcg_reg = 0x75090,
3482	.hwcg_bit = 1,
3483	.clkr = {
3484	.enable_reg = 0x75090,
3485	.enable_mask = BIT(1),
3486	.hw.init = &(struct clk_init_data){
3487	.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
3488	.parent_hws = (const struct clk_hw *[]){
3489	&gcc_ufs_card_phy_aux_clk.clkr.hw
3490	},
3491	.num_parents = 1,
3492	.flags = CLK_SET_RATE_PARENT,
3493	.ops = &clk_branch_simple_ops,
3494	},
3495	},
3496	};
3497
3498	static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
3499	.halt_reg = 0x7501c,
3500	.halt_check = BRANCH_HALT_DELAY,
3501	.clkr = {
3502	.enable_reg = 0x7501c,
3503	.enable_mask = BIT(0),
3504	.hw.init = &(struct clk_init_data){
3505	.name = "gcc_ufs_card_rx_symbol_0_clk",
3506	.ops = &clk_branch2_ops,
3507	},
3508	},
3509	};
3510
3511	static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
3512	.halt_reg = 0x750ac,
3513	.halt_check = BRANCH_HALT_DELAY,
3514	.clkr = {
3515	.enable_reg = 0x750ac,
3516	.enable_mask = BIT(0),
3517	.hw.init = &(struct clk_init_data){
3518	.name = "gcc_ufs_card_rx_symbol_1_clk",
3519	.ops = &clk_branch2_ops,
3520	},
3521	},
3522	};
3523
3524	static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
3525	.halt_reg = 0x75018,
3526	.halt_check = BRANCH_HALT_DELAY,
3527	.clkr = {
3528	.enable_reg = 0x75018,
3529	.enable_mask = BIT(0),
3530	.hw.init = &(struct clk_init_data){
3531	.name = "gcc_ufs_card_tx_symbol_0_clk",
3532	.ops = &clk_branch2_ops,
3533	},
3534	},
3535	};
3536
3537	static struct clk_branch gcc_ufs_card_unipro_core_clk = {
3538	.halt_reg = 0x75058,
3539	.halt_check = BRANCH_HALT,
3540	.hwcg_reg = 0x75058,
3541	.hwcg_bit = 1,
3542	.clkr = {
3543	.enable_reg = 0x75058,
3544	.enable_mask = BIT(0),
3545	.hw.init = &(struct clk_init_data){
3546	.name = "gcc_ufs_card_unipro_core_clk",
3547	.parent_hws = (const struct clk_hw *[]){
3548	&gcc_ufs_card_unipro_core_clk_src.clkr.hw
3549	},
3550	.num_parents = 1,
3551	.flags = CLK_SET_RATE_PARENT,
3552	.ops = &clk_branch2_ops,
3553	},
3554	},
3555	};
3556
3557	static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
3558	.halt_reg = 0x75058,
3559	.halt_check = BRANCH_HALT,
3560	.hwcg_reg = 0x75058,
3561	.hwcg_bit = 1,
3562	.clkr = {
3563	.enable_reg = 0x75058,
3564	.enable_mask = BIT(1),
3565	.hw.init = &(struct clk_init_data){
3566	.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
3567	.parent_hws = (const struct clk_hw *[]){
3568	&gcc_ufs_card_unipro_core_clk.clkr.hw
3569	},
3570	.num_parents = 1,
3571	.flags = CLK_SET_RATE_PARENT,
3572	.ops = &clk_branch_simple_ops,
3573	},
3574	},
3575	};
3576
3577	static struct clk_branch gcc_ufs_mem_clkref_en = {
3578	.halt_reg = 0x8c000,
3579	.halt_check = BRANCH_HALT,
3580	.clkr = {
3581	.enable_reg = 0x8c000,
3582	.enable_mask = BIT(0),
3583	.hw.init = &(const struct clk_init_data) {
3584	.name = "gcc_ufs_mem_clkref_en",
3585	.ops = &clk_branch2_ops,
3586	},
3587	},
3588	};
3589
3590	static struct clk_branch gcc_ufs_phy_ahb_clk = {
3591	.halt_reg = 0x77014,
3592	.halt_check = BRANCH_HALT,
3593	.hwcg_reg = 0x77014,
3594	.hwcg_bit = 1,
3595	.clkr = {
3596	.enable_reg = 0x77014,
3597	.enable_mask = BIT(0),
3598	.hw.init = &(struct clk_init_data){
3599	.name = "gcc_ufs_phy_ahb_clk",
3600	.ops = &clk_branch2_ops,
3601	},
3602	},
3603	};
3604
3605	static struct clk_branch gcc_ufs_phy_axi_clk = {
3606	.halt_reg = 0x77010,
3607	.halt_check = BRANCH_HALT,
3608	.hwcg_reg = 0x77010,
3609	.hwcg_bit = 1,
3610	.clkr = {
3611	.enable_reg = 0x77010,
3612	.enable_mask = BIT(0),
3613	.hw.init = &(struct clk_init_data){
3614	.name = "gcc_ufs_phy_axi_clk",
3615	.parent_hws = (const struct clk_hw *[]){
3616	&gcc_ufs_phy_axi_clk_src.clkr.hw
3617	},
3618	.num_parents = 1,
3619	.flags = CLK_SET_RATE_PARENT,
3620	.ops = &clk_branch2_ops,
3621	},
3622	},
3623	};
3624
3625	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3626	.halt_reg = 0x77010,
3627	.halt_check = BRANCH_HALT,
3628	.hwcg_reg = 0x77010,
3629	.hwcg_bit = 1,
3630	.clkr = {
3631	.enable_reg = 0x77010,
3632	.enable_mask = BIT(1),
3633	.hw.init = &(struct clk_init_data){
3634	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3635	.parent_hws = (const struct clk_hw *[]){
3636	&gcc_ufs_phy_axi_clk.clkr.hw
3637	},
3638	.num_parents = 1,
3639	.flags = CLK_SET_RATE_PARENT,
3640	.ops = &clk_branch_simple_ops,
3641	},
3642	},
3643	};
3644
3645	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3646	.halt_reg = 0x7705c,
3647	.halt_check = BRANCH_HALT,
3648	.hwcg_reg = 0x7705c,
3649	.hwcg_bit = 1,
3650	.clkr = {
3651	.enable_reg = 0x7705c,
3652	.enable_mask = BIT(0),
3653	.hw.init = &(struct clk_init_data){
3654	.name = "gcc_ufs_phy_ice_core_clk",
3655	.parent_hws = (const struct clk_hw *[]){
3656	&gcc_ufs_phy_ice_core_clk_src.clkr.hw
3657	},
3658	.num_parents = 1,
3659	.flags = CLK_SET_RATE_PARENT,
3660	.ops = &clk_branch2_ops,
3661	},
3662	},
3663	};
3664
3665	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3666	.halt_reg = 0x7705c,
3667	.halt_check = BRANCH_HALT,
3668	.hwcg_reg = 0x7705c,
3669	.hwcg_bit = 1,
3670	.clkr = {
3671	.enable_reg = 0x7705c,
3672	.enable_mask = BIT(1),
3673	.hw.init = &(struct clk_init_data){
3674	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3675	.parent_hws = (const struct clk_hw *[]){
3676	&gcc_ufs_phy_ice_core_clk.clkr.hw
3677	},
3678	.num_parents = 1,
3679	.flags = CLK_SET_RATE_PARENT,
3680	.ops = &clk_branch_simple_ops,
3681	},
3682	},
3683	};
3684
3685	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3686	.halt_reg = 0x77090,
3687	.halt_check = BRANCH_HALT,
3688	.hwcg_reg = 0x77090,
3689	.hwcg_bit = 1,
3690	.clkr = {
3691	.enable_reg = 0x77090,
3692	.enable_mask = BIT(0),
3693	.hw.init = &(struct clk_init_data){
3694	.name = "gcc_ufs_phy_phy_aux_clk",
3695	.parent_hws = (const struct clk_hw *[]){
3696	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw
3697	},
3698	.num_parents = 1,
3699	.flags = CLK_SET_RATE_PARENT,
3700	.ops = &clk_branch2_ops,
3701	},
3702	},
3703	};
3704
3705	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3706	.halt_reg = 0x77090,
3707	.halt_check = BRANCH_HALT,
3708	.hwcg_reg = 0x77090,
3709	.hwcg_bit = 1,
3710	.clkr = {
3711	.enable_reg = 0x77090,
3712	.enable_mask = BIT(1),
3713	.hw.init = &(struct clk_init_data){
3714	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3715	.parent_hws = (const struct clk_hw *[]){
3716	&gcc_ufs_phy_phy_aux_clk.clkr.hw
3717	},
3718	.num_parents = 1,
3719	.flags = CLK_SET_RATE_PARENT,
3720	.ops = &clk_branch_simple_ops,
3721	},
3722	},
3723	};
3724
3725	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3726	.halt_reg = 0x7701c,
3727	.halt_check = BRANCH_HALT_SKIP,
3728	.clkr = {
3729	.enable_reg = 0x7701c,
3730	.enable_mask = BIT(0),
3731	.hw.init = &(struct clk_init_data){
3732	.name = "gcc_ufs_phy_rx_symbol_0_clk",
3733	.ops = &clk_branch2_ops,
3734	},
3735	},
3736	};
3737
3738	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3739	.halt_reg = 0x770ac,
3740	.halt_check = BRANCH_HALT_SKIP,
3741	.clkr = {
3742	.enable_reg = 0x770ac,
3743	.enable_mask = BIT(0),
3744	.hw.init = &(struct clk_init_data){
3745	.name = "gcc_ufs_phy_rx_symbol_1_clk",
3746	.ops = &clk_branch2_ops,
3747	},
3748	},
3749	};
3750
3751	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3752	.halt_reg = 0x77018,
3753	.halt_check = BRANCH_HALT_SKIP,
3754	.clkr = {
3755	.enable_reg = 0x77018,
3756	.enable_mask = BIT(0),
3757	.hw.init = &(struct clk_init_data){
3758	.name = "gcc_ufs_phy_tx_symbol_0_clk",
3759	.ops = &clk_branch2_ops,
3760	},
3761	},
3762	};
3763
3764	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3765	.halt_reg = 0x77058,
3766	.halt_check = BRANCH_HALT,
3767	.hwcg_reg = 0x77058,
3768	.hwcg_bit = 1,
3769	.clkr = {
3770	.enable_reg = 0x77058,
3771	.enable_mask = BIT(0),
3772	.hw.init = &(struct clk_init_data){
3773	.name = "gcc_ufs_phy_unipro_core_clk",
3774	.parent_hws = (const struct clk_hw *[]){
3775	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw
3776	},
3777	.num_parents = 1,
3778	.flags = CLK_SET_RATE_PARENT,
3779	.ops = &clk_branch2_ops,
3780	},
3781	},
3782	};
3783
3784	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3785	.halt_reg = 0x77058,
3786	.halt_check = BRANCH_HALT,
3787	.hwcg_reg = 0x77058,
3788	.hwcg_bit = 1,
3789	.clkr = {
3790	.enable_reg = 0x77058,
3791	.enable_mask = BIT(1),
3792	.hw.init = &(struct clk_init_data){
3793	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3794	.parent_hws = (const struct clk_hw *[]){
3795	&gcc_ufs_phy_unipro_core_clk.clkr.hw
3796	},
3797	.num_parents = 1,
3798	.flags = CLK_SET_RATE_PARENT,
3799	.ops = &clk_branch_simple_ops,
3800	},
3801	},
3802	};
3803
3804	static struct clk_branch gcc_usb30_mp_master_clk = {
3805	.halt_reg = 0xa6010,
3806	.halt_check = BRANCH_HALT,
3807	.clkr = {
3808	.enable_reg = 0xa6010,
3809	.enable_mask = BIT(0),
3810	.hw.init = &(struct clk_init_data){
3811	.name = "gcc_usb30_mp_master_clk",
3812	.parent_hws = (const struct clk_hw *[]){
3813	&gcc_usb30_mp_master_clk_src.clkr.hw },
3814	.num_parents = 1,
3815	.flags = CLK_SET_RATE_PARENT,
3816	.ops = &clk_branch2_ops,
3817	},
3818	},
3819	};
3820
3821	static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
3822	.halt_reg = 0xa6018,
3823	.halt_check = BRANCH_HALT,
3824	.clkr = {
3825	.enable_reg = 0xa6018,
3826	.enable_mask = BIT(0),
3827	.hw.init = &(struct clk_init_data){
3828	.name = "gcc_usb30_mp_mock_utmi_clk",
3829	.parent_hws = (const struct clk_hw *[]){
3830	&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw
3831	},
3832	.num_parents = 1,
3833	.flags = CLK_SET_RATE_PARENT,
3834	.ops = &clk_branch2_ops,
3835	},
3836	},
3837	};
3838
3839	static struct clk_branch gcc_usb30_mp_sleep_clk = {
3840	.halt_reg = 0xa6014,
3841	.halt_check = BRANCH_HALT,
3842	.clkr = {
3843	.enable_reg = 0xa6014,
3844	.enable_mask = BIT(0),
3845	.hw.init = &(struct clk_init_data){
3846	.name = "gcc_usb30_mp_sleep_clk",
3847	.ops = &clk_branch2_ops,
3848	},
3849	},
3850	};
3851
3852	static struct clk_branch gcc_usb30_prim_master_clk = {
3853	.halt_reg = 0xf010,
3854	.halt_check = BRANCH_HALT,
3855	.clkr = {
3856	.enable_reg = 0xf010,
3857	.enable_mask = BIT(0),
3858	.hw.init = &(struct clk_init_data){
3859	.name = "gcc_usb30_prim_master_clk",
3860	.parent_hws = (const struct clk_hw *[]){
3861	&gcc_usb30_prim_master_clk_src.clkr.hw },
3862	.num_parents = 1,
3863	.flags = CLK_SET_RATE_PARENT,
3864	.ops = &clk_branch2_ops,
3865	},
3866	},
3867	};
3868
3869	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3870	.halt_reg = 0xf018,
3871	.halt_check = BRANCH_HALT,
3872	.clkr = {
3873	.enable_reg = 0xf018,
3874	.enable_mask = BIT(0),
3875	.hw.init = &(struct clk_init_data){
3876	.name = "gcc_usb30_prim_mock_utmi_clk",
3877	.parent_hws = (const struct clk_hw *[]){
3878	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw
3879	},
3880	.num_parents = 1,
3881	.flags = CLK_SET_RATE_PARENT,
3882	.ops = &clk_branch2_ops,
3883	},
3884	},
3885	};
3886
3887	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3888	.halt_reg = 0xf014,
3889	.halt_check = BRANCH_HALT,
3890	.clkr = {
3891	.enable_reg = 0xf014,
3892	.enable_mask = BIT(0),
3893	.hw.init = &(struct clk_init_data){
3894	.name = "gcc_usb30_prim_sleep_clk",
3895	.ops = &clk_branch2_ops,
3896	},
3897	},
3898	};
3899
3900	static struct clk_branch gcc_usb30_sec_master_clk = {
3901	.halt_reg = 0x10010,
3902	.halt_check = BRANCH_HALT,
3903	.clkr = {
3904	.enable_reg = 0x10010,
3905	.enable_mask = BIT(0),
3906	.hw.init = &(struct clk_init_data){
3907	.name = "gcc_usb30_sec_master_clk",
3908	.parent_hws = (const struct clk_hw *[]){
3909	&gcc_usb30_sec_master_clk_src.clkr.hw },
3910	.num_parents = 1,
3911	.flags = CLK_SET_RATE_PARENT,
3912	.ops = &clk_branch2_ops,
3913	},
3914	},
3915	};
3916
3917	static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3918	.halt_reg = 0x10018,
3919	.halt_check = BRANCH_HALT,
3920	.clkr = {
3921	.enable_reg = 0x10018,
3922	.enable_mask = BIT(0),
3923	.hw.init = &(struct clk_init_data){
3924	.name = "gcc_usb30_sec_mock_utmi_clk",
3925	.parent_hws = (const struct clk_hw *[]){
3926	&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw
3927	},
3928	.num_parents = 1,
3929	.flags = CLK_SET_RATE_PARENT,
3930	.ops = &clk_branch2_ops,
3931	},
3932	},
3933	};
3934
3935	static struct clk_branch gcc_usb30_sec_sleep_clk = {
3936	.halt_reg = 0x10014,
3937	.halt_check = BRANCH_HALT,
3938	.clkr = {
3939	.enable_reg = 0x10014,
3940	.enable_mask = BIT(0),
3941	.hw.init = &(struct clk_init_data){
3942	.name = "gcc_usb30_sec_sleep_clk",
3943	.ops = &clk_branch2_ops,
3944	},
3945	},
3946	};
3947
3948	static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
3949	.halt_reg = 0xa6050,
3950	.halt_check = BRANCH_HALT,
3951	.clkr = {
3952	.enable_reg = 0xa6050,
3953	.enable_mask = BIT(0),
3954	.hw.init = &(struct clk_init_data){
3955	.name = "gcc_usb3_mp_phy_aux_clk",
3956	.parent_hws = (const struct clk_hw *[]){
3957	&gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3958	},
3959	.num_parents = 1,
3960	.flags = CLK_SET_RATE_PARENT,
3961	.ops = &clk_branch2_ops,
3962	},
3963	},
3964	};
3965
3966	static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
3967	.halt_reg = 0xa6054,
3968	.halt_check = BRANCH_HALT,
3969	.clkr = {
3970	.enable_reg = 0xa6054,
3971	.enable_mask = BIT(0),
3972	.hw.init = &(struct clk_init_data){
3973	.name = "gcc_usb3_mp_phy_com_aux_clk",
3974	.parent_hws = (const struct clk_hw *[]){
3975	&gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3976	},
3977	.num_parents = 1,
3978	.flags = CLK_SET_RATE_PARENT,
3979	.ops = &clk_branch2_ops,
3980	},
3981	},
3982	};
3983
3984	static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
3985	.halt_reg = 0xa6058,
3986	.halt_check = BRANCH_HALT_SKIP,
3987	.clkr = {
3988	.enable_reg = 0xa6058,
3989	.enable_mask = BIT(0),
3990	.hw.init = &(struct clk_init_data){
3991	.name = "gcc_usb3_mp_phy_pipe_0_clk",
3992	.ops = &clk_branch2_ops,
3993	},
3994	},
3995	};
3996
3997	static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
3998	.halt_reg = 0xa605c,
3999	.halt_check = BRANCH_HALT_SKIP,
4000	.clkr = {
4001	.enable_reg = 0xa605c,
4002	.enable_mask = BIT(0),
4003	.hw.init = &(struct clk_init_data){
4004	.name = "gcc_usb3_mp_phy_pipe_1_clk",
4005	.ops = &clk_branch2_ops,
4006	},
4007	},
4008	};
4009
4010	static struct clk_branch gcc_usb3_prim_clkref_clk = {
4011	.halt_reg = 0x8c008,
4012	.halt_check = BRANCH_HALT,
4013	.clkr = {
4014	.enable_reg = 0x8c008,
4015	.enable_mask = BIT(0),
4016	.hw.init = &(struct clk_init_data){
4017	.name = "gcc_usb3_prim_clkref_clk",
4018	.ops = &clk_branch2_ops,
4019	},
4020	},
4021	};
4022
4023	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
4024	.halt_reg = 0xf050,
4025	.halt_check = BRANCH_HALT,
4026	.clkr = {
4027	.enable_reg = 0xf050,
4028	.enable_mask = BIT(0),
4029	.hw.init = &(struct clk_init_data){
4030	.name = "gcc_usb3_prim_phy_aux_clk",
4031	.parent_hws = (const struct clk_hw *[]){
4032	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4033	},
4034	.num_parents = 1,
4035	.flags = CLK_SET_RATE_PARENT,
4036	.ops = &clk_branch2_ops,
4037	},
4038	},
4039	};
4040
4041	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
4042	.halt_reg = 0xf054,
4043	.halt_check = BRANCH_HALT,
4044	.clkr = {
4045	.enable_reg = 0xf054,
4046	.enable_mask = BIT(0),
4047	.hw.init = &(struct clk_init_data){
4048	.name = "gcc_usb3_prim_phy_com_aux_clk",
4049	.parent_hws = (const struct clk_hw *[]){
4050	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4051	},
4052	.num_parents = 1,
4053	.flags = CLK_SET_RATE_PARENT,
4054	.ops = &clk_branch2_ops,
4055	},
4056	},
4057	};
4058
4059	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
4060	.halt_reg = 0xf058,
4061	.halt_check = BRANCH_HALT_SKIP,
4062	.clkr = {
4063	.enable_reg = 0xf058,
4064	.enable_mask = BIT(0),
4065	.hw.init = &(struct clk_init_data){
4066	.name = "gcc_usb3_prim_phy_pipe_clk",
4067	.ops = &clk_branch2_ops,
4068	},
4069	},
4070	};
4071
4072	static struct clk_branch gcc_usb3_sec_clkref_clk = {
4073	.halt_reg = 0x8c028,
4074	.halt_check = BRANCH_HALT,
4075	.clkr = {
4076	.enable_reg = 0x8c028,
4077	.enable_mask = BIT(0),
4078	.hw.init = &(struct clk_init_data){
4079	.name = "gcc_usb3_sec_clkref_clk",
4080	.ops = &clk_branch2_ops,
4081	},
4082	},
4083	};
4084
4085	static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
4086	.halt_reg = 0x10050,
4087	.halt_check = BRANCH_HALT,
4088	.clkr = {
4089	.enable_reg = 0x10050,
4090	.enable_mask = BIT(0),
4091	.hw.init = &(struct clk_init_data){
4092	.name = "gcc_usb3_sec_phy_aux_clk",
4093	.parent_hws = (const struct clk_hw *[]){
4094	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4095	},
4096	.num_parents = 1,
4097	.flags = CLK_SET_RATE_PARENT,
4098	.ops = &clk_branch2_ops,
4099	},
4100	},
4101	};
4102
4103	static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
4104	.halt_reg = 0x10054,
4105	.halt_check = BRANCH_HALT,
4106	.clkr = {
4107	.enable_reg = 0x10054,
4108	.enable_mask = BIT(0),
4109	.hw.init = &(struct clk_init_data){
4110	.name = "gcc_usb3_sec_phy_com_aux_clk",
4111	.parent_hws = (const struct clk_hw *[]){
4112	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4113	},
4114	.num_parents = 1,
4115	.flags = CLK_SET_RATE_PARENT,
4116	.ops = &clk_branch2_ops,
4117	},
4118	},
4119	};
4120
4121	static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
4122	.halt_reg = 0x10058,
4123	.halt_check = BRANCH_HALT_SKIP,
4124	.clkr = {
4125	.enable_reg = 0x10058,
4126	.enable_mask = BIT(0),
4127	.hw.init = &(struct clk_init_data){
4128	.name = "gcc_usb3_sec_phy_pipe_clk",
4129	.ops = &clk_branch2_ops,
4130	},
4131	},
4132	};
4133
4134	static struct clk_branch gcc_video_axi0_clk = {
4135	.halt_reg = 0xb024,
4136	.halt_check = BRANCH_HALT,
4137	.clkr = {
4138	.enable_reg = 0xb024,
4139	.enable_mask = BIT(0),
4140	.hw.init = &(struct clk_init_data){
4141	.name = "gcc_video_axi0_clk",
4142	.ops = &clk_branch2_ops,
4143	},
4144	},
4145	};
4146
4147	static struct clk_branch gcc_video_axi1_clk = {
4148	.halt_reg = 0xb028,
4149	.halt_check = BRANCH_HALT,
4150	.clkr = {
4151	.enable_reg = 0xb028,
4152	.enable_mask = BIT(0),
4153	.hw.init = &(struct clk_init_data){
4154	.name = "gcc_video_axi1_clk",
4155	.ops = &clk_branch2_ops,
4156	},
4157	},
4158	};
4159
4160	static struct clk_branch gcc_video_axic_clk = {
4161	.halt_reg = 0xb02c,
4162	.halt_check = BRANCH_HALT,
4163	.clkr = {
4164	.enable_reg = 0xb02c,
4165	.enable_mask = BIT(0),
4166	.hw.init = &(struct clk_init_data){
4167	.name = "gcc_video_axic_clk",
4168	.ops = &clk_branch2_ops,
4169	},
4170	},
4171	};
4172
4173	static struct gdsc usb30_sec_gdsc = {
4174	.gdscr = 0x10004,
4175	.pd = {
4176	.name = "usb30_sec_gdsc",
4177	},
4178	.pwrsts = PWRSTS_OFF_ON,
4179	.flags = POLL_CFG_GDSCR,
4180	};
4181
4182	static struct gdsc emac_gdsc = {
4183	.gdscr = 0x6004,
4184	.pd = {
4185	.name = "emac_gdsc",
4186	},
4187	.pwrsts = PWRSTS_OFF_ON,
4188	.flags = POLL_CFG_GDSCR,
4189	};
4190
4191	static struct gdsc usb30_prim_gdsc = {
4192	.gdscr = 0xf004,
4193	.pd = {
4194	.name = "usb30_prim_gdsc",
4195	},
4196	.pwrsts = PWRSTS_OFF_ON,
4197	.flags = POLL_CFG_GDSCR,
4198	};
4199
4200	static struct gdsc pcie_0_gdsc = {
4201	.gdscr = 0x6b004,
4202	.pd = {
4203	.name = "pcie_0_gdsc",
4204	},
4205	.pwrsts = PWRSTS_OFF_ON,
4206	.flags = POLL_CFG_GDSCR,
4207	};
4208
4209	static struct gdsc ufs_card_gdsc = {
4210	.gdscr = 0x75004,
4211	.pd = {
4212	.name = "ufs_card_gdsc",
4213	},
4214	.pwrsts = PWRSTS_OFF_ON,
4215	.flags = POLL_CFG_GDSCR,
4216	};
4217
4218	static struct gdsc ufs_phy_gdsc = {
4219	.gdscr = 0x77004,
4220	.pd = {
4221	.name = "ufs_phy_gdsc",
4222	},
4223	.pwrsts = PWRSTS_OFF_ON,
4224	.flags = POLL_CFG_GDSCR,
4225	};
4226
4227	static struct gdsc pcie_1_gdsc = {
4228	.gdscr = 0x8d004,
4229	.pd = {
4230	.name = "pcie_1_gdsc",
4231	},
4232	.pwrsts = PWRSTS_OFF_ON,
4233	.flags = POLL_CFG_GDSCR,
4234	};
4235
4236	static struct gdsc pcie_2_gdsc = {
4237	.gdscr = 0x9d004,
4238	.pd = {
4239	.name = "pcie_2_gdsc",
4240	},
4241	.pwrsts = PWRSTS_OFF_ON,
4242	.flags = POLL_CFG_GDSCR,
4243	};
4244
4245	static struct gdsc ufs_card_2_gdsc = {
4246	.gdscr = 0xa2004,
4247	.pd = {
4248	.name = "ufs_card_2_gdsc",
4249	},
4250	.pwrsts = PWRSTS_OFF_ON,
4251	.flags = POLL_CFG_GDSCR,
4252	};
4253
4254	static struct gdsc pcie_3_gdsc = {
4255	.gdscr = 0xa3004,
4256	.pd = {
4257	.name = "pcie_3_gdsc",
4258	},
4259	.pwrsts = PWRSTS_OFF_ON,
4260	.flags = POLL_CFG_GDSCR,
4261	};
4262
4263	static struct gdsc usb30_mp_gdsc = {
4264	.gdscr = 0xa6004,
4265	.pd = {
4266	.name = "usb30_mp_gdsc",
4267	},
4268	.pwrsts = PWRSTS_OFF_ON,
4269	.flags = POLL_CFG_GDSCR,
4270	};
4271
4272	static struct clk_regmap *gcc_sc8180x_clocks[] = {
4273	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
4274	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4275	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
4276	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4277	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
4278	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
4279	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4280	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
4281	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
4282	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
4283	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
4284	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
4285	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
4286	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
4287	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
4288	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
4289	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
4290	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
4291	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
4292	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
4293	[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
4294	[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
4295	[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
4296	[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
4297	[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
4298	[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
4299	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4300	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
4301	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4302	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
4303	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4304	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
4305	[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
4306	[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
4307	[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
4308	[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
4309	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
4310	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
4311	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
4312	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
4313	[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
4314	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
4315	[GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,
4316	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
4317	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
4318	[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
4319	[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
4320	[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
4321	[GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
4322	[GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr,
4323	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
4324	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
4325	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
4326	[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
4327	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
4328	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
4329	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
4330	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
4331	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
4332	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
4333	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
4334	[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
4335	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
4336	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
4337	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
4338	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
4339	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
4340	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
4341	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
4342	[GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,
4343	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
4344	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
4345	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
4346	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
4347	[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
4348	[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
4349	[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
4350	[GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,
4351	[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
4352	[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
4353	[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
4354	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
4355	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
4356	[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
4357	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4358	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
4359	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4360	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
4361	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4362	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
4363	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
4364	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
4365	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
4366	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
4367	[GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr,
4368	[GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr,
4369	[GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr,
4370	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
4371	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
4372	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
4373	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
4374	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4375	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4376	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4377	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4378	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4379	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4380	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4381	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4382	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4383	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4384	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4385	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
4386	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
4387	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
4388	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
4389	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4390	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4391	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4392	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4393	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4394	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4395	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4396	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4397	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4398	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4399	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4400	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4401	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
4402	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
4403	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
4404	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
4405	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
4406	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
4407	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
4408	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
4409	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
4410	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
4411	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
4412	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
4413	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4414	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4415	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4416	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4417	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
4418	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
4419	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4420	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4421	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
4422	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
4423	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
4424	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
4425	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
4426	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
4427	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
4428	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
4429	[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
4430	[GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr,
4431	[GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr,
4432	[GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr,
4433	[GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr,
4434	[GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr,
4435	[GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr,
4436	[GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr,
4437	[GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr,
4438	[GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr,
4439	[GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
4440	[GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
4441	[GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
4442	[GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr,
4443	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
4444	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
4445	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
4446	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
4447	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
4448	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
4449	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
4450	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
4451	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
4452	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
4453	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
4454	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
4455	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
4456	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
4457	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
4458	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
4459	[GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr,
4460	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4461	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4462	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4463	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
4464	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4465	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4466	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
4467	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4468	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4469	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
4470	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4471	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
4472	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4473	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4474	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4475	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
4476	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
4477	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
4478	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
4479	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
4480	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
4481	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4482	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4483	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4484	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4485	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4486	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
4487	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
4488	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
4489	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
4490	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
4491	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
4492	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
4493	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
4494	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
4495	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
4496	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
4497	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
4498	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4499	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4500	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4501	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
4502	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
4503	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
4504	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
4505	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
4506	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4507	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
4508	[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
4509	[GPLL0] = &gpll0.clkr,
4510	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
4511	[GPLL1] = &gpll1.clkr,
4512	[GPLL4] = &gpll4.clkr,
4513	[GPLL7] = &gpll7.clkr,
4514	};
4515
4516	static const struct qcom_reset_map gcc_sc8180x_resets[] = {
4517	[GCC_EMAC_BCR] = { 0x6000 },
4518	[GCC_GPU_BCR] = { 0x71000 },
4519	[GCC_MMSS_BCR] = { 0xb000 },
4520	[GCC_NPU_BCR] = { 0x4d000 },
4521	[GCC_PCIE_0_BCR] = { 0x6b000 },
4522	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4523	[GCC_PCIE_1_BCR] = { 0x8d000 },
4524	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4525	[GCC_PCIE_2_BCR] = { 0x9d000 },
4526	[GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4527	[GCC_PCIE_3_BCR] = { 0xa3000 },
4528	[GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4529	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
4530	[GCC_PDM_BCR] = { 0x33000 },
4531	[GCC_PRNG_BCR] = { 0x34000 },
4532	[GCC_QSPI_1_BCR] = { 0x4a000 },
4533	[GCC_QSPI_BCR] = { 0x24008 },
4534	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4535	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4536	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4537	[GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4538	[GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4539	[GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4540	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4541	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4542	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4543	[GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4544	[GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4545	[GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4546	[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4547	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4548	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4549	[GCC_SDCC2_BCR] = { 0x14000 },
4550	[GCC_SDCC4_BCR] = { 0x16000 },
4551	[GCC_TSIF_BCR] = { 0x36000 },
4552	[GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4553	[GCC_UFS_CARD_BCR] = { 0x75000 },
4554	[GCC_UFS_PHY_BCR] = { 0x77000 },
4555	[GCC_USB30_MP_BCR] = { 0xa6000 },
4556	[GCC_USB30_PRIM_BCR] = { 0xf000 },
4557	[GCC_USB30_SEC_BCR] = { 0x10000 },
4558	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4559	[GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },
4560	[GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },
4561	[GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
4562	};
4563
4564	static struct gdsc *gcc_sc8180x_gdscs[] = {
4565	[EMAC_GDSC] = &emac_gdsc,
4566	[PCIE_0_GDSC] = &pcie_0_gdsc,
4567	[PCIE_1_GDSC] = &pcie_1_gdsc,
4568	[PCIE_2_GDSC] = &pcie_2_gdsc,
4569	[PCIE_3_GDSC] = &pcie_3_gdsc,
4570	[UFS_CARD_GDSC] = &ufs_card_gdsc,
4571	[UFS_CARD_2_GDSC] = &ufs_card_2_gdsc,
4572	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
4573	[USB30_MP_GDSC] = &usb30_mp_gdsc,
4574	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4575	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
4576	};
4577
4578	static const struct regmap_config gcc_sc8180x_regmap_config = {
4579	.reg_bits = 32,
4580	.reg_stride = 4,
4581	.val_bits = 32,
4582	.max_register = 0xc0004,
4583	.fast_io = true,
4584	};
4585
4586	static const struct qcom_cc_desc gcc_sc8180x_desc = {
4587	.config = &gcc_sc8180x_regmap_config,
4588	.clks = gcc_sc8180x_clocks,
4589	.num_clks = ARRAY_SIZE(gcc_sc8180x_clocks),
4590	.resets = gcc_sc8180x_resets,
4591	.num_resets = ARRAY_SIZE(gcc_sc8180x_resets),
4592	.gdscs = gcc_sc8180x_gdscs,
4593	.num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),
4594	};
4595
4596	static const struct of_device_id gcc_sc8180x_match_table[] = {
4597	{ .compatible = "qcom,gcc-sc8180x" },
4598	{ }
4599	};
4600	MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
4601
4602	static int gcc_sc8180x_probe(struct platform_device *pdev)
4603	{
4604	struct regmap *regmap;
4605
4606	regmap = qcom_cc_map(pdev, desc: &gcc_sc8180x_desc);
4607	if (IS_ERR(ptr: regmap))
4608	return PTR_ERR(ptr: regmap);
4609
4610	/* Keep some clocks always-on */
4611	qcom_branch_set_clk_en(regmap, cbcr: 0xb004); /* GCC_VIDEO_AHB_CLK */
4612	qcom_branch_set_clk_en(regmap, cbcr: 0xb008); /* GCC_CAMERA_AHB_CLK */
4613	qcom_branch_set_clk_en(regmap, cbcr: 0xb00c); /* GCC_DISP_AHB_CLK */
4614	qcom_branch_set_clk_en(regmap, cbcr: 0xb040); /* GCC_VIDEO_XO_CLK */
4615	qcom_branch_set_clk_en(regmap, cbcr: 0xb044); /* GCC_CAMERA_XO_CLK */
4616	qcom_branch_set_clk_en(regmap, cbcr: 0xb048); /* GCC_DISP_XO_CLK */
4617	qcom_branch_set_clk_en(regmap, cbcr: 0x48004); /* GCC_CPUSS_GNOC_CLK */
4618	qcom_branch_set_clk_en(regmap, cbcr: 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */
4619	qcom_branch_set_clk_en(regmap, cbcr: 0x4d004); /* GCC_NPU_CFG_AHB_CLK */
4620	qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
4621
4622	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
4623	regmap_update_bits(map: regmap, reg: 0x4d110, mask: 0x3, val: 0x3);
4624	regmap_update_bits(map: regmap, reg: 0x71028, mask: 0x3, val: 0x3);
4625
4626	return qcom_cc_really_probe(pdev, desc: &gcc_sc8180x_desc, regmap);
4627	}
4628
4629	static struct platform_driver gcc_sc8180x_driver = {
4630	.probe = gcc_sc8180x_probe,
4631	.driver = {
4632	.name = "gcc-sc8180x",
4633	.of_match_table = gcc_sc8180x_match_table,
4634	},
4635	};
4636
4637	static int __init gcc_sc8180x_init(void)
4638	{
4639	return platform_driver_register(&gcc_sc8180x_driver);
4640	}
4641	core_initcall(gcc_sc8180x_init);
4642
4643	static void __exit gcc_sc8180x_exit(void)
4644	{
4645	platform_driver_unregister(&gcc_sc8180x_driver);
4646	}
4647	module_exit(gcc_sc8180x_exit);
4648
4649	MODULE_DESCRIPTION("QTI GCC SC8180x driver");
4650	MODULE_LICENSE("GPL v2");
4651