1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4	*/
5
6	#include <linux/kernel.h>
7	#include <linux/err.h>
8	#include <linux/module.h>
9	#include <linux/platform_device.h>
10	#include <linux/of.h>
11	#include <linux/clk-provider.h>
12	#include <linux/regmap.h>
13	#include <linux/reset-controller.h>
14
15	#include <dt-bindings/clock/qcom,gcc-sm6125.h>
16
17	#include "clk-alpha-pll.h"
18	#include "clk-branch.h"
19	#include "clk-rcg.h"
20	#include "clk-regmap.h"
21	#include "common.h"
22	#include "gdsc.h"
23	#include "reset.h"
24
25	enum {
26	P_BI_TCXO,
27	P_GPLL0_OUT_AUX2,
28	P_GPLL0_OUT_EARLY,
29	P_GPLL3_OUT_EARLY,
30	P_GPLL4_OUT_MAIN,
31	P_GPLL5_OUT_MAIN,
32	P_GPLL6_OUT_EARLY,
33	P_GPLL6_OUT_MAIN,
34	P_GPLL7_OUT_MAIN,
35	P_GPLL8_OUT_EARLY,
36	P_GPLL8_OUT_MAIN,
37	P_GPLL9_OUT_MAIN,
38	P_SLEEP_CLK,
39	};
40
41	static struct clk_alpha_pll gpll0_out_early = {
42	.offset = 0x0,
43	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
44	.clkr = {
45	.enable_reg = 0x79000,
46	.enable_mask = BIT(0),
47	.hw.init = &(struct clk_init_data){
48	.name = "gpll0_out_early",
49	.parent_data = &(const struct clk_parent_data){
50	.fw_name = "bi_tcxo",
51	},
52	.num_parents = 1,
53	.ops = &clk_alpha_pll_ops,
54	},
55	},
56	};
57
58	static struct clk_fixed_factor gpll0_out_aux2 = {
59	.mult = 1,
60	.div = 2,
61	.hw.init = &(struct clk_init_data){
62	.name = "gpll0_out_aux2",
63	.parent_hws = (const struct clk_hw*[]){
64	&gpll0_out_early.clkr.hw,
65	},
66	.num_parents = 1,
67	.ops = &clk_fixed_factor_ops,
68	},
69	};
70
71	static struct clk_fixed_factor gpll0_out_main = {
72	.mult = 1,
73	.div = 2,
74	.hw.init = &(struct clk_init_data){
75	.name = "gpll0_out_main",
76	.parent_hws = (const struct clk_hw*[]){
77	&gpll0_out_early.clkr.hw,
78	},
79	.num_parents = 1,
80	.ops = &clk_fixed_factor_ops,
81	},
82	};
83
84	static struct clk_alpha_pll gpll3_out_early = {
85	.offset = 0x3000,
86	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
87	.clkr = {
88	.enable_reg = 0x79000,
89	.enable_mask = BIT(3),
90	.hw.init = &(struct clk_init_data){
91	.name = "gpll3_out_early",
92	.parent_data = &(const struct clk_parent_data){
93	.fw_name = "bi_tcxo",
94	},
95	.num_parents = 1,
96	.ops = &clk_alpha_pll_ops,
97	},
98	},
99	};
100
101	static struct clk_alpha_pll gpll4_out_main = {
102	.offset = 0x4000,
103	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
104	.clkr = {
105	.enable_reg = 0x79000,
106	.enable_mask = BIT(4),
107	.hw.init = &(struct clk_init_data){
108	.name = "gpll4_out_main",
109	.parent_data = &(const struct clk_parent_data){
110	.fw_name = "bi_tcxo",
111	},
112	.num_parents = 1,
113	.ops = &clk_alpha_pll_ops,
114	},
115	},
116	};
117
118	static struct clk_alpha_pll gpll5_out_main = {
119	.offset = 0x5000,
120	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
121	.clkr = {
122	.enable_reg = 0x79000,
123	.enable_mask = BIT(5),
124	.hw.init = &(struct clk_init_data){
125	.name = "gpll5_out_main",
126	.parent_data = &(const struct clk_parent_data){
127	.fw_name = "bi_tcxo",
128	},
129	.num_parents = 1,
130	.ops = &clk_alpha_pll_ops,
131	},
132	},
133	};
134
135	static struct clk_alpha_pll gpll6_out_early = {
136	.offset = 0x6000,
137	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
138	.clkr = {
139	.enable_reg = 0x79000,
140	.enable_mask = BIT(6),
141	.hw.init = &(struct clk_init_data){
142	.name = "gpll6_out_early",
143	.parent_data = &(const struct clk_parent_data){
144	.fw_name = "bi_tcxo",
145	},
146	.num_parents = 1,
147	.ops = &clk_alpha_pll_ops,
148	},
149	},
150	};
151
152	static struct clk_fixed_factor gpll6_out_main = {
153	.mult = 1,
154	.div = 2,
155	.hw.init = &(struct clk_init_data){
156	.name = "gpll6_out_main",
157	.parent_hws = (const struct clk_hw*[]){
158	&gpll6_out_early.clkr.hw,
159	},
160	.num_parents = 1,
161	.ops = &clk_fixed_factor_ops,
162	},
163	};
164
165	static struct clk_alpha_pll gpll7_out_early = {
166	.offset = 0x7000,
167	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
168	.clkr = {
169	.enable_reg = 0x79000,
170	.enable_mask = BIT(7),
171	.hw.init = &(struct clk_init_data){
172	.name = "gpll7_out_early",
173	.parent_data = &(const struct clk_parent_data){
174	.fw_name = "bi_tcxo",
175	},
176	.num_parents = 1,
177	.ops = &clk_alpha_pll_ops,
178	},
179	},
180	};
181
182	static struct clk_fixed_factor gpll7_out_main = {
183	.mult = 1,
184	.div = 2,
185	.hw.init = &(struct clk_init_data){
186	.name = "gpll7_out_main",
187	.parent_hws = (const struct clk_hw*[]){
188	&gpll7_out_early.clkr.hw,
189	},
190	.num_parents = 1,
191	.ops = &clk_fixed_factor_ops,
192	},
193	};
194
195	static struct clk_alpha_pll gpll8_out_early = {
196	.offset = 0x8000,
197	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
198	.clkr = {
199	.enable_reg = 0x79000,
200	.enable_mask = BIT(8),
201	.hw.init = &(struct clk_init_data){
202	.name = "gpll8_out_early",
203	.parent_data = &(const struct clk_parent_data){
204	.fw_name = "bi_tcxo",
205	},
206	.num_parents = 1,
207	.ops = &clk_alpha_pll_ops,
208	},
209	},
210	};
211
212	static struct clk_fixed_factor gpll8_out_main = {
213	.mult = 1,
214	.div = 2,
215	.hw.init = &(struct clk_init_data){
216	.name = "gpll8_out_main",
217	.parent_hws = (const struct clk_hw*[]){
218	&gpll8_out_early.clkr.hw,
219	},
220	.num_parents = 1,
221	.ops = &clk_fixed_factor_ops,
222	},
223	};
224
225	static struct clk_alpha_pll gpll9_out_early = {
226	.offset = 0x9000,
227	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
228	.clkr = {
229	.enable_reg = 0x79000,
230	.enable_mask = BIT(9),
231	.hw.init = &(struct clk_init_data){
232	.name = "gpll9_out_early",
233	.parent_data = &(const struct clk_parent_data){
234	.fw_name = "bi_tcxo",
235	},
236	.num_parents = 1,
237	.ops = &clk_alpha_pll_ops,
238	},
239	},
240	};
241
242	static struct clk_fixed_factor gpll9_out_main = {
243	.mult = 1,
244	.div = 2,
245	.hw.init = &(struct clk_init_data){
246	.name = "gpll9_out_main",
247	.parent_hws = (const struct clk_hw*[]){
248	&gpll9_out_early.clkr.hw,
249	},
250	.num_parents = 1,
251	.ops = &clk_fixed_factor_ops,
252	},
253	};
254
255	static const struct parent_map gcc_parent_map_0[] = {
256	{ P_BI_TCXO, 0 },
257	{ P_GPLL0_OUT_EARLY, 1 },
258	{ P_GPLL0_OUT_AUX2, 2 },
259	};
260
261	static const struct clk_parent_data gcc_parent_data_0[] = {
262	{ .fw_name = "bi_tcxo" },
263	{ .hw = &gpll0_out_early.clkr.hw },
264	{ .hw = &gpll0_out_aux2.hw },
265	};
266
267	static const struct parent_map gcc_parent_map_1[] = {
268	{ P_BI_TCXO, 0 },
269	{ P_GPLL0_OUT_EARLY, 1 },
270	{ P_GPLL0_OUT_AUX2, 2 },
271	{ P_GPLL6_OUT_MAIN, 4 },
272	};
273
274	static const struct clk_parent_data gcc_parent_data_1[] = {
275	{ .fw_name = "bi_tcxo" },
276	{ .hw = &gpll0_out_early.clkr.hw },
277	{ .hw = &gpll0_out_aux2.hw },
278	{ .hw = &gpll6_out_main.hw },
279	};
280
281	static const struct parent_map gcc_parent_map_2[] = {
282	{ P_BI_TCXO, 0 },
283	{ P_GPLL0_OUT_EARLY, 1 },
284	{ P_GPLL0_OUT_AUX2, 2 },
285	{ P_SLEEP_CLK, 5 },
286	};
287
288	static const struct clk_parent_data gcc_parent_data_2[] = {
289	{ .fw_name = "bi_tcxo" },
290	{ .hw = &gpll0_out_early.clkr.hw },
291	{ .hw = &gpll0_out_aux2.hw },
292	{ .fw_name = "sleep_clk" },
293	};
294
295	static const struct parent_map gcc_parent_map_3[] = {
296	{ P_BI_TCXO, 0 },
297	{ P_GPLL0_OUT_EARLY, 1 },
298	{ P_GPLL5_OUT_MAIN, 3 },
299	{ P_GPLL4_OUT_MAIN, 5 },
300	};
301
302	static const struct clk_parent_data gcc_parent_data_3[] = {
303	{ .fw_name = "bi_tcxo" },
304	{ .hw = &gpll0_out_early.clkr.hw },
305	{ .hw = &gpll5_out_main.clkr.hw },
306	{ .hw = &gpll4_out_main.clkr.hw },
307	};
308
309	static const struct parent_map gcc_parent_map_4[] = {
310	{ P_BI_TCXO, 0 },
311	{ P_GPLL0_OUT_EARLY, 1 },
312	{ P_GPLL9_OUT_MAIN, 2 },
313	};
314
315	static const struct clk_parent_data gcc_parent_data_4[] = {
316	{ .fw_name = "bi_tcxo" },
317	{ .hw = &gpll0_out_early.clkr.hw },
318	{ .hw = &gpll9_out_main.hw },
319	};
320
321	static const struct parent_map gcc_parent_map_5[] = {
322	{ P_BI_TCXO, 0 },
323	{ P_GPLL0_OUT_EARLY, 1 },
324	};
325
326	static const struct clk_parent_data gcc_parent_data_5[] = {
327	{ .fw_name = "bi_tcxo" },
328	{ .hw = &gpll0_out_early.clkr.hw },
329	};
330
331	static const struct parent_map gcc_parent_map_6[] = {
332	{ P_BI_TCXO, 0 },
333	{ P_GPLL0_OUT_EARLY, 1 },
334	{ P_GPLL4_OUT_MAIN, 5 },
335	};
336
337	static const struct clk_parent_data gcc_parent_data_6[] = {
338	{ .fw_name = "bi_tcxo" },
339	{ .hw = &gpll0_out_early.clkr.hw },
340	{ .hw = &gpll4_out_main.clkr.hw },
341	};
342
343	static const struct parent_map gcc_parent_map_7[] = {
344	{ P_BI_TCXO, 0 },
345	{ P_GPLL0_OUT_EARLY, 1 },
346	{ P_SLEEP_CLK, 5 },
347	};
348
349	static const struct clk_parent_data gcc_parent_data_7[] = {
350	{ .fw_name = "bi_tcxo" },
351	{ .hw = &gpll0_out_early.clkr.hw },
352	{ .fw_name = "sleep_clk" },
353	};
354
355	static const struct parent_map gcc_parent_map_8[] = {
356	{ P_BI_TCXO, 0 },
357	{ P_GPLL0_OUT_EARLY, 1 },
358	{ P_GPLL9_OUT_MAIN, 2 },
359	{ P_GPLL6_OUT_EARLY, 3 },
360	{ P_GPLL8_OUT_MAIN, 4 },
361	{ P_GPLL4_OUT_MAIN, 5 },
362	{ P_GPLL3_OUT_EARLY, 6 },
363	};
364
365	static const struct clk_parent_data gcc_parent_data_8[] = {
366	{ .fw_name = "bi_tcxo" },
367	{ .hw = &gpll0_out_early.clkr.hw },
368	{ .hw = &gpll9_out_main.hw },
369	{ .hw = &gpll6_out_early.clkr.hw },
370	{ .hw = &gpll8_out_main.hw },
371	{ .hw = &gpll4_out_main.clkr.hw },
372	{ .hw = &gpll3_out_early.clkr.hw },
373	};
374
375	static const struct parent_map gcc_parent_map_9[] = {
376	{ P_BI_TCXO, 0 },
377	{ P_GPLL0_OUT_EARLY, 1 },
378	{ P_GPLL8_OUT_MAIN, 4 },
379	};
380
381	static const struct clk_parent_data gcc_parent_data_9[] = {
382	{ .fw_name = "bi_tcxo" },
383	{ .hw = &gpll0_out_early.clkr.hw },
384	{ .hw = &gpll8_out_main.hw },
385	};
386
387	static const struct parent_map gcc_parent_map_10[] = {
388	{ P_BI_TCXO, 0 },
389	{ P_GPLL0_OUT_EARLY, 1 },
390	{ P_GPLL9_OUT_MAIN, 2 },
391	{ P_GPLL6_OUT_EARLY, 3 },
392	{ P_GPLL8_OUT_MAIN, 4 },
393	{ P_GPLL3_OUT_EARLY, 6 },
394	};
395
396	static const struct clk_parent_data gcc_parent_data_10[] = {
397	{ .fw_name = "bi_tcxo" },
398	{ .hw = &gpll0_out_early.clkr.hw },
399	{ .hw = &gpll9_out_main.hw },
400	{ .hw = &gpll6_out_early.clkr.hw },
401	{ .hw = &gpll8_out_main.hw },
402	{ .hw = &gpll3_out_early.clkr.hw },
403	};
404
405	static const struct parent_map gcc_parent_map_11[] = {
406	{ P_BI_TCXO, 0 },
407	{ P_GPLL0_OUT_EARLY, 1 },
408	{ P_GPLL8_OUT_EARLY, 4 },
409	{ P_GPLL4_OUT_MAIN, 5 },
410	};
411
412	static const struct clk_parent_data gcc_parent_data_11[] = {
413	{ .fw_name = "bi_tcxo" },
414	{ .hw = &gpll0_out_early.clkr.hw },
415	{ .hw = &gpll8_out_early.clkr.hw },
416	{ .hw = &gpll4_out_main.clkr.hw },
417	};
418
419	static const struct parent_map gcc_parent_map_12[] = {
420	{ P_BI_TCXO, 0 },
421	{ P_GPLL0_OUT_EARLY, 1 },
422	{ P_GPLL6_OUT_EARLY, 3 },
423	{ P_GPLL8_OUT_EARLY, 4 },
424	};
425
426	static const struct clk_parent_data gcc_parent_data_12[] = {
427	{ .fw_name = "bi_tcxo" },
428	{ .hw = &gpll0_out_early.clkr.hw },
429	{ .hw = &gpll6_out_early.clkr.hw },
430	{ .hw = &gpll8_out_early.clkr.hw },
431	};
432
433	static const struct parent_map gcc_parent_map_13[] = {
434	{ P_BI_TCXO, 0 },
435	{ P_GPLL0_OUT_EARLY, 1 },
436	{ P_GPLL0_OUT_AUX2, 2 },
437	{ P_GPLL7_OUT_MAIN, 3 },
438	{ P_GPLL4_OUT_MAIN, 5 },
439	};
440
441	static const struct clk_parent_data gcc_parent_data_13[] = {
442	{ .fw_name = "bi_tcxo" },
443	{ .hw = &gpll0_out_early.clkr.hw },
444	{ .hw = &gpll0_out_aux2.hw },
445	{ .hw = &gpll7_out_main.hw },
446	{ .hw = &gpll4_out_main.clkr.hw },
447	};
448
449	static const struct parent_map gcc_parent_map_14[] = {
450	{ P_BI_TCXO, 0 },
451	{ P_SLEEP_CLK, 5 },
452	};
453
454	static const struct clk_parent_data gcc_parent_data_14[] = {
455	{ .fw_name = "bi_tcxo" },
456	{ .fw_name = "sleep_clk" },
457	};
458
459	static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = {
460	F(19200000, P_BI_TCXO, 1, 0, 0),
461	F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0),
462	F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0),
463	{ }
464	};
465
466	static struct clk_rcg2 gcc_camss_ahb_clk_src = {
467	.cmd_rcgr = 0x56088,
468	.mnd_width = 0,
469	.hid_width = 5,
470	.parent_map = gcc_parent_map_9,
471	.freq_tbl = ftbl_gcc_camss_ahb_clk_src,
472	.clkr.hw.init = &(struct clk_init_data){
473	.name = "gcc_camss_ahb_clk_src",
474	.parent_data = gcc_parent_data_9,
475	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
476	.ops = &clk_rcg2_ops,
477	},
478	};
479
480	static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
481	F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0),
482	F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
483	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
484	{ }
485	};
486
487	static struct clk_rcg2 gcc_camss_cci_clk_src = {
488	.cmd_rcgr = 0x52004,
489	.mnd_width = 8,
490	.hid_width = 5,
491	.parent_map = gcc_parent_map_5,
492	.freq_tbl = ftbl_gcc_camss_cci_clk_src,
493	.clkr.hw.init = &(struct clk_init_data){
494	.name = "gcc_camss_cci_clk_src",
495	.parent_data = gcc_parent_data_5,
496	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
497	.ops = &clk_rcg2_ops,
498	},
499	};
500
501	static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = {
502	F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
503	F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
504	F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0),
505	F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
506	F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
507	{ }
508	};
509
510	static struct clk_rcg2 gcc_camss_cpp_clk_src = {
511	.cmd_rcgr = 0x560c8,
512	.mnd_width = 0,
513	.hid_width = 5,
514	.parent_map = gcc_parent_map_10,
515	.freq_tbl = ftbl_gcc_camss_cpp_clk_src,
516	.clkr.hw.init = &(struct clk_init_data){
517	.name = "gcc_camss_cpp_clk_src",
518	.parent_data = gcc_parent_data_10,
519	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
520	.ops = &clk_rcg2_ops,
521	},
522	};
523
524	static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = {
525	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
526	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
527	F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0),
528	F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
529	F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0),
530	{ }
531	};
532
533	static struct clk_rcg2 gcc_camss_csi0_clk_src = {
534	.cmd_rcgr = 0x55030,
535	.mnd_width = 0,
536	.hid_width = 5,
537	.parent_map = gcc_parent_map_3,
538	.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
539	.clkr.hw.init = &(struct clk_init_data){
540	.name = "gcc_camss_csi0_clk_src",
541	.parent_data = gcc_parent_data_3,
542	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
543	.ops = &clk_rcg2_ops,
544	},
545	};
546
547	static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
548	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
549	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
550	F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
551	{ }
552	};
553
554	static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
555	.cmd_rcgr = 0x53004,
556	.mnd_width = 0,
557	.hid_width = 5,
558	.parent_map = gcc_parent_map_6,
559	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
560	.clkr.hw.init = &(struct clk_init_data){
561	.name = "gcc_camss_csi0phytimer_clk_src",
562	.parent_data = gcc_parent_data_6,
563	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
564	.ops = &clk_rcg2_ops,
565	},
566	};
567
568	static struct clk_rcg2 gcc_camss_csi1_clk_src = {
569	.cmd_rcgr = 0x5506c,
570	.mnd_width = 0,
571	.hid_width = 5,
572	.parent_map = gcc_parent_map_3,
573	.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
574	.clkr.hw.init = &(struct clk_init_data){
575	.name = "gcc_camss_csi1_clk_src",
576	.parent_data = gcc_parent_data_3,
577	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
578	.ops = &clk_rcg2_ops,
579	},
580	};
581
582	static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
583	.cmd_rcgr = 0x53024,
584	.mnd_width = 0,
585	.hid_width = 5,
586	.parent_map = gcc_parent_map_6,
587	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
588	.clkr.hw.init = &(struct clk_init_data){
589	.name = "gcc_camss_csi1phytimer_clk_src",
590	.parent_data = gcc_parent_data_6,
591	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
592	.ops = &clk_rcg2_ops,
593	},
594	};
595
596	static struct clk_rcg2 gcc_camss_csi2_clk_src = {
597	.cmd_rcgr = 0x550a4,
598	.mnd_width = 0,
599	.hid_width = 5,
600	.parent_map = gcc_parent_map_3,
601	.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
602	.clkr.hw.init = &(struct clk_init_data){
603	.name = "gcc_camss_csi2_clk_src",
604	.parent_data = gcc_parent_data_3,
605	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
606	.ops = &clk_rcg2_ops,
607	},
608	};
609
610	static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
611	.cmd_rcgr = 0x53044,
612	.mnd_width = 0,
613	.hid_width = 5,
614	.parent_map = gcc_parent_map_6,
615	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
616	.clkr.hw.init = &(struct clk_init_data){
617	.name = "gcc_camss_csi2phytimer_clk_src",
618	.parent_data = gcc_parent_data_6,
619	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
620	.ops = &clk_rcg2_ops,
621	},
622	};
623
624	static struct clk_rcg2 gcc_camss_csi3_clk_src = {
625	.cmd_rcgr = 0x550e0,
626	.mnd_width = 0,
627	.hid_width = 5,
628	.parent_map = gcc_parent_map_3,
629	.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
630	.clkr.hw.init = &(struct clk_init_data){
631	.name = "gcc_camss_csi3_clk_src",
632	.parent_data = gcc_parent_data_3,
633	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
634	.ops = &clk_rcg2_ops,
635	},
636	};
637
638	static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = {
639	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
640	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
641	F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
642	F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
643	{ }
644	};
645
646	static struct clk_rcg2 gcc_camss_csiphy_clk_src = {
647	.cmd_rcgr = 0x55000,
648	.mnd_width = 0,
649	.hid_width = 5,
650	.parent_map = gcc_parent_map_11,
651	.freq_tbl = ftbl_gcc_camss_csiphy_clk_src,
652	.clkr.hw.init = &(struct clk_init_data){
653	.name = "gcc_camss_csiphy_clk_src",
654	.parent_data = gcc_parent_data_11,
655	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
656	.ops = &clk_rcg2_ops,
657	},
658	};
659
660	static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = {
661	F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
662	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
663	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
664	{ }
665	};
666
667	static struct clk_rcg2 gcc_camss_gp0_clk_src = {
668	.cmd_rcgr = 0x50000,
669	.mnd_width = 8,
670	.hid_width = 5,
671	.parent_map = gcc_parent_map_7,
672	.freq_tbl = ftbl_gcc_camss_gp0_clk_src,
673	.clkr.hw.init = &(struct clk_init_data){
674	.name = "gcc_camss_gp0_clk_src",
675	.parent_data = gcc_parent_data_7,
676	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
677	.ops = &clk_rcg2_ops,
678	},
679	};
680
681	static struct clk_rcg2 gcc_camss_gp1_clk_src = {
682	.cmd_rcgr = 0x5001c,
683	.mnd_width = 8,
684	.hid_width = 5,
685	.parent_map = gcc_parent_map_7,
686	.freq_tbl = ftbl_gcc_camss_gp0_clk_src,
687	.clkr.hw.init = &(struct clk_init_data){
688	.name = "gcc_camss_gp1_clk_src",
689	.parent_data = gcc_parent_data_7,
690	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
691	.ops = &clk_rcg2_ops,
692	},
693	};
694
695	static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = {
696	F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0),
697	F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
698	F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0),
699	F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
700	F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0),
701	{ }
702	};
703
704	static struct clk_rcg2 gcc_camss_jpeg_clk_src = {
705	.cmd_rcgr = 0x52028,
706	.mnd_width = 0,
707	.hid_width = 5,
708	.parent_map = gcc_parent_map_12,
709	.freq_tbl = ftbl_gcc_camss_jpeg_clk_src,
710	.clkr.hw.init = &(struct clk_init_data){
711	.name = "gcc_camss_jpeg_clk_src",
712	.parent_data = gcc_parent_data_12,
713	.num_parents = ARRAY_SIZE(gcc_parent_data_12),
714	.ops = &clk_rcg2_ops,
715	},
716	};
717
718	static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
719	F(19200000, P_BI_TCXO, 1, 0, 0),
720	F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
721	F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
722	{ }
723	};
724
725	static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
726	.cmd_rcgr = 0x51000,
727	.mnd_width = 8,
728	.hid_width = 5,
729	.parent_map = gcc_parent_map_4,
730	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
731	.clkr.hw.init = &(struct clk_init_data){
732	.name = "gcc_camss_mclk0_clk_src",
733	.parent_data = gcc_parent_data_4,
734	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
735	.ops = &clk_rcg2_ops,
736	},
737	};
738
739	static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
740	.cmd_rcgr = 0x5101c,
741	.mnd_width = 8,
742	.hid_width = 5,
743	.parent_map = gcc_parent_map_4,
744	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
745	.clkr.hw.init = &(struct clk_init_data){
746	.name = "gcc_camss_mclk1_clk_src",
747	.parent_data = gcc_parent_data_4,
748	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
749	.ops = &clk_rcg2_ops,
750	},
751	};
752
753	static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
754	.cmd_rcgr = 0x51038,
755	.mnd_width = 8,
756	.hid_width = 5,
757	.parent_map = gcc_parent_map_4,
758	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
759	.clkr.hw.init = &(struct clk_init_data){
760	.name = "gcc_camss_mclk2_clk_src",
761	.parent_data = gcc_parent_data_4,
762	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
763	.ops = &clk_rcg2_ops,
764	},
765	};
766
767	static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
768	.cmd_rcgr = 0x51054,
769	.mnd_width = 8,
770	.hid_width = 5,
771	.parent_map = gcc_parent_map_4,
772	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
773	.clkr.hw.init = &(struct clk_init_data){
774	.name = "gcc_camss_mclk3_clk_src",
775	.parent_data = gcc_parent_data_4,
776	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
777	.ops = &clk_rcg2_ops,
778	},
779	};
780
781	static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = {
782	F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
783	F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0),
784	F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
785	F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
786	F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0),
787	F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
788	{ }
789	};
790
791	static struct clk_rcg2 gcc_camss_vfe0_clk_src = {
792	.cmd_rcgr = 0x54010,
793	.mnd_width = 0,
794	.hid_width = 5,
795	.parent_map = gcc_parent_map_8,
796	.freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
797	.clkr.hw.init = &(struct clk_init_data){
798	.name = "gcc_camss_vfe0_clk_src",
799	.parent_data = gcc_parent_data_8,
800	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
801	.ops = &clk_rcg2_ops,
802	},
803	};
804
805	static struct clk_rcg2 gcc_camss_vfe1_clk_src = {
806	.cmd_rcgr = 0x54048,
807	.mnd_width = 0,
808	.hid_width = 5,
809	.parent_map = gcc_parent_map_8,
810	.freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
811	.clkr.hw.init = &(struct clk_init_data){
812	.name = "gcc_camss_vfe1_clk_src",
813	.parent_data = gcc_parent_data_8,
814	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
815	.ops = &clk_rcg2_ops,
816	},
817	};
818
819	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
820	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
821	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
822	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
823	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
824	{ }
825	};
826
827	static struct clk_rcg2 gcc_gp1_clk_src = {
828	.cmd_rcgr = 0x4d004,
829	.mnd_width = 8,
830	.hid_width = 5,
831	.parent_map = gcc_parent_map_2,
832	.freq_tbl = ftbl_gcc_gp1_clk_src,
833	.clkr.hw.init = &(struct clk_init_data){
834	.name = "gcc_gp1_clk_src",
835	.parent_data = gcc_parent_data_2,
836	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
837	.ops = &clk_rcg2_ops,
838	},
839	};
840
841	static struct clk_rcg2 gcc_gp2_clk_src = {
842	.cmd_rcgr = 0x4e004,
843	.mnd_width = 8,
844	.hid_width = 5,
845	.parent_map = gcc_parent_map_2,
846	.freq_tbl = ftbl_gcc_gp1_clk_src,
847	.clkr.hw.init = &(struct clk_init_data){
848	.name = "gcc_gp2_clk_src",
849	.parent_data = gcc_parent_data_2,
850	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
851	.ops = &clk_rcg2_ops,
852	},
853	};
854
855	static struct clk_rcg2 gcc_gp3_clk_src = {
856	.cmd_rcgr = 0x4f004,
857	.mnd_width = 8,
858	.hid_width = 5,
859	.parent_map = gcc_parent_map_2,
860	.freq_tbl = ftbl_gcc_gp1_clk_src,
861	.clkr.hw.init = &(struct clk_init_data){
862	.name = "gcc_gp3_clk_src",
863	.parent_data = gcc_parent_data_2,
864	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
865	.ops = &clk_rcg2_ops,
866	},
867	};
868
869	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
870	F(19200000, P_BI_TCXO, 1, 0, 0),
871	F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
872	{ }
873	};
874
875	static struct clk_rcg2 gcc_pdm2_clk_src = {
876	.cmd_rcgr = 0x20010,
877	.mnd_width = 0,
878	.hid_width = 5,
879	.parent_map = gcc_parent_map_0,
880	.freq_tbl = ftbl_gcc_pdm2_clk_src,
881	.clkr.hw.init = &(struct clk_init_data){
882	.name = "gcc_pdm2_clk_src",
883	.parent_data = gcc_parent_data_0,
884	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
885	.ops = &clk_rcg2_ops,
886	},
887	};
888
889	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
890	F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
891	F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
892	F(19200000, P_BI_TCXO, 1, 0, 0),
893	F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
894	F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
895	F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
896	F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
897	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
898	F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
899	F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
900	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
901	F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
902	F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
903	F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
904	F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
905	F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
906	{ }
907	};
908
909	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
910	.name = "gcc_qupv3_wrap0_s0_clk_src",
911	.parent_data = gcc_parent_data_1,
912	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
913	.ops = &clk_rcg2_ops,
914	};
915
916	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
917	.cmd_rcgr = 0x1f148,
918	.mnd_width = 16,
919	.hid_width = 5,
920	.parent_map = gcc_parent_map_1,
921	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
922	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
923	};
924
925	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
926	.name = "gcc_qupv3_wrap0_s1_clk_src",
927	.parent_data = gcc_parent_data_1,
928	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
929	.ops = &clk_rcg2_ops,
930	};
931
932	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
933	.cmd_rcgr = 0x1f278,
934	.mnd_width = 16,
935	.hid_width = 5,
936	.parent_map = gcc_parent_map_1,
937	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
938	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
939	};
940
941	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
942	.name = "gcc_qupv3_wrap0_s2_clk_src",
943	.parent_data = gcc_parent_data_1,
944	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
945	.ops = &clk_rcg2_ops,
946	};
947
948	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
949	.cmd_rcgr = 0x1f3a8,
950	.mnd_width = 16,
951	.hid_width = 5,
952	.parent_map = gcc_parent_map_1,
953	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
954	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
955	};
956
957	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
958	.name = "gcc_qupv3_wrap0_s3_clk_src",
959	.parent_data = gcc_parent_data_1,
960	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
961	.ops = &clk_rcg2_ops,
962	};
963
964	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
965	.cmd_rcgr = 0x1f4d8,
966	.mnd_width = 16,
967	.hid_width = 5,
968	.parent_map = gcc_parent_map_1,
969	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
970	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
971	};
972
973	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
974	.name = "gcc_qupv3_wrap0_s4_clk_src",
975	.parent_data = gcc_parent_data_1,
976	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
977	.ops = &clk_rcg2_ops,
978	};
979
980	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
981	.cmd_rcgr = 0x1f608,
982	.mnd_width = 16,
983	.hid_width = 5,
984	.parent_map = gcc_parent_map_1,
985	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
986	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
987	};
988
989	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
990	.name = "gcc_qupv3_wrap0_s5_clk_src",
991	.parent_data = gcc_parent_data_1,
992	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
993	.ops = &clk_rcg2_ops,
994	};
995
996	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
997	.cmd_rcgr = 0x1f738,
998	.mnd_width = 16,
999	.hid_width = 5,
1000	.parent_map = gcc_parent_map_1,
1001	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1002	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1003	};
1004
1005	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1006	.name = "gcc_qupv3_wrap1_s0_clk_src",
1007	.parent_data = gcc_parent_data_1,
1008	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1009	.ops = &clk_rcg2_ops,
1010	};
1011
1012	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1013	.cmd_rcgr = 0x39148,
1014	.mnd_width = 16,
1015	.hid_width = 5,
1016	.parent_map = gcc_parent_map_1,
1017	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1018	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1019	};
1020
1021	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1022	.name = "gcc_qupv3_wrap1_s1_clk_src",
1023	.parent_data = gcc_parent_data_1,
1024	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1025	.ops = &clk_rcg2_ops,
1026	};
1027
1028	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1029	.cmd_rcgr = 0x39278,
1030	.mnd_width = 16,
1031	.hid_width = 5,
1032	.parent_map = gcc_parent_map_1,
1033	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1034	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1035	};
1036
1037	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1038	.name = "gcc_qupv3_wrap1_s2_clk_src",
1039	.parent_data = gcc_parent_data_1,
1040	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1041	.ops = &clk_rcg2_ops,
1042	};
1043
1044	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1045	.cmd_rcgr = 0x393a8,
1046	.mnd_width = 16,
1047	.hid_width = 5,
1048	.parent_map = gcc_parent_map_1,
1049	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1050	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1051	};
1052
1053	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1054	.name = "gcc_qupv3_wrap1_s3_clk_src",
1055	.parent_data = gcc_parent_data_1,
1056	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1057	.ops = &clk_rcg2_ops,
1058	};
1059
1060	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1061	.cmd_rcgr = 0x394d8,
1062	.mnd_width = 16,
1063	.hid_width = 5,
1064	.parent_map = gcc_parent_map_1,
1065	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1066	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1067	};
1068
1069	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1070	.name = "gcc_qupv3_wrap1_s4_clk_src",
1071	.parent_data = gcc_parent_data_1,
1072	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1073	.ops = &clk_rcg2_ops,
1074	};
1075
1076	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1077	.cmd_rcgr = 0x39608,
1078	.mnd_width = 16,
1079	.hid_width = 5,
1080	.parent_map = gcc_parent_map_1,
1081	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1082	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1083	};
1084
1085	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1086	.name = "gcc_qupv3_wrap1_s5_clk_src",
1087	.parent_data = gcc_parent_data_1,
1088	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1089	.ops = &clk_rcg2_ops,
1090	};
1091
1092	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1093	.cmd_rcgr = 0x39738,
1094	.mnd_width = 16,
1095	.hid_width = 5,
1096	.parent_map = gcc_parent_map_1,
1097	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1098	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1099	};
1100
1101	static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1102	F(144000, P_BI_TCXO, 16, 3, 25),
1103	F(400000, P_BI_TCXO, 12, 1, 4),
1104	F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1105	F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1106	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1107	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1108	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1109	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1110	{ }
1111	};
1112
1113	static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1114	.cmd_rcgr = 0x38028,
1115	.mnd_width = 8,
1116	.hid_width = 5,
1117	.parent_map = gcc_parent_map_1,
1118	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1119	.clkr.hw.init = &(struct clk_init_data){
1120	.name = "gcc_sdcc1_apps_clk_src",
1121	.parent_data = gcc_parent_data_1,
1122	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1123	.ops = &clk_rcg2_floor_ops,
1124	},
1125	};
1126
1127	static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1128	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1129	F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1130	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1131	F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1132	{ }
1133	};
1134
1135	static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1136	.cmd_rcgr = 0x38010,
1137	.mnd_width = 0,
1138	.hid_width = 5,
1139	.parent_map = gcc_parent_map_0,
1140	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1141	.clkr.hw.init = &(struct clk_init_data){
1142	.name = "gcc_sdcc1_ice_core_clk_src",
1143	.parent_data = gcc_parent_data_0,
1144	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1145	.ops = &clk_rcg2_ops,
1146	},
1147	};
1148
1149	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1150	F(400000, P_BI_TCXO, 12, 1, 4),
1151	F(19200000, P_BI_TCXO, 1, 0, 0),
1152	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1153	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1154	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1155	{ }
1156	};
1157
1158	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1159	.cmd_rcgr = 0x1e00c,
1160	.mnd_width = 8,
1161	.hid_width = 5,
1162	.parent_map = gcc_parent_map_13,
1163	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1164	.clkr.hw.init = &(struct clk_init_data){
1165	.name = "gcc_sdcc2_apps_clk_src",
1166	.parent_data = gcc_parent_data_13,
1167	.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1168	.ops = &clk_rcg2_floor_ops,
1169	},
1170	};
1171
1172	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1173	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1174	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1175	F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
1176	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1177	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1178	{ }
1179	};
1180
1181	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1182	.cmd_rcgr = 0x45020,
1183	.mnd_width = 8,
1184	.hid_width = 5,
1185	.parent_map = gcc_parent_map_0,
1186	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1187	.clkr.hw.init = &(struct clk_init_data){
1188	.name = "gcc_ufs_phy_axi_clk_src",
1189	.parent_data = gcc_parent_data_0,
1190	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1191	.ops = &clk_rcg2_ops,
1192	},
1193	};
1194
1195	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1196	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1197	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1198	F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1199	F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1200	{ }
1201	};
1202
1203	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1204	.cmd_rcgr = 0x45048,
1205	.mnd_width = 0,
1206	.hid_width = 5,
1207	.parent_map = gcc_parent_map_0,
1208	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1209	.clkr.hw.init = &(struct clk_init_data){
1210	.name = "gcc_ufs_phy_ice_core_clk_src",
1211	.parent_data = gcc_parent_data_0,
1212	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1213	.ops = &clk_rcg2_ops,
1214	},
1215	};
1216
1217	static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1218	F(9600000, P_BI_TCXO, 2, 0, 0),
1219	F(19200000, P_BI_TCXO, 1, 0, 0),
1220	{ }
1221	};
1222
1223	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1224	.cmd_rcgr = 0x4507c,
1225	.mnd_width = 0,
1226	.hid_width = 5,
1227	.parent_map = gcc_parent_map_0,
1228	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1229	.clkr.hw.init = &(struct clk_init_data){
1230	.name = "gcc_ufs_phy_phy_aux_clk_src",
1231	.parent_data = gcc_parent_data_0,
1232	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1233	.ops = &clk_rcg2_ops,
1234	},
1235	};
1236
1237	static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1238	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1239	F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0),
1240	F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1241	{ }
1242	};
1243
1244	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1245	.cmd_rcgr = 0x45060,
1246	.mnd_width = 0,
1247	.hid_width = 5,
1248	.parent_map = gcc_parent_map_0,
1249	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1250	.clkr.hw.init = &(struct clk_init_data){
1251	.name = "gcc_ufs_phy_unipro_core_clk_src",
1252	.parent_data = gcc_parent_data_0,
1253	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1254	.ops = &clk_rcg2_ops,
1255	},
1256	};
1257
1258	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1259	F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1260	F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1261	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1262	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1263	{ }
1264	};
1265
1266	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1267	.cmd_rcgr = 0x1a01c,
1268	.mnd_width = 8,
1269	.hid_width = 5,
1270	.parent_map = gcc_parent_map_0,
1271	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1272	.clkr.hw.init = &(struct clk_init_data){
1273	.name = "gcc_usb30_prim_master_clk_src",
1274	.parent_data = gcc_parent_data_0,
1275	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1276	.ops = &clk_rcg2_ops,
1277	},
1278	};
1279
1280	static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1281	F(19200000, P_BI_TCXO, 1, 0, 0),
1282	F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0),
1283	F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1284	F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
1285	{ }
1286	};
1287
1288	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1289	.cmd_rcgr = 0x1a034,
1290	.mnd_width = 0,
1291	.hid_width = 5,
1292	.parent_map = gcc_parent_map_0,
1293	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1294	.clkr.hw.init = &(struct clk_init_data){
1295	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1296	.parent_data = gcc_parent_data_0,
1297	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1298	.ops = &clk_rcg2_ops,
1299	},
1300	};
1301
1302	static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
1303	F(19200000, P_BI_TCXO, 1, 0, 0),
1304	{ }
1305	};
1306
1307	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1308	.cmd_rcgr = 0x1a060,
1309	.mnd_width = 0,
1310	.hid_width = 5,
1311	.parent_map = gcc_parent_map_14,
1312	.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
1313	.clkr.hw.init = &(struct clk_init_data){
1314	.name = "gcc_usb3_prim_phy_aux_clk_src",
1315	.parent_data = gcc_parent_data_14,
1316	.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1317	.ops = &clk_rcg2_ops,
1318	},
1319	};
1320
1321	static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
1322	.cmd_rcgr = 0x42030,
1323	.mnd_width = 0,
1324	.hid_width = 5,
1325	.parent_map = gcc_parent_map_5,
1326	.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
1327	.clkr.hw.init = &(struct clk_init_data){
1328	.name = "gcc_vs_ctrl_clk_src",
1329	.parent_data = gcc_parent_data_5,
1330	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1331	.ops = &clk_rcg2_ops,
1332	},
1333	};
1334
1335	static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1336	F(19200000, P_BI_TCXO, 1, 0, 0),
1337	F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0),
1338	F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0),
1339	{ }
1340	};
1341
1342	static struct clk_rcg2 gcc_vsensor_clk_src = {
1343	.cmd_rcgr = 0x42018,
1344	.mnd_width = 0,
1345	.hid_width = 5,
1346	.parent_map = gcc_parent_map_5,
1347	.freq_tbl = ftbl_gcc_vsensor_clk_src,
1348	.clkr.hw.init = &(struct clk_init_data){
1349	.name = "gcc_vsensor_clk_src",
1350	.parent_data = gcc_parent_data_5,
1351	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1352	.ops = &clk_rcg2_ops,
1353	},
1354	};
1355
1356	static struct clk_branch gcc_ahb2phy_csi_clk = {
1357	.halt_reg = 0x1d004,
1358	.halt_check = BRANCH_HALT,
1359	.hwcg_reg = 0x1d004,
1360	.hwcg_bit = 1,
1361	.clkr = {
1362	.enable_reg = 0x1d004,
1363	.enable_mask = BIT(0),
1364	.hw.init = &(struct clk_init_data){
1365	.name = "gcc_ahb2phy_csi_clk",
1366	.ops = &clk_branch2_ops,
1367	},
1368	},
1369	};
1370
1371	static struct clk_branch gcc_ahb2phy_usb_clk = {
1372	.halt_reg = 0x1d008,
1373	.halt_check = BRANCH_HALT,
1374	.hwcg_reg = 0x1d008,
1375	.hwcg_bit = 1,
1376	.clkr = {
1377	.enable_reg = 0x1d008,
1378	.enable_mask = BIT(0),
1379	.hw.init = &(struct clk_init_data){
1380	.name = "gcc_ahb2phy_usb_clk",
1381	.ops = &clk_branch2_ops,
1382	},
1383	},
1384	};
1385
1386	static struct clk_branch gcc_apc_vs_clk = {
1387	.halt_reg = 0x4204c,
1388	.halt_check = BRANCH_HALT,
1389	.clkr = {
1390	.enable_reg = 0x4204c,
1391	.enable_mask = BIT(0),
1392	.hw.init = &(struct clk_init_data){
1393	.name = "gcc_apc_vs_clk",
1394	.parent_hws = (const struct clk_hw*[]){
1395	&gcc_vsensor_clk_src.clkr.hw,
1396	},
1397	.num_parents = 1,
1398	.flags = CLK_SET_RATE_PARENT,
1399	.ops = &clk_branch2_ops,
1400	},
1401	},
1402	};
1403
1404	static struct clk_branch gcc_bimc_gpu_axi_clk = {
1405	.halt_reg = 0x71154,
1406	.halt_check = BRANCH_HALT_DELAY,
1407	.clkr = {
1408	.enable_reg = 0x71154,
1409	.enable_mask = BIT(0),
1410	.hw.init = &(struct clk_init_data){
1411	.name = "gcc_bimc_gpu_axi_clk",
1412	.ops = &clk_branch2_ops,
1413	},
1414	},
1415	};
1416
1417	static struct clk_branch gcc_boot_rom_ahb_clk = {
1418	.halt_reg = 0x23004,
1419	.halt_check = BRANCH_HALT_VOTED,
1420	.hwcg_reg = 0x23004,
1421	.hwcg_bit = 1,
1422	.clkr = {
1423	.enable_reg = 0x79004,
1424	.enable_mask = BIT(10),
1425	.hw.init = &(struct clk_init_data){
1426	.name = "gcc_boot_rom_ahb_clk",
1427	.ops = &clk_branch2_ops,
1428	},
1429	},
1430	};
1431
1432	static struct clk_branch gcc_camera_ahb_clk = {
1433	.halt_reg = 0x17008,
1434	.halt_check = BRANCH_HALT_DELAY,
1435	.hwcg_reg = 0x17008,
1436	.hwcg_bit = 1,
1437	.clkr = {
1438	.enable_reg = 0x17008,
1439	.enable_mask = BIT(0),
1440	.hw.init = &(struct clk_init_data){
1441	.name = "gcc_camera_ahb_clk",
1442	.flags = CLK_IS_CRITICAL,
1443	.ops = &clk_branch2_ops,
1444	},
1445	},
1446	};
1447
1448	static struct clk_branch gcc_camera_xo_clk = {
1449	.halt_reg = 0x17028,
1450	.halt_check = BRANCH_HALT,
1451	.clkr = {
1452	.enable_reg = 0x17028,
1453	.enable_mask = BIT(0),
1454	.hw.init = &(struct clk_init_data){
1455	.name = "gcc_camera_xo_clk",
1456	.flags = CLK_IS_CRITICAL,
1457	.ops = &clk_branch2_ops,
1458	},
1459	},
1460	};
1461
1462	static struct clk_branch gcc_camss_cci_ahb_clk = {
1463	.halt_reg = 0x52020,
1464	.halt_check = BRANCH_HALT,
1465	.clkr = {
1466	.enable_reg = 0x52020,
1467	.enable_mask = BIT(0),
1468	.hw.init = &(struct clk_init_data){
1469	.name = "gcc_camss_cci_ahb_clk",
1470	.parent_hws = (const struct clk_hw*[]){
1471	&gcc_camss_ahb_clk_src.clkr.hw,
1472	},
1473	.num_parents = 1,
1474	.flags = CLK_SET_RATE_PARENT,
1475	.ops = &clk_branch2_ops,
1476	},
1477	},
1478	};
1479
1480	static struct clk_branch gcc_camss_cci_clk = {
1481	.halt_reg = 0x5201c,
1482	.halt_check = BRANCH_HALT,
1483	.clkr = {
1484	.enable_reg = 0x5201c,
1485	.enable_mask = BIT(0),
1486	.hw.init = &(struct clk_init_data){
1487	.name = "gcc_camss_cci_clk",
1488	.parent_hws = (const struct clk_hw*[]){
1489	&gcc_camss_cci_clk_src.clkr.hw,
1490	},
1491	.num_parents = 1,
1492	.flags = CLK_SET_RATE_PARENT,
1493	.ops = &clk_branch2_ops,
1494	},
1495	},
1496	};
1497
1498	static struct clk_branch gcc_camss_cphy_csid0_clk = {
1499	.halt_reg = 0x5504c,
1500	.halt_check = BRANCH_HALT,
1501	.clkr = {
1502	.enable_reg = 0x5504c,
1503	.enable_mask = BIT(0),
1504	.hw.init = &(struct clk_init_data){
1505	.name = "gcc_camss_cphy_csid0_clk",
1506	.parent_hws = (const struct clk_hw*[]){
1507	&gcc_camss_csiphy_clk_src.clkr.hw,
1508	},
1509	.num_parents = 1,
1510	.flags = CLK_SET_RATE_PARENT,
1511	.ops = &clk_branch2_ops,
1512	},
1513	},
1514	};
1515
1516	static struct clk_branch gcc_camss_cphy_csid1_clk = {
1517	.halt_reg = 0x55088,
1518	.halt_check = BRANCH_HALT,
1519	.clkr = {
1520	.enable_reg = 0x55088,
1521	.enable_mask = BIT(0),
1522	.hw.init = &(struct clk_init_data){
1523	.name = "gcc_camss_cphy_csid1_clk",
1524	.parent_hws = (const struct clk_hw*[]){
1525	&gcc_camss_csiphy_clk_src.clkr.hw,
1526	},
1527	.num_parents = 1,
1528	.flags = CLK_SET_RATE_PARENT,
1529	.ops = &clk_branch2_ops,
1530	},
1531	},
1532	};
1533
1534	static struct clk_branch gcc_camss_cphy_csid2_clk = {
1535	.halt_reg = 0x550c0,
1536	.halt_check = BRANCH_HALT,
1537	.clkr = {
1538	.enable_reg = 0x550c0,
1539	.enable_mask = BIT(0),
1540	.hw.init = &(struct clk_init_data){
1541	.name = "gcc_camss_cphy_csid2_clk",
1542	.parent_hws = (const struct clk_hw*[]){
1543	&gcc_camss_csiphy_clk_src.clkr.hw,
1544	},
1545	.num_parents = 1,
1546	.flags = CLK_SET_RATE_PARENT,
1547	.ops = &clk_branch2_ops,
1548	},
1549	},
1550	};
1551
1552	static struct clk_branch gcc_camss_cphy_csid3_clk = {
1553	.halt_reg = 0x550fc,
1554	.halt_check = BRANCH_HALT,
1555	.clkr = {
1556	.enable_reg = 0x550fc,
1557	.enable_mask = BIT(0),
1558	.hw.init = &(struct clk_init_data){
1559	.name = "gcc_camss_cphy_csid3_clk",
1560	.parent_hws = (const struct clk_hw*[]){
1561	&gcc_camss_csiphy_clk_src.clkr.hw,
1562	},
1563	.num_parents = 1,
1564	.flags = CLK_SET_RATE_PARENT,
1565	.ops = &clk_branch2_ops,
1566	},
1567	},
1568	};
1569
1570	static struct clk_branch gcc_camss_cpp_ahb_clk = {
1571	.halt_reg = 0x560e8,
1572	.halt_check = BRANCH_HALT,
1573	.clkr = {
1574	.enable_reg = 0x560e8,
1575	.enable_mask = BIT(0),
1576	.hw.init = &(struct clk_init_data){
1577	.name = "gcc_camss_cpp_ahb_clk",
1578	.parent_hws = (const struct clk_hw*[]){
1579	&gcc_camss_ahb_clk_src.clkr.hw,
1580	},
1581	.num_parents = 1,
1582	.flags = CLK_SET_RATE_PARENT,
1583	.ops = &clk_branch2_ops,
1584	},
1585	},
1586	};
1587
1588	static struct clk_branch gcc_camss_cpp_axi_clk = {
1589	.halt_reg = 0x560f4,
1590	.halt_check = BRANCH_HALT,
1591	.clkr = {
1592	.enable_reg = 0x560f4,
1593	.enable_mask = BIT(0),
1594	.hw.init = &(struct clk_init_data){
1595	.name = "gcc_camss_cpp_axi_clk",
1596	.ops = &clk_branch2_ops,
1597	},
1598	},
1599	};
1600
1601	static struct clk_branch gcc_camss_cpp_clk = {
1602	.halt_reg = 0x560e0,
1603	.halt_check = BRANCH_HALT,
1604	.clkr = {
1605	.enable_reg = 0x560e0,
1606	.enable_mask = BIT(0),
1607	.hw.init = &(struct clk_init_data){
1608	.name = "gcc_camss_cpp_clk",
1609	.parent_hws = (const struct clk_hw*[]){
1610	&gcc_camss_cpp_clk_src.clkr.hw,
1611	},
1612	.num_parents = 1,
1613	.flags = CLK_SET_RATE_PARENT,
1614	.ops = &clk_branch2_ops,
1615	},
1616	},
1617	};
1618
1619	static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = {
1620	.halt_reg = 0x560f0,
1621	.halt_check = BRANCH_HALT,
1622	.clkr = {
1623	.enable_reg = 0x560f0,
1624	.enable_mask = BIT(0),
1625	.hw.init = &(struct clk_init_data){
1626	.name = "gcc_camss_cpp_vbif_ahb_clk",
1627	.parent_hws = (const struct clk_hw*[]){
1628	&gcc_camss_ahb_clk_src.clkr.hw,
1629	},
1630	.num_parents = 1,
1631	.flags = CLK_SET_RATE_PARENT,
1632	.ops = &clk_branch2_ops,
1633	},
1634	},
1635	};
1636
1637	static struct clk_branch gcc_camss_csi0_ahb_clk = {
1638	.halt_reg = 0x55050,
1639	.halt_check = BRANCH_HALT,
1640	.clkr = {
1641	.enable_reg = 0x55050,
1642	.enable_mask = BIT(0),
1643	.hw.init = &(struct clk_init_data){
1644	.name = "gcc_camss_csi0_ahb_clk",
1645	.parent_hws = (const struct clk_hw*[]){
1646	&gcc_camss_ahb_clk_src.clkr.hw,
1647	},
1648	.num_parents = 1,
1649	.flags = CLK_SET_RATE_PARENT,
1650	.ops = &clk_branch2_ops,
1651	},
1652	},
1653	};
1654
1655	static struct clk_branch gcc_camss_csi0_clk = {
1656	.halt_reg = 0x55048,
1657	.halt_check = BRANCH_HALT,
1658	.clkr = {
1659	.enable_reg = 0x55048,
1660	.enable_mask = BIT(0),
1661	.hw.init = &(struct clk_init_data){
1662	.name = "gcc_camss_csi0_clk",
1663	.parent_hws = (const struct clk_hw*[]){
1664	&gcc_camss_csi0_clk_src.clkr.hw,
1665	},
1666	.num_parents = 1,
1667	.flags = CLK_SET_RATE_PARENT,
1668	.ops = &clk_branch2_ops,
1669	},
1670	},
1671	};
1672
1673	static struct clk_branch gcc_camss_csi0phytimer_clk = {
1674	.halt_reg = 0x5301c,
1675	.halt_check = BRANCH_HALT,
1676	.clkr = {
1677	.enable_reg = 0x5301c,
1678	.enable_mask = BIT(0),
1679	.hw.init = &(struct clk_init_data){
1680	.name = "gcc_camss_csi0phytimer_clk",
1681	.parent_hws = (const struct clk_hw*[]){
1682	&gcc_camss_csi0phytimer_clk_src.clkr.hw,
1683	},
1684	.num_parents = 1,
1685	.flags = CLK_SET_RATE_PARENT,
1686	.ops = &clk_branch2_ops,
1687	},
1688	},
1689	};
1690
1691	static struct clk_branch gcc_camss_csi0pix_clk = {
1692	.halt_reg = 0x55060,
1693	.halt_check = BRANCH_HALT,
1694	.clkr = {
1695	.enable_reg = 0x55060,
1696	.enable_mask = BIT(0),
1697	.hw.init = &(struct clk_init_data){
1698	.name = "gcc_camss_csi0pix_clk",
1699	.parent_hws = (const struct clk_hw*[]){
1700	&gcc_camss_csi0_clk_src.clkr.hw,
1701	},
1702	.num_parents = 1,
1703	.flags = CLK_SET_RATE_PARENT,
1704	.ops = &clk_branch2_ops,
1705	},
1706	},
1707	};
1708
1709	static struct clk_branch gcc_camss_csi0rdi_clk = {
1710	.halt_reg = 0x55058,
1711	.halt_check = BRANCH_HALT,
1712	.clkr = {
1713	.enable_reg = 0x55058,
1714	.enable_mask = BIT(0),
1715	.hw.init = &(struct clk_init_data){
1716	.name = "gcc_camss_csi0rdi_clk",
1717	.parent_hws = (const struct clk_hw*[]){
1718	&gcc_camss_csi0_clk_src.clkr.hw,
1719	},
1720	.num_parents = 1,
1721	.flags = CLK_SET_RATE_PARENT,
1722	.ops = &clk_branch2_ops,
1723	},
1724	},
1725	};
1726
1727	static struct clk_branch gcc_camss_csi1_ahb_clk = {
1728	.halt_reg = 0x5508c,
1729	.halt_check = BRANCH_HALT,
1730	.clkr = {
1731	.enable_reg = 0x5508c,
1732	.enable_mask = BIT(0),
1733	.hw.init = &(struct clk_init_data){
1734	.name = "gcc_camss_csi1_ahb_clk",
1735	.parent_hws = (const struct clk_hw*[]){
1736	&gcc_camss_ahb_clk_src.clkr.hw,
1737	},
1738	.num_parents = 1,
1739	.flags = CLK_SET_RATE_PARENT,
1740	.ops = &clk_branch2_ops,
1741	},
1742	},
1743	};
1744
1745	static struct clk_branch gcc_camss_csi1_clk = {
1746	.halt_reg = 0x55084,
1747	.halt_check = BRANCH_HALT,
1748	.clkr = {
1749	.enable_reg = 0x55084,
1750	.enable_mask = BIT(0),
1751	.hw.init = &(struct clk_init_data){
1752	.name = "gcc_camss_csi1_clk",
1753	.parent_hws = (const struct clk_hw*[]){
1754	&gcc_camss_csi1_clk_src.clkr.hw,
1755	},
1756	.num_parents = 1,
1757	.flags = CLK_SET_RATE_PARENT,
1758	.ops = &clk_branch2_ops,
1759	},
1760	},
1761	};
1762
1763	static struct clk_branch gcc_camss_csi1phytimer_clk = {
1764	.halt_reg = 0x5303c,
1765	.halt_check = BRANCH_HALT,
1766	.clkr = {
1767	.enable_reg = 0x5303c,
1768	.enable_mask = BIT(0),
1769	.hw.init = &(struct clk_init_data){
1770	.name = "gcc_camss_csi1phytimer_clk",
1771	.parent_hws = (const struct clk_hw*[]){
1772	&gcc_camss_csi1phytimer_clk_src.clkr.hw,
1773	},
1774	.num_parents = 1,
1775	.flags = CLK_SET_RATE_PARENT,
1776	.ops = &clk_branch2_ops,
1777	},
1778	},
1779	};
1780
1781	static struct clk_branch gcc_camss_csi1pix_clk = {
1782	.halt_reg = 0x5509c,
1783	.halt_check = BRANCH_HALT,
1784	.clkr = {
1785	.enable_reg = 0x5509c,
1786	.enable_mask = BIT(0),
1787	.hw.init = &(struct clk_init_data){
1788	.name = "gcc_camss_csi1pix_clk",
1789	.parent_hws = (const struct clk_hw*[]){
1790	&gcc_camss_csi1_clk_src.clkr.hw,
1791	},
1792	.num_parents = 1,
1793	.flags = CLK_SET_RATE_PARENT,
1794	.ops = &clk_branch2_ops,
1795	},
1796	},
1797	};
1798
1799	static struct clk_branch gcc_camss_csi1rdi_clk = {
1800	.halt_reg = 0x55094,
1801	.halt_check = BRANCH_HALT,
1802	.clkr = {
1803	.enable_reg = 0x55094,
1804	.enable_mask = BIT(0),
1805	.hw.init = &(struct clk_init_data){
1806	.name = "gcc_camss_csi1rdi_clk",
1807	.parent_hws = (const struct clk_hw*[]){
1808	&gcc_camss_csi1_clk_src.clkr.hw,
1809	},
1810	.num_parents = 1,
1811	.flags = CLK_SET_RATE_PARENT,
1812	.ops = &clk_branch2_ops,
1813	},
1814	},
1815	};
1816
1817	static struct clk_branch gcc_camss_csi2_ahb_clk = {
1818	.halt_reg = 0x550c4,
1819	.halt_check = BRANCH_HALT,
1820	.clkr = {
1821	.enable_reg = 0x550c4,
1822	.enable_mask = BIT(0),
1823	.hw.init = &(struct clk_init_data){
1824	.name = "gcc_camss_csi2_ahb_clk",
1825	.parent_hws = (const struct clk_hw*[]){
1826	&gcc_camss_ahb_clk_src.clkr.hw,
1827	},
1828	.num_parents = 1,
1829	.flags = CLK_SET_RATE_PARENT,
1830	.ops = &clk_branch2_ops,
1831	},
1832	},
1833	};
1834
1835	static struct clk_branch gcc_camss_csi2_clk = {
1836	.halt_reg = 0x550bc,
1837	.halt_check = BRANCH_HALT,
1838	.clkr = {
1839	.enable_reg = 0x550bc,
1840	.enable_mask = BIT(0),
1841	.hw.init = &(struct clk_init_data){
1842	.name = "gcc_camss_csi2_clk",
1843	.parent_hws = (const struct clk_hw*[]){
1844	&gcc_camss_csi2_clk_src.clkr.hw,
1845	},
1846	.num_parents = 1,
1847	.flags = CLK_SET_RATE_PARENT,
1848	.ops = &clk_branch2_ops,
1849	},
1850	},
1851	};
1852
1853	static struct clk_branch gcc_camss_csi2phytimer_clk = {
1854	.halt_reg = 0x5305c,
1855	.halt_check = BRANCH_HALT,
1856	.clkr = {
1857	.enable_reg = 0x5305c,
1858	.enable_mask = BIT(0),
1859	.hw.init = &(struct clk_init_data){
1860	.name = "gcc_camss_csi2phytimer_clk",
1861	.parent_hws = (const struct clk_hw*[]){
1862	&gcc_camss_csi2phytimer_clk_src.clkr.hw,
1863	},
1864	.num_parents = 1,
1865	.flags = CLK_SET_RATE_PARENT,
1866	.ops = &clk_branch2_ops,
1867	},
1868	},
1869	};
1870
1871	static struct clk_branch gcc_camss_csi2pix_clk = {
1872	.halt_reg = 0x550d4,
1873	.halt_check = BRANCH_HALT,
1874	.clkr = {
1875	.enable_reg = 0x550d4,
1876	.enable_mask = BIT(0),
1877	.hw.init = &(struct clk_init_data){
1878	.name = "gcc_camss_csi2pix_clk",
1879	.parent_hws = (const struct clk_hw*[]){
1880	&gcc_camss_csi2_clk_src.clkr.hw,
1881	},
1882	.num_parents = 1,
1883	.flags = CLK_SET_RATE_PARENT,
1884	.ops = &clk_branch2_ops,
1885	},
1886	},
1887	};
1888
1889	static struct clk_branch gcc_camss_csi2rdi_clk = {
1890	.halt_reg = 0x550cc,
1891	.halt_check = BRANCH_HALT,
1892	.clkr = {
1893	.enable_reg = 0x550cc,
1894	.enable_mask = BIT(0),
1895	.hw.init = &(struct clk_init_data){
1896	.name = "gcc_camss_csi2rdi_clk",
1897	.parent_hws = (const struct clk_hw*[]){
1898	&gcc_camss_csi2_clk_src.clkr.hw,
1899	},
1900	.num_parents = 1,
1901	.flags = CLK_SET_RATE_PARENT,
1902	.ops = &clk_branch2_ops,
1903	},
1904	},
1905	};
1906
1907	static struct clk_branch gcc_camss_csi3_ahb_clk = {
1908	.halt_reg = 0x55100,
1909	.halt_check = BRANCH_HALT,
1910	.clkr = {
1911	.enable_reg = 0x55100,
1912	.enable_mask = BIT(0),
1913	.hw.init = &(struct clk_init_data){
1914	.name = "gcc_camss_csi3_ahb_clk",
1915	.parent_hws = (const struct clk_hw*[]){
1916	&gcc_camss_ahb_clk_src.clkr.hw,
1917	},
1918	.num_parents = 1,
1919	.flags = CLK_SET_RATE_PARENT,
1920	.ops = &clk_branch2_ops,
1921	},
1922	},
1923	};
1924
1925	static struct clk_branch gcc_camss_csi3_clk = {
1926	.halt_reg = 0x550f8,
1927	.halt_check = BRANCH_HALT,
1928	.clkr = {
1929	.enable_reg = 0x550f8,
1930	.enable_mask = BIT(0),
1931	.hw.init = &(struct clk_init_data){
1932	.name = "gcc_camss_csi3_clk",
1933	.parent_hws = (const struct clk_hw*[]){
1934	&gcc_camss_csi3_clk_src.clkr.hw,
1935	},
1936	.num_parents = 1,
1937	.flags = CLK_SET_RATE_PARENT,
1938	.ops = &clk_branch2_ops,
1939	},
1940	},
1941	};
1942
1943	static struct clk_branch gcc_camss_csi3pix_clk = {
1944	.halt_reg = 0x55110,
1945	.halt_check = BRANCH_HALT,
1946	.clkr = {
1947	.enable_reg = 0x55110,
1948	.enable_mask = BIT(0),
1949	.hw.init = &(struct clk_init_data){
1950	.name = "gcc_camss_csi3pix_clk",
1951	.parent_hws = (const struct clk_hw*[]){
1952	&gcc_camss_csi3_clk_src.clkr.hw,
1953	},
1954	.num_parents = 1,
1955	.flags = CLK_SET_RATE_PARENT,
1956	.ops = &clk_branch2_ops,
1957	},
1958	},
1959	};
1960
1961	static struct clk_branch gcc_camss_csi3rdi_clk = {
1962	.halt_reg = 0x55108,
1963	.halt_check = BRANCH_HALT,
1964	.clkr = {
1965	.enable_reg = 0x55108,
1966	.enable_mask = BIT(0),
1967	.hw.init = &(struct clk_init_data){
1968	.name = "gcc_camss_csi3rdi_clk",
1969	.parent_hws = (const struct clk_hw*[]){
1970	&gcc_camss_csi3_clk_src.clkr.hw,
1971	},
1972	.num_parents = 1,
1973	.flags = CLK_SET_RATE_PARENT,
1974	.ops = &clk_branch2_ops,
1975	},
1976	},
1977	};
1978
1979	static struct clk_branch gcc_camss_csi_vfe0_clk = {
1980	.halt_reg = 0x54074,
1981	.halt_check = BRANCH_HALT,
1982	.clkr = {
1983	.enable_reg = 0x54074,
1984	.enable_mask = BIT(0),
1985	.hw.init = &(struct clk_init_data){
1986	.name = "gcc_camss_csi_vfe0_clk",
1987	.parent_hws = (const struct clk_hw*[]){
1988	&gcc_camss_vfe0_clk_src.clkr.hw,
1989	},
1990	.num_parents = 1,
1991	.flags = CLK_SET_RATE_PARENT,
1992	.ops = &clk_branch2_ops,
1993	},
1994	},
1995	};
1996
1997	static struct clk_branch gcc_camss_csi_vfe1_clk = {
1998	.halt_reg = 0x54080,
1999	.halt_check = BRANCH_HALT,
2000	.clkr = {
2001	.enable_reg = 0x54080,
2002	.enable_mask = BIT(0),
2003	.hw.init = &(struct clk_init_data){
2004	.name = "gcc_camss_csi_vfe1_clk",
2005	.parent_hws = (const struct clk_hw*[]){
2006	&gcc_camss_vfe1_clk_src.clkr.hw,
2007	},
2008	.num_parents = 1,
2009	.flags = CLK_SET_RATE_PARENT,
2010	.ops = &clk_branch2_ops,
2011	},
2012	},
2013	};
2014
2015	static struct clk_branch gcc_camss_csiphy0_clk = {
2016	.halt_reg = 0x55018,
2017	.halt_check = BRANCH_HALT,
2018	.clkr = {
2019	.enable_reg = 0x55018,
2020	.enable_mask = BIT(0),
2021	.hw.init = &(struct clk_init_data){
2022	.name = "gcc_camss_csiphy0_clk",
2023	.parent_hws = (const struct clk_hw*[]){
2024	&gcc_camss_csiphy_clk_src.clkr.hw,
2025	},
2026	.num_parents = 1,
2027	.flags = CLK_SET_RATE_PARENT,
2028	.ops = &clk_branch2_ops,
2029	},
2030	},
2031	};
2032
2033	static struct clk_branch gcc_camss_csiphy1_clk = {
2034	.halt_reg = 0x5501c,
2035	.halt_check = BRANCH_HALT,
2036	.clkr = {
2037	.enable_reg = 0x5501c,
2038	.enable_mask = BIT(0),
2039	.hw.init = &(struct clk_init_data){
2040	.name = "gcc_camss_csiphy1_clk",
2041	.parent_hws = (const struct clk_hw*[]){
2042	&gcc_camss_csiphy_clk_src.clkr.hw,
2043	},
2044	.num_parents = 1,
2045	.flags = CLK_SET_RATE_PARENT,
2046	.ops = &clk_branch2_ops,
2047	},
2048	},
2049	};
2050
2051	static struct clk_branch gcc_camss_csiphy2_clk = {
2052	.halt_reg = 0x55020,
2053	.halt_check = BRANCH_HALT,
2054	.clkr = {
2055	.enable_reg = 0x55020,
2056	.enable_mask = BIT(0),
2057	.hw.init = &(struct clk_init_data){
2058	.name = "gcc_camss_csiphy2_clk",
2059	.parent_hws = (const struct clk_hw*[]){
2060	&gcc_camss_csiphy_clk_src.clkr.hw,
2061	},
2062	.num_parents = 1,
2063	.flags = CLK_SET_RATE_PARENT,
2064	.ops = &clk_branch2_ops,
2065	},
2066	},
2067	};
2068
2069	static struct clk_branch gcc_camss_gp0_clk = {
2070	.halt_reg = 0x50018,
2071	.halt_check = BRANCH_HALT,
2072	.clkr = {
2073	.enable_reg = 0x50018,
2074	.enable_mask = BIT(0),
2075	.hw.init = &(struct clk_init_data){
2076	.name = "gcc_camss_gp0_clk",
2077	.parent_hws = (const struct clk_hw*[]){
2078	&gcc_camss_gp0_clk_src.clkr.hw,
2079	},
2080	.num_parents = 1,
2081	.flags = CLK_SET_RATE_PARENT,
2082	.ops = &clk_branch2_ops,
2083	},
2084	},
2085	};
2086
2087	static struct clk_branch gcc_camss_gp1_clk = {
2088	.halt_reg = 0x50034,
2089	.halt_check = BRANCH_HALT,
2090	.clkr = {
2091	.enable_reg = 0x50034,
2092	.enable_mask = BIT(0),
2093	.hw.init = &(struct clk_init_data){
2094	.name = "gcc_camss_gp1_clk",
2095	.parent_hws = (const struct clk_hw*[]){
2096	&gcc_camss_gp1_clk_src.clkr.hw,
2097	},
2098	.num_parents = 1,
2099	.flags = CLK_SET_RATE_PARENT,
2100	.ops = &clk_branch2_ops,
2101	},
2102	},
2103	};
2104
2105	static struct clk_branch gcc_camss_ispif_ahb_clk = {
2106	.halt_reg = 0x540a4,
2107	.halt_check = BRANCH_HALT,
2108	.clkr = {
2109	.enable_reg = 0x540a4,
2110	.enable_mask = BIT(0),
2111	.hw.init = &(struct clk_init_data){
2112	.name = "gcc_camss_ispif_ahb_clk",
2113	.parent_hws = (const struct clk_hw*[]){
2114	&gcc_camss_ahb_clk_src.clkr.hw,
2115	},
2116	.num_parents = 1,
2117	.flags = CLK_SET_RATE_PARENT,
2118	.ops = &clk_branch2_ops,
2119	},
2120	},
2121	};
2122
2123	static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2124	.halt_reg = 0x52048,
2125	.halt_check = BRANCH_HALT,
2126	.clkr = {
2127	.enable_reg = 0x52048,
2128	.enable_mask = BIT(0),
2129	.hw.init = &(struct clk_init_data){
2130	.name = "gcc_camss_jpeg_ahb_clk",
2131	.parent_hws = (const struct clk_hw*[]){
2132	&gcc_camss_ahb_clk_src.clkr.hw,
2133	},
2134	.num_parents = 1,
2135	.flags = CLK_SET_RATE_PARENT,
2136	.ops = &clk_branch2_ops,
2137	},
2138	},
2139	};
2140
2141	static struct clk_branch gcc_camss_jpeg_axi_clk = {
2142	.halt_reg = 0x5204c,
2143	.halt_check = BRANCH_HALT,
2144	.clkr = {
2145	.enable_reg = 0x5204c,
2146	.enable_mask = BIT(0),
2147	.hw.init = &(struct clk_init_data){
2148	.name = "gcc_camss_jpeg_axi_clk",
2149	.ops = &clk_branch2_ops,
2150	},
2151	},
2152	};
2153
2154	static struct clk_branch gcc_camss_jpeg_clk = {
2155	.halt_reg = 0x52040,
2156	.halt_check = BRANCH_HALT,
2157	.clkr = {
2158	.enable_reg = 0x52040,
2159	.enable_mask = BIT(0),
2160	.hw.init = &(struct clk_init_data){
2161	.name = "gcc_camss_jpeg_clk",
2162	.parent_hws = (const struct clk_hw*[]){
2163	&gcc_camss_jpeg_clk_src.clkr.hw,
2164	},
2165	.num_parents = 1,
2166	.flags = CLK_SET_RATE_PARENT,
2167	.ops = &clk_branch2_ops,
2168	},
2169	},
2170	};
2171
2172	static struct clk_branch gcc_camss_mclk0_clk = {
2173	.halt_reg = 0x51018,
2174	.halt_check = BRANCH_HALT,
2175	.clkr = {
2176	.enable_reg = 0x51018,
2177	.enable_mask = BIT(0),
2178	.hw.init = &(struct clk_init_data){
2179	.name = "gcc_camss_mclk0_clk",
2180	.parent_hws = (const struct clk_hw*[]){
2181	&gcc_camss_mclk0_clk_src.clkr.hw,
2182	},
2183	.num_parents = 1,
2184	.flags = CLK_SET_RATE_PARENT,
2185	.ops = &clk_branch2_ops,
2186	},
2187	},
2188	};
2189
2190	static struct clk_branch gcc_camss_mclk1_clk = {
2191	.halt_reg = 0x51034,
2192	.halt_check = BRANCH_HALT,
2193	.clkr = {
2194	.enable_reg = 0x51034,
2195	.enable_mask = BIT(0),
2196	.hw.init = &(struct clk_init_data){
2197	.name = "gcc_camss_mclk1_clk",
2198	.parent_hws = (const struct clk_hw*[]){
2199	&gcc_camss_mclk1_clk_src.clkr.hw,
2200	},
2201	.num_parents = 1,
2202	.flags = CLK_SET_RATE_PARENT,
2203	.ops = &clk_branch2_ops,
2204	},
2205	},
2206	};
2207
2208	static struct clk_branch gcc_camss_mclk2_clk = {
2209	.halt_reg = 0x51050,
2210	.halt_check = BRANCH_HALT,
2211	.clkr = {
2212	.enable_reg = 0x51050,
2213	.enable_mask = BIT(0),
2214	.hw.init = &(struct clk_init_data){
2215	.name = "gcc_camss_mclk2_clk",
2216	.parent_hws = (const struct clk_hw*[]){
2217	&gcc_camss_mclk2_clk_src.clkr.hw,
2218	},
2219	.num_parents = 1,
2220	.flags = CLK_SET_RATE_PARENT,
2221	.ops = &clk_branch2_ops,
2222	},
2223	},
2224	};
2225
2226	static struct clk_branch gcc_camss_mclk3_clk = {
2227	.halt_reg = 0x5106c,
2228	.halt_check = BRANCH_HALT,
2229	.clkr = {
2230	.enable_reg = 0x5106c,
2231	.enable_mask = BIT(0),
2232	.hw.init = &(struct clk_init_data){
2233	.name = "gcc_camss_mclk3_clk",
2234	.parent_hws = (const struct clk_hw*[]){
2235	&gcc_camss_mclk3_clk_src.clkr.hw,
2236	},
2237	.num_parents = 1,
2238	.flags = CLK_SET_RATE_PARENT,
2239	.ops = &clk_branch2_ops,
2240	},
2241	},
2242	};
2243
2244	static struct clk_branch gcc_camss_micro_ahb_clk = {
2245	.halt_reg = 0x560b0,
2246	.halt_check = BRANCH_HALT,
2247	.clkr = {
2248	.enable_reg = 0x560b0,
2249	.enable_mask = BIT(0),
2250	.hw.init = &(struct clk_init_data){
2251	.name = "gcc_camss_micro_ahb_clk",
2252	.parent_hws = (const struct clk_hw*[]){
2253	&gcc_camss_ahb_clk_src.clkr.hw,
2254	},
2255	.num_parents = 1,
2256	.flags = CLK_SET_RATE_PARENT,
2257	.ops = &clk_branch2_ops,
2258	},
2259	},
2260	};
2261
2262	static struct clk_branch gcc_camss_throttle_nrt_axi_clk = {
2263	.halt_reg = 0x560a4,
2264	.halt_check = BRANCH_HALT_VOTED,
2265	.clkr = {
2266	.enable_reg = 0x79004,
2267	.enable_mask = BIT(27),
2268	.hw.init = &(struct clk_init_data){
2269	.name = "gcc_camss_throttle_nrt_axi_clk",
2270	.ops = &clk_branch2_ops,
2271	},
2272	},
2273	};
2274
2275	static struct clk_branch gcc_camss_throttle_rt_axi_clk = {
2276	.halt_reg = 0x560a8,
2277	.halt_check = BRANCH_HALT_VOTED,
2278	.clkr = {
2279	.enable_reg = 0x79004,
2280	.enable_mask = BIT(26),
2281	.hw.init = &(struct clk_init_data){
2282	.name = "gcc_camss_throttle_rt_axi_clk",
2283	.ops = &clk_branch2_ops,
2284	},
2285	},
2286	};
2287
2288	static struct clk_branch gcc_camss_top_ahb_clk = {
2289	.halt_reg = 0x560a0,
2290	.halt_check = BRANCH_HALT,
2291	.clkr = {
2292	.enable_reg = 0x560a0,
2293	.enable_mask = BIT(0),
2294	.hw.init = &(struct clk_init_data){
2295	.name = "gcc_camss_top_ahb_clk",
2296	.parent_hws = (const struct clk_hw*[]){
2297	&gcc_camss_ahb_clk_src.clkr.hw,
2298	},
2299	.num_parents = 1,
2300	.flags = CLK_SET_RATE_PARENT,
2301	.ops = &clk_branch2_ops,
2302	},
2303	},
2304	};
2305
2306	static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2307	.halt_reg = 0x54034,
2308	.halt_check = BRANCH_HALT,
2309	.clkr = {
2310	.enable_reg = 0x54034,
2311	.enable_mask = BIT(0),
2312	.hw.init = &(struct clk_init_data){
2313	.name = "gcc_camss_vfe0_ahb_clk",
2314	.parent_hws = (const struct clk_hw*[]){
2315	&gcc_camss_ahb_clk_src.clkr.hw,
2316	},
2317	.num_parents = 1,
2318	.flags = CLK_SET_RATE_PARENT,
2319	.ops = &clk_branch2_ops,
2320	},
2321	},
2322	};
2323
2324	static struct clk_branch gcc_camss_vfe0_clk = {
2325	.halt_reg = 0x54028,
2326	.halt_check = BRANCH_HALT,
2327	.clkr = {
2328	.enable_reg = 0x54028,
2329	.enable_mask = BIT(0),
2330	.hw.init = &(struct clk_init_data){
2331	.name = "gcc_camss_vfe0_clk",
2332	.parent_hws = (const struct clk_hw*[]){
2333	&gcc_camss_vfe0_clk_src.clkr.hw,
2334	},
2335	.num_parents = 1,
2336	.flags = CLK_SET_RATE_PARENT,
2337	.ops = &clk_branch2_ops,
2338	},
2339	},
2340	};
2341
2342	static struct clk_branch gcc_camss_vfe0_stream_clk = {
2343	.halt_reg = 0x54030,
2344	.halt_check = BRANCH_HALT,
2345	.clkr = {
2346	.enable_reg = 0x54030,
2347	.enable_mask = BIT(0),
2348	.hw.init = &(struct clk_init_data){
2349	.name = "gcc_camss_vfe0_stream_clk",
2350	.parent_hws = (const struct clk_hw*[]){
2351	&gcc_camss_vfe0_clk_src.clkr.hw,
2352	},
2353	.num_parents = 1,
2354	.flags = CLK_SET_RATE_PARENT,
2355	.ops = &clk_branch2_ops,
2356	},
2357	},
2358	};
2359
2360	static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2361	.halt_reg = 0x5406c,
2362	.halt_check = BRANCH_HALT,
2363	.clkr = {
2364	.enable_reg = 0x5406c,
2365	.enable_mask = BIT(0),
2366	.hw.init = &(struct clk_init_data){
2367	.name = "gcc_camss_vfe1_ahb_clk",
2368	.parent_hws = (const struct clk_hw*[]){
2369	&gcc_camss_ahb_clk_src.clkr.hw,
2370	},
2371	.num_parents = 1,
2372	.flags = CLK_SET_RATE_PARENT,
2373	.ops = &clk_branch2_ops,
2374	},
2375	},
2376	};
2377
2378	static struct clk_branch gcc_camss_vfe1_clk = {
2379	.halt_reg = 0x54060,
2380	.halt_check = BRANCH_HALT,
2381	.clkr = {
2382	.enable_reg = 0x54060,
2383	.enable_mask = BIT(0),
2384	.hw.init = &(struct clk_init_data){
2385	.name = "gcc_camss_vfe1_clk",
2386	.parent_hws = (const struct clk_hw*[]){
2387	&gcc_camss_vfe1_clk_src.clkr.hw,
2388	},
2389	.num_parents = 1,
2390	.flags = CLK_SET_RATE_PARENT,
2391	.ops = &clk_branch2_ops,
2392	},
2393	},
2394	};
2395
2396	static struct clk_branch gcc_camss_vfe1_stream_clk = {
2397	.halt_reg = 0x54068,
2398	.halt_check = BRANCH_HALT,
2399	.clkr = {
2400	.enable_reg = 0x54068,
2401	.enable_mask = BIT(0),
2402	.hw.init = &(struct clk_init_data){
2403	.name = "gcc_camss_vfe1_stream_clk",
2404	.parent_hws = (const struct clk_hw*[]){
2405	&gcc_camss_vfe1_clk_src.clkr.hw,
2406	},
2407	.num_parents = 1,
2408	.flags = CLK_SET_RATE_PARENT,
2409	.ops = &clk_branch2_ops,
2410	},
2411	},
2412	};
2413
2414	static struct clk_branch gcc_camss_vfe_tsctr_clk = {
2415	.halt_reg = 0x5409c,
2416	.halt_check = BRANCH_HALT,
2417	.clkr = {
2418	.enable_reg = 0x5409c,
2419	.enable_mask = BIT(0),
2420	.hw.init = &(struct clk_init_data){
2421	.name = "gcc_camss_vfe_tsctr_clk",
2422	.ops = &clk_branch2_ops,
2423	},
2424	},
2425	};
2426
2427	static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = {
2428	.halt_reg = 0x5408c,
2429	.halt_check = BRANCH_HALT,
2430	.clkr = {
2431	.enable_reg = 0x5408c,
2432	.enable_mask = BIT(0),
2433	.hw.init = &(struct clk_init_data){
2434	.name = "gcc_camss_vfe_vbif_ahb_clk",
2435	.parent_hws = (const struct clk_hw*[]){
2436	&gcc_camss_ahb_clk_src.clkr.hw,
2437	},
2438	.num_parents = 1,
2439	.flags = CLK_SET_RATE_PARENT,
2440	.ops = &clk_branch2_ops,
2441	},
2442	},
2443	};
2444
2445	static struct clk_branch gcc_camss_vfe_vbif_axi_clk = {
2446	.halt_reg = 0x54090,
2447	.halt_check = BRANCH_HALT,
2448	.clkr = {
2449	.enable_reg = 0x54090,
2450	.enable_mask = BIT(0),
2451	.hw.init = &(struct clk_init_data){
2452	.name = "gcc_camss_vfe_vbif_axi_clk",
2453	.ops = &clk_branch2_ops,
2454	},
2455	},
2456	};
2457
2458	static struct clk_branch gcc_ce1_ahb_clk = {
2459	.halt_reg = 0x2700c,
2460	.halt_check = BRANCH_HALT_VOTED,
2461	.hwcg_reg = 0x2700c,
2462	.hwcg_bit = 1,
2463	.clkr = {
2464	.enable_reg = 0x79004,
2465	.enable_mask = BIT(3),
2466	.hw.init = &(struct clk_init_data){
2467	.name = "gcc_ce1_ahb_clk",
2468	.ops = &clk_branch2_ops,
2469	},
2470	},
2471	};
2472
2473	static struct clk_branch gcc_ce1_axi_clk = {
2474	.halt_reg = 0x27008,
2475	.halt_check = BRANCH_HALT_VOTED,
2476	.clkr = {
2477	.enable_reg = 0x79004,
2478	.enable_mask = BIT(4),
2479	.hw.init = &(struct clk_init_data){
2480	.name = "gcc_ce1_axi_clk",
2481	.ops = &clk_branch2_ops,
2482	},
2483	},
2484	};
2485
2486	static struct clk_branch gcc_ce1_clk = {
2487	.halt_reg = 0x27004,
2488	.halt_check = BRANCH_HALT_VOTED,
2489	.clkr = {
2490	.enable_reg = 0x79004,
2491	.enable_mask = BIT(5),
2492	.hw.init = &(struct clk_init_data){
2493	.name = "gcc_ce1_clk",
2494	.ops = &clk_branch2_ops,
2495	},
2496	},
2497	};
2498
2499	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2500	.halt_reg = 0x1a084,
2501	.halt_check = BRANCH_HALT,
2502	.clkr = {
2503	.enable_reg = 0x1a084,
2504	.enable_mask = BIT(0),
2505	.hw.init = &(struct clk_init_data){
2506	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2507	.parent_hws = (const struct clk_hw*[]){
2508	&gcc_usb30_prim_master_clk_src.clkr.hw,
2509	},
2510	.num_parents = 1,
2511	.flags = CLK_SET_RATE_PARENT,
2512	.ops = &clk_branch2_ops,
2513	},
2514	},
2515	};
2516
2517	static struct clk_branch gcc_cpuss_gnoc_clk = {
2518	.halt_reg = 0x2b004,
2519	.halt_check = BRANCH_HALT_VOTED,
2520	.hwcg_reg = 0x2b004,
2521	.hwcg_bit = 1,
2522	.clkr = {
2523	.enable_reg = 0x79004,
2524	.enable_mask = BIT(22),
2525	.hw.init = &(struct clk_init_data){
2526	.name = "gcc_cpuss_gnoc_clk",
2527	.flags = CLK_IS_CRITICAL,
2528	.ops = &clk_branch2_ops,
2529	},
2530	},
2531	};
2532
2533	static struct clk_branch gcc_disp_ahb_clk = {
2534	.halt_reg = 0x1700c,
2535	.halt_check = BRANCH_HALT,
2536	.hwcg_reg = 0x1700c,
2537	.hwcg_bit = 1,
2538	.clkr = {
2539	.enable_reg = 0x1700c,
2540	.enable_mask = BIT(0),
2541	.hw.init = &(struct clk_init_data){
2542	.name = "gcc_disp_ahb_clk",
2543	.flags = CLK_IS_CRITICAL,
2544	.ops = &clk_branch2_ops,
2545	},
2546	},
2547	};
2548
2549	static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2550	.halt_check = BRANCH_HALT_DELAY,
2551	.clkr = {
2552	.enable_reg = 0x79004,
2553	.enable_mask = BIT(20),
2554	.hw.init = &(struct clk_init_data){
2555	.name = "gcc_disp_gpll0_div_clk_src",
2556	.parent_hws = (const struct clk_hw*[]){
2557	&gpll0_out_early.clkr.hw,
2558	},
2559	.num_parents = 1,
2560	.ops = &clk_branch2_ops,
2561	},
2562	},
2563	};
2564
2565	static struct clk_branch gcc_disp_hf_axi_clk = {
2566	.halt_reg = 0x17020,
2567	.halt_check = BRANCH_HALT,
2568	.clkr = {
2569	.enable_reg = 0x17020,
2570	.enable_mask = BIT(0),
2571	.hw.init = &(struct clk_init_data){
2572	.name = "gcc_disp_hf_axi_clk",
2573	.ops = &clk_branch2_ops,
2574	},
2575	},
2576	};
2577
2578	static struct clk_branch gcc_disp_throttle_core_clk = {
2579	.halt_reg = 0x17064,
2580	.halt_check = BRANCH_HALT_VOTED,
2581	.clkr = {
2582	.enable_reg = 0x7900c,
2583	.enable_mask = BIT(5),
2584	.hw.init = &(struct clk_init_data){
2585	.name = "gcc_disp_throttle_core_clk",
2586	.ops = &clk_branch2_ops,
2587	},
2588	},
2589	};
2590
2591	static struct clk_branch gcc_disp_xo_clk = {
2592	.halt_reg = 0x1702c,
2593	.halt_check = BRANCH_HALT,
2594	.clkr = {
2595	.enable_reg = 0x1702c,
2596	.enable_mask = BIT(0),
2597	.hw.init = &(struct clk_init_data){
2598	.name = "gcc_disp_xo_clk",
2599	.flags = CLK_IS_CRITICAL,
2600	.ops = &clk_branch2_ops,
2601	},
2602	},
2603	};
2604
2605	static struct clk_branch gcc_gp1_clk = {
2606	.halt_reg = 0x4d000,
2607	.halt_check = BRANCH_HALT,
2608	.clkr = {
2609	.enable_reg = 0x4d000,
2610	.enable_mask = BIT(0),
2611	.hw.init = &(struct clk_init_data){
2612	.name = "gcc_gp1_clk",
2613	.parent_hws = (const struct clk_hw*[]){
2614	&gcc_gp1_clk_src.clkr.hw,
2615	},
2616	.num_parents = 1,
2617	.flags = CLK_SET_RATE_PARENT,
2618	.ops = &clk_branch2_ops,
2619	},
2620	},
2621	};
2622
2623	static struct clk_branch gcc_gp2_clk = {
2624	.halt_reg = 0x4e000,
2625	.halt_check = BRANCH_HALT,
2626	.clkr = {
2627	.enable_reg = 0x4e000,
2628	.enable_mask = BIT(0),
2629	.hw.init = &(struct clk_init_data){
2630	.name = "gcc_gp2_clk",
2631	.parent_hws = (const struct clk_hw*[]){
2632	&gcc_gp2_clk_src.clkr.hw,
2633	},
2634	.num_parents = 1,
2635	.flags = CLK_SET_RATE_PARENT,
2636	.ops = &clk_branch2_ops,
2637	},
2638	},
2639	};
2640
2641	static struct clk_branch gcc_gp3_clk = {
2642	.halt_reg = 0x4f000,
2643	.halt_check = BRANCH_HALT,
2644	.clkr = {
2645	.enable_reg = 0x4f000,
2646	.enable_mask = BIT(0),
2647	.hw.init = &(struct clk_init_data){
2648	.name = "gcc_gp3_clk",
2649	.parent_hws = (const struct clk_hw*[]){
2650	&gcc_gp3_clk_src.clkr.hw,
2651	},
2652	.num_parents = 1,
2653	.flags = CLK_SET_RATE_PARENT,
2654	.ops = &clk_branch2_ops,
2655	},
2656	},
2657	};
2658
2659	static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2660	.halt_reg = 0x36004,
2661	.halt_check = BRANCH_HALT,
2662	.hwcg_reg = 0x36004,
2663	.hwcg_bit = 1,
2664	.clkr = {
2665	.enable_reg = 0x36004,
2666	.enable_mask = BIT(0),
2667	.hw.init = &(struct clk_init_data){
2668	.name = "gcc_gpu_cfg_ahb_clk",
2669	.flags = CLK_IS_CRITICAL,
2670	.ops = &clk_branch2_ops,
2671	},
2672	},
2673	};
2674
2675	static struct clk_branch gcc_gpu_gpll0_clk_src = {
2676	.halt_check = BRANCH_HALT_DELAY,
2677	.clkr = {
2678	.enable_reg = 0x79004,
2679	.enable_mask = BIT(15),
2680	.hw.init = &(struct clk_init_data){
2681	.name = "gcc_gpu_gpll0_clk_src",
2682	.parent_hws = (const struct clk_hw*[]){
2683	&gpll0_out_early.clkr.hw,
2684	},
2685	.num_parents = 1,
2686	.ops = &clk_branch2_ops,
2687	},
2688	},
2689	};
2690
2691	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2692	.halt_check = BRANCH_HALT_DELAY,
2693	.clkr = {
2694	.enable_reg = 0x79004,
2695	.enable_mask = BIT(16),
2696	.hw.init = &(struct clk_init_data){
2697	.name = "gcc_gpu_gpll0_div_clk_src",
2698	.parent_hws = (const struct clk_hw*[]){
2699	&gpll0_out_aux2.hw,
2700	},
2701	.num_parents = 1,
2702	.ops = &clk_branch2_ops,
2703	},
2704	},
2705	};
2706
2707	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2708	.halt_reg = 0x3600c,
2709	.halt_check = BRANCH_VOTED,
2710	.clkr = {
2711	.enable_reg = 0x3600c,
2712	.enable_mask = BIT(0),
2713	.hw.init = &(struct clk_init_data){
2714	.name = "gcc_gpu_memnoc_gfx_clk",
2715	.ops = &clk_branch2_ops,
2716	},
2717	},
2718	};
2719
2720	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2721	.halt_reg = 0x36018,
2722	.halt_check = BRANCH_HALT,
2723	.clkr = {
2724	.enable_reg = 0x36018,
2725	.enable_mask = BIT(0),
2726	.hw.init = &(struct clk_init_data){
2727	.name = "gcc_gpu_snoc_dvm_gfx_clk",
2728	.ops = &clk_branch2_ops,
2729	},
2730	},
2731	};
2732
2733	static struct clk_branch gcc_gpu_throttle_core_clk = {
2734	.halt_reg = 0x36048,
2735	.halt_check = BRANCH_HALT_VOTED,
2736	.clkr = {
2737	.enable_reg = 0x79004,
2738	.enable_mask = BIT(31),
2739	.hw.init = &(struct clk_init_data){
2740	.name = "gcc_gpu_throttle_core_clk",
2741	.ops = &clk_branch2_ops,
2742	},
2743	},
2744	};
2745
2746	static struct clk_branch gcc_gpu_throttle_xo_clk = {
2747	.halt_reg = 0x36044,
2748	.halt_check = BRANCH_HALT,
2749	.clkr = {
2750	.enable_reg = 0x36044,
2751	.enable_mask = BIT(0),
2752	.hw.init = &(struct clk_init_data){
2753	.name = "gcc_gpu_throttle_xo_clk",
2754	.ops = &clk_branch2_ops,
2755	},
2756	},
2757	};
2758
2759	static struct clk_branch gcc_mss_vs_clk = {
2760	.halt_reg = 0x42048,
2761	.halt_check = BRANCH_HALT,
2762	.clkr = {
2763	.enable_reg = 0x42048,
2764	.enable_mask = BIT(0),
2765	.hw.init = &(struct clk_init_data){
2766	.name = "gcc_mss_vs_clk",
2767	.parent_hws = (const struct clk_hw*[]){
2768	&gcc_vsensor_clk_src.clkr.hw,
2769	},
2770	.num_parents = 1,
2771	.flags = CLK_SET_RATE_PARENT,
2772	.ops = &clk_branch2_ops,
2773	},
2774	},
2775	};
2776
2777	static struct clk_branch gcc_pdm2_clk = {
2778	.halt_reg = 0x2000c,
2779	.halt_check = BRANCH_HALT,
2780	.clkr = {
2781	.enable_reg = 0x2000c,
2782	.enable_mask = BIT(0),
2783	.hw.init = &(struct clk_init_data){
2784	.name = "gcc_pdm2_clk",
2785	.parent_hws = (const struct clk_hw*[]){
2786	&gcc_pdm2_clk_src.clkr.hw,
2787	},
2788	.num_parents = 1,
2789	.flags = CLK_SET_RATE_PARENT,
2790	.ops = &clk_branch2_ops,
2791	},
2792	},
2793	};
2794
2795	static struct clk_branch gcc_pdm_ahb_clk = {
2796	.halt_reg = 0x20004,
2797	.halt_check = BRANCH_HALT,
2798	.hwcg_reg = 0x20004,
2799	.hwcg_bit = 1,
2800	.clkr = {
2801	.enable_reg = 0x20004,
2802	.enable_mask = BIT(0),
2803	.hw.init = &(struct clk_init_data){
2804	.name = "gcc_pdm_ahb_clk",
2805	.ops = &clk_branch2_ops,
2806	},
2807	},
2808	};
2809
2810	static struct clk_branch gcc_pdm_xo4_clk = {
2811	.halt_reg = 0x20008,
2812	.halt_check = BRANCH_HALT,
2813	.clkr = {
2814	.enable_reg = 0x20008,
2815	.enable_mask = BIT(0),
2816	.hw.init = &(struct clk_init_data){
2817	.name = "gcc_pdm_xo4_clk",
2818	.ops = &clk_branch2_ops,
2819	},
2820	},
2821	};
2822
2823	static struct clk_branch gcc_prng_ahb_clk = {
2824	.halt_reg = 0x21004,
2825	.halt_check = BRANCH_HALT_VOTED,
2826	.hwcg_reg = 0x21004,
2827	.hwcg_bit = 1,
2828	.clkr = {
2829	.enable_reg = 0x79004,
2830	.enable_mask = BIT(13),
2831	.hw.init = &(struct clk_init_data){
2832	.name = "gcc_prng_ahb_clk",
2833	.ops = &clk_branch2_ops,
2834	},
2835	},
2836	};
2837
2838	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2839	.halt_reg = 0x17014,
2840	.halt_check = BRANCH_HALT,
2841	.hwcg_reg = 0x17014,
2842	.hwcg_bit = 1,
2843	.clkr = {
2844	.enable_reg = 0x7900c,
2845	.enable_mask = BIT(0),
2846	.hw.init = &(struct clk_init_data){
2847	.name = "gcc_qmip_camera_nrt_ahb_clk",
2848	.ops = &clk_branch2_ops,
2849	},
2850	},
2851	};
2852
2853	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2854	.halt_reg = 0x17060,
2855	.halt_check = BRANCH_HALT_VOTED,
2856	.hwcg_reg = 0x17060,
2857	.hwcg_bit = 1,
2858	.clkr = {
2859	.enable_reg = 0x7900c,
2860	.enable_mask = BIT(2),
2861	.hw.init = &(struct clk_init_data){
2862	.name = "gcc_qmip_camera_rt_ahb_clk",
2863	.ops = &clk_branch2_ops,
2864	},
2865	},
2866	};
2867
2868	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2869	.halt_reg = 0x17018,
2870	.halt_check = BRANCH_HALT,
2871	.hwcg_reg = 0x17018,
2872	.hwcg_bit = 1,
2873	.clkr = {
2874	.enable_reg = 0x7900c,
2875	.enable_mask = BIT(1),
2876	.hw.init = &(struct clk_init_data){
2877	.name = "gcc_qmip_disp_ahb_clk",
2878	.ops = &clk_branch2_ops,
2879	},
2880	},
2881	};
2882
2883	static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2884	.halt_reg = 0x36040,
2885	.halt_check = BRANCH_HALT_VOTED,
2886	.hwcg_reg = 0x36040,
2887	.hwcg_bit = 1,
2888	.clkr = {
2889	.enable_reg = 0x7900c,
2890	.enable_mask = BIT(4),
2891	.hw.init = &(struct clk_init_data){
2892	.name = "gcc_qmip_gpu_cfg_ahb_clk",
2893	.ops = &clk_branch2_ops,
2894	},
2895	},
2896	};
2897
2898	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2899	.halt_reg = 0x17010,
2900	.halt_check = BRANCH_HALT,
2901	.hwcg_reg = 0x17010,
2902	.hwcg_bit = 1,
2903	.clkr = {
2904	.enable_reg = 0x79004,
2905	.enable_mask = BIT(25),
2906	.hw.init = &(struct clk_init_data){
2907	.name = "gcc_qmip_video_vcodec_ahb_clk",
2908	.ops = &clk_branch2_ops,
2909	},
2910	},
2911	};
2912
2913	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2914	.halt_reg = 0x1f014,
2915	.halt_check = BRANCH_HALT_VOTED,
2916	.clkr = {
2917	.enable_reg = 0x7900c,
2918	.enable_mask = BIT(9),
2919	.hw.init = &(struct clk_init_data){
2920	.name = "gcc_qupv3_wrap0_core_2x_clk",
2921	.ops = &clk_branch2_ops,
2922	},
2923	},
2924	};
2925
2926	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2927	.halt_reg = 0x1f00c,
2928	.halt_check = BRANCH_HALT_VOTED,
2929	.clkr = {
2930	.enable_reg = 0x7900c,
2931	.enable_mask = BIT(8),
2932	.hw.init = &(struct clk_init_data){
2933	.name = "gcc_qupv3_wrap0_core_clk",
2934	.ops = &clk_branch2_ops,
2935	},
2936	},
2937	};
2938
2939	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2940	.halt_reg = 0x1f144,
2941	.halt_check = BRANCH_HALT_VOTED,
2942	.clkr = {
2943	.enable_reg = 0x7900c,
2944	.enable_mask = BIT(10),
2945	.hw.init = &(struct clk_init_data){
2946	.name = "gcc_qupv3_wrap0_s0_clk",
2947	.parent_hws = (const struct clk_hw*[]){
2948	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2949	},
2950	.num_parents = 1,
2951	.flags = CLK_SET_RATE_PARENT,
2952	.ops = &clk_branch2_ops,
2953	},
2954	},
2955	};
2956
2957	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2958	.halt_reg = 0x1f274,
2959	.halt_check = BRANCH_HALT_VOTED,
2960	.clkr = {
2961	.enable_reg = 0x7900c,
2962	.enable_mask = BIT(11),
2963	.hw.init = &(struct clk_init_data){
2964	.name = "gcc_qupv3_wrap0_s1_clk",
2965	.parent_hws = (const struct clk_hw*[]){
2966	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2967	},
2968	.num_parents = 1,
2969	.flags = CLK_SET_RATE_PARENT,
2970	.ops = &clk_branch2_ops,
2971	},
2972	},
2973	};
2974
2975	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2976	.halt_reg = 0x1f3a4,
2977	.halt_check = BRANCH_HALT_VOTED,
2978	.clkr = {
2979	.enable_reg = 0x7900c,
2980	.enable_mask = BIT(12),
2981	.hw.init = &(struct clk_init_data){
2982	.name = "gcc_qupv3_wrap0_s2_clk",
2983	.parent_hws = (const struct clk_hw*[]){
2984	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2985	},
2986	.num_parents = 1,
2987	.flags = CLK_SET_RATE_PARENT,
2988	.ops = &clk_branch2_ops,
2989	},
2990	},
2991	};
2992
2993	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2994	.halt_reg = 0x1f4d4,
2995	.halt_check = BRANCH_HALT_VOTED,
2996	.clkr = {
2997	.enable_reg = 0x7900c,
2998	.enable_mask = BIT(13),
2999	.hw.init = &(struct clk_init_data){
3000	.name = "gcc_qupv3_wrap0_s3_clk",
3001	.parent_hws = (const struct clk_hw*[]){
3002	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
3003	},
3004	.num_parents = 1,
3005	.flags = CLK_SET_RATE_PARENT,
3006	.ops = &clk_branch2_ops,
3007	},
3008	},
3009	};
3010
3011	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
3012	.halt_reg = 0x1f604,
3013	.halt_check = BRANCH_HALT_VOTED,
3014	.clkr = {
3015	.enable_reg = 0x7900c,
3016	.enable_mask = BIT(14),
3017	.hw.init = &(struct clk_init_data){
3018	.name = "gcc_qupv3_wrap0_s4_clk",
3019	.parent_hws = (const struct clk_hw*[]){
3020	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
3021	},
3022	.num_parents = 1,
3023	.flags = CLK_SET_RATE_PARENT,
3024	.ops = &clk_branch2_ops,
3025	},
3026	},
3027	};
3028
3029	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
3030	.halt_reg = 0x1f734,
3031	.halt_check = BRANCH_HALT_VOTED,
3032	.clkr = {
3033	.enable_reg = 0x7900c,
3034	.enable_mask = BIT(15),
3035	.hw.init = &(struct clk_init_data){
3036	.name = "gcc_qupv3_wrap0_s5_clk",
3037	.parent_hws = (const struct clk_hw*[]){
3038	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
3039	},
3040	.num_parents = 1,
3041	.flags = CLK_SET_RATE_PARENT,
3042	.ops = &clk_branch2_ops,
3043	},
3044	},
3045	};
3046
3047	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
3048	.halt_reg = 0x39014,
3049	.halt_check = BRANCH_HALT_VOTED,
3050	.clkr = {
3051	.enable_reg = 0x7900c,
3052	.enable_mask = BIT(18),
3053	.hw.init = &(struct clk_init_data){
3054	.name = "gcc_qupv3_wrap1_core_2x_clk",
3055	.ops = &clk_branch2_ops,
3056	},
3057	},
3058	};
3059
3060	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
3061	.halt_reg = 0x3900c,
3062	.halt_check = BRANCH_HALT_VOTED,
3063	.clkr = {
3064	.enable_reg = 0x7900c,
3065	.enable_mask = BIT(19),
3066	.hw.init = &(struct clk_init_data){
3067	.name = "gcc_qupv3_wrap1_core_clk",
3068	.ops = &clk_branch2_ops,
3069	},
3070	},
3071	};
3072
3073	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
3074	.halt_reg = 0x39144,
3075	.halt_check = BRANCH_HALT_VOTED,
3076	.clkr = {
3077	.enable_reg = 0x7900c,
3078	.enable_mask = BIT(22),
3079	.hw.init = &(struct clk_init_data){
3080	.name = "gcc_qupv3_wrap1_s0_clk",
3081	.parent_hws = (const struct clk_hw*[]){
3082	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
3083	},
3084	.num_parents = 1,
3085	.flags = CLK_SET_RATE_PARENT,
3086	.ops = &clk_branch2_ops,
3087	},
3088	},
3089	};
3090
3091	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
3092	.halt_reg = 0x39274,
3093	.halt_check = BRANCH_HALT_VOTED,
3094	.clkr = {
3095	.enable_reg = 0x7900c,
3096	.enable_mask = BIT(23),
3097	.hw.init = &(struct clk_init_data){
3098	.name = "gcc_qupv3_wrap1_s1_clk",
3099	.parent_hws = (const struct clk_hw*[]){
3100	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
3101	},
3102	.num_parents = 1,
3103	.flags = CLK_SET_RATE_PARENT,
3104	.ops = &clk_branch2_ops,
3105	},
3106	},
3107	};
3108
3109	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
3110	.halt_reg = 0x393a4,
3111	.halt_check = BRANCH_HALT_VOTED,
3112	.clkr = {
3113	.enable_reg = 0x7900c,
3114	.enable_mask = BIT(24),
3115	.hw.init = &(struct clk_init_data){
3116	.name = "gcc_qupv3_wrap1_s2_clk",
3117	.parent_hws = (const struct clk_hw*[]){
3118	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
3119	},
3120	.num_parents = 1,
3121	.flags = CLK_SET_RATE_PARENT,
3122	.ops = &clk_branch2_ops,
3123	},
3124	},
3125	};
3126
3127	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
3128	.halt_reg = 0x394d4,
3129	.halt_check = BRANCH_HALT_VOTED,
3130	.clkr = {
3131	.enable_reg = 0x7900c,
3132	.enable_mask = BIT(25),
3133	.hw.init = &(struct clk_init_data){
3134	.name = "gcc_qupv3_wrap1_s3_clk",
3135	.parent_hws = (const struct clk_hw*[]){
3136	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
3137	},
3138	.num_parents = 1,
3139	.flags = CLK_SET_RATE_PARENT,
3140	.ops = &clk_branch2_ops,
3141	},
3142	},
3143	};
3144
3145	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
3146	.halt_reg = 0x39604,
3147	.halt_check = BRANCH_HALT_VOTED,
3148	.clkr = {
3149	.enable_reg = 0x7900c,
3150	.enable_mask = BIT(26),
3151	.hw.init = &(struct clk_init_data){
3152	.name = "gcc_qupv3_wrap1_s4_clk",
3153	.parent_hws = (const struct clk_hw*[]){
3154	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
3155	},
3156	.num_parents = 1,
3157	.flags = CLK_SET_RATE_PARENT,
3158	.ops = &clk_branch2_ops,
3159	},
3160	},
3161	};
3162
3163	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
3164	.halt_reg = 0x39734,
3165	.halt_check = BRANCH_HALT_VOTED,
3166	.clkr = {
3167	.enable_reg = 0x7900c,
3168	.enable_mask = BIT(27),
3169	.hw.init = &(struct clk_init_data){
3170	.name = "gcc_qupv3_wrap1_s5_clk",
3171	.parent_hws = (const struct clk_hw*[]){
3172	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
3173	},
3174	.num_parents = 1,
3175	.flags = CLK_SET_RATE_PARENT,
3176	.ops = &clk_branch2_ops,
3177	},
3178	},
3179	};
3180
3181	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3182	.halt_reg = 0x1f004,
3183	.halt_check = BRANCH_HALT_VOTED,
3184	.clkr = {
3185	.enable_reg = 0x7900c,
3186	.enable_mask = BIT(6),
3187	.hw.init = &(struct clk_init_data){
3188	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
3189	.ops = &clk_branch2_ops,
3190	},
3191	},
3192	};
3193
3194	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3195	.halt_reg = 0x1f008,
3196	.halt_check = BRANCH_HALT_VOTED,
3197	.hwcg_reg = 0x1f008,
3198	.hwcg_bit = 1,
3199	.clkr = {
3200	.enable_reg = 0x7900c,
3201	.enable_mask = BIT(7),
3202	.hw.init = &(struct clk_init_data){
3203	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
3204	.ops = &clk_branch2_ops,
3205	},
3206	},
3207	};
3208
3209	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3210	.halt_reg = 0x39004,
3211	.halt_check = BRANCH_HALT_VOTED,
3212	.clkr = {
3213	.enable_reg = 0x7900c,
3214	.enable_mask = BIT(20),
3215	.hw.init = &(struct clk_init_data){
3216	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
3217	.ops = &clk_branch2_ops,
3218	},
3219	},
3220	};
3221
3222	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3223	.halt_reg = 0x39008,
3224	.halt_check = BRANCH_HALT_VOTED,
3225	.hwcg_reg = 0x39008,
3226	.hwcg_bit = 1,
3227	.clkr = {
3228	.enable_reg = 0x7900c,
3229	.enable_mask = BIT(21),
3230	.hw.init = &(struct clk_init_data){
3231	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
3232	.ops = &clk_branch2_ops,
3233	},
3234	},
3235	};
3236
3237	static struct clk_branch gcc_sdcc1_ahb_clk = {
3238	.halt_reg = 0x38008,
3239	.halt_check = BRANCH_HALT,
3240	.clkr = {
3241	.enable_reg = 0x38008,
3242	.enable_mask = BIT(0),
3243	.hw.init = &(struct clk_init_data){
3244	.name = "gcc_sdcc1_ahb_clk",
3245	.ops = &clk_branch2_ops,
3246	},
3247	},
3248	};
3249
3250	static struct clk_branch gcc_sdcc1_apps_clk = {
3251	.halt_reg = 0x38004,
3252	.halt_check = BRANCH_HALT,
3253	.clkr = {
3254	.enable_reg = 0x38004,
3255	.enable_mask = BIT(0),
3256	.hw.init = &(struct clk_init_data){
3257	.name = "gcc_sdcc1_apps_clk",
3258	.parent_hws = (const struct clk_hw*[]){
3259	&gcc_sdcc1_apps_clk_src.clkr.hw,
3260	},
3261	.num_parents = 1,
3262	.flags = CLK_SET_RATE_PARENT,
3263	.ops = &clk_branch2_ops,
3264	},
3265	},
3266	};
3267
3268	static struct clk_branch gcc_sdcc1_ice_core_clk = {
3269	.halt_reg = 0x3800c,
3270	.halt_check = BRANCH_HALT,
3271	.clkr = {
3272	.enable_reg = 0x3800c,
3273	.enable_mask = BIT(0),
3274	.hw.init = &(struct clk_init_data){
3275	.name = "gcc_sdcc1_ice_core_clk",
3276	.parent_hws = (const struct clk_hw*[]){
3277	&gcc_sdcc1_ice_core_clk_src.clkr.hw,
3278	},
3279	.num_parents = 1,
3280	.flags = CLK_SET_RATE_PARENT,
3281	.ops = &clk_branch2_ops,
3282	},
3283	},
3284	};
3285
3286	static struct clk_branch gcc_sdcc2_ahb_clk = {
3287	.halt_reg = 0x1e008,
3288	.halt_check = BRANCH_HALT,
3289	.clkr = {
3290	.enable_reg = 0x1e008,
3291	.enable_mask = BIT(0),
3292	.hw.init = &(struct clk_init_data){
3293	.name = "gcc_sdcc2_ahb_clk",
3294	.ops = &clk_branch2_ops,
3295	},
3296	},
3297	};
3298
3299	static struct clk_branch gcc_sdcc2_apps_clk = {
3300	.halt_reg = 0x1e004,
3301	.halt_check = BRANCH_HALT,
3302	.clkr = {
3303	.enable_reg = 0x1e004,
3304	.enable_mask = BIT(0),
3305	.hw.init = &(struct clk_init_data){
3306	.name = "gcc_sdcc2_apps_clk",
3307	.parent_hws = (const struct clk_hw*[]){
3308	&gcc_sdcc2_apps_clk_src.clkr.hw,
3309	},
3310	.num_parents = 1,
3311	.flags = CLK_SET_RATE_PARENT,
3312	.ops = &clk_branch2_ops,
3313	},
3314	},
3315	};
3316
3317	static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = {
3318	.halt_reg = 0x1050c,
3319	.halt_check = BRANCH_HALT,
3320	.clkr = {
3321	.enable_reg = 0x1050c,
3322	.enable_mask = BIT(0),
3323	.hw.init = &(struct clk_init_data){
3324	.name = "gcc_sys_noc_compute_sf_axi_clk",
3325	.flags = CLK_IS_CRITICAL,
3326	.ops = &clk_branch2_ops,
3327	},
3328	},
3329	};
3330
3331	static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3332	.halt_reg = 0x2b06c,
3333	.halt_check = BRANCH_HALT_VOTED,
3334	.clkr = {
3335	.enable_reg = 0x79004,
3336	.enable_mask = BIT(0),
3337	.hw.init = &(struct clk_init_data){
3338	.name = "gcc_sys_noc_cpuss_ahb_clk",
3339	.flags = CLK_IS_CRITICAL,
3340	.ops = &clk_branch2_ops,
3341	},
3342	},
3343	};
3344
3345	static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
3346	.halt_reg = 0x45098,
3347	.halt_check = BRANCH_HALT,
3348	.clkr = {
3349	.enable_reg = 0x45098,
3350	.enable_mask = BIT(0),
3351	.hw.init = &(struct clk_init_data){
3352	.name = "gcc_sys_noc_ufs_phy_axi_clk",
3353	.parent_hws = (const struct clk_hw*[]){
3354	&gcc_ufs_phy_axi_clk_src.clkr.hw,
3355	},
3356	.num_parents = 1,
3357	.flags = CLK_SET_RATE_PARENT,
3358	.ops = &clk_branch2_ops,
3359	},
3360	},
3361	};
3362
3363	static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
3364	.halt_reg = 0x1a080,
3365	.halt_check = BRANCH_HALT,
3366	.clkr = {
3367	.enable_reg = 0x1a080,
3368	.enable_mask = BIT(0),
3369	.hw.init = &(struct clk_init_data){
3370	.name = "gcc_sys_noc_usb3_prim_axi_clk",
3371	.parent_hws = (const struct clk_hw*[]){
3372	&gcc_usb30_prim_master_clk_src.clkr.hw,
3373	},
3374	.num_parents = 1,
3375	.flags = CLK_SET_RATE_PARENT,
3376	.ops = &clk_branch2_ops,
3377	},
3378	},
3379	};
3380
3381	static struct clk_branch gcc_ufs_mem_clkref_clk = {
3382	.halt_reg = 0x8c000,
3383	.halt_check = BRANCH_HALT,
3384	.clkr = {
3385	.enable_reg = 0x8c000,
3386	.enable_mask = BIT(0),
3387	.hw.init = &(struct clk_init_data){
3388	.name = "gcc_ufs_mem_clkref_clk",
3389	.ops = &clk_branch2_ops,
3390	},
3391	},
3392	};
3393
3394	static struct clk_branch gcc_ufs_phy_ahb_clk = {
3395	.halt_reg = 0x45014,
3396	.halt_check = BRANCH_HALT,
3397	.hwcg_reg = 0x45014,
3398	.hwcg_bit = 1,
3399	.clkr = {
3400	.enable_reg = 0x45014,
3401	.enable_mask = BIT(0),
3402	.hw.init = &(struct clk_init_data){
3403	.name = "gcc_ufs_phy_ahb_clk",
3404	.ops = &clk_branch2_ops,
3405	},
3406	},
3407	};
3408
3409	static struct clk_branch gcc_ufs_phy_axi_clk = {
3410	.halt_reg = 0x45010,
3411	.halt_check = BRANCH_HALT,
3412	.hwcg_reg = 0x45010,
3413	.hwcg_bit = 1,
3414	.clkr = {
3415	.enable_reg = 0x45010,
3416	.enable_mask = BIT(0),
3417	.hw.init = &(struct clk_init_data){
3418	.name = "gcc_ufs_phy_axi_clk",
3419	.parent_hws = (const struct clk_hw*[]){
3420	&gcc_ufs_phy_axi_clk_src.clkr.hw,
3421	},
3422	.num_parents = 1,
3423	.flags = CLK_SET_RATE_PARENT,
3424	.ops = &clk_branch2_ops,
3425	},
3426	},
3427	};
3428
3429	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3430	.halt_reg = 0x45044,
3431	.halt_check = BRANCH_HALT,
3432	.hwcg_reg = 0x45044,
3433	.hwcg_bit = 1,
3434	.clkr = {
3435	.enable_reg = 0x45044,
3436	.enable_mask = BIT(0),
3437	.hw.init = &(struct clk_init_data){
3438	.name = "gcc_ufs_phy_ice_core_clk",
3439	.parent_hws = (const struct clk_hw*[]){
3440	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3441	},
3442	.num_parents = 1,
3443	.flags = CLK_SET_RATE_PARENT,
3444	.ops = &clk_branch2_ops,
3445	},
3446	},
3447	};
3448
3449	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3450	.halt_reg = 0x45078,
3451	.halt_check = BRANCH_HALT,
3452	.hwcg_reg = 0x45078,
3453	.hwcg_bit = 1,
3454	.clkr = {
3455	.enable_reg = 0x45078,
3456	.enable_mask = BIT(0),
3457	.hw.init = &(struct clk_init_data){
3458	.name = "gcc_ufs_phy_phy_aux_clk",
3459	.parent_hws = (const struct clk_hw*[]){
3460	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3461	},
3462	.num_parents = 1,
3463	.flags = CLK_SET_RATE_PARENT,
3464	.ops = &clk_branch2_ops,
3465	},
3466	},
3467	};
3468
3469	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3470	.halt_reg = 0x4501c,
3471	.halt_check = BRANCH_HALT_SKIP,
3472	.clkr = {
3473	.enable_reg = 0x4501c,
3474	.enable_mask = BIT(0),
3475	.hw.init = &(struct clk_init_data){
3476	.name = "gcc_ufs_phy_rx_symbol_0_clk",
3477	.ops = &clk_branch2_ops,
3478	},
3479	},
3480	};
3481
3482	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3483	.halt_reg = 0x45018,
3484	.halt_check = BRANCH_HALT_SKIP,
3485	.clkr = {
3486	.enable_reg = 0x45018,
3487	.enable_mask = BIT(0),
3488	.hw.init = &(struct clk_init_data){
3489	.name = "gcc_ufs_phy_tx_symbol_0_clk",
3490	.ops = &clk_branch2_ops,
3491	},
3492	},
3493	};
3494
3495	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3496	.halt_reg = 0x45040,
3497	.halt_check = BRANCH_HALT,
3498	.hwcg_reg = 0x45040,
3499	.hwcg_bit = 1,
3500	.clkr = {
3501	.enable_reg = 0x45040,
3502	.enable_mask = BIT(0),
3503	.hw.init = &(struct clk_init_data){
3504	.name = "gcc_ufs_phy_unipro_core_clk",
3505	.parent_hws = (const struct clk_hw*[]){
3506	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3507	},
3508	.num_parents = 1,
3509	.flags = CLK_SET_RATE_PARENT,
3510	.ops = &clk_branch2_ops,
3511	},
3512	},
3513	};
3514
3515	static struct clk_branch gcc_usb30_prim_master_clk = {
3516	.halt_reg = 0x1a010,
3517	.halt_check = BRANCH_HALT,
3518	.clkr = {
3519	.enable_reg = 0x1a010,
3520	.enable_mask = BIT(0),
3521	.hw.init = &(struct clk_init_data){
3522	.name = "gcc_usb30_prim_master_clk",
3523	.parent_hws = (const struct clk_hw*[]){
3524	&gcc_usb30_prim_master_clk_src.clkr.hw,
3525	},
3526	.num_parents = 1,
3527	.flags = CLK_SET_RATE_PARENT,
3528	.ops = &clk_branch2_ops,
3529	},
3530	},
3531	};
3532
3533	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3534	.halt_reg = 0x1a018,
3535	.halt_check = BRANCH_HALT,
3536	.clkr = {
3537	.enable_reg = 0x1a018,
3538	.enable_mask = BIT(0),
3539	.hw.init = &(struct clk_init_data){
3540	.name = "gcc_usb30_prim_mock_utmi_clk",
3541	.parent_hws = (const struct clk_hw*[]){
3542	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3543	},
3544	.num_parents = 1,
3545	.flags = CLK_SET_RATE_PARENT,
3546	.ops = &clk_branch2_ops,
3547	},
3548	},
3549	};
3550
3551	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3552	.halt_reg = 0x1a014,
3553	.halt_check = BRANCH_HALT,
3554	.clkr = {
3555	.enable_reg = 0x1a014,
3556	.enable_mask = BIT(0),
3557	.hw.init = &(struct clk_init_data){
3558	.name = "gcc_usb30_prim_sleep_clk",
3559	.ops = &clk_branch2_ops,
3560	},
3561	},
3562	};
3563
3564	static struct clk_branch gcc_usb3_prim_clkref_clk = {
3565	.halt_reg = 0x80278,
3566	.halt_check = BRANCH_HALT,
3567	.clkr = {
3568	.enable_reg = 0x80278,
3569	.enable_mask = BIT(0),
3570	.hw.init = &(struct clk_init_data){
3571	.name = "gcc_usb3_prim_clkref_clk",
3572	.ops = &clk_branch2_ops,
3573	},
3574	},
3575	};
3576
3577	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3578	.halt_reg = 0x1a054,
3579	.halt_check = BRANCH_HALT,
3580	.clkr = {
3581	.enable_reg = 0x1a054,
3582	.enable_mask = BIT(0),
3583	.hw.init = &(struct clk_init_data){
3584	.name = "gcc_usb3_prim_phy_com_aux_clk",
3585	.parent_hws = (const struct clk_hw*[]){
3586	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3587	},
3588	.num_parents = 1,
3589	.flags = CLK_SET_RATE_PARENT,
3590	.ops = &clk_branch2_ops,
3591	},
3592	},
3593	};
3594
3595	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3596	.halt_check = BRANCH_HALT_SKIP,
3597	.clkr = {
3598	.enable_reg = 0x1a058,
3599	.enable_mask = BIT(0),
3600	.hw.init = &(struct clk_init_data){
3601	.name = "gcc_usb3_prim_phy_pipe_clk",
3602	.ops = &clk_branch2_ops,
3603	},
3604	},
3605	};
3606
3607	static struct clk_branch gcc_vdda_vs_clk = {
3608	.halt_reg = 0x4200c,
3609	.halt_check = BRANCH_HALT,
3610	.clkr = {
3611	.enable_reg = 0x4200c,
3612	.enable_mask = BIT(0),
3613	.hw.init = &(struct clk_init_data){
3614	.name = "gcc_vdda_vs_clk",
3615	.parent_hws = (const struct clk_hw*[]){
3616	&gcc_vsensor_clk_src.clkr.hw,
3617	},
3618	.num_parents = 1,
3619	.flags = CLK_SET_RATE_PARENT,
3620	.ops = &clk_branch2_ops,
3621	},
3622	},
3623	};
3624
3625	static struct clk_branch gcc_vddcx_vs_clk = {
3626	.halt_reg = 0x42004,
3627	.halt_check = BRANCH_HALT,
3628	.clkr = {
3629	.enable_reg = 0x42004,
3630	.enable_mask = BIT(0),
3631	.hw.init = &(struct clk_init_data){
3632	.name = "gcc_vddcx_vs_clk",
3633	.parent_hws = (const struct clk_hw*[]){
3634	&gcc_vsensor_clk_src.clkr.hw,
3635	},
3636	.num_parents = 1,
3637	.flags = CLK_SET_RATE_PARENT,
3638	.ops = &clk_branch2_ops,
3639	},
3640	},
3641	};
3642
3643	static struct clk_branch gcc_vddmx_vs_clk = {
3644	.halt_reg = 0x42008,
3645	.halt_check = BRANCH_HALT,
3646	.clkr = {
3647	.enable_reg = 0x42008,
3648	.enable_mask = BIT(0),
3649	.hw.init = &(struct clk_init_data){
3650	.name = "gcc_vddmx_vs_clk",
3651	.parent_hws = (const struct clk_hw*[]){
3652	&gcc_vsensor_clk_src.clkr.hw,
3653	},
3654	.num_parents = 1,
3655	.flags = CLK_SET_RATE_PARENT,
3656	.ops = &clk_branch2_ops,
3657	},
3658	},
3659	};
3660
3661	static struct clk_branch gcc_video_ahb_clk = {
3662	.halt_reg = 0x17004,
3663	.halt_check = BRANCH_HALT,
3664	.hwcg_reg = 0x17004,
3665	.hwcg_bit = 1,
3666	.clkr = {
3667	.enable_reg = 0x17004,
3668	.enable_mask = BIT(0),
3669	.hw.init = &(struct clk_init_data){
3670	.name = "gcc_video_ahb_clk",
3671	.flags = CLK_IS_CRITICAL,
3672	.ops = &clk_branch2_ops,
3673	},
3674	},
3675	};
3676
3677	static struct clk_branch gcc_video_axi0_clk = {
3678	.halt_reg = 0x1701c,
3679	.halt_check = BRANCH_HALT,
3680	.clkr = {
3681	.enable_reg = 0x1701c,
3682	.enable_mask = BIT(0),
3683	.hw.init = &(struct clk_init_data){
3684	.name = "gcc_video_axi0_clk",
3685	.ops = &clk_branch2_ops,
3686	},
3687	},
3688	};
3689
3690	static struct clk_branch gcc_video_throttle_core_clk = {
3691	.halt_reg = 0x17068,
3692	.halt_check = BRANCH_HALT_VOTED,
3693	.clkr = {
3694	.enable_reg = 0x79004,
3695	.enable_mask = BIT(28),
3696	.hw.init = &(struct clk_init_data){
3697	.name = "gcc_video_throttle_core_clk",
3698	.ops = &clk_branch2_ops,
3699	},
3700	},
3701	};
3702
3703	static struct clk_branch gcc_video_xo_clk = {
3704	.halt_reg = 0x17024,
3705	.halt_check = BRANCH_HALT,
3706	.clkr = {
3707	.enable_reg = 0x17024,
3708	.enable_mask = BIT(0),
3709	.hw.init = &(struct clk_init_data){
3710	.name = "gcc_video_xo_clk",
3711	.flags = CLK_IS_CRITICAL,
3712	.ops = &clk_branch2_ops,
3713	},
3714	},
3715	};
3716
3717	static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3718	.halt_reg = 0x42014,
3719	.halt_check = BRANCH_HALT,
3720	.hwcg_reg = 0x42014,
3721	.hwcg_bit = 1,
3722	.clkr = {
3723	.enable_reg = 0x42014,
3724	.enable_mask = BIT(0),
3725	.hw.init = &(struct clk_init_data){
3726	.name = "gcc_vs_ctrl_ahb_clk",
3727	.ops = &clk_branch2_ops,
3728	},
3729	},
3730	};
3731
3732	static struct clk_branch gcc_vs_ctrl_clk = {
3733	.halt_reg = 0x42010,
3734	.halt_check = BRANCH_HALT,
3735	.clkr = {
3736	.enable_reg = 0x42010,
3737	.enable_mask = BIT(0),
3738	.hw.init = &(struct clk_init_data){
3739	.name = "gcc_vs_ctrl_clk",
3740	.parent_hws = (const struct clk_hw*[]){
3741	&gcc_vs_ctrl_clk_src.clkr.hw,
3742	},
3743	.num_parents = 1,
3744	.flags = CLK_SET_RATE_PARENT,
3745	.ops = &clk_branch2_ops,
3746	},
3747	},
3748	};
3749
3750	static struct clk_branch gcc_wcss_vs_clk = {
3751	.halt_reg = 0x42050,
3752	.halt_check = BRANCH_HALT,
3753	.clkr = {
3754	.enable_reg = 0x42050,
3755	.enable_mask = BIT(0),
3756	.hw.init = &(struct clk_init_data){
3757	.name = "gcc_wcss_vs_clk",
3758	.parent_hws = (const struct clk_hw*[]){
3759	&gcc_vsensor_clk_src.clkr.hw,
3760	},
3761	.num_parents = 1,
3762	.flags = CLK_SET_RATE_PARENT,
3763	.ops = &clk_branch2_ops,
3764	},
3765	},
3766	};
3767
3768	static struct gdsc usb30_prim_gdsc = {
3769	.gdscr = 0x1a004,
3770	.pd = {
3771	.name = "usb30_prim_gdsc",
3772	},
3773	.pwrsts = PWRSTS_OFF_ON,
3774	};
3775
3776	static struct gdsc ufs_phy_gdsc = {
3777	.gdscr = 0x45004,
3778	.pd = {
3779	.name = "ufs_phy_gdsc",
3780	},
3781	.pwrsts = PWRSTS_OFF_ON,
3782	};
3783
3784	static struct gdsc camss_vfe0_gdsc = {
3785	.gdscr = 0x54004,
3786	.pd = {
3787	.name = "camss_vfe0_gdsc",
3788	},
3789	.pwrsts = PWRSTS_OFF_ON,
3790	};
3791
3792	static struct gdsc camss_vfe1_gdsc = {
3793	.gdscr = 0x5403c,
3794	.pd = {
3795	.name = "camss_vfe1_gdsc",
3796	},
3797	.pwrsts = PWRSTS_OFF_ON,
3798	};
3799
3800	static struct gdsc camss_top_gdsc = {
3801	.gdscr = 0x5607c,
3802	.pd = {
3803	.name = "camss_top_gdsc",
3804	},
3805	.pwrsts = PWRSTS_OFF_ON,
3806	};
3807
3808	static struct gdsc cam_cpp_gdsc = {
3809	.gdscr = 0x560bc,
3810	.pd = {
3811	.name = "cam_cpp_gdsc",
3812	},
3813	.pwrsts = PWRSTS_OFF_ON,
3814	};
3815
3816	static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3817	.gdscr = 0x7d060,
3818	.pd = {
3819	.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3820	},
3821	.pwrsts = PWRSTS_OFF_ON,
3822	.flags = VOTABLE,
3823	};
3824
3825	static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3826	.gdscr = 0x80074,
3827	.pd = {
3828	.name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
3829	},
3830	.pwrsts = PWRSTS_OFF_ON,
3831	.flags = VOTABLE,
3832	};
3833
3834	static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3835	.gdscr = 0x80084,
3836	.pd = {
3837	.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
3838	},
3839	.pwrsts = PWRSTS_OFF_ON,
3840	.flags = VOTABLE,
3841	};
3842
3843
3844	static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3845	.gdscr = 0x80094,
3846	.pd = {
3847	.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3848	},
3849	.pwrsts = PWRSTS_OFF_ON,
3850	.flags = VOTABLE,
3851	};
3852
3853	static struct gdsc *gcc_sm6125_gdscs[] = {
3854	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3855	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3856	[CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
3857	[CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
3858	[CAMSS_TOP_GDSC] = &camss_top_gdsc,
3859	[CAM_CPP_GDSC] = &cam_cpp_gdsc,
3860	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3861	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3862	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3863	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3864	};
3865
3866	static struct clk_hw *gcc_sm6125_hws[] = {
3867	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,
3868	[GPLL0_OUT_MAIN] = &gpll0_out_main.hw,
3869	[GPLL6_OUT_MAIN] = &gpll6_out_main.hw,
3870	[GPLL7_OUT_MAIN] = &gpll7_out_main.hw,
3871	[GPLL8_OUT_MAIN] = &gpll8_out_main.hw,
3872	[GPLL9_OUT_MAIN] = &gpll9_out_main.hw,
3873	};
3874
3875	static struct clk_regmap *gcc_sm6125_clocks[] = {
3876	[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3877	[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3878	[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3879	[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3880	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3881	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3882	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3883	[GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr,
3884	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3885	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3886	[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
3887	[GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr,
3888	[GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr,
3889	[GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr,
3890	[GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr,
3891	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3892	[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
3893	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3894	[GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr,
3895	[GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr,
3896	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3897	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3898	[GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr,
3899	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3900	[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3901	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3902	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3903	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3904	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3905	[GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr,
3906	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3907	[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3908	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3909	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3910	[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3911	[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3912	[GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr,
3913	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3914	[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3915	[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3916	[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3917	[GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr,
3918	[GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr,
3919	[GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr,
3920	[GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr,
3921	[GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr,
3922	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3923	[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3924	[GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr,
3925	[GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr,
3926	[GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr,
3927	[GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr,
3928	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3929	[GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr,
3930	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3931	[GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr,
3932	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3933	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3934	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3935	[GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr,
3936	[GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr,
3937	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3938	[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3939	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3940	[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3941	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3942	[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3943	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3944	[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3945	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3946	[GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr,
3947	[GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr,
3948	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3949	[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3950	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3951	[GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr,
3952	[GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr,
3953	[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3954	[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3955	[GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr,
3956	[GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr,
3957	[GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr,
3958	[GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr,
3959	[GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr,
3960	[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3961	[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3962	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3963	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3964	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3965	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3966	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3967	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3968	[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3969	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3970	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3971	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3972	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3973	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3974	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3975	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3976	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3977	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3978	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3979	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3980	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3981	[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3982	[GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr,
3983	[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3984	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3985	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3986	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3987	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3988	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3989	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3990	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3991	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3992	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3993	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3994	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3995	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3996	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3997	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3998	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3999	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4000	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4001	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4002	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4003	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4004	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4005	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4006	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4007	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4008	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
4009	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
4010	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4011	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4012	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4013	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4014	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4015	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4016	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4017	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4018	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4019	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4020	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4021	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4022	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4023	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4024	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4025	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4026	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4027	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4028	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
4029	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4030	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
4031	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4032	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4033	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
4034	[GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr,
4035	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
4036	[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
4037	[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
4038	[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
4039	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4040	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4041	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4042	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4043	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4044	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4045	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4046	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4047	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4048	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4049	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
4050	&gcc_ufs_phy_unipro_core_clk_src.clkr,
4051	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4052	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4053	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4054	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
4055	&gcc_usb30_prim_mock_utmi_clk_src.clkr,
4056	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4057	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4058	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4059	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4060	[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
4061	[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
4062	[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
4063	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
4064	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4065	[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
4066	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
4067	[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
4068	[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
4069	[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
4070	[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
4071	[GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr,
4072	[GPLL0_OUT_EARLY] = &gpll0_out_early.clkr,
4073	[GPLL3_OUT_EARLY] = &gpll3_out_early.clkr,
4074	[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
4075	[GPLL5_OUT_MAIN] = &gpll5_out_main.clkr,
4076	[GPLL6_OUT_EARLY] = &gpll6_out_early.clkr,
4077	[GPLL7_OUT_EARLY] = &gpll7_out_early.clkr,
4078	[GPLL8_OUT_EARLY] = &gpll8_out_early.clkr,
4079	[GPLL9_OUT_EARLY] = &gpll9_out_early.clkr,
4080	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
4081	};
4082
4083	static const struct qcom_reset_map gcc_sm6125_resets[] = {
4084	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
4085	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
4086	[GCC_UFS_PHY_BCR] = { 0x45000 },
4087	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
4088	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
4089	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
4090	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
4091	[GCC_CAMSS_MICRO_BCR] = { 0x560ac },
4092	};
4093
4094	static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
4095	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
4096	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
4097	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
4098	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
4099	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
4100	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
4101	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
4102	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
4103	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
4104	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
4105	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
4106	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
4107	};
4108
4109	static const struct regmap_config gcc_sm6125_regmap_config = {
4110	.reg_bits = 32,
4111	.reg_stride = 4,
4112	.val_bits = 32,
4113	.max_register = 0xc7000,
4114	.fast_io = true,
4115	};
4116
4117	static const struct qcom_cc_desc gcc_sm6125_desc = {
4118	.config = &gcc_sm6125_regmap_config,
4119	.clks = gcc_sm6125_clocks,
4120	.num_clks = ARRAY_SIZE(gcc_sm6125_clocks),
4121	.clk_hws = gcc_sm6125_hws,
4122	.num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws),
4123	.resets = gcc_sm6125_resets,
4124	.num_resets = ARRAY_SIZE(gcc_sm6125_resets),
4125	.gdscs = gcc_sm6125_gdscs,
4126	.num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs),
4127	};
4128
4129	static const struct of_device_id gcc_sm6125_match_table[] = {
4130	{ .compatible = "qcom,gcc-sm6125" },
4131	{ }
4132	};
4133	MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table);
4134
4135	static int gcc_sm6125_probe(struct platform_device *pdev)
4136	{
4137	struct regmap *regmap;
4138	int ret;
4139
4140	regmap = qcom_cc_map(pdev, desc: &gcc_sm6125_desc);
4141	if (IS_ERR(ptr: regmap))
4142	return PTR_ERR(ptr: regmap);
4143
4144	/*
4145	* Disable the GPLL0 active input to video block via
4146	* MISC registers.
4147	*/
4148	regmap_update_bits(map: regmap, reg: 0x80258, mask: 0x1, val: 0x1);
4149
4150	/*
4151	* Enable DUAL_EDGE mode for MCLK RCGs
4152	* This is required to enable MND divider mode
4153	*/
4154	regmap_update_bits(map: regmap, reg: 0x51004, mask: 0x3000, val: 0x2000);
4155	regmap_update_bits(map: regmap, reg: 0x51020, mask: 0x3000, val: 0x2000);
4156	regmap_update_bits(map: regmap, reg: 0x5103c, mask: 0x3000, val: 0x2000);
4157	regmap_update_bits(map: regmap, reg: 0x51058, mask: 0x3000, val: 0x2000);
4158
4159	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
4160	ARRAY_SIZE(gcc_dfs_clocks));
4161	if (ret)
4162	return ret;
4163
4164	return qcom_cc_really_probe(pdev, desc: &gcc_sm6125_desc, regmap);
4165	}
4166
4167	static struct platform_driver gcc_sm6125_driver = {
4168	.probe = gcc_sm6125_probe,
4169	.driver = {
4170	.name = "gcc-sm6125",
4171	.of_match_table = gcc_sm6125_match_table,
4172	},
4173	};
4174
4175	static int __init gcc_sm6125_init(void)
4176	{
4177	return platform_driver_register(&gcc_sm6125_driver);
4178	}
4179	subsys_initcall(gcc_sm6125_init);
4180
4181	static void __exit gcc_sm6125_exit(void)
4182	{
4183	platform_driver_unregister(&gcc_sm6125_driver);
4184	}
4185	module_exit(gcc_sm6125_exit);
4186
4187	MODULE_DESCRIPTION("QTI GCC SM6125 Driver");
4188	MODULE_LICENSE("GPL v2");
4189