1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
5	*/
6
7	#include <linux/clk-provider.h>
8	#include <linux/module.h>
9	#include <linux/platform_device.h>
10	#include <linux/regmap.h>
11
12	#include <dt-bindings/clock/qcom,gcc-sm6350.h>
13
14	#include "clk-alpha-pll.h"
15	#include "clk-branch.h"
16	#include "clk-rcg.h"
17	#include "clk-regmap.h"
18	#include "clk-regmap-divider.h"
19	#include "clk-regmap-mux.h"
20	#include "common.h"
21	#include "gdsc.h"
22	#include "reset.h"
23
24	enum {
25	P_BI_TCXO,
26	P_GPLL0_OUT_EVEN,
27	P_GPLL0_OUT_MAIN,
28	P_GPLL0_OUT_ODD,
29	P_GPLL6_OUT_EVEN,
30	P_GPLL7_OUT_MAIN,
31	P_SLEEP_CLK,
32	};
33
34	static struct clk_alpha_pll gpll0 = {
35	.offset = 0x0,
36	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
37	.clkr = {
38	.enable_reg = 0x52010,
39	.enable_mask = BIT(0),
40	.hw.init = &(struct clk_init_data){
41	.name = "gpll0",
42	.parent_data = &(const struct clk_parent_data){
43	.fw_name = "bi_tcxo",
44	},
45	.num_parents = 1,
46	.ops = &clk_alpha_pll_fixed_fabia_ops,
47	},
48	},
49	};
50
51	static const struct clk_div_table post_div_table_gpll0_out_even[] = {
52	{ 0x1, 2 },
53	{ }
54	};
55
56	static struct clk_alpha_pll_postdiv gpll0_out_even = {
57	.offset = 0x0,
58	.post_div_shift = 8,
59	.post_div_table = post_div_table_gpll0_out_even,
60	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
61	.width = 4,
62	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
63	.clkr.hw.init = &(struct clk_init_data){
64	.name = "gpll0_out_even",
65	.parent_hws = (const struct clk_hw*[]){
66	&gpll0.clkr.hw,
67	},
68	.num_parents = 1,
69	.ops = &clk_alpha_pll_postdiv_fabia_ops,
70	},
71	};
72
73	static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
74	{ 0x3, 3 },
75	{ }
76	};
77
78	static struct clk_alpha_pll_postdiv gpll0_out_odd = {
79	.offset = 0x0,
80	.post_div_shift = 12,
81	.post_div_table = post_div_table_gpll0_out_odd,
82	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
83	.width = 4,
84	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
85	.clkr.hw.init = &(struct clk_init_data){
86	.name = "gpll0_out_odd",
87	.parent_hws = (const struct clk_hw*[]){
88	&gpll0.clkr.hw,
89	},
90	.num_parents = 1,
91	.ops = &clk_alpha_pll_postdiv_fabia_ops,
92	},
93	};
94
95	static struct clk_alpha_pll gpll6 = {
96	.offset = 0x6000,
97	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
98	.clkr = {
99	.enable_reg = 0x52010,
100	.enable_mask = BIT(6),
101	.hw.init = &(struct clk_init_data){
102	.name = "gpll6",
103	.parent_hws = (const struct clk_hw*[]){
104	&gpll0.clkr.hw,
105	},
106	.num_parents = 1,
107	.ops = &clk_alpha_pll_fixed_fabia_ops,
108	},
109	},
110	};
111
112	static const struct clk_div_table post_div_table_gpll6_out_even[] = {
113	{ 0x1, 2 },
114	{ }
115	};
116
117	static struct clk_alpha_pll_postdiv gpll6_out_even = {
118	.offset = 0x6000,
119	.post_div_shift = 8,
120	.post_div_table = post_div_table_gpll6_out_even,
121	.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
122	.width = 4,
123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
124	.clkr.hw.init = &(struct clk_init_data){
125	.name = "gpll6_out_even",
126	.parent_hws = (const struct clk_hw*[]){
127	&gpll0.clkr.hw,
128	},
129	.num_parents = 1,
130	.ops = &clk_alpha_pll_postdiv_fabia_ops,
131	},
132	};
133
134	static struct clk_alpha_pll gpll7 = {
135	.offset = 0x7000,
136	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
137	.clkr = {
138	.enable_reg = 0x52010,
139	.enable_mask = BIT(7),
140	.hw.init = &(struct clk_init_data){
141	.name = "gpll7",
142	.parent_hws = (const struct clk_hw*[]){
143	&gpll0.clkr.hw,
144	},
145	.num_parents = 1,
146	.ops = &clk_alpha_pll_fixed_fabia_ops,
147	},
148	},
149	};
150
151	static const struct parent_map gcc_parent_map_0[] = {
152	{ P_BI_TCXO, 0 },
153	{ P_GPLL0_OUT_MAIN, 1 },
154	{ P_GPLL6_OUT_EVEN, 2 },
155	{ P_GPLL0_OUT_EVEN, 6 },
156	};
157
158	static const struct clk_parent_data gcc_parent_data_0[] = {
159	{ .fw_name = "bi_tcxo" },
160	{ .hw = &gpll0.clkr.hw },
161	{ .hw = &gpll6_out_even.clkr.hw },
162	{ .hw = &gpll0_out_even.clkr.hw },
163	};
164
165	static const struct parent_map gcc_parent_map_1[] = {
166	{ P_BI_TCXO, 0 },
167	{ P_GPLL0_OUT_EVEN, 6 },
168	};
169
170	static const struct clk_parent_data gcc_parent_data_1[] = {
171	{ .fw_name = "bi_tcxo" },
172	{ .hw = &gpll0_out_even.clkr.hw },
173	};
174
175	static const struct parent_map gcc_parent_map_2[] = {
176	{ P_BI_TCXO, 0 },
177	{ P_GPLL0_OUT_ODD, 2 },
178	};
179
180	static const struct clk_parent_data gcc_parent_data_2_ao[] = {
181	{ .fw_name = "bi_tcxo_ao" },
182	{ .hw = &gpll0_out_odd.clkr.hw },
183	};
184
185	static const struct parent_map gcc_parent_map_4[] = {
186	{ P_BI_TCXO, 0 },
187	{ P_GPLL0_OUT_MAIN, 1 },
188	{ P_GPLL0_OUT_ODD, 2 },
189	};
190
191	static const struct clk_parent_data gcc_parent_data_4[] = {
192	{ .fw_name = "bi_tcxo" },
193	{ .hw = &gpll0.clkr.hw },
194	{ .hw = &gpll0_out_odd.clkr.hw },
195	};
196
197	static const struct parent_map gcc_parent_map_5[] = {
198	{ P_BI_TCXO, 0 },
199	{ P_GPLL0_OUT_ODD, 2 },
200	{ P_SLEEP_CLK, 5 },
201	{ P_GPLL0_OUT_EVEN, 6 },
202	};
203
204	static const struct clk_parent_data gcc_parent_data_5[] = {
205	{ .fw_name = "bi_tcxo" },
206	{ .hw = &gpll0_out_odd.clkr.hw },
207	{ .fw_name = "sleep_clk" },
208	{ .hw = &gpll0_out_even.clkr.hw },
209	};
210
211	static const struct parent_map gcc_parent_map_6[] = {
212	{ P_BI_TCXO, 0 },
213	{ P_SLEEP_CLK, 5 },
214	};
215
216	static const struct clk_parent_data gcc_parent_data_6[] = {
217	{ .fw_name = "bi_tcxo" },
218	{ .fw_name = "sleep_clk" }
219	};
220
221	static const struct parent_map gcc_parent_map_7[] = {
222	{ P_BI_TCXO, 0 },
223	{ P_GPLL6_OUT_EVEN, 2 },
224	{ P_GPLL0_OUT_EVEN, 6 },
225	};
226
227	static const struct clk_parent_data gcc_parent_data_7[] = {
228	{ .fw_name = "bi_tcxo" },
229	{ .hw = &gpll6_out_even.clkr.hw },
230	{ .hw = &gpll0_out_even.clkr.hw },
231	};
232
233	static const struct parent_map gcc_parent_map_8[] = {
234	{ P_BI_TCXO, 0 },
235	{ P_GPLL0_OUT_ODD, 2 },
236	{ P_GPLL7_OUT_MAIN, 3 },
237	};
238
239	static const struct clk_parent_data gcc_parent_data_8[] = {
240	{ .fw_name = "bi_tcxo" },
241	{ .hw = &gpll0_out_odd.clkr.hw },
242	{ .hw = &gpll7.clkr.hw },
243	};
244
245	static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = {
246	.reg = 0x4514C,
247	.shift = 0,
248	.width = 2,
249	.clkr.hw.init = &(struct clk_init_data) {
250	.name = "gcc_gpu_gpll0_main_div_clk_src",
251	.parent_hws = (const struct clk_hw*[]){
252	&gpll0.clkr.hw,
253	},
254	.num_parents = 1,
255	.ops = &clk_regmap_div_ro_ops,
256	},
257	};
258
259	static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = {
260	.reg = 0x4ce00,
261	.shift = 0,
262	.width = 2,
263	.clkr.hw.init = &(struct clk_init_data) {
264	.name = "gcc_npu_pll0_main_div_clk_src",
265	.parent_hws = (const struct clk_hw*[]){
266	&gpll0.clkr.hw,
267	},
268	.num_parents = 1,
269	.ops = &clk_regmap_div_ro_ops,
270	},
271	};
272
273	static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
274	F(19200000, P_BI_TCXO, 1, 0, 0),
275	{ }
276	};
277
278	static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
279	.cmd_rcgr = 0x30014,
280	.mnd_width = 0,
281	.hid_width = 5,
282	.parent_map = gcc_parent_map_2,
283	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
284	.clkr.hw.init = &(struct clk_init_data){
285	.name = "gcc_cpuss_ahb_clk_src",
286	.parent_data = gcc_parent_data_2_ao,
287	.num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
288	.ops = &clk_rcg2_ops,
289	},
290	};
291
292	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
293	F(19200000, P_BI_TCXO, 1, 0, 0),
294	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
295	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
296	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
297	F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
298	{ }
299	};
300
301	static struct clk_rcg2 gcc_gp1_clk_src = {
302	.cmd_rcgr = 0x37004,
303	.mnd_width = 8,
304	.hid_width = 5,
305	.parent_map = gcc_parent_map_5,
306	.freq_tbl = ftbl_gcc_gp1_clk_src,
307	.clkr.hw.init = &(struct clk_init_data){
308	.name = "gcc_gp1_clk_src",
309	.parent_data = gcc_parent_data_5,
310	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
311	.ops = &clk_rcg2_ops,
312	},
313	};
314
315	static struct clk_rcg2 gcc_gp2_clk_src = {
316	.cmd_rcgr = 0x38004,
317	.mnd_width = 8,
318	.hid_width = 5,
319	.parent_map = gcc_parent_map_5,
320	.freq_tbl = ftbl_gcc_gp1_clk_src,
321	.clkr.hw.init = &(struct clk_init_data){
322	.name = "gcc_gp2_clk_src",
323	.parent_data = gcc_parent_data_5,
324	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
325	.ops = &clk_rcg2_ops,
326	},
327	};
328
329	static struct clk_rcg2 gcc_gp3_clk_src = {
330	.cmd_rcgr = 0x39004,
331	.mnd_width = 8,
332	.hid_width = 5,
333	.parent_map = gcc_parent_map_5,
334	.freq_tbl = ftbl_gcc_gp1_clk_src,
335	.clkr.hw.init = &(struct clk_init_data){
336	.name = "gcc_gp3_clk_src",
337	.parent_data = gcc_parent_data_5,
338	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
339	.ops = &clk_rcg2_ops,
340	},
341	};
342
343	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
344	F(19200000, P_BI_TCXO, 1, 0, 0),
345	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
346	{ }
347	};
348
349	static struct clk_rcg2 gcc_pdm2_clk_src = {
350	.cmd_rcgr = 0x23010,
351	.mnd_width = 0,
352	.hid_width = 5,
353	.parent_map = gcc_parent_map_1,
354	.freq_tbl = ftbl_gcc_pdm2_clk_src,
355	.clkr.hw.init = &(struct clk_init_data){
356	.name = "gcc_pdm2_clk_src",
357	.parent_data = gcc_parent_data_1,
358	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
359	.ops = &clk_rcg2_ops,
360	},
361	};
362
363	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
364	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
365	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
366	F(19200000, P_BI_TCXO, 1, 0, 0),
367	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
368	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
369	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
370	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
371	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
372	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
373	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
374	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
375	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
376	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
377	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
378	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
379	F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
380	{ }
381	};
382
383	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
384	.name = "gcc_qupv3_wrap0_s0_clk_src",
385	.parent_data = gcc_parent_data_0,
386	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
387	.ops = &clk_rcg2_ops,
388	};
389
390	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
391	.cmd_rcgr = 0x21148,
392	.mnd_width = 16,
393	.hid_width = 5,
394	.parent_map = gcc_parent_map_0,
395	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
396	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
397	};
398
399	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
400	.name = "gcc_qupv3_wrap0_s1_clk_src",
401	.parent_data = gcc_parent_data_0,
402	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
403	.ops = &clk_rcg2_ops,
404	};
405
406	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
407	.cmd_rcgr = 0x21278,
408	.mnd_width = 16,
409	.hid_width = 5,
410	.parent_map = gcc_parent_map_0,
411	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
412	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
413	};
414
415	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
416	.name = "gcc_qupv3_wrap0_s2_clk_src",
417	.parent_data = gcc_parent_data_0,
418	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
419	.ops = &clk_rcg2_ops,
420	};
421
422	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
423	.cmd_rcgr = 0x213a8,
424	.mnd_width = 16,
425	.hid_width = 5,
426	.parent_map = gcc_parent_map_0,
427	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
428	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
429	};
430
431	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
432	.name = "gcc_qupv3_wrap0_s3_clk_src",
433	.parent_data = gcc_parent_data_0,
434	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
435	.ops = &clk_rcg2_ops,
436	};
437
438	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
439	.cmd_rcgr = 0x214d8,
440	.mnd_width = 16,
441	.hid_width = 5,
442	.parent_map = gcc_parent_map_0,
443	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
444	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
445	};
446
447	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
448	.name = "gcc_qupv3_wrap0_s4_clk_src",
449	.parent_data = gcc_parent_data_0,
450	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
451	.ops = &clk_rcg2_ops,
452	};
453
454	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
455	.cmd_rcgr = 0x21608,
456	.mnd_width = 16,
457	.hid_width = 5,
458	.parent_map = gcc_parent_map_0,
459	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
460	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
461	};
462
463	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
464	.name = "gcc_qupv3_wrap0_s5_clk_src",
465	.parent_data = gcc_parent_data_0,
466	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
467	.ops = &clk_rcg2_ops,
468	};
469
470	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
471	.cmd_rcgr = 0x21738,
472	.mnd_width = 16,
473	.hid_width = 5,
474	.parent_map = gcc_parent_map_0,
475	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
476	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
477	};
478
479	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
480	.name = "gcc_qupv3_wrap1_s0_clk_src",
481	.parent_data = gcc_parent_data_0,
482	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
483	.ops = &clk_rcg2_ops,
484	};
485
486	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
487	.cmd_rcgr = 0x22018,
488	.mnd_width = 16,
489	.hid_width = 5,
490	.parent_map = gcc_parent_map_0,
491	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
492	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
493	};
494
495	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
496	.name = "gcc_qupv3_wrap1_s1_clk_src",
497	.parent_data = gcc_parent_data_0,
498	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
499	.ops = &clk_rcg2_ops,
500	};
501
502	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
503	.cmd_rcgr = 0x22148,
504	.mnd_width = 16,
505	.hid_width = 5,
506	.parent_map = gcc_parent_map_0,
507	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
508	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
509	};
510
511	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
512	.name = "gcc_qupv3_wrap1_s2_clk_src",
513	.parent_data = gcc_parent_data_0,
514	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
515	.ops = &clk_rcg2_ops,
516	};
517
518	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
519	.cmd_rcgr = 0x22278,
520	.mnd_width = 16,
521	.hid_width = 5,
522	.parent_map = gcc_parent_map_0,
523	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
524	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
525	};
526
527	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
528	.name = "gcc_qupv3_wrap1_s3_clk_src",
529	.parent_data = gcc_parent_data_0,
530	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
531	.ops = &clk_rcg2_ops,
532	};
533
534	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
535	.cmd_rcgr = 0x223a8,
536	.mnd_width = 16,
537	.hid_width = 5,
538	.parent_map = gcc_parent_map_0,
539	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
540	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
541	};
542
543	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
544	.name = "gcc_qupv3_wrap1_s4_clk_src",
545	.parent_data = gcc_parent_data_0,
546	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
547	.ops = &clk_rcg2_ops,
548	};
549
550	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
551	.cmd_rcgr = 0x224d8,
552	.mnd_width = 16,
553	.hid_width = 5,
554	.parent_map = gcc_parent_map_0,
555	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
556	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
557	};
558
559	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
560	.name = "gcc_qupv3_wrap1_s5_clk_src",
561	.parent_data = gcc_parent_data_0,
562	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
563	.ops = &clk_rcg2_ops,
564	};
565
566	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
567	.cmd_rcgr = 0x22608,
568	.mnd_width = 16,
569	.hid_width = 5,
570	.parent_map = gcc_parent_map_0,
571	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
572	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
573	};
574
575	static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
576	F(144000, P_BI_TCXO, 16, 3, 25),
577	F(400000, P_BI_TCXO, 12, 1, 4),
578	F(19200000, P_BI_TCXO, 1, 0, 0),
579	F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
580	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
581	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
582	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
583	F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
584	F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
585	{ }
586	};
587
588	static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
589	.cmd_rcgr = 0x4b024,
590	.mnd_width = 8,
591	.hid_width = 5,
592	.parent_map = gcc_parent_map_7,
593	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
594	.clkr.hw.init = &(struct clk_init_data){
595	.name = "gcc_sdcc1_apps_clk_src",
596	.parent_data = gcc_parent_data_7,
597	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
598	.ops = &clk_rcg2_ops,
599	},
600	};
601
602	static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
603	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
604	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
605	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
606	{ }
607	};
608
609	static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
610	.cmd_rcgr = 0x4b00c,
611	.mnd_width = 0,
612	.hid_width = 5,
613	.parent_map = gcc_parent_map_1,
614	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
615	.clkr.hw.init = &(struct clk_init_data){
616	.name = "gcc_sdcc1_ice_core_clk_src",
617	.parent_data = gcc_parent_data_1,
618	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
619	.ops = &clk_rcg2_ops,
620	},
621	};
622
623	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
624	F(400000, P_BI_TCXO, 12, 1, 4),
625	F(9600000, P_BI_TCXO, 2, 0, 0),
626	F(19200000, P_BI_TCXO, 1, 0, 0),
627	F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
628	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
629	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
630	F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
631	{ }
632	};
633
634	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
635	.cmd_rcgr = 0x2000c,
636	.mnd_width = 8,
637	.hid_width = 5,
638	.parent_map = gcc_parent_map_8,
639	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
640	.clkr.hw.init = &(struct clk_init_data){
641	.name = "gcc_sdcc2_apps_clk_src",
642	.parent_data = gcc_parent_data_8,
643	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
644	.flags = CLK_OPS_PARENT_ENABLE,
645	.ops = &clk_rcg2_floor_ops,
646	},
647	};
648
649	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
650	F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
651	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
652	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
653	F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
654	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
655	{ }
656	};
657
658	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
659	.cmd_rcgr = 0x3a01c,
660	.mnd_width = 8,
661	.hid_width = 5,
662	.parent_map = gcc_parent_map_4,
663	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
664	.clkr.hw.init = &(struct clk_init_data){
665	.name = "gcc_ufs_phy_axi_clk_src",
666	.parent_data = gcc_parent_data_4,
667	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
668	.ops = &clk_rcg2_ops,
669	},
670	};
671
672	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
673	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
674	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
675	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
676	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
677	{ }
678	};
679
680	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
681	.cmd_rcgr = 0x3a048,
682	.mnd_width = 0,
683	.hid_width = 5,
684	.parent_map = gcc_parent_map_1,
685	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
686	.clkr.hw.init = &(struct clk_init_data){
687	.name = "gcc_ufs_phy_ice_core_clk_src",
688	.parent_data = gcc_parent_data_1,
689	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
690	.ops = &clk_rcg2_ops,
691	},
692	};
693
694	static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
695	F(9600000, P_BI_TCXO, 2, 0, 0),
696	F(19200000, P_BI_TCXO, 1, 0, 0),
697	{ }
698	};
699
700	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
701	.cmd_rcgr = 0x3a0b0,
702	.mnd_width = 0,
703	.hid_width = 5,
704	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
705	.clkr.hw.init = &(struct clk_init_data){
706	.name = "gcc_ufs_phy_phy_aux_clk_src",
707	.parent_data = &(const struct clk_parent_data){
708	.fw_name = "bi_tcxo",
709	},
710	.num_parents = 1,
711	.ops = &clk_rcg2_ops,
712	},
713	};
714
715	static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
716	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
717	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
718	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
719	{ }
720	};
721
722	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
723	.cmd_rcgr = 0x3a060,
724	.mnd_width = 0,
725	.hid_width = 5,
726	.parent_map = gcc_parent_map_1,
727	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
728	.clkr.hw.init = &(struct clk_init_data){
729	.name = "gcc_ufs_phy_unipro_core_clk_src",
730	.parent_data = gcc_parent_data_1,
731	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
732	.ops = &clk_rcg2_ops,
733	},
734	};
735
736	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
737	F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
738	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
739	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
740	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
741	{ }
742	};
743
744	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
745	.cmd_rcgr = 0x1a01c,
746	.mnd_width = 8,
747	.hid_width = 5,
748	.parent_map = gcc_parent_map_4,
749	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
750	.clkr.hw.init = &(struct clk_init_data){
751	.name = "gcc_usb30_prim_master_clk_src",
752	.parent_data = gcc_parent_data_4,
753	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
754	.ops = &clk_rcg2_ops,
755	},
756	};
757
758	static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
759	F(19200000, P_BI_TCXO, 1, 0, 0),
760	{ }
761	};
762
763	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
764	.cmd_rcgr = 0x1a034,
765	.mnd_width = 0,
766	.hid_width = 5,
767	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
768	.clkr.hw.init = &(struct clk_init_data){
769	.name = "gcc_usb30_prim_mock_utmi_clk_src",
770	.parent_data = &(const struct clk_parent_data){
771	.fw_name = "bi_tcxo",
772	},
773	.num_parents = 1,
774	.ops = &clk_rcg2_ops,
775	},
776	};
777
778	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
779	.cmd_rcgr = 0x1a060,
780	.mnd_width = 0,
781	.hid_width = 5,
782	.parent_map = gcc_parent_map_6,
783	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
784	.clkr.hw.init = &(struct clk_init_data){
785	.name = "gcc_usb3_prim_phy_aux_clk_src",
786	.parent_data = gcc_parent_data_6,
787	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
788	.ops = &clk_rcg2_ops,
789	},
790	};
791
792	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
793	.halt_reg = 0x3e014,
794	.halt_check = BRANCH_HALT_DELAY,
795	.hwcg_reg = 0x3e014,
796	.hwcg_bit = 1,
797	.clkr = {
798	.enable_reg = 0x3e014,
799	.enable_mask = BIT(0),
800	.hw.init = &(struct clk_init_data){
801	.name = "gcc_aggre_ufs_phy_axi_clk",
802	.parent_hws = (const struct clk_hw*[]){
803	&gcc_ufs_phy_axi_clk_src.clkr.hw,
804	},
805	.num_parents = 1,
806	.flags = CLK_SET_RATE_PARENT,
807	.ops = &clk_branch2_ops,
808	},
809	},
810	};
811
812	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
813	.halt_reg = 0x3e014,
814	.halt_check = BRANCH_HALT,
815	.hwcg_reg = 0x3e014,
816	.hwcg_bit = 1,
817	.clkr = {
818	.enable_reg = 0x3e014,
819	.enable_mask = BIT(1),
820	.hw.init = &(struct clk_init_data){
821	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
822	.parent_hws = (const struct clk_hw*[]){
823	&gcc_ufs_phy_axi_clk_src.clkr.hw,
824	},
825	.num_parents = 1,
826	.flags = CLK_SET_RATE_PARENT,
827	.ops = &clk_branch2_ops,
828	},
829	},
830	};
831
832	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
833	.halt_reg = 0x3e014,
834	.halt_check = BRANCH_HALT,
835	.hwcg_reg = 0x3e014,
836	.hwcg_bit = 1,
837	.clkr = {
838	.enable_reg = 0x3e014,
839	.enable_mask = BIT(1),
840	.hw.init = &(struct clk_init_data){
841	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
842	.parent_hws = (const struct clk_hw*[]){
843	&gcc_ufs_phy_axi_clk_src.clkr.hw,
844	},
845	.num_parents = 1,
846	.flags = CLK_SET_RATE_PARENT,
847	.ops = &clk_branch2_ops,
848	},
849	},
850	};
851
852	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
853	.halt_reg = 0x3e010,
854	.halt_check = BRANCH_HALT,
855	.hwcg_reg = 0x3e010,
856	.hwcg_bit = 1,
857	.clkr = {
858	.enable_reg = 0x3e010,
859	.enable_mask = BIT(0),
860	.hw.init = &(struct clk_init_data){
861	.name = "gcc_aggre_usb3_prim_axi_clk",
862	.parent_hws = (const struct clk_hw*[]){
863	&gcc_usb30_prim_master_clk_src.clkr.hw,
864	},
865	.num_parents = 1,
866	.flags = CLK_SET_RATE_PARENT,
867	.ops = &clk_branch2_ops,
868	},
869	},
870	};
871
872	static struct clk_branch gcc_boot_rom_ahb_clk = {
873	.halt_reg = 0x26004,
874	.halt_check = BRANCH_HALT_VOTED,
875	.hwcg_reg = 0x26004,
876	.hwcg_bit = 1,
877	.clkr = {
878	.enable_reg = 0x52000,
879	.enable_mask = BIT(28),
880	.hw.init = &(struct clk_init_data){
881	.name = "gcc_boot_rom_ahb_clk",
882	.ops = &clk_branch2_ops,
883	},
884	},
885	};
886
887	static struct clk_branch gcc_camera_ahb_clk = {
888	.halt_reg = 0x17008,
889	.halt_check = BRANCH_HALT,
890	.hwcg_reg = 0x17008,
891	.hwcg_bit = 1,
892	.clkr = {
893	.enable_reg = 0x17008,
894	.enable_mask = BIT(0),
895	.hw.init = &(struct clk_init_data){
896	.name = "gcc_camera_ahb_clk",
897	.flags = CLK_IS_CRITICAL,
898	.ops = &clk_branch2_ops,
899	},
900	},
901	};
902
903	static struct clk_branch gcc_camera_axi_clk = {
904	.halt_reg = 0x17018,
905	.halt_check = BRANCH_HALT,
906	.hwcg_reg = 0x17018,
907	.hwcg_bit = 1,
908	.clkr = {
909	.enable_reg = 0x17018,
910	.enable_mask = BIT(0),
911	.hw.init = &(struct clk_init_data){
912	.name = "gcc_camera_axi_clk",
913	.ops = &clk_branch2_ops,
914	},
915	},
916	};
917
918	static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
919	.halt_reg = 0x17078,
920	.halt_check = BRANCH_VOTED,
921	.hwcg_reg = 0x17078,
922	.hwcg_bit = 1,
923	.clkr = {
924	.enable_reg = 0x17078,
925	.enable_mask = BIT(0),
926	.hw.init = &(struct clk_init_data){
927	.name = "gcc_camera_throttle_nrt_axi_clk",
928	.ops = &clk_branch2_ops,
929	},
930	},
931	};
932
933	static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
934	.halt_reg = 0x17024,
935	.halt_check = BRANCH_VOTED,
936	.hwcg_reg = 0x17024,
937	.hwcg_bit = 1,
938	.clkr = {
939	.enable_reg = 0x17024,
940	.enable_mask = BIT(0),
941	.hw.init = &(struct clk_init_data){
942	.name = "gcc_camera_throttle_rt_axi_clk",
943	.ops = &clk_branch2_ops,
944	},
945	},
946	};
947
948	static struct clk_branch gcc_camera_xo_clk = {
949	.halt_reg = 0x17030,
950	.halt_check = BRANCH_HALT,
951	.clkr = {
952	.enable_reg = 0x17030,
953	.enable_mask = BIT(0),
954	.hw.init = &(struct clk_init_data){
955	.name = "gcc_camera_xo_clk",
956	.flags = CLK_IS_CRITICAL,
957	.ops = &clk_branch2_ops,
958	},
959	},
960	};
961
962	static struct clk_branch gcc_ce1_ahb_clk = {
963	.halt_reg = 0x2b00c,
964	.halt_check = BRANCH_HALT_VOTED,
965	.hwcg_reg = 0x2b00c,
966	.hwcg_bit = 1,
967	.clkr = {
968	.enable_reg = 0x52008,
969	.enable_mask = BIT(3),
970	.hw.init = &(struct clk_init_data){
971	.name = "gcc_ce1_ahb_clk",
972	.ops = &clk_branch2_ops,
973	},
974	},
975	};
976
977	static struct clk_branch gcc_ce1_axi_clk = {
978	.halt_reg = 0x2b008,
979	.halt_check = BRANCH_HALT_VOTED,
980	.clkr = {
981	.enable_reg = 0x52008,
982	.enable_mask = BIT(2),
983	.hw.init = &(struct clk_init_data){
984	.name = "gcc_ce1_axi_clk",
985	.ops = &clk_branch2_ops,
986	},
987	},
988	};
989
990	static struct clk_branch gcc_ce1_clk = {
991	.halt_reg = 0x2b004,
992	.halt_check = BRANCH_HALT_VOTED,
993	.clkr = {
994	.enable_reg = 0x52008,
995	.enable_mask = BIT(1),
996	.hw.init = &(struct clk_init_data){
997	.name = "gcc_ce1_clk",
998	.ops = &clk_branch2_ops,
999	},
1000	},
1001	};
1002
1003	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1004	.halt_reg = 0x1101c,
1005	.halt_check = BRANCH_HALT,
1006	.hwcg_reg = 0x1101c,
1007	.hwcg_bit = 1,
1008	.clkr = {
1009	.enable_reg = 0x1101c,
1010	.enable_mask = BIT(0),
1011	.hw.init = &(struct clk_init_data){
1012	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1013	.parent_hws = (const struct clk_hw*[]){
1014	&gcc_usb30_prim_master_clk_src.clkr.hw,
1015	},
1016	.num_parents = 1,
1017	.flags = CLK_SET_RATE_PARENT,
1018	.ops = &clk_branch2_ops,
1019	},
1020	},
1021	};
1022
1023	static struct clk_branch gcc_cpuss_ahb_clk = {
1024	.halt_reg = 0x30000,
1025	.halt_check = BRANCH_HALT_VOTED,
1026	.hwcg_reg = 0x30000,
1027	.hwcg_bit = 1,
1028	.clkr = {
1029	.enable_reg = 0x52008,
1030	.enable_mask = BIT(4),
1031	.hw.init = &(struct clk_init_data){
1032	.name = "gcc_cpuss_ahb_clk",
1033	.parent_hws = (const struct clk_hw*[]){
1034	&gcc_cpuss_ahb_clk_src.clkr.hw,
1035	},
1036	.num_parents = 1,
1037	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1038	.ops = &clk_branch2_ops,
1039	},
1040	},
1041	};
1042
1043	static struct clk_branch gcc_cpuss_gnoc_clk = {
1044	.halt_reg = 0x30004,
1045	.halt_check = BRANCH_HALT_VOTED,
1046	.hwcg_reg = 0x30004,
1047	.hwcg_bit = 1,
1048	.clkr = {
1049	.enable_reg = 0x52008,
1050	.enable_mask = BIT(5),
1051	.hw.init = &(struct clk_init_data){
1052	.name = "gcc_cpuss_gnoc_clk",
1053	.flags = CLK_IS_CRITICAL,
1054	.ops = &clk_branch2_ops,
1055	},
1056	},
1057	};
1058
1059	static struct clk_branch gcc_cpuss_rbcpr_clk = {
1060	.halt_reg = 0x30008,
1061	.halt_check = BRANCH_HALT,
1062	.clkr = {
1063	.enable_reg = 0x30008,
1064	.enable_mask = BIT(0),
1065	.hw.init = &(struct clk_init_data){
1066	.name = "gcc_cpuss_rbcpr_clk",
1067	.ops = &clk_branch2_ops,
1068	},
1069	},
1070	};
1071
1072	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1073	.halt_reg = 0x2d038,
1074	.halt_check = BRANCH_VOTED,
1075	.hwcg_reg = 0x2d038,
1076	.hwcg_bit = 1,
1077	.clkr = {
1078	.enable_reg = 0x2d038,
1079	.enable_mask = BIT(0),
1080	.hw.init = &(struct clk_init_data){
1081	.name = "gcc_ddrss_gpu_axi_clk",
1082	.ops = &clk_branch2_ops,
1083	},
1084	},
1085	};
1086
1087	static struct clk_branch gcc_disp_ahb_clk = {
1088	.halt_reg = 0x1700c,
1089	.halt_check = BRANCH_HALT,
1090	.hwcg_reg = 0x1700c,
1091	.hwcg_bit = 1,
1092	.clkr = {
1093	.enable_reg = 0x1700c,
1094	.enable_mask = BIT(0),
1095	.hw.init = &(struct clk_init_data){
1096	.name = "gcc_disp_ahb_clk",
1097	.flags = CLK_IS_CRITICAL,
1098	.ops = &clk_branch2_ops,
1099	},
1100	},
1101	};
1102
1103	static struct clk_branch gcc_disp_axi_clk = {
1104	.halt_reg = 0x1701c,
1105	.halt_check = BRANCH_HALT,
1106	.hwcg_reg = 0x1701c,
1107	.hwcg_bit = 1,
1108	.clkr = {
1109	.enable_reg = 0x1701c,
1110	.enable_mask = BIT(0),
1111	.hw.init = &(struct clk_init_data){
1112	.name = "gcc_disp_axi_clk",
1113	.ops = &clk_branch2_ops,
1114	},
1115	},
1116	};
1117
1118	static struct clk_branch gcc_disp_cc_sleep_clk = {
1119	.halt_reg = 0x17074,
1120	.halt_check = BRANCH_HALT_DELAY,
1121	.hwcg_reg = 0x17074,
1122	.hwcg_bit = 1,
1123	.clkr = {
1124	.enable_reg = 0x17074,
1125	.enable_mask = BIT(0),
1126	.hw.init = &(struct clk_init_data){
1127	.name = "gcc_disp_cc_sleep_clk",
1128	.ops = &clk_branch2_ops,
1129	},
1130	},
1131	};
1132
1133	static struct clk_branch gcc_disp_cc_xo_clk = {
1134	.halt_reg = 0x17070,
1135	.halt_check = BRANCH_HALT,
1136	.hwcg_reg = 0x17070,
1137	.hwcg_bit = 1,
1138	.clkr = {
1139	.enable_reg = 0x17070,
1140	.enable_mask = BIT(0),
1141	.hw.init = &(struct clk_init_data){
1142	.name = "gcc_disp_cc_xo_clk",
1143	.flags = CLK_IS_CRITICAL,
1144	.ops = &clk_branch2_ops,
1145	},
1146	},
1147	};
1148
1149	static struct clk_branch gcc_disp_gpll0_clk = {
1150	.halt_check = BRANCH_HALT_DELAY,
1151	.clkr = {
1152	.enable_reg = 0x52000,
1153	.enable_mask = BIT(2),
1154	.hw.init = &(struct clk_init_data){
1155	.name = "gcc_disp_gpll0_clk",
1156	.parent_hws = (const struct clk_hw*[]){
1157	&gpll0.clkr.hw,
1158	},
1159	.num_parents = 1,
1160	.ops = &clk_branch2_ops,
1161	},
1162	},
1163	};
1164
1165	static struct clk_branch gcc_disp_throttle_axi_clk = {
1166	.halt_reg = 0x17028,
1167	.halt_check = BRANCH_HALT,
1168	.hwcg_reg = 0x17028,
1169	.hwcg_bit = 1,
1170	.clkr = {
1171	.enable_reg = 0x17028,
1172	.enable_mask = BIT(0),
1173	.hw.init = &(struct clk_init_data){
1174	.name = "gcc_disp_throttle_axi_clk",
1175	.ops = &clk_branch2_ops,
1176	},
1177	},
1178	};
1179
1180	static struct clk_branch gcc_disp_xo_clk = {
1181	.halt_reg = 0x17034,
1182	.halt_check = BRANCH_HALT,
1183	.clkr = {
1184	.enable_reg = 0x17034,
1185	.enable_mask = BIT(0),
1186	.hw.init = &(struct clk_init_data){
1187	.name = "gcc_disp_xo_clk",
1188	.ops = &clk_branch2_ops,
1189	},
1190	},
1191	};
1192
1193	static struct clk_branch gcc_gp1_clk = {
1194	.halt_reg = 0x37000,
1195	.halt_check = BRANCH_HALT,
1196	.clkr = {
1197	.enable_reg = 0x37000,
1198	.enable_mask = BIT(0),
1199	.hw.init = &(struct clk_init_data){
1200	.name = "gcc_gp1_clk",
1201	.parent_hws = (const struct clk_hw*[]){
1202	&gcc_gp1_clk_src.clkr.hw,
1203	},
1204	.num_parents = 1,
1205	.flags = CLK_SET_RATE_PARENT,
1206	.ops = &clk_branch2_ops,
1207	},
1208	},
1209	};
1210
1211	static struct clk_branch gcc_gp2_clk = {
1212	.halt_reg = 0x38000,
1213	.halt_check = BRANCH_HALT,
1214	.clkr = {
1215	.enable_reg = 0x38000,
1216	.enable_mask = BIT(0),
1217	.hw.init = &(struct clk_init_data){
1218	.name = "gcc_gp2_clk",
1219	.parent_hws = (const struct clk_hw*[]){
1220	&gcc_gp2_clk_src.clkr.hw,
1221	},
1222	.num_parents = 1,
1223	.flags = CLK_SET_RATE_PARENT,
1224	.ops = &clk_branch2_ops,
1225	},
1226	},
1227	};
1228
1229	static struct clk_branch gcc_gp3_clk = {
1230	.halt_reg = 0x39000,
1231	.halt_check = BRANCH_HALT,
1232	.clkr = {
1233	.enable_reg = 0x39000,
1234	.enable_mask = BIT(0),
1235	.hw.init = &(struct clk_init_data){
1236	.name = "gcc_gp3_clk",
1237	.parent_hws = (const struct clk_hw*[]){
1238	&gcc_gp3_clk_src.clkr.hw,
1239	},
1240	.num_parents = 1,
1241	.flags = CLK_SET_RATE_PARENT,
1242	.ops = &clk_branch2_ops,
1243	},
1244	},
1245	};
1246
1247	static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1248	.halt_reg = 0x45004,
1249	.halt_check = BRANCH_HALT,
1250	.hwcg_reg = 0x45004,
1251	.hwcg_bit = 1,
1252	.clkr = {
1253	.enable_reg = 0x45004,
1254	.enable_mask = BIT(0),
1255	.hw.init = &(struct clk_init_data){
1256	.name = "gcc_gpu_cfg_ahb_clk",
1257	.flags = CLK_IS_CRITICAL,
1258	.ops = &clk_branch2_ops,
1259	},
1260	},
1261	};
1262
1263	static struct clk_branch gcc_gpu_gpll0_clk = {
1264	.halt_check = BRANCH_HALT_DELAY,
1265	.clkr = {
1266	.enable_reg = 0x52008,
1267	.enable_mask = BIT(7),
1268	.hw.init = &(struct clk_init_data){
1269	.name = "gcc_gpu_gpll0_clk",
1270	.parent_hws = (const struct clk_hw*[]){
1271	&gpll0.clkr.hw,
1272	},
1273	.num_parents = 1,
1274	.ops = &clk_branch2_ops,
1275	},
1276	},
1277	};
1278
1279	static struct clk_branch gcc_gpu_gpll0_div_clk = {
1280	.halt_check = BRANCH_HALT_DELAY,
1281	.clkr = {
1282	.enable_reg = 0x52008,
1283	.enable_mask = BIT(8),
1284	.hw.init = &(struct clk_init_data){
1285	.name = "gcc_gpu_gpll0_div_clk",
1286	.parent_hws = (const struct clk_hw*[]){
1287	&gcc_gpu_gpll0_main_div_clk_src.clkr.hw,
1288	},
1289	.num_parents = 1,
1290	.ops = &clk_branch2_ops,
1291	},
1292	},
1293	};
1294
1295	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1296	.halt_reg = 0x4500c,
1297	.halt_check = BRANCH_VOTED,
1298	.hwcg_reg = 0x4500c,
1299	.hwcg_bit = 1,
1300	.clkr = {
1301	.enable_reg = 0x4500c,
1302	.enable_mask = BIT(0),
1303	.hw.init = &(struct clk_init_data){
1304	.name = "gcc_gpu_memnoc_gfx_clk",
1305	.ops = &clk_branch2_ops,
1306	},
1307	},
1308	};
1309
1310	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1311	.halt_reg = 0x45014,
1312	.halt_check = BRANCH_HALT,
1313	.hwcg_reg = 0x45014,
1314	.hwcg_bit = 1,
1315	.clkr = {
1316	.enable_reg = 0x45014,
1317	.enable_mask = BIT(0),
1318	.hw.init = &(struct clk_init_data){
1319	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1320	.ops = &clk_branch2_ops,
1321	},
1322	},
1323	};
1324
1325	static struct clk_branch gcc_npu_axi_clk = {
1326	.halt_reg = 0x4c008,
1327	.halt_check = BRANCH_VOTED,
1328	.hwcg_reg = 0x4c008,
1329	.hwcg_bit = 1,
1330	.clkr = {
1331	.enable_reg = 0x4c008,
1332	.enable_mask = BIT(0),
1333	.hw.init = &(struct clk_init_data){
1334	.name = "gcc_npu_axi_clk",
1335	.ops = &clk_branch2_ops,
1336	},
1337	},
1338	};
1339
1340	static struct clk_branch gcc_npu_bwmon_axi_clk = {
1341	.halt_reg = 0x4d004,
1342	.halt_check = BRANCH_HALT_DELAY,
1343	.hwcg_reg = 0x4d004,
1344	.hwcg_bit = 1,
1345	.clkr = {
1346	.enable_reg = 0x4d004,
1347	.enable_mask = BIT(0),
1348	.hw.init = &(struct clk_init_data){
1349	.name = "gcc_npu_bwmon_axi_clk",
1350	.ops = &clk_branch2_ops,
1351	},
1352	},
1353	};
1354
1355	static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1356	.halt_reg = 0x4d008,
1357	.halt_check = BRANCH_HALT,
1358	.clkr = {
1359	.enable_reg = 0x4d008,
1360	.enable_mask = BIT(0),
1361	.hw.init = &(struct clk_init_data){
1362	.name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1363	.ops = &clk_branch2_ops,
1364	},
1365	},
1366	};
1367
1368	static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1369	.halt_reg = 0x4d00c,
1370	.halt_check = BRANCH_HALT,
1371	.clkr = {
1372	.enable_reg = 0x4d00c,
1373	.enable_mask = BIT(0),
1374	.hw.init = &(struct clk_init_data){
1375	.name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1376	.ops = &clk_branch2_ops,
1377	},
1378	},
1379	};
1380
1381	static struct clk_branch gcc_npu_cfg_ahb_clk = {
1382	.halt_reg = 0x4c004,
1383	.halt_check = BRANCH_HALT,
1384	.hwcg_reg = 0x4c004,
1385	.hwcg_bit = 1,
1386	.clkr = {
1387	.enable_reg = 0x4c004,
1388	.enable_mask = BIT(0),
1389	.hw.init = &(struct clk_init_data){
1390	.name = "gcc_npu_cfg_ahb_clk",
1391	.flags = CLK_IS_CRITICAL,
1392	.ops = &clk_branch2_ops,
1393	},
1394	},
1395	};
1396
1397	static struct clk_branch gcc_npu_dma_clk = {
1398	.halt_reg = 0x4c140,
1399	.halt_check = BRANCH_VOTED,
1400	.hwcg_reg = 0x4c140,
1401	.hwcg_bit = 1,
1402	.clkr = {
1403	.enable_reg = 0x4c140,
1404	.enable_mask = BIT(0),
1405	.hw.init = &(struct clk_init_data){
1406	.name = "gcc_npu_dma_clk",
1407	.ops = &clk_branch2_ops,
1408	},
1409	},
1410	};
1411
1412	static struct clk_branch gcc_npu_gpll0_clk = {
1413	.halt_check = BRANCH_HALT_DELAY,
1414	.clkr = {
1415	.enable_reg = 0x52008,
1416	.enable_mask = BIT(9),
1417	.hw.init = &(struct clk_init_data){
1418	.name = "gcc_npu_gpll0_clk",
1419	.parent_hws = (const struct clk_hw*[]){
1420	&gpll0.clkr.hw,
1421	},
1422	.num_parents = 1,
1423	.ops = &clk_branch2_ops,
1424	},
1425	},
1426	};
1427
1428	static struct clk_branch gcc_npu_gpll0_div_clk = {
1429	.halt_check = BRANCH_HALT_DELAY,
1430	.clkr = {
1431	.enable_reg = 0x52008,
1432	.enable_mask = BIT(10),
1433	.hw.init = &(struct clk_init_data){
1434	.name = "gcc_npu_gpll0_div_clk",
1435	.parent_hws = (const struct clk_hw*[]){
1436	&gcc_npu_pll0_main_div_clk_src.clkr.hw,
1437	},
1438	.num_parents = 1,
1439	.ops = &clk_branch2_ops,
1440	},
1441	},
1442	};
1443
1444	static struct clk_branch gcc_pdm2_clk = {
1445	.halt_reg = 0x2300c,
1446	.halt_check = BRANCH_HALT,
1447	.clkr = {
1448	.enable_reg = 0x2300c,
1449	.enable_mask = BIT(0),
1450	.hw.init = &(struct clk_init_data){
1451	.name = "gcc_pdm2_clk",
1452	.parent_hws = (const struct clk_hw*[]){
1453	&gcc_pdm2_clk_src.clkr.hw,
1454	},
1455	.num_parents = 1,
1456	.flags = CLK_SET_RATE_PARENT,
1457	.ops = &clk_branch2_ops,
1458	},
1459	},
1460	};
1461
1462	static struct clk_branch gcc_pdm_ahb_clk = {
1463	.halt_reg = 0x23004,
1464	.halt_check = BRANCH_HALT,
1465	.hwcg_reg = 0x23004,
1466	.hwcg_bit = 1,
1467	.clkr = {
1468	.enable_reg = 0x23004,
1469	.enable_mask = BIT(0),
1470	.hw.init = &(struct clk_init_data){
1471	.name = "gcc_pdm_ahb_clk",
1472	.ops = &clk_branch2_ops,
1473	},
1474	},
1475	};
1476
1477	static struct clk_branch gcc_pdm_xo4_clk = {
1478	.halt_reg = 0x23008,
1479	.halt_check = BRANCH_HALT,
1480	.clkr = {
1481	.enable_reg = 0x23008,
1482	.enable_mask = BIT(0),
1483	.hw.init = &(struct clk_init_data){
1484	.name = "gcc_pdm_xo4_clk",
1485	.ops = &clk_branch2_ops,
1486	},
1487	},
1488	};
1489
1490	static struct clk_branch gcc_prng_ahb_clk = {
1491	.halt_reg = 0x24004,
1492	.halt_check = BRANCH_HALT_VOTED,
1493	.hwcg_reg = 0x24004,
1494	.hwcg_bit = 1,
1495	.clkr = {
1496	.enable_reg = 0x52000,
1497	.enable_mask = BIT(26),
1498	.hw.init = &(struct clk_init_data){
1499	.name = "gcc_prng_ahb_clk",
1500	.ops = &clk_branch2_ops,
1501	},
1502	},
1503	};
1504
1505	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1506	.halt_reg = 0x21014,
1507	.halt_check = BRANCH_HALT_VOTED,
1508	.clkr = {
1509	.enable_reg = 0x52000,
1510	.enable_mask = BIT(9),
1511	.hw.init = &(struct clk_init_data){
1512	.name = "gcc_qupv3_wrap0_core_2x_clk",
1513	.ops = &clk_branch2_ops,
1514	},
1515	},
1516	};
1517
1518	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1519	.halt_reg = 0x2100c,
1520	.halt_check = BRANCH_HALT_VOTED,
1521	.clkr = {
1522	.enable_reg = 0x52000,
1523	.enable_mask = BIT(8),
1524	.hw.init = &(struct clk_init_data){
1525	.name = "gcc_qupv3_wrap0_core_clk",
1526	.ops = &clk_branch2_ops,
1527	},
1528	},
1529	};
1530
1531	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1532	.halt_reg = 0x21144,
1533	.halt_check = BRANCH_HALT_VOTED,
1534	.clkr = {
1535	.enable_reg = 0x52000,
1536	.enable_mask = BIT(10),
1537	.hw.init = &(struct clk_init_data){
1538	.name = "gcc_qupv3_wrap0_s0_clk",
1539	.parent_hws = (const struct clk_hw*[]){
1540	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1541	},
1542	.num_parents = 1,
1543	.flags = CLK_SET_RATE_PARENT,
1544	.ops = &clk_branch2_ops,
1545	},
1546	},
1547	};
1548
1549	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1550	.halt_reg = 0x21274,
1551	.halt_check = BRANCH_HALT_VOTED,
1552	.clkr = {
1553	.enable_reg = 0x52000,
1554	.enable_mask = BIT(11),
1555	.hw.init = &(struct clk_init_data){
1556	.name = "gcc_qupv3_wrap0_s1_clk",
1557	.parent_hws = (const struct clk_hw*[]){
1558	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1559	},
1560	.num_parents = 1,
1561	.flags = CLK_SET_RATE_PARENT,
1562	.ops = &clk_branch2_ops,
1563	},
1564	},
1565	};
1566
1567	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1568	.halt_reg = 0x213a4,
1569	.halt_check = BRANCH_HALT_VOTED,
1570	.clkr = {
1571	.enable_reg = 0x52000,
1572	.enable_mask = BIT(12),
1573	.hw.init = &(struct clk_init_data){
1574	.name = "gcc_qupv3_wrap0_s2_clk",
1575	.parent_hws = (const struct clk_hw*[]){
1576	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1577	},
1578	.num_parents = 1,
1579	.flags = CLK_SET_RATE_PARENT,
1580	.ops = &clk_branch2_ops,
1581	},
1582	},
1583	};
1584
1585	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1586	.halt_reg = 0x214d4,
1587	.halt_check = BRANCH_HALT_VOTED,
1588	.clkr = {
1589	.enable_reg = 0x52000,
1590	.enable_mask = BIT(13),
1591	.hw.init = &(struct clk_init_data){
1592	.name = "gcc_qupv3_wrap0_s3_clk",
1593	.parent_hws = (const struct clk_hw*[]){
1594	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1595	},
1596	.num_parents = 1,
1597	.flags = CLK_SET_RATE_PARENT,
1598	.ops = &clk_branch2_ops,
1599	},
1600	},
1601	};
1602
1603	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1604	.halt_reg = 0x21604,
1605	.halt_check = BRANCH_HALT_VOTED,
1606	.clkr = {
1607	.enable_reg = 0x52000,
1608	.enable_mask = BIT(14),
1609	.hw.init = &(struct clk_init_data){
1610	.name = "gcc_qupv3_wrap0_s4_clk",
1611	.parent_hws = (const struct clk_hw*[]){
1612	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1613	},
1614	.num_parents = 1,
1615	.flags = CLK_SET_RATE_PARENT,
1616	.ops = &clk_branch2_ops,
1617	},
1618	},
1619	};
1620
1621	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1622	.halt_reg = 0x21734,
1623	.halt_check = BRANCH_HALT_VOTED,
1624	.clkr = {
1625	.enable_reg = 0x52000,
1626	.enable_mask = BIT(15),
1627	.hw.init = &(struct clk_init_data){
1628	.name = "gcc_qupv3_wrap0_s5_clk",
1629	.parent_hws = (const struct clk_hw*[]){
1630	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1631	},
1632	.num_parents = 1,
1633	.flags = CLK_SET_RATE_PARENT,
1634	.ops = &clk_branch2_ops,
1635	},
1636	},
1637	};
1638
1639	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1640	.halt_reg = 0x22004,
1641	.halt_check = BRANCH_HALT_VOTED,
1642	.clkr = {
1643	.enable_reg = 0x52000,
1644	.enable_mask = BIT(16),
1645	.hw.init = &(struct clk_init_data){
1646	.name = "gcc_qupv3_wrap1_core_2x_clk",
1647	.ops = &clk_branch2_ops,
1648	},
1649	},
1650	};
1651
1652	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1653	.halt_reg = 0x22008,
1654	.halt_check = BRANCH_HALT_VOTED,
1655	.clkr = {
1656	.enable_reg = 0x52000,
1657	.enable_mask = BIT(17),
1658	.hw.init = &(struct clk_init_data){
1659	.name = "gcc_qupv3_wrap1_core_clk",
1660	.ops = &clk_branch2_ops,
1661	},
1662	},
1663	};
1664
1665	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1666	.halt_reg = 0x22014,
1667	.halt_check = BRANCH_HALT_VOTED,
1668	.clkr = {
1669	.enable_reg = 0x52000,
1670	.enable_mask = BIT(20),
1671	.hw.init = &(struct clk_init_data){
1672	.name = "gcc_qupv3_wrap1_s0_clk",
1673	.parent_hws = (const struct clk_hw*[]){
1674	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1675	},
1676	.num_parents = 1,
1677	.flags = CLK_SET_RATE_PARENT,
1678	.ops = &clk_branch2_ops,
1679	},
1680	},
1681	};
1682
1683	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1684	.halt_reg = 0x22144,
1685	.halt_check = BRANCH_HALT_VOTED,
1686	.clkr = {
1687	.enable_reg = 0x52000,
1688	.enable_mask = BIT(21),
1689	.hw.init = &(struct clk_init_data){
1690	.name = "gcc_qupv3_wrap1_s1_clk",
1691	.parent_hws = (const struct clk_hw*[]){
1692	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1693	},
1694	.num_parents = 1,
1695	.flags = CLK_SET_RATE_PARENT,
1696	.ops = &clk_branch2_ops,
1697	},
1698	},
1699	};
1700
1701	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1702	.halt_reg = 0x22274,
1703	.halt_check = BRANCH_HALT_VOTED,
1704	.clkr = {
1705	.enable_reg = 0x52000,
1706	.enable_mask = BIT(22),
1707	.hw.init = &(struct clk_init_data){
1708	.name = "gcc_qupv3_wrap1_s2_clk",
1709	.parent_hws = (const struct clk_hw*[]){
1710	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1711	},
1712	.num_parents = 1,
1713	.flags = CLK_SET_RATE_PARENT,
1714	.ops = &clk_branch2_ops,
1715	},
1716	},
1717	};
1718
1719	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1720	.halt_reg = 0x223a4,
1721	.halt_check = BRANCH_HALT_VOTED,
1722	.clkr = {
1723	.enable_reg = 0x52000,
1724	.enable_mask = BIT(23),
1725	.hw.init = &(struct clk_init_data){
1726	.name = "gcc_qupv3_wrap1_s3_clk",
1727	.parent_hws = (const struct clk_hw*[]){
1728	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1729	},
1730	.num_parents = 1,
1731	.flags = CLK_SET_RATE_PARENT,
1732	.ops = &clk_branch2_ops,
1733	},
1734	},
1735	};
1736
1737	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1738	.halt_reg = 0x224d4,
1739	.halt_check = BRANCH_HALT_VOTED,
1740	.clkr = {
1741	.enable_reg = 0x52000,
1742	.enable_mask = BIT(24),
1743	.hw.init = &(struct clk_init_data){
1744	.name = "gcc_qupv3_wrap1_s4_clk",
1745	.parent_hws = (const struct clk_hw*[]){
1746	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1747	},
1748	.num_parents = 1,
1749	.flags = CLK_SET_RATE_PARENT,
1750	.ops = &clk_branch2_ops,
1751	},
1752	},
1753	};
1754
1755	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1756	.halt_reg = 0x22604,
1757	.halt_check = BRANCH_HALT_VOTED,
1758	.clkr = {
1759	.enable_reg = 0x52000,
1760	.enable_mask = BIT(25),
1761	.hw.init = &(struct clk_init_data){
1762	.name = "gcc_qupv3_wrap1_s5_clk",
1763	.parent_hws = (const struct clk_hw*[]){
1764	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1765	},
1766	.num_parents = 1,
1767	.flags = CLK_SET_RATE_PARENT,
1768	.ops = &clk_branch2_ops,
1769	},
1770	},
1771	};
1772
1773	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1774	.halt_reg = 0x21004,
1775	.halt_check = BRANCH_HALT_VOTED,
1776	.hwcg_reg = 0x21004,
1777	.hwcg_bit = 1,
1778	.clkr = {
1779	.enable_reg = 0x52000,
1780	.enable_mask = BIT(6),
1781	.hw.init = &(struct clk_init_data){
1782	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
1783	.ops = &clk_branch2_ops,
1784	},
1785	},
1786	};
1787
1788	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1789	.halt_reg = 0x21008,
1790	.halt_check = BRANCH_HALT_VOTED,
1791	.hwcg_reg = 0x21008,
1792	.hwcg_bit = 1,
1793	.clkr = {
1794	.enable_reg = 0x52000,
1795	.enable_mask = BIT(7),
1796	.hw.init = &(struct clk_init_data){
1797	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
1798	.ops = &clk_branch2_ops,
1799	},
1800	},
1801	};
1802
1803	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1804	.halt_reg = 0x2200c,
1805	.halt_check = BRANCH_HALT_VOTED,
1806	.hwcg_reg = 0x2200c,
1807	.hwcg_bit = 1,
1808	.clkr = {
1809	.enable_reg = 0x52000,
1810	.enable_mask = BIT(18),
1811	.hw.init = &(struct clk_init_data){
1812	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
1813	.ops = &clk_branch2_ops,
1814	},
1815	},
1816	};
1817
1818	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1819	.halt_reg = 0x22010,
1820	.halt_check = BRANCH_HALT_VOTED,
1821	.hwcg_reg = 0x22010,
1822	.hwcg_bit = 1,
1823	.clkr = {
1824	.enable_reg = 0x52000,
1825	.enable_mask = BIT(19),
1826	.hw.init = &(struct clk_init_data){
1827	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
1828	.ops = &clk_branch2_ops,
1829	},
1830	},
1831	};
1832
1833	static struct clk_branch gcc_sdcc1_ahb_clk = {
1834	.halt_reg = 0x4b004,
1835	.halt_check = BRANCH_HALT,
1836	.clkr = {
1837	.enable_reg = 0x4b004,
1838	.enable_mask = BIT(0),
1839	.hw.init = &(struct clk_init_data){
1840	.name = "gcc_sdcc1_ahb_clk",
1841	.ops = &clk_branch2_ops,
1842	},
1843	},
1844	};
1845
1846	static struct clk_branch gcc_sdcc1_apps_clk = {
1847	.halt_reg = 0x4b008,
1848	.halt_check = BRANCH_HALT,
1849	.clkr = {
1850	.enable_reg = 0x4b008,
1851	.enable_mask = BIT(0),
1852	.hw.init = &(struct clk_init_data){
1853	.name = "gcc_sdcc1_apps_clk",
1854	.parent_hws = (const struct clk_hw*[]){
1855	&gcc_sdcc1_apps_clk_src.clkr.hw,
1856	},
1857	.num_parents = 1,
1858	.flags = CLK_SET_RATE_PARENT,
1859	.ops = &clk_branch2_ops,
1860	},
1861	},
1862	};
1863
1864	static struct clk_branch gcc_sdcc1_ice_core_clk = {
1865	.halt_reg = 0x4b03c,
1866	.halt_check = BRANCH_HALT,
1867	.hwcg_reg = 0x4b03c,
1868	.hwcg_bit = 1,
1869	.clkr = {
1870	.enable_reg = 0x4b03c,
1871	.enable_mask = BIT(0),
1872	.hw.init = &(struct clk_init_data){
1873	.name = "gcc_sdcc1_ice_core_clk",
1874	.parent_hws = (const struct clk_hw*[]){
1875	&gcc_sdcc1_ice_core_clk_src.clkr.hw,
1876	},
1877	.num_parents = 1,
1878	.flags = CLK_SET_RATE_PARENT,
1879	.ops = &clk_branch2_ops,
1880	},
1881	},
1882	};
1883
1884	static struct clk_branch gcc_sdcc2_ahb_clk = {
1885	.halt_reg = 0x20008,
1886	.halt_check = BRANCH_HALT,
1887	.clkr = {
1888	.enable_reg = 0x20008,
1889	.enable_mask = BIT(0),
1890	.hw.init = &(struct clk_init_data){
1891	.name = "gcc_sdcc2_ahb_clk",
1892	.ops = &clk_branch2_ops,
1893	},
1894	},
1895	};
1896
1897	static struct clk_branch gcc_sdcc2_apps_clk = {
1898	.halt_reg = 0x20004,
1899	.halt_check = BRANCH_HALT,
1900	.clkr = {
1901	.enable_reg = 0x20004,
1902	.enable_mask = BIT(0),
1903	.hw.init = &(struct clk_init_data){
1904	.name = "gcc_sdcc2_apps_clk",
1905	.parent_hws = (const struct clk_hw*[]){
1906	&gcc_sdcc2_apps_clk_src.clkr.hw,
1907	},
1908	.num_parents = 1,
1909	.flags = CLK_SET_RATE_PARENT,
1910	.ops = &clk_branch2_ops,
1911	},
1912	},
1913	};
1914
1915	static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1916	.halt_reg = 0x10140,
1917	.halt_check = BRANCH_HALT_VOTED,
1918	.hwcg_reg = 0x10140,
1919	.hwcg_bit = 1,
1920	.clkr = {
1921	.enable_reg = 0x52000,
1922	.enable_mask = BIT(0),
1923	.hw.init = &(struct clk_init_data){
1924	.name = "gcc_sys_noc_cpuss_ahb_clk",
1925	.parent_hws = (const struct clk_hw*[]){
1926	&gcc_cpuss_ahb_clk_src.clkr.hw,
1927	},
1928	.num_parents = 1,
1929	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1930	.ops = &clk_branch2_ops,
1931	},
1932	},
1933	};
1934
1935	static struct clk_branch gcc_ufs_mem_clkref_clk = {
1936	.halt_reg = 0x8c000,
1937	.halt_check = BRANCH_HALT,
1938	.clkr = {
1939	.enable_reg = 0x8c000,
1940	.enable_mask = BIT(0),
1941	.hw.init = &(struct clk_init_data){
1942	.name = "gcc_ufs_mem_clkref_clk",
1943	.ops = &clk_branch2_ops,
1944	},
1945	},
1946	};
1947
1948	static struct clk_branch gcc_ufs_phy_ahb_clk = {
1949	.halt_reg = 0x3a00c,
1950	.halt_check = BRANCH_HALT,
1951	.hwcg_reg = 0x3a00c,
1952	.hwcg_bit = 1,
1953	.clkr = {
1954	.enable_reg = 0x3a00c,
1955	.enable_mask = BIT(0),
1956	.hw.init = &(struct clk_init_data){
1957	.name = "gcc_ufs_phy_ahb_clk",
1958	.ops = &clk_branch2_ops,
1959	},
1960	},
1961	};
1962
1963	static struct clk_branch gcc_ufs_phy_axi_clk = {
1964	.halt_reg = 0x3a034,
1965	.halt_check = BRANCH_HALT,
1966	.hwcg_reg = 0x3a034,
1967	.hwcg_bit = 1,
1968	.clkr = {
1969	.enable_reg = 0x3a034,
1970	.enable_mask = BIT(0),
1971	.hw.init = &(struct clk_init_data){
1972	.name = "gcc_ufs_phy_axi_clk",
1973	.parent_hws = (const struct clk_hw*[]){
1974	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1975	},
1976	.num_parents = 1,
1977	.flags = CLK_SET_RATE_PARENT,
1978	.ops = &clk_branch2_ops,
1979	},
1980	},
1981	};
1982
1983	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1984	.halt_reg = 0x3a0a4,
1985	.halt_check = BRANCH_HALT,
1986	.hwcg_reg = 0x3a0a4,
1987	.hwcg_bit = 1,
1988	.clkr = {
1989	.enable_reg = 0x3a0a4,
1990	.enable_mask = BIT(0),
1991	.hw.init = &(struct clk_init_data){
1992	.name = "gcc_ufs_phy_ice_core_clk",
1993	.parent_hws = (const struct clk_hw*[]){
1994	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1995	},
1996	.num_parents = 1,
1997	.flags = CLK_SET_RATE_PARENT,
1998	.ops = &clk_branch2_ops,
1999	},
2000	},
2001	};
2002
2003	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2004	.halt_reg = 0x3a0a4,
2005	.halt_check = BRANCH_HALT,
2006	.hwcg_reg = 0x3a0a4,
2007	.hwcg_bit = 1,
2008	.clkr = {
2009	.enable_reg = 0x3a0a4,
2010	.enable_mask = BIT(1),
2011	.hw.init = &(struct clk_init_data){
2012	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2013	.parent_hws = (const struct clk_hw*[]){
2014	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2015	},
2016	.num_parents = 1,
2017	.flags = CLK_SET_RATE_PARENT,
2018	.ops = &clk_branch2_ops,
2019	},
2020	},
2021	};
2022
2023	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2024	.halt_reg = 0x3a0ac,
2025	.halt_check = BRANCH_HALT,
2026	.hwcg_reg = 0x3a0ac,
2027	.hwcg_bit = 1,
2028	.clkr = {
2029	.enable_reg = 0x3a0ac,
2030	.enable_mask = BIT(0),
2031	.hw.init = &(struct clk_init_data){
2032	.name = "gcc_ufs_phy_phy_aux_clk",
2033	.parent_hws = (const struct clk_hw*[]){
2034	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2035	},
2036	.num_parents = 1,
2037	.flags = CLK_SET_RATE_PARENT,
2038	.ops = &clk_branch2_ops,
2039	},
2040	},
2041	};
2042
2043	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2044	.halt_reg = 0x3a0ac,
2045	.halt_check = BRANCH_HALT,
2046	.hwcg_reg = 0x3a0ac,
2047	.hwcg_bit = 1,
2048	.clkr = {
2049	.enable_reg = 0x3a0ac,
2050	.enable_mask = BIT(1),
2051	.hw.init = &(struct clk_init_data){
2052	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2053	.parent_hws = (const struct clk_hw*[]){
2054	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2055	},
2056	.num_parents = 1,
2057	.flags = CLK_SET_RATE_PARENT,
2058	.ops = &clk_branch2_ops,
2059	},
2060	},
2061	};
2062
2063	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2064	.halt_reg = 0x3a014,
2065	.halt_check = BRANCH_HALT_SKIP,
2066	.clkr = {
2067	.enable_reg = 0x3a014,
2068	.enable_mask = BIT(0),
2069	.hw.init = &(struct clk_init_data){
2070	.name = "gcc_ufs_phy_rx_symbol_0_clk",
2071	.ops = &clk_branch2_ops,
2072	},
2073	},
2074	};
2075
2076	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2077	.halt_reg = 0x3a018,
2078	.halt_check = BRANCH_HALT_SKIP,
2079	.clkr = {
2080	.enable_reg = 0x3a018,
2081	.enable_mask = BIT(0),
2082	.hw.init = &(struct clk_init_data){
2083	.name = "gcc_ufs_phy_rx_symbol_1_clk",
2084	.ops = &clk_branch2_ops,
2085	},
2086	},
2087	};
2088
2089	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2090	.halt_reg = 0x3a010,
2091	.halt_check = BRANCH_HALT_SKIP,
2092	.clkr = {
2093	.enable_reg = 0x3a010,
2094	.enable_mask = BIT(0),
2095	.hw.init = &(struct clk_init_data){
2096	.name = "gcc_ufs_phy_tx_symbol_0_clk",
2097	.ops = &clk_branch2_ops,
2098	},
2099	},
2100	};
2101
2102	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2103	.halt_reg = 0x3a09c,
2104	.halt_check = BRANCH_HALT,
2105	.hwcg_reg = 0x3a09c,
2106	.hwcg_bit = 1,
2107	.clkr = {
2108	.enable_reg = 0x3a09c,
2109	.enable_mask = BIT(0),
2110	.hw.init = &(struct clk_init_data){
2111	.name = "gcc_ufs_phy_unipro_core_clk",
2112	.parent_hws = (const struct clk_hw*[]){
2113	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2114	},
2115	.num_parents = 1,
2116	.flags = CLK_SET_RATE_PARENT,
2117	.ops = &clk_branch2_ops,
2118	},
2119	},
2120	};
2121
2122	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2123	.halt_reg = 0x3a09c,
2124	.halt_check = BRANCH_HALT,
2125	.hwcg_reg = 0x3a09c,
2126	.hwcg_bit = 1,
2127	.clkr = {
2128	.enable_reg = 0x3a09c,
2129	.enable_mask = BIT(1),
2130	.hw.init = &(struct clk_init_data){
2131	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2132	.parent_hws = (const struct clk_hw*[]){
2133	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2134	},
2135	.num_parents = 1,
2136	.flags = CLK_SET_RATE_PARENT,
2137	.ops = &clk_branch2_ops,
2138	},
2139	},
2140	};
2141
2142	static struct clk_branch gcc_usb30_prim_master_clk = {
2143	.halt_reg = 0x1a00c,
2144	.halt_check = BRANCH_HALT,
2145	.clkr = {
2146	.enable_reg = 0x1a00c,
2147	.enable_mask = BIT(0),
2148	.hw.init = &(struct clk_init_data){
2149	.name = "gcc_usb30_prim_master_clk",
2150	.parent_hws = (const struct clk_hw*[]){
2151	&gcc_usb30_prim_master_clk_src.clkr.hw,
2152	},
2153	.num_parents = 1,
2154	.flags = CLK_SET_RATE_PARENT,
2155	.ops = &clk_branch2_ops,
2156	},
2157	},
2158	};
2159
2160	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2161	.halt_reg = 0x1a018,
2162	.halt_check = BRANCH_HALT,
2163	.clkr = {
2164	.enable_reg = 0x1a018,
2165	.enable_mask = BIT(0),
2166	.hw.init = &(struct clk_init_data){
2167	.name = "gcc_usb30_prim_mock_utmi_clk",
2168	.parent_hws = (const struct clk_hw*[]){
2169	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2170	},
2171	.num_parents = 1,
2172	.flags = CLK_SET_RATE_PARENT,
2173	.ops = &clk_branch2_ops,
2174	},
2175	},
2176	};
2177
2178	static struct clk_branch gcc_usb30_prim_sleep_clk = {
2179	.halt_reg = 0x1a014,
2180	.halt_check = BRANCH_HALT,
2181	.clkr = {
2182	.enable_reg = 0x1a014,
2183	.enable_mask = BIT(0),
2184	.hw.init = &(struct clk_init_data){
2185	.name = "gcc_usb30_prim_sleep_clk",
2186	.ops = &clk_branch2_ops,
2187	},
2188	},
2189	};
2190
2191	static struct clk_branch gcc_usb3_prim_clkref_clk = {
2192	.halt_reg = 0x8c010,
2193	.halt_check = BRANCH_HALT,
2194	.clkr = {
2195	.enable_reg = 0x8c010,
2196	.enable_mask = BIT(0),
2197	.hw.init = &(struct clk_init_data){
2198	.name = "gcc_usb3_prim_clkref_clk",
2199	.ops = &clk_branch2_ops,
2200	},
2201	},
2202	};
2203
2204	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2205	.halt_reg = 0x1a050,
2206	.halt_check = BRANCH_HALT,
2207	.clkr = {
2208	.enable_reg = 0x1a050,
2209	.enable_mask = BIT(0),
2210	.hw.init = &(struct clk_init_data){
2211	.name = "gcc_usb3_prim_phy_aux_clk",
2212	.parent_hws = (const struct clk_hw*[]){
2213	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2214	},
2215	.num_parents = 1,
2216	.flags = CLK_SET_RATE_PARENT,
2217	.ops = &clk_branch2_ops,
2218	},
2219	},
2220	};
2221
2222	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2223	.halt_reg = 0x1a054,
2224	.halt_check = BRANCH_HALT,
2225	.clkr = {
2226	.enable_reg = 0x1a054,
2227	.enable_mask = BIT(0),
2228	.hw.init = &(struct clk_init_data){
2229	.name = "gcc_usb3_prim_phy_com_aux_clk",
2230	.parent_hws = (const struct clk_hw*[]){
2231	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2232	},
2233	.num_parents = 1,
2234	.flags = CLK_SET_RATE_PARENT,
2235	.ops = &clk_branch2_ops,
2236	},
2237	},
2238	};
2239
2240	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2241	.halt_reg = 0x1a058,
2242	.halt_check = BRANCH_HALT_SKIP,
2243	.hwcg_reg = 0x1a058,
2244	.hwcg_bit = 1,
2245	.clkr = {
2246	.enable_reg = 0x1a058,
2247	.enable_mask = BIT(0),
2248	.hw.init = &(struct clk_init_data){
2249	.name = "gcc_usb3_prim_phy_pipe_clk",
2250	.ops = &clk_branch2_ops,
2251	},
2252	},
2253	};
2254
2255	static struct clk_branch gcc_video_ahb_clk = {
2256	.halt_reg = 0x17004,
2257	.halt_check = BRANCH_HALT,
2258	.hwcg_reg = 0x17004,
2259	.hwcg_bit = 1,
2260	.clkr = {
2261	.enable_reg = 0x17004,
2262	.enable_mask = BIT(0),
2263	.hw.init = &(struct clk_init_data){
2264	.name = "gcc_video_ahb_clk",
2265	.flags = CLK_IS_CRITICAL,
2266	.ops = &clk_branch2_ops,
2267	},
2268	},
2269	};
2270
2271	static struct clk_branch gcc_video_axi_clk = {
2272	.halt_reg = 0x17014,
2273	.halt_check = BRANCH_HALT,
2274	.hwcg_reg = 0x17014,
2275	.hwcg_bit = 1,
2276	.clkr = {
2277	.enable_reg = 0x17014,
2278	.enable_mask = BIT(0),
2279	.hw.init = &(struct clk_init_data){
2280	.name = "gcc_video_axi_clk",
2281	.ops = &clk_branch2_ops,
2282	},
2283	},
2284	};
2285
2286	static struct clk_branch gcc_video_throttle_axi_clk = {
2287	.halt_reg = 0x17020,
2288	.halt_check = BRANCH_HALT,
2289	.hwcg_reg = 0x17020,
2290	.hwcg_bit = 1,
2291	.clkr = {
2292	.enable_reg = 0x17020,
2293	.enable_mask = BIT(0),
2294	.hw.init = &(struct clk_init_data){
2295	.name = "gcc_video_throttle_axi_clk",
2296	.ops = &clk_branch2_ops,
2297	},
2298	},
2299	};
2300
2301	static struct clk_branch gcc_video_xo_clk = {
2302	.halt_reg = 0x1702c,
2303	.halt_check = BRANCH_HALT,
2304	.clkr = {
2305	.enable_reg = 0x1702c,
2306	.enable_mask = BIT(0),
2307	.hw.init = &(struct clk_init_data){
2308	.name = "gcc_video_xo_clk",
2309	.flags = CLK_IS_CRITICAL,
2310	.ops = &clk_branch2_ops,
2311	},
2312	},
2313	};
2314
2315	static struct gdsc usb30_prim_gdsc = {
2316	.gdscr = 0x1a004,
2317	.pd = {
2318	.name = "usb30_prim_gdsc",
2319	},
2320	.pwrsts = PWRSTS_RET_ON,
2321	};
2322
2323	static struct gdsc ufs_phy_gdsc = {
2324	.gdscr = 0x3a004,
2325	.pd = {
2326	.name = "ufs_phy_gdsc",
2327	},
2328	.pwrsts = PWRSTS_OFF_ON,
2329	};
2330
2331	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2332	.gdscr = 0xb7040,
2333	.pd = {
2334	.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2335	},
2336	.pwrsts = PWRSTS_OFF_ON,
2337	.flags = VOTABLE,
2338	};
2339
2340	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2341	.gdscr = 0xb7044,
2342	.pd = {
2343	.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2344	},
2345	.pwrsts = PWRSTS_OFF_ON,
2346	.flags = VOTABLE,
2347	};
2348
2349	static struct clk_regmap *gcc_sm6350_clocks[] = {
2350	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2351	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2352	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2353	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2354	[GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
2355	[GCC_CAMERA_THROTTLE_NRT_AXI_CLK] =
2356	&gcc_camera_throttle_nrt_axi_clk.clkr,
2357	[GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
2358	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2359	[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2360	[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2361	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2362	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2363	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2364	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2365	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
2366	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2367	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2368	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2369	[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
2370	[GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr,
2371	[GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr,
2372	[GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr,
2373	[GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr,
2374	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2375	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2376	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2377	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2378	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2379	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2380	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2381	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2382	[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2383	[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2384	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2385	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2386	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2387	[GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2388	[GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2389	[GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2390	[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2391	[GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2392	[GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr,
2393	[GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr,
2394	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2395	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2396	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2397	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2398	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2399	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2400	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2401	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2402	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2403	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2404	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2405	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2406	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2407	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2408	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2409	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2410	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2411	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2412	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2413	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2414	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2415	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2416	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2417	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2418	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2419	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2420	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2421	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2422	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2423	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2424	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2425	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2426	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2427	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2428	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2429	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2430	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2431	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2432	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2433	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2434	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2435	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2436	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2437	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2438	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2439	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2440	[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2441	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2442	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2443	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2444	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2445	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2446	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2447	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2448	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2449	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
2450	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2451	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2452	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2453	&gcc_ufs_phy_unipro_core_clk_src.clkr,
2454	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2455	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2456	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2457	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2458	&gcc_usb30_prim_mock_utmi_clk_src.clkr,
2459	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2460	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2461	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2462	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2463	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2464	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2465	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2466	[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2467	[GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2468	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2469	[GPLL0] = &gpll0.clkr,
2470	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2471	[GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2472	[GPLL6] = &gpll6.clkr,
2473	[GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
2474	[GPLL7] = &gpll7.clkr,
2475	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2476	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2477	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
2478	&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2479	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
2480	&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2481	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
2482	&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2483	[GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr,
2484	[GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr,
2485	};
2486
2487	static struct gdsc *gcc_sm6350_gdscs[] = {
2488	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2489	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
2490	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2491	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2492	};
2493
2494	static const struct qcom_reset_map gcc_sm6350_resets[] = {
2495	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2496	[GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2497	[GCC_SDCC1_BCR] = { 0x4b000 },
2498	[GCC_SDCC2_BCR] = { 0x20000 },
2499	[GCC_UFS_PHY_BCR] = { 0x3a000 },
2500	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
2501	[GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2502	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2503	};
2504
2505	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2506	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2507	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2508	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2509	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2510	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2511	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2512	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2513	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2514	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2515	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2516	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2517	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2518	};
2519
2520	static const struct regmap_config gcc_sm6350_regmap_config = {
2521	.reg_bits = 32,
2522	.reg_stride = 4,
2523	.val_bits = 32,
2524	.max_register = 0xbf030,
2525	.fast_io = true,
2526	};
2527
2528	static const struct qcom_cc_desc gcc_sm6350_desc = {
2529	.config = &gcc_sm6350_regmap_config,
2530	.clks = gcc_sm6350_clocks,
2531	.num_clks = ARRAY_SIZE(gcc_sm6350_clocks),
2532	.resets = gcc_sm6350_resets,
2533	.num_resets = ARRAY_SIZE(gcc_sm6350_resets),
2534	.gdscs = gcc_sm6350_gdscs,
2535	.num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
2536	};
2537
2538	static const struct of_device_id gcc_sm6350_match_table[] = {
2539	{ .compatible = "qcom,gcc-sm6350" },
2540	{ }
2541	};
2542	MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table);
2543
2544	static int gcc_sm6350_probe(struct platform_device *pdev)
2545	{
2546	struct regmap *regmap;
2547	int ret;
2548
2549	regmap = qcom_cc_map(pdev, desc: &gcc_sm6350_desc);
2550	if (IS_ERR(ptr: regmap))
2551	return PTR_ERR(ptr: regmap);
2552
2553	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
2554	regmap_update_bits(map: regmap, reg: 0x4cf00, mask: 0x3, val: 0x3);
2555	regmap_update_bits(map: regmap, reg: 0x45f00, mask: 0x3, val: 0x3);
2556
2557	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
2558	ARRAY_SIZE(gcc_dfs_clocks));
2559	if (ret)
2560	return ret;
2561
2562	return qcom_cc_really_probe(pdev, desc: &gcc_sm6350_desc, regmap);
2563	}
2564
2565	static struct platform_driver gcc_sm6350_driver = {
2566	.probe = gcc_sm6350_probe,
2567	.driver = {
2568	.name = "gcc-sm6350",
2569	.of_match_table = gcc_sm6350_match_table,
2570	},
2571	};
2572
2573	static int __init gcc_sm6350_init(void)
2574	{
2575	return platform_driver_register(&gcc_sm6350_driver);
2576	}
2577	core_initcall(gcc_sm6350_init);
2578
2579	static void __exit gcc_sm6350_exit(void)
2580	{
2581	platform_driver_unregister(&gcc_sm6350_driver);
2582	}
2583	module_exit(gcc_sm6350_exit);
2584
2585	MODULE_DESCRIPTION("QTI GCC SM6350 Driver");
2586	MODULE_LICENSE("GPL v2");
2587