1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
5	*/
6
7	#include <linux/clk-provider.h>
8	#include <linux/module.h>
9	#include <linux/of.h>
10	#include <linux/platform_device.h>
11	#include <linux/regmap.h>
12
13	#include <dt-bindings/clock/qcom,sm6375-gcc.h>
14
15	#include "clk-alpha-pll.h"
16	#include "clk-branch.h"
17	#include "clk-rcg.h"
18	#include "clk-regmap.h"
19	#include "clk-regmap-divider.h"
20	#include "clk-regmap-mux.h"
21	#include "clk-regmap-phy-mux.h"
22	#include "gdsc.h"
23	#include "reset.h"
24
25	enum {
26	DT_BI_TCXO,
27	DT_BI_TCXO_AO,
28	DT_SLEEP_CLK
29	};
30
31	enum {
32	P_BI_TCXO,
33	P_GPLL0_OUT_EVEN,
34	P_GPLL0_OUT_MAIN,
35	P_GPLL0_OUT_ODD,
36	P_GPLL10_OUT_EVEN,
37	P_GPLL11_OUT_EVEN,
38	P_GPLL11_OUT_ODD,
39	P_GPLL3_OUT_EVEN,
40	P_GPLL3_OUT_MAIN,
41	P_GPLL4_OUT_EVEN,
42	P_GPLL5_OUT_EVEN,
43	P_GPLL6_OUT_EVEN,
44	P_GPLL6_OUT_MAIN,
45	P_GPLL7_OUT_EVEN,
46	P_GPLL8_OUT_EVEN,
47	P_GPLL8_OUT_MAIN,
48	P_GPLL9_OUT_EARLY,
49	P_GPLL9_OUT_MAIN,
50	P_SLEEP_CLK,
51	};
52
53	static struct pll_vco lucid_vco[] = {
54	{ 249600000, 2000000000, 0 },
55	};
56
57	static struct pll_vco zonda_vco[] = {
58	{ 595200000, 3600000000UL, 0 },
59	};
60
61	static struct clk_alpha_pll gpll0 = {
62	.offset = 0x0,
63	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
64	.clkr = {
65	.enable_reg = 0x79000,
66	.enable_mask = BIT(0),
67	.hw.init = &(struct clk_init_data){
68	.name = "gpll0",
69	.parent_data = &(const struct clk_parent_data){
70	.index = DT_BI_TCXO,
71	},
72	.num_parents = 1,
73	.ops = &clk_alpha_pll_fixed_lucid_ops,
74	},
75	},
76	};
77
78	static const struct clk_div_table post_div_table_gpll0_out_even[] = {
79	{ 0x1, 2 },
80	{ }
81	};
82
83	static struct clk_alpha_pll_postdiv gpll0_out_even = {
84	.offset = 0x0,
85	.post_div_shift = 8,
86	.post_div_table = post_div_table_gpll0_out_even,
87	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
88	.width = 4,
89	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
90	.clkr.hw.init = &(struct clk_init_data){
91	.name = "gpll0_out_even",
92	.parent_hws = (const struct clk_hw*[]){
93	&gpll0.clkr.hw,
94	},
95	.num_parents = 1,
96	.ops = &clk_alpha_pll_postdiv_lucid_ops,
97	},
98	};
99
100	static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
101	{ 0x3, 3 },
102	{ }
103	};
104
105	static struct clk_alpha_pll_postdiv gpll0_out_odd = {
106	.offset = 0x0,
107	.post_div_shift = 12,
108	.post_div_table = post_div_table_gpll0_out_odd,
109	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
110	.width = 4,
111	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
112	.clkr.hw.init = &(struct clk_init_data){
113	.name = "gpll0_out_odd",
114	.parent_hws = (const struct clk_hw*[]){
115	&gpll0.clkr.hw,
116	},
117	.num_parents = 1,
118	.ops = &clk_alpha_pll_postdiv_lucid_ops,
119	},
120	};
121
122	static struct clk_alpha_pll gpll1 = {
123	.offset = 0x1000,
124	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
125	.clkr = {
126	.enable_reg = 0x79000,
127	.enable_mask = BIT(1),
128	.hw.init = &(struct clk_init_data){
129	.name = "gpll1",
130	.parent_data = &(const struct clk_parent_data){
131	.index = DT_BI_TCXO,
132	},
133	.num_parents = 1,
134	.ops = &clk_alpha_pll_lucid_ops,
135	},
136	},
137	};
138
139	/* 1152MHz Configuration */
140	static const struct alpha_pll_config gpll10_config = {
141	.l = 0x3c,
142	.alpha = 0x0,
143	.config_ctl_val = 0x20485699,
144	.config_ctl_hi_val = 0x00002261,
145	.config_ctl_hi1_val = 0x329a299c,
146	.user_ctl_val = 0x00000001,
147	.user_ctl_hi_val = 0x00000805,
148	.user_ctl_hi1_val = 0x00000000,
149	};
150
151	static struct clk_alpha_pll gpll10 = {
152	.offset = 0xa000,
153	.vco_table = lucid_vco,
154	.num_vco = ARRAY_SIZE(lucid_vco),
155	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
156	.flags = SUPPORTS_FSM_LEGACY_MODE,
157	.clkr = {
158	.enable_reg = 0x79000,
159	.enable_mask = BIT(10),
160	.hw.init = &(struct clk_init_data){
161	.name = "gpll10",
162	.parent_data = &(const struct clk_parent_data){
163	.index = DT_BI_TCXO,
164	},
165	.num_parents = 1,
166	.ops = &clk_alpha_pll_fixed_lucid_ops,
167	},
168	},
169	};
170
171	/* 532MHz Configuration */
172	static const struct alpha_pll_config gpll11_config = {
173	.l = 0x1b,
174	.alpha = 0xb555,
175	.config_ctl_val = 0x20485699,
176	.config_ctl_hi_val = 0x00002261,
177	.config_ctl_hi1_val = 0x329a299c,
178	.user_ctl_val = 0x00000001,
179	.user_ctl_hi_val = 0x00000805,
180	.user_ctl_hi1_val = 0x00000000,
181	};
182
183	static struct clk_alpha_pll gpll11 = {
184	.offset = 0xb000,
185	.vco_table = lucid_vco,
186	.num_vco = ARRAY_SIZE(lucid_vco),
187	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
188	.flags = SUPPORTS_FSM_LEGACY_MODE,
189	.clkr = {
190	.enable_reg = 0x79000,
191	.enable_mask = BIT(11),
192	.hw.init = &(struct clk_init_data){
193	.name = "gpll11",
194	.parent_data = &(const struct clk_parent_data){
195	.index = DT_BI_TCXO,
196	},
197	.num_parents = 1,
198	.ops = &clk_alpha_pll_lucid_ops,
199	},
200	},
201	};
202
203	static struct clk_alpha_pll gpll3 = {
204	.offset = 0x3000,
205	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
206	.clkr = {
207	.enable_reg = 0x79000,
208	.enable_mask = BIT(3),
209	.hw.init = &(struct clk_init_data){
210	.name = "gpll3",
211	.parent_data = &(const struct clk_parent_data){
212	.index = DT_BI_TCXO,
213	},
214	.num_parents = 1,
215	.ops = &clk_alpha_pll_fixed_lucid_ops,
216	},
217	},
218	};
219
220	static const struct clk_div_table post_div_table_gpll3_out_even[] = {
221	{ 0x1, 2 },
222	{ }
223	};
224
225	static struct clk_alpha_pll_postdiv gpll3_out_even = {
226	.offset = 0x3000,
227	.post_div_shift = 8,
228	.post_div_table = post_div_table_gpll3_out_even,
229	.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even),
230	.width = 4,
231	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
232	.clkr.hw.init = &(struct clk_init_data){
233	.name = "gpll3_out_even",
234	.parent_hws = (const struct clk_hw*[]){
235	&gpll3.clkr.hw,
236	},
237	.num_parents = 1,
238	.ops = &clk_alpha_pll_postdiv_lucid_ops,
239	},
240	};
241
242	static struct clk_alpha_pll gpll4 = {
243	.offset = 0x4000,
244	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
245	.clkr = {
246	.enable_reg = 0x79000,
247	.enable_mask = BIT(4),
248	.hw.init = &(struct clk_init_data){
249	.name = "gpll4",
250	.parent_data = &(const struct clk_parent_data){
251	.index = DT_BI_TCXO,
252	},
253	.num_parents = 1,
254	.ops = &clk_alpha_pll_fixed_lucid_ops,
255	},
256	},
257	};
258
259	static struct clk_alpha_pll gpll5 = {
260	.offset = 0x5000,
261	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
262	.clkr = {
263	.enable_reg = 0x79000,
264	.enable_mask = BIT(5),
265	.hw.init = &(struct clk_init_data){
266	.name = "gpll5",
267	.parent_data = &(const struct clk_parent_data){
268	.index = DT_BI_TCXO,
269	},
270	.num_parents = 1,
271	.ops = &clk_alpha_pll_fixed_lucid_ops,
272	},
273	},
274	};
275
276	static struct clk_alpha_pll gpll6 = {
277	.offset = 0x6000,
278	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
279	.clkr = {
280	.enable_reg = 0x79000,
281	.enable_mask = BIT(6),
282	.hw.init = &(struct clk_init_data){
283	.name = "gpll6",
284	.parent_data = &(const struct clk_parent_data){
285	.index = DT_BI_TCXO,
286	},
287	.num_parents = 1,
288	.ops = &clk_alpha_pll_fixed_lucid_ops,
289	},
290	},
291	};
292
293	static const struct clk_div_table post_div_table_gpll6_out_even[] = {
294	{ 0x1, 2 },
295	{ }
296	};
297
298	static struct clk_alpha_pll_postdiv gpll6_out_even = {
299	.offset = 0x6000,
300	.post_div_shift = 8,
301	.post_div_table = post_div_table_gpll6_out_even,
302	.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
303	.width = 4,
304	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
305	.clkr.hw.init = &(struct clk_init_data){
306	.name = "gpll6_out_even",
307	.parent_hws = (const struct clk_hw*[]){
308	&gpll6.clkr.hw,
309	},
310	.num_parents = 1,
311	.ops = &clk_alpha_pll_postdiv_lucid_ops,
312	},
313	};
314
315	static struct clk_alpha_pll gpll7 = {
316	.offset = 0x7000,
317	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
318	.clkr = {
319	.enable_reg = 0x79000,
320	.enable_mask = BIT(7),
321	.hw.init = &(struct clk_init_data){
322	.name = "gpll7",
323	.parent_data = &(const struct clk_parent_data){
324	.index = DT_BI_TCXO,
325	},
326	.num_parents = 1,
327	.ops = &clk_alpha_pll_fixed_lucid_ops,
328	},
329	},
330	};
331
332	/* 400MHz Configuration */
333	static const struct alpha_pll_config gpll8_config = {
334	.l = 0x14,
335	.alpha = 0xd555,
336	.config_ctl_val = 0x20485699,
337	.config_ctl_hi_val = 0x00002261,
338	.config_ctl_hi1_val = 0x329a299c,
339	.user_ctl_val = 0x00000101,
340	.user_ctl_hi_val = 0x00000805,
341	.user_ctl_hi1_val = 0x00000000,
342	};
343
344	static struct clk_alpha_pll gpll8 = {
345	.offset = 0x8000,
346	.vco_table = lucid_vco,
347	.num_vco = ARRAY_SIZE(lucid_vco),
348	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
349	.flags = SUPPORTS_FSM_LEGACY_MODE,
350	.clkr = {
351	.enable_reg = 0x79000,
352	.enable_mask = BIT(8),
353	.hw.init = &(struct clk_init_data){
354	.name = "gpll8",
355	.parent_data = &(const struct clk_parent_data){
356	.index = DT_BI_TCXO,
357	},
358	.num_parents = 1,
359	.ops = &clk_alpha_pll_lucid_ops,
360	},
361	},
362	};
363
364	static const struct clk_div_table post_div_table_gpll8_out_even[] = {
365	{ 0x1, 2 },
366	{ }
367	};
368
369	static struct clk_alpha_pll_postdiv gpll8_out_even = {
370	.offset = 0x8000,
371	.post_div_shift = 8,
372	.post_div_table = post_div_table_gpll8_out_even,
373	.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even),
374	.width = 4,
375	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
376	.clkr.hw.init = &(struct clk_init_data){
377	.name = "gpll8_out_even",
378	.parent_hws = (const struct clk_hw*[]){
379	&gpll8.clkr.hw,
380	},
381	.num_parents = 1,
382	.flags = CLK_SET_RATE_PARENT,
383	.ops = &clk_alpha_pll_postdiv_lucid_ops,
384	},
385	};
386
387	/* 1440MHz Configuration */
388	static const struct alpha_pll_config gpll9_config = {
389	.l = 0x4b,
390	.alpha = 0x0,
391	.config_ctl_val = 0x08200800,
392	.config_ctl_hi_val = 0x05022011,
393	.config_ctl_hi1_val = 0x08000000,
394	.user_ctl_val = 0x00000301,
395	};
396
397	static struct clk_alpha_pll gpll9 = {
398	.offset = 0x9000,
399	.vco_table = zonda_vco,
400	.num_vco = ARRAY_SIZE(zonda_vco),
401	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
402	.clkr = {
403	.enable_reg = 0x79000,
404	.enable_mask = BIT(9),
405	.hw.init = &(struct clk_init_data){
406	.name = "gpll9",
407	.parent_data = &(const struct clk_parent_data){
408	.index = DT_BI_TCXO,
409	},
410	.num_parents = 1,
411	.ops = &clk_alpha_pll_zonda_ops,
412	},
413	},
414	};
415
416	static const struct clk_div_table post_div_table_gpll9_out_main[] = {
417	{ 0x3, 4 },
418	{ }
419	};
420
421	static struct clk_alpha_pll_postdiv gpll9_out_main = {
422	.offset = 0x9000,
423	.post_div_shift = 8,
424	.post_div_table = post_div_table_gpll9_out_main,
425	.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
426	.width = 2,
427	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
428	.clkr.hw.init = &(struct clk_init_data){
429	.name = "gpll9_out_main",
430	.parent_hws = (const struct clk_hw*[]){
431	&gpll9.clkr.hw,
432	},
433	.num_parents = 1,
434	.flags = CLK_SET_RATE_PARENT,
435	.ops = &clk_alpha_pll_postdiv_zonda_ops,
436	},
437	};
438
439	static const struct parent_map gcc_parent_map_0[] = {
440	{ P_BI_TCXO, 0 },
441	{ P_GPLL0_OUT_MAIN, 1 },
442	{ P_GPLL0_OUT_EVEN, 2 },
443	};
444
445	static const struct clk_parent_data gcc_parent_data_0[] = {
446	{ .index = DT_BI_TCXO },
447	{ .hw = &gpll0.clkr.hw },
448	{ .hw = &gpll0_out_even.clkr.hw },
449	};
450
451	static const struct parent_map gcc_parent_map_1[] = {
452	{ P_BI_TCXO, 0 },
453	{ P_GPLL0_OUT_MAIN, 1 },
454	{ P_GPLL0_OUT_EVEN, 2 },
455	{ P_GPLL6_OUT_EVEN, 4 },
456	};
457
458	static const struct clk_parent_data gcc_parent_data_1[] = {
459	{ .index = DT_BI_TCXO },
460	{ .hw = &gpll0.clkr.hw },
461	{ .hw = &gpll0_out_even.clkr.hw },
462	{ .hw = &gpll6_out_even.clkr.hw },
463	};
464
465	static const struct parent_map gcc_parent_map_2[] = {
466	{ P_BI_TCXO, 0 },
467	{ P_GPLL0_OUT_MAIN, 1 },
468	{ P_GPLL0_OUT_EVEN, 2 },
469	{ P_GPLL0_OUT_ODD, 4 },
470	};
471
472	static const struct clk_parent_data gcc_parent_data_2[] = {
473	{ .index = DT_BI_TCXO },
474	{ .hw = &gpll0.clkr.hw },
475	{ .hw = &gpll0_out_even.clkr.hw },
476	{ .hw = &gpll0_out_odd.clkr.hw },
477	};
478
479	static const struct clk_parent_data gcc_parent_data_2_ao[] = {
480	{ .index = DT_BI_TCXO_AO },
481	{ .hw = &gpll0.clkr.hw },
482	{ .hw = &gpll0_out_even.clkr.hw },
483	{ .hw = &gpll0_out_odd.clkr.hw },
484	};
485
486	static const struct parent_map gcc_parent_map_3[] = {
487	{ P_BI_TCXO, 0 },
488	{ P_GPLL0_OUT_MAIN, 1 },
489	{ P_GPLL9_OUT_EARLY, 2 },
490	{ P_GPLL10_OUT_EVEN, 3 },
491	{ P_GPLL9_OUT_MAIN, 4 },
492	{ P_GPLL3_OUT_EVEN, 6 },
493	};
494
495	static const struct clk_parent_data gcc_parent_data_3[] = {
496	{ .index = DT_BI_TCXO },
497	{ .hw = &gpll0.clkr.hw },
498	{ .hw = &gpll9.clkr.hw },
499	{ .hw = &gpll10.clkr.hw },
500	{ .hw = &gpll9_out_main.clkr.hw },
501	{ .hw = &gpll3_out_even.clkr.hw },
502	};
503
504	static const struct parent_map gcc_parent_map_4[] = {
505	{ P_BI_TCXO, 0 },
506	{ P_GPLL0_OUT_MAIN, 1 },
507	{ P_GPLL0_OUT_EVEN, 2 },
508	{ P_GPLL0_OUT_ODD, 4 },
509	{ P_GPLL4_OUT_EVEN, 5 },
510	{ P_GPLL3_OUT_EVEN, 6 },
511	};
512
513	static const struct clk_parent_data gcc_parent_data_4[] = {
514	{ .index = DT_BI_TCXO },
515	{ .hw = &gpll0.clkr.hw },
516	{ .hw = &gpll0_out_even.clkr.hw },
517	{ .hw = &gpll0_out_odd.clkr.hw },
518	{ .hw = &gpll4.clkr.hw },
519	{ .hw = &gpll3_out_even.clkr.hw },
520	};
521
522	static const struct parent_map gcc_parent_map_5[] = {
523	{ P_BI_TCXO, 0 },
524	{ P_GPLL0_OUT_MAIN, 1 },
525	{ P_GPLL8_OUT_MAIN, 2 },
526	{ P_GPLL10_OUT_EVEN, 3 },
527	{ P_GPLL9_OUT_MAIN, 4 },
528	{ P_GPLL8_OUT_EVEN, 5 },
529	{ P_GPLL3_OUT_EVEN, 6 },
530	};
531
532	static const struct clk_parent_data gcc_parent_data_5[] = {
533	{ .index = DT_BI_TCXO },
534	{ .hw = &gpll0.clkr.hw },
535	{ .hw = &gpll8.clkr.hw },
536	{ .hw = &gpll10.clkr.hw },
537	{ .hw = &gpll9_out_main.clkr.hw },
538	{ .hw = &gpll8_out_even.clkr.hw },
539	{ .hw = &gpll3_out_even.clkr.hw },
540	};
541
542	static const struct parent_map gcc_parent_map_6[] = {
543	{ P_BI_TCXO, 0 },
544	{ P_GPLL0_OUT_MAIN, 1 },
545	{ P_GPLL8_OUT_MAIN, 2 },
546	{ P_GPLL5_OUT_EVEN, 3 },
547	{ P_GPLL9_OUT_MAIN, 4 },
548	{ P_GPLL8_OUT_EVEN, 5 },
549	{ P_GPLL3_OUT_MAIN, 6 },
550	};
551
552	static const struct clk_parent_data gcc_parent_data_6[] = {
553	{ .index = DT_BI_TCXO },
554	{ .hw = &gpll0.clkr.hw },
555	{ .hw = &gpll8.clkr.hw },
556	{ .hw = &gpll5.clkr.hw },
557	{ .hw = &gpll9_out_main.clkr.hw },
558	{ .hw = &gpll8_out_even.clkr.hw },
559	{ .hw = &gpll3.clkr.hw },
560	};
561
562	static const struct parent_map gcc_parent_map_7[] = {
563	{ P_BI_TCXO, 0 },
564	{ P_GPLL0_OUT_MAIN, 1 },
565	{ P_GPLL0_OUT_EVEN, 2 },
566	{ P_GPLL0_OUT_ODD, 4 },
567	{ P_SLEEP_CLK, 5 },
568	};
569
570	static const struct clk_parent_data gcc_parent_data_7[] = {
571	{ .index = DT_BI_TCXO },
572	{ .hw = &gpll0.clkr.hw },
573	{ .hw = &gpll0_out_even.clkr.hw },
574	{ .hw = &gpll0_out_odd.clkr.hw },
575	{ .index = DT_SLEEP_CLK },
576	};
577
578	static const struct parent_map gcc_parent_map_8[] = {
579	{ P_BI_TCXO, 0 },
580	{ P_GPLL0_OUT_MAIN, 1 },
581	{ P_GPLL0_OUT_EVEN, 2 },
582	{ P_GPLL10_OUT_EVEN, 3 },
583	{ P_GPLL4_OUT_EVEN, 5 },
584	{ P_GPLL3_OUT_MAIN, 6 },
585	};
586
587	static const struct clk_parent_data gcc_parent_data_8[] = {
588	{ .index = DT_BI_TCXO },
589	{ .hw = &gpll0.clkr.hw },
590	{ .hw = &gpll0_out_even.clkr.hw },
591	{ .hw = &gpll10.clkr.hw },
592	{ .hw = &gpll4.clkr.hw },
593	{ .hw = &gpll3.clkr.hw },
594	};
595
596	static const struct parent_map gcc_parent_map_9[] = {
597	{ P_BI_TCXO, 0 },
598	{ P_GPLL0_OUT_MAIN, 1 },
599	{ P_GPLL0_OUT_EVEN, 2 },
600	{ P_GPLL10_OUT_EVEN, 3 },
601	{ P_GPLL9_OUT_MAIN, 4 },
602	{ P_GPLL8_OUT_EVEN, 5 },
603	{ P_GPLL3_OUT_MAIN, 6 },
604	};
605
606	static const struct clk_parent_data gcc_parent_data_9[] = {
607	{ .index = DT_BI_TCXO },
608	{ .hw = &gpll0.clkr.hw },
609	{ .hw = &gpll0_out_even.clkr.hw },
610	{ .hw = &gpll10.clkr.hw },
611	{ .hw = &gpll9_out_main.clkr.hw },
612	{ .hw = &gpll8_out_even.clkr.hw },
613	{ .hw = &gpll3.clkr.hw },
614	};
615
616	static const struct parent_map gcc_parent_map_10[] = {
617	{ P_BI_TCXO, 0 },
618	{ P_GPLL0_OUT_MAIN, 1 },
619	{ P_GPLL8_OUT_MAIN, 2 },
620	{ P_GPLL10_OUT_EVEN, 3 },
621	{ P_GPLL9_OUT_MAIN, 4 },
622	{ P_GPLL8_OUT_EVEN, 5 },
623	{ P_GPLL3_OUT_MAIN, 6 },
624	};
625
626	static const struct clk_parent_data gcc_parent_data_10[] = {
627	{ .index = DT_BI_TCXO },
628	{ .hw = &gpll0.clkr.hw },
629	{ .hw = &gpll8.clkr.hw },
630	{ .hw = &gpll10.clkr.hw },
631	{ .hw = &gpll9_out_main.clkr.hw },
632	{ .hw = &gpll8_out_even.clkr.hw },
633	{ .hw = &gpll3.clkr.hw },
634	};
635
636	static const struct parent_map gcc_parent_map_11[] = {
637	{ P_BI_TCXO, 0 },
638	{ P_GPLL0_OUT_MAIN, 1 },
639	{ P_GPLL8_OUT_MAIN, 2 },
640	{ P_GPLL10_OUT_EVEN, 3 },
641	{ P_GPLL6_OUT_MAIN, 4 },
642	{ P_GPLL3_OUT_EVEN, 6 },
643	};
644
645	static const struct clk_parent_data gcc_parent_data_11[] = {
646	{ .index = DT_BI_TCXO },
647	{ .hw = &gpll0.clkr.hw },
648	{ .hw = &gpll8.clkr.hw },
649	{ .hw = &gpll10.clkr.hw },
650	{ .hw = &gpll6.clkr.hw },
651	{ .hw = &gpll3_out_even.clkr.hw },
652	};
653
654	static const struct parent_map gcc_parent_map_12[] = {
655	{ P_BI_TCXO, 0 },
656	{ P_GPLL0_OUT_MAIN, 1 },
657	{ P_GPLL0_OUT_EVEN, 2 },
658	{ P_GPLL7_OUT_EVEN, 3 },
659	{ P_GPLL4_OUT_EVEN, 5 },
660	};
661
662	static const struct clk_parent_data gcc_parent_data_12[] = {
663	{ .index = DT_BI_TCXO },
664	{ .hw = &gpll0.clkr.hw },
665	{ .hw = &gpll0_out_even.clkr.hw },
666	{ .hw = &gpll7.clkr.hw },
667	{ .hw = &gpll4.clkr.hw },
668	};
669
670	static const struct parent_map gcc_parent_map_13[] = {
671	{ P_BI_TCXO, 0 },
672	{ P_SLEEP_CLK, 5 },
673	};
674
675	static const struct clk_parent_data gcc_parent_data_13[] = {
676	{ .index = DT_BI_TCXO },
677	{ .index = DT_SLEEP_CLK },
678	};
679
680	static const struct parent_map gcc_parent_map_14[] = {
681	{ P_BI_TCXO, 0 },
682	{ P_GPLL11_OUT_ODD, 2 },
683	{ P_GPLL11_OUT_EVEN, 3 },
684	};
685
686	static const struct clk_parent_data gcc_parent_data_14[] = {
687	{ .index = DT_BI_TCXO },
688	{ .hw = &gpll11.clkr.hw },
689	{ .hw = &gpll11.clkr.hw },
690	};
691
692	static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
693	F(19200000, P_BI_TCXO, 1, 0, 0),
694	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
695	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
696	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
697	{ }
698	};
699
700	static struct clk_rcg2 gcc_camss_axi_clk_src = {
701	.cmd_rcgr = 0x5802c,
702	.mnd_width = 0,
703	.hid_width = 5,
704	.parent_map = gcc_parent_map_8,
705	.freq_tbl = ftbl_gcc_camss_axi_clk_src,
706	.clkr.hw.init = &(struct clk_init_data){
707	.name = "gcc_camss_axi_clk_src",
708	.parent_data = gcc_parent_data_8,
709	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
710	.ops = &clk_rcg2_shared_ops,
711	},
712	};
713
714	static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = {
715	F(19200000, P_BI_TCXO, 1, 0, 0),
716	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
717	{ }
718	};
719
720	static struct clk_rcg2 gcc_camss_cci_0_clk_src = {
721	.cmd_rcgr = 0x56000,
722	.mnd_width = 0,
723	.hid_width = 5,
724	.parent_map = gcc_parent_map_9,
725	.freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
726	.clkr.hw.init = &(struct clk_init_data){
727	.name = "gcc_camss_cci_0_clk_src",
728	.parent_data = gcc_parent_data_9,
729	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
730	.ops = &clk_rcg2_shared_ops,
731	},
732	};
733
734	static struct clk_rcg2 gcc_camss_cci_1_clk_src = {
735	.cmd_rcgr = 0x5c000,
736	.mnd_width = 0,
737	.hid_width = 5,
738	.parent_map = gcc_parent_map_9,
739	.freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
740	.clkr.hw.init = &(struct clk_init_data){
741	.name = "gcc_camss_cci_1_clk_src",
742	.parent_data = gcc_parent_data_9,
743	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
744	.ops = &clk_rcg2_shared_ops,
745	},
746	};
747
748	static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
749	F(19200000, P_BI_TCXO, 1, 0, 0),
750	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
751	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
752	{ }
753	};
754
755	static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
756	.cmd_rcgr = 0x59000,
757	.mnd_width = 0,
758	.hid_width = 5,
759	.parent_map = gcc_parent_map_4,
760	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
761	.clkr.hw.init = &(struct clk_init_data){
762	.name = "gcc_camss_csi0phytimer_clk_src",
763	.parent_data = gcc_parent_data_4,
764	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
765	.ops = &clk_rcg2_shared_ops,
766	},
767	};
768
769	static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
770	.cmd_rcgr = 0x5901c,
771	.mnd_width = 0,
772	.hid_width = 5,
773	.parent_map = gcc_parent_map_4,
774	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
775	.clkr.hw.init = &(struct clk_init_data){
776	.name = "gcc_camss_csi1phytimer_clk_src",
777	.parent_data = gcc_parent_data_4,
778	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
779	.ops = &clk_rcg2_shared_ops,
780	},
781	};
782
783	static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
784	.cmd_rcgr = 0x59038,
785	.mnd_width = 0,
786	.hid_width = 5,
787	.parent_map = gcc_parent_map_4,
788	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
789	.clkr.hw.init = &(struct clk_init_data){
790	.name = "gcc_camss_csi2phytimer_clk_src",
791	.parent_data = gcc_parent_data_4,
792	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
793	.ops = &clk_rcg2_shared_ops,
794	},
795	};
796
797	static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = {
798	.cmd_rcgr = 0x59054,
799	.mnd_width = 0,
800	.hid_width = 5,
801	.parent_map = gcc_parent_map_4,
802	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
803	.clkr.hw.init = &(struct clk_init_data){
804	.name = "gcc_camss_csi3phytimer_clk_src",
805	.parent_data = gcc_parent_data_4,
806	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
807	.ops = &clk_rcg2_shared_ops,
808	},
809	};
810
811	static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
812	F(19200000, P_BI_TCXO, 1, 0, 0),
813	F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15),
814	F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2),
815	{ }
816	};
817
818	static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
819	.cmd_rcgr = 0x51000,
820	.mnd_width = 8,
821	.hid_width = 5,
822	.parent_map = gcc_parent_map_3,
823	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
824	.clkr.hw.init = &(struct clk_init_data){
825	.name = "gcc_camss_mclk0_clk_src",
826	.parent_data = gcc_parent_data_3,
827	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
828	.ops = &clk_rcg2_shared_ops,
829	},
830	};
831
832	static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
833	.cmd_rcgr = 0x5101c,
834	.mnd_width = 8,
835	.hid_width = 5,
836	.parent_map = gcc_parent_map_3,
837	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
838	.clkr.hw.init = &(struct clk_init_data){
839	.name = "gcc_camss_mclk1_clk_src",
840	.parent_data = gcc_parent_data_3,
841	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
842	.ops = &clk_rcg2_shared_ops,
843	},
844	};
845
846	static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
847	.cmd_rcgr = 0x51038,
848	.mnd_width = 8,
849	.hid_width = 5,
850	.parent_map = gcc_parent_map_3,
851	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
852	.clkr.hw.init = &(struct clk_init_data){
853	.name = "gcc_camss_mclk2_clk_src",
854	.parent_data = gcc_parent_data_3,
855	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
856	.ops = &clk_rcg2_shared_ops,
857	},
858	};
859
860	static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
861	.cmd_rcgr = 0x51054,
862	.mnd_width = 8,
863	.hid_width = 5,
864	.parent_map = gcc_parent_map_3,
865	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
866	.clkr.hw.init = &(struct clk_init_data){
867	.name = "gcc_camss_mclk3_clk_src",
868	.parent_data = gcc_parent_data_3,
869	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
870	.ops = &clk_rcg2_shared_ops,
871	},
872	};
873
874	static struct clk_rcg2 gcc_camss_mclk4_clk_src = {
875	.cmd_rcgr = 0x51070,
876	.mnd_width = 8,
877	.hid_width = 5,
878	.parent_map = gcc_parent_map_3,
879	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
880	.clkr.hw.init = &(struct clk_init_data){
881	.name = "gcc_camss_mclk4_clk_src",
882	.parent_data = gcc_parent_data_3,
883	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
884	.ops = &clk_rcg2_shared_ops,
885	},
886	};
887
888	static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
889	F(19200000, P_BI_TCXO, 1, 0, 0),
890	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
891	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
892	{ }
893	};
894
895	static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
896	.cmd_rcgr = 0x55024,
897	.mnd_width = 0,
898	.hid_width = 5,
899	.parent_map = gcc_parent_map_10,
900	.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
901	.clkr.hw.init = &(struct clk_init_data){
902	.name = "gcc_camss_ope_ahb_clk_src",
903	.parent_data = gcc_parent_data_10,
904	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
905	.ops = &clk_rcg2_shared_ops,
906	},
907	};
908
909	static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
910	F(19200000, P_BI_TCXO, 1, 0, 0),
911	F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
912	F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
913	F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
914	F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
915	{ }
916	};
917
918	static struct clk_rcg2 gcc_camss_ope_clk_src = {
919	.cmd_rcgr = 0x55004,
920	.mnd_width = 0,
921	.hid_width = 5,
922	.parent_map = gcc_parent_map_10,
923	.freq_tbl = ftbl_gcc_camss_ope_clk_src,
924	.clkr.hw.init = &(struct clk_init_data){
925	.name = "gcc_camss_ope_clk_src",
926	.parent_data = gcc_parent_data_10,
927	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
928	.flags = CLK_SET_RATE_PARENT,
929	.ops = &clk_rcg2_shared_ops,
930	},
931	};
932
933	static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
934	F(19200000, P_BI_TCXO, 1, 0, 0),
935	F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
936	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
937	F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
938	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
939	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
940	F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0),
941	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
942	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
943	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
944	F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
945	F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
946	F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0),
947	F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0),
948	{ }
949	};
950
951	static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
952	.cmd_rcgr = 0x52004,
953	.mnd_width = 8,
954	.hid_width = 5,
955	.parent_map = gcc_parent_map_5,
956	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
957	.clkr.hw.init = &(struct clk_init_data){
958	.name = "gcc_camss_tfe_0_clk_src",
959	.parent_data = gcc_parent_data_5,
960	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
961	.ops = &clk_rcg2_shared_ops,
962	},
963	};
964
965	static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
966	F(19200000, P_BI_TCXO, 1, 0, 0),
967	F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
968	F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0),
969	F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
970	F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0),
971	{ }
972	};
973
974	static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
975	.cmd_rcgr = 0x52094,
976	.mnd_width = 0,
977	.hid_width = 5,
978	.parent_map = gcc_parent_map_6,
979	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
980	.clkr.hw.init = &(struct clk_init_data){
981	.name = "gcc_camss_tfe_0_csid_clk_src",
982	.parent_data = gcc_parent_data_6,
983	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
984	.ops = &clk_rcg2_shared_ops,
985	},
986	};
987
988	static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
989	.cmd_rcgr = 0x52024,
990	.mnd_width = 8,
991	.hid_width = 5,
992	.parent_map = gcc_parent_map_5,
993	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
994	.clkr.hw.init = &(struct clk_init_data){
995	.name = "gcc_camss_tfe_1_clk_src",
996	.parent_data = gcc_parent_data_5,
997	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
998	.ops = &clk_rcg2_shared_ops,
999	},
1000	};
1001
1002	static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
1003	.cmd_rcgr = 0x520b4,
1004	.mnd_width = 0,
1005	.hid_width = 5,
1006	.parent_map = gcc_parent_map_6,
1007	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
1008	.clkr.hw.init = &(struct clk_init_data){
1009	.name = "gcc_camss_tfe_1_csid_clk_src",
1010	.parent_data = gcc_parent_data_6,
1011	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1012	.ops = &clk_rcg2_shared_ops,
1013	},
1014	};
1015
1016	static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
1017	.cmd_rcgr = 0x52044,
1018	.mnd_width = 8,
1019	.hid_width = 5,
1020	.parent_map = gcc_parent_map_5,
1021	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
1022	.clkr.hw.init = &(struct clk_init_data){
1023	.name = "gcc_camss_tfe_2_clk_src",
1024	.parent_data = gcc_parent_data_5,
1025	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1026	.ops = &clk_rcg2_shared_ops,
1027	},
1028	};
1029
1030	static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
1031	.cmd_rcgr = 0x520d4,
1032	.mnd_width = 0,
1033	.hid_width = 5,
1034	.parent_map = gcc_parent_map_6,
1035	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
1036	.clkr.hw.init = &(struct clk_init_data){
1037	.name = "gcc_camss_tfe_2_csid_clk_src",
1038	.parent_data = gcc_parent_data_6,
1039	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1040	.ops = &clk_rcg2_shared_ops,
1041	},
1042	};
1043
1044	static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
1045	F(19200000, P_BI_TCXO, 1, 0, 0),
1046	F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1047	F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1048	{ }
1049	};
1050
1051	static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
1052	.cmd_rcgr = 0x52064,
1053	.mnd_width = 0,
1054	.hid_width = 5,
1055	.parent_map = gcc_parent_map_11,
1056	.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
1057	.clkr.hw.init = &(struct clk_init_data){
1058	.name = "gcc_camss_tfe_cphy_rx_clk_src",
1059	.parent_data = gcc_parent_data_11,
1060	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1061	.ops = &clk_rcg2_shared_ops,
1062	},
1063	};
1064
1065	static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
1066	F(19200000, P_BI_TCXO, 1, 0, 0),
1067	F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1068	F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
1069	{ }
1070	};
1071
1072	static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
1073	.cmd_rcgr = 0x58010,
1074	.mnd_width = 0,
1075	.hid_width = 5,
1076	.parent_map = gcc_parent_map_8,
1077	.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
1078	.clkr.hw.init = &(struct clk_init_data){
1079	.name = "gcc_camss_top_ahb_clk_src",
1080	.parent_data = gcc_parent_data_8,
1081	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1082	.ops = &clk_rcg2_shared_ops,
1083	},
1084	};
1085
1086	static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
1087	F(19200000, P_BI_TCXO, 1, 0, 0),
1088	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1089	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1090	{ }
1091	};
1092
1093	static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
1094	.cmd_rcgr = 0x2b13c,
1095	.mnd_width = 0,
1096	.hid_width = 5,
1097	.parent_map = gcc_parent_map_2,
1098	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
1099	.clkr.hw.init = &(struct clk_init_data){
1100	.name = "gcc_cpuss_ahb_clk_src",
1101	.parent_data = gcc_parent_data_2_ao,
1102	.num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
1103	.ops = &clk_rcg2_shared_ops,
1104	},
1105	};
1106
1107	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1108	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1109	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1110	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1111	F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1112	{ }
1113	};
1114
1115	static struct clk_rcg2 gcc_gp1_clk_src = {
1116	.cmd_rcgr = 0x4d004,
1117	.mnd_width = 16,
1118	.hid_width = 5,
1119	.parent_map = gcc_parent_map_7,
1120	.freq_tbl = ftbl_gcc_gp1_clk_src,
1121	.clkr.hw.init = &(struct clk_init_data){
1122	.name = "gcc_gp1_clk_src",
1123	.parent_data = gcc_parent_data_7,
1124	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1125	.ops = &clk_rcg2_shared_ops,
1126	},
1127	};
1128
1129	static struct clk_rcg2 gcc_gp2_clk_src = {
1130	.cmd_rcgr = 0x4e004,
1131	.mnd_width = 16,
1132	.hid_width = 5,
1133	.parent_map = gcc_parent_map_7,
1134	.freq_tbl = ftbl_gcc_gp1_clk_src,
1135	.clkr.hw.init = &(struct clk_init_data){
1136	.name = "gcc_gp2_clk_src",
1137	.parent_data = gcc_parent_data_7,
1138	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1139	.ops = &clk_rcg2_shared_ops,
1140	},
1141	};
1142
1143	static struct clk_rcg2 gcc_gp3_clk_src = {
1144	.cmd_rcgr = 0x4f004,
1145	.mnd_width = 16,
1146	.hid_width = 5,
1147	.parent_map = gcc_parent_map_7,
1148	.freq_tbl = ftbl_gcc_gp1_clk_src,
1149	.clkr.hw.init = &(struct clk_init_data){
1150	.name = "gcc_gp3_clk_src",
1151	.parent_data = gcc_parent_data_7,
1152	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1153	.ops = &clk_rcg2_shared_ops,
1154	},
1155	};
1156
1157	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1158	F(19200000, P_BI_TCXO, 1, 0, 0),
1159	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1160	{ }
1161	};
1162
1163	static struct clk_rcg2 gcc_pdm2_clk_src = {
1164	.cmd_rcgr = 0x20010,
1165	.mnd_width = 0,
1166	.hid_width = 5,
1167	.parent_map = gcc_parent_map_0,
1168	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1169	.clkr.hw.init = &(struct clk_init_data){
1170	.name = "gcc_pdm2_clk_src",
1171	.parent_data = gcc_parent_data_0,
1172	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1173	.ops = &clk_rcg2_shared_ops,
1174	},
1175	};
1176
1177	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1178	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
1179	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
1180	F(19200000, P_BI_TCXO, 1, 0, 0),
1181	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
1182	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
1183	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
1184	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
1185	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1186	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
1187	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
1188	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1189	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
1190	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
1191	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
1192	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
1193	F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
1194	{ }
1195	};
1196
1197	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1198	.name = "gcc_qupv3_wrap0_s0_clk_src",
1199	.parent_data = gcc_parent_data_1,
1200	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1201	.ops = &clk_rcg2_shared_ops,
1202	};
1203
1204	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1205	.cmd_rcgr = 0x1f148,
1206	.mnd_width = 16,
1207	.hid_width = 5,
1208	.parent_map = gcc_parent_map_1,
1209	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1210	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1211	};
1212
1213	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1214	.name = "gcc_qupv3_wrap0_s1_clk_src",
1215	.parent_data = gcc_parent_data_1,
1216	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1217	.ops = &clk_rcg2_shared_ops,
1218	};
1219
1220	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1221	.cmd_rcgr = 0x1f278,
1222	.mnd_width = 16,
1223	.hid_width = 5,
1224	.parent_map = gcc_parent_map_1,
1225	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1226	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1227	};
1228
1229	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1230	.name = "gcc_qupv3_wrap0_s2_clk_src",
1231	.parent_data = gcc_parent_data_1,
1232	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1233	.ops = &clk_rcg2_shared_ops,
1234	};
1235
1236	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1237	.cmd_rcgr = 0x1f3a8,
1238	.mnd_width = 16,
1239	.hid_width = 5,
1240	.parent_map = gcc_parent_map_1,
1241	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1242	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1243	};
1244
1245	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1246	.name = "gcc_qupv3_wrap0_s3_clk_src",
1247	.parent_data = gcc_parent_data_1,
1248	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1249	.ops = &clk_rcg2_shared_ops,
1250	};
1251
1252	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1253	.cmd_rcgr = 0x1f4d8,
1254	.mnd_width = 16,
1255	.hid_width = 5,
1256	.parent_map = gcc_parent_map_1,
1257	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1258	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1259	};
1260
1261	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1262	.name = "gcc_qupv3_wrap0_s4_clk_src",
1263	.parent_data = gcc_parent_data_1,
1264	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1265	.ops = &clk_rcg2_shared_ops,
1266	};
1267
1268	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1269	.cmd_rcgr = 0x1f608,
1270	.mnd_width = 16,
1271	.hid_width = 5,
1272	.parent_map = gcc_parent_map_1,
1273	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1274	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1275	};
1276
1277	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1278	.name = "gcc_qupv3_wrap0_s5_clk_src",
1279	.parent_data = gcc_parent_data_1,
1280	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1281	.ops = &clk_rcg2_shared_ops,
1282	};
1283
1284	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1285	.cmd_rcgr = 0x1f738,
1286	.mnd_width = 16,
1287	.hid_width = 5,
1288	.parent_map = gcc_parent_map_1,
1289	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1290	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1291	};
1292
1293	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1294	.name = "gcc_qupv3_wrap1_s0_clk_src",
1295	.parent_data = gcc_parent_data_1,
1296	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1297	.ops = &clk_rcg2_shared_ops,
1298	};
1299
1300	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1301	.cmd_rcgr = 0x5301c,
1302	.mnd_width = 16,
1303	.hid_width = 5,
1304	.parent_map = gcc_parent_map_1,
1305	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1306	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1307	};
1308
1309	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1310	.name = "gcc_qupv3_wrap1_s1_clk_src",
1311	.parent_data = gcc_parent_data_1,
1312	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1313	.ops = &clk_rcg2_shared_ops,
1314	};
1315
1316	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1317	.cmd_rcgr = 0x5314c,
1318	.mnd_width = 16,
1319	.hid_width = 5,
1320	.parent_map = gcc_parent_map_1,
1321	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1322	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1323	};
1324
1325	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1326	.name = "gcc_qupv3_wrap1_s2_clk_src",
1327	.parent_data = gcc_parent_data_1,
1328	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1329	.ops = &clk_rcg2_shared_ops,
1330	};
1331
1332	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1333	.cmd_rcgr = 0x5327c,
1334	.mnd_width = 16,
1335	.hid_width = 5,
1336	.parent_map = gcc_parent_map_1,
1337	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1338	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1339	};
1340
1341	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1342	.name = "gcc_qupv3_wrap1_s3_clk_src",
1343	.parent_data = gcc_parent_data_1,
1344	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1345	.ops = &clk_rcg2_shared_ops,
1346	};
1347
1348	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1349	.cmd_rcgr = 0x533ac,
1350	.mnd_width = 16,
1351	.hid_width = 5,
1352	.parent_map = gcc_parent_map_1,
1353	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1354	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1355	};
1356
1357	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1358	.name = "gcc_qupv3_wrap1_s4_clk_src",
1359	.parent_data = gcc_parent_data_1,
1360	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1361	.ops = &clk_rcg2_shared_ops,
1362	};
1363
1364	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1365	.cmd_rcgr = 0x534dc,
1366	.mnd_width = 16,
1367	.hid_width = 5,
1368	.parent_map = gcc_parent_map_1,
1369	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1370	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1371	};
1372
1373	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1374	.name = "gcc_qupv3_wrap1_s5_clk_src",
1375	.parent_data = gcc_parent_data_1,
1376	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1377	.ops = &clk_rcg2_shared_ops,
1378	};
1379
1380	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1381	.cmd_rcgr = 0x5360c,
1382	.mnd_width = 16,
1383	.hid_width = 5,
1384	.parent_map = gcc_parent_map_1,
1385	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1386	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1387	};
1388
1389	static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1390	F(144000, P_BI_TCXO, 16, 3, 25),
1391	F(400000, P_BI_TCXO, 12, 1, 4),
1392	F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
1393	F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
1394	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1395	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1396	F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
1397	F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
1398	{ }
1399	};
1400
1401	static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1402	.cmd_rcgr = 0x38028,
1403	.mnd_width = 8,
1404	.hid_width = 5,
1405	.parent_map = gcc_parent_map_1,
1406	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1407	.clkr.hw.init = &(struct clk_init_data){
1408	.name = "gcc_sdcc1_apps_clk_src",
1409	.parent_data = gcc_parent_data_1,
1410	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1411	.ops = &clk_rcg2_shared_ops,
1412	},
1413	};
1414
1415	static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1416	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1417	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1418	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1419	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1420	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1421	{ }
1422	};
1423
1424	static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1425	.cmd_rcgr = 0x38010,
1426	.mnd_width = 0,
1427	.hid_width = 5,
1428	.parent_map = gcc_parent_map_0,
1429	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1430	.clkr.hw.init = &(struct clk_init_data){
1431	.name = "gcc_sdcc1_ice_core_clk_src",
1432	.parent_data = gcc_parent_data_0,
1433	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1434	.ops = &clk_rcg2_shared_ops,
1435	},
1436	};
1437
1438	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1439	F(400000, P_BI_TCXO, 12, 1, 4),
1440	F(19200000, P_BI_TCXO, 1, 0, 0),
1441	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1442	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1443	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1444	F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
1445	{ }
1446	};
1447
1448	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1449	.cmd_rcgr = 0x1e00c,
1450	.mnd_width = 8,
1451	.hid_width = 5,
1452	.parent_map = gcc_parent_map_12,
1453	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1454	.clkr.hw.init = &(struct clk_init_data){
1455	.name = "gcc_sdcc2_apps_clk_src",
1456	.parent_data = gcc_parent_data_12,
1457	.num_parents = ARRAY_SIZE(gcc_parent_data_12),
1458	.ops = &clk_rcg2_shared_ops,
1459	},
1460	};
1461
1462	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1463	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1464	F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1465	F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1466	F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1467	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1468	{ }
1469	};
1470
1471	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1472	.cmd_rcgr = 0x45020,
1473	.mnd_width = 8,
1474	.hid_width = 5,
1475	.parent_map = gcc_parent_map_2,
1476	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1477	.clkr.hw.init = &(struct clk_init_data){
1478	.name = "gcc_ufs_phy_axi_clk_src",
1479	.parent_data = gcc_parent_data_2,
1480	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1481	.ops = &clk_rcg2_shared_ops,
1482	},
1483	};
1484
1485	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1486	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1487	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1488	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1489	F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1490	{ }
1491	};
1492
1493	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1494	.cmd_rcgr = 0x45048,
1495	.mnd_width = 0,
1496	.hid_width = 5,
1497	.parent_map = gcc_parent_map_0,
1498	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1499	.clkr.hw.init = &(struct clk_init_data){
1500	.name = "gcc_ufs_phy_ice_core_clk_src",
1501	.parent_data = gcc_parent_data_0,
1502	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1503	.ops = &clk_rcg2_shared_ops,
1504	},
1505	};
1506
1507	static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1508	F(9600000, P_BI_TCXO, 2, 0, 0),
1509	F(19200000, P_BI_TCXO, 1, 0, 0),
1510	{ }
1511	};
1512
1513	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1514	.cmd_rcgr = 0x4507c,
1515	.mnd_width = 0,
1516	.hid_width = 5,
1517	.parent_map = gcc_parent_map_0,
1518	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1519	.clkr.hw.init = &(struct clk_init_data){
1520	.name = "gcc_ufs_phy_phy_aux_clk_src",
1521	.parent_data = gcc_parent_data_0,
1522	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1523	.ops = &clk_rcg2_shared_ops,
1524	},
1525	};
1526
1527	static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1528	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1529	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1530	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1531	{ }
1532	};
1533
1534	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1535	.cmd_rcgr = 0x45060,
1536	.mnd_width = 0,
1537	.hid_width = 5,
1538	.parent_map = gcc_parent_map_0,
1539	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1540	.clkr.hw.init = &(struct clk_init_data){
1541	.name = "gcc_ufs_phy_unipro_core_clk_src",
1542	.parent_data = gcc_parent_data_0,
1543	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1544	.ops = &clk_rcg2_shared_ops,
1545	},
1546	};
1547
1548	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1549	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1550	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1551	F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1552	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1553	{ }
1554	};
1555
1556	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1557	.cmd_rcgr = 0x1a01c,
1558	.mnd_width = 8,
1559	.hid_width = 5,
1560	.parent_map = gcc_parent_map_2,
1561	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1562	.clkr.hw.init = &(struct clk_init_data){
1563	.name = "gcc_usb30_prim_master_clk_src",
1564	.parent_data = gcc_parent_data_2,
1565	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1566	.ops = &clk_rcg2_shared_ops,
1567	},
1568	};
1569
1570	static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1571	F(19200000, P_BI_TCXO, 1, 0, 0),
1572	{ }
1573	};
1574
1575	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1576	.cmd_rcgr = 0x1a034,
1577	.mnd_width = 0,
1578	.hid_width = 5,
1579	.parent_map = gcc_parent_map_0,
1580	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1581	.clkr.hw.init = &(struct clk_init_data){
1582	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1583	.parent_data = gcc_parent_data_0,
1584	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1585	.ops = &clk_rcg2_shared_ops,
1586	},
1587	};
1588
1589	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1590	.cmd_rcgr = 0x1a060,
1591	.mnd_width = 0,
1592	.hid_width = 5,
1593	.parent_map = gcc_parent_map_13,
1594	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1595	.clkr.hw.init = &(struct clk_init_data){
1596	.name = "gcc_usb3_prim_phy_aux_clk_src",
1597	.parent_data = gcc_parent_data_13,
1598	.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1599	.ops = &clk_rcg2_shared_ops,
1600	},
1601	};
1602
1603	static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1604	F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0),
1605	F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0),
1606	F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1607	F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1608	{ }
1609	};
1610
1611	static struct clk_rcg2 gcc_video_venus_clk_src = {
1612	.cmd_rcgr = 0x58060,
1613	.mnd_width = 0,
1614	.hid_width = 5,
1615	.parent_map = gcc_parent_map_14,
1616	.freq_tbl = ftbl_gcc_video_venus_clk_src,
1617	.clkr.hw.init = &(struct clk_init_data){
1618	.name = "gcc_video_venus_clk_src",
1619	.parent_data = gcc_parent_data_14,
1620	.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1621	.flags = CLK_SET_RATE_PARENT,
1622	.ops = &clk_rcg2_shared_ops,
1623	},
1624	};
1625
1626	static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
1627	.reg = 0x2b154,
1628	.shift = 0,
1629	.width = 4,
1630	.clkr.hw.init = &(struct clk_init_data) {
1631	.name = "gcc_cpuss_ahb_postdiv_clk_src",
1632	.parent_hws = (const struct clk_hw*[]){
1633	&gcc_cpuss_ahb_clk_src.clkr.hw,
1634	},
1635	.num_parents = 1,
1636	.flags = CLK_SET_RATE_PARENT,
1637	.ops = &clk_regmap_div_ro_ops,
1638	},
1639	};
1640
1641	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1642	.reg = 0x1a04c,
1643	.shift = 0,
1644	.width = 4,
1645	.clkr.hw.init = &(struct clk_init_data) {
1646	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1647	.parent_hws = (const struct clk_hw*[]){
1648	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1649	},
1650	.num_parents = 1,
1651	.flags = CLK_SET_RATE_PARENT,
1652	.ops = &clk_regmap_div_ro_ops,
1653	},
1654	};
1655
1656	static struct clk_branch gcc_ahb2phy_csi_clk = {
1657	.halt_reg = 0x1d004,
1658	.halt_check = BRANCH_HALT_VOTED,
1659	.hwcg_reg = 0x1d004,
1660	.hwcg_bit = 1,
1661	.clkr = {
1662	.enable_reg = 0x1d004,
1663	.enable_mask = BIT(0),
1664	.hw.init = &(struct clk_init_data){
1665	.name = "gcc_ahb2phy_csi_clk",
1666	.ops = &clk_branch2_ops,
1667	},
1668	},
1669	};
1670
1671	static struct clk_branch gcc_ahb2phy_usb_clk = {
1672	.halt_reg = 0x1d008,
1673	.halt_check = BRANCH_HALT_VOTED,
1674	.hwcg_reg = 0x1d008,
1675	.hwcg_bit = 1,
1676	.clkr = {
1677	.enable_reg = 0x1d008,
1678	.enable_mask = BIT(0),
1679	.hw.init = &(struct clk_init_data){
1680	.name = "gcc_ahb2phy_usb_clk",
1681	.ops = &clk_branch2_ops,
1682	},
1683	},
1684	};
1685
1686	static struct clk_branch gcc_bimc_gpu_axi_clk = {
1687	.halt_reg = 0x71154,
1688	.halt_check = BRANCH_HALT_VOTED,
1689	.hwcg_reg = 0x71154,
1690	.hwcg_bit = 1,
1691	.clkr = {
1692	.enable_reg = 0x71154,
1693	.enable_mask = BIT(0),
1694	.hw.init = &(struct clk_init_data){
1695	.name = "gcc_bimc_gpu_axi_clk",
1696	.ops = &clk_branch2_ops,
1697	},
1698	},
1699	};
1700
1701	static struct clk_branch gcc_boot_rom_ahb_clk = {
1702	.halt_reg = 0x23004,
1703	.halt_check = BRANCH_HALT_VOTED,
1704	.hwcg_reg = 0x23004,
1705	.hwcg_bit = 1,
1706	.clkr = {
1707	.enable_reg = 0x79004,
1708	.enable_mask = BIT(10),
1709	.hw.init = &(struct clk_init_data){
1710	.name = "gcc_boot_rom_ahb_clk",
1711	.ops = &clk_branch2_ops,
1712	},
1713	},
1714	};
1715
1716	static struct clk_branch gcc_cam_throttle_nrt_clk = {
1717	.halt_reg = 0x17070,
1718	.halt_check = BRANCH_HALT_VOTED,
1719	.hwcg_reg = 0x17070,
1720	.hwcg_bit = 1,
1721	.clkr = {
1722	.enable_reg = 0x79004,
1723	.enable_mask = BIT(27),
1724	.hw.init = &(struct clk_init_data){
1725	.name = "gcc_cam_throttle_nrt_clk",
1726	.ops = &clk_branch2_ops,
1727	},
1728	},
1729	};
1730
1731	static struct clk_branch gcc_cam_throttle_rt_clk = {
1732	.halt_reg = 0x1706c,
1733	.halt_check = BRANCH_HALT_VOTED,
1734	.hwcg_reg = 0x1706c,
1735	.hwcg_bit = 1,
1736	.clkr = {
1737	.enable_reg = 0x79004,
1738	.enable_mask = BIT(26),
1739	.hw.init = &(struct clk_init_data){
1740	.name = "gcc_cam_throttle_rt_clk",
1741	.ops = &clk_branch2_ops,
1742	},
1743	},
1744	};
1745
1746	static struct clk_branch gcc_camera_ahb_clk = {
1747	.halt_reg = 0x17008,
1748	.halt_check = BRANCH_HALT_DELAY,
1749	.hwcg_reg = 0x17008,
1750	.hwcg_bit = 1,
1751	.clkr = {
1752	.enable_reg = 0x17008,
1753	.enable_mask = BIT(0),
1754	.hw.init = &(struct clk_init_data){
1755	.name = "gcc_camera_ahb_clk",
1756	.flags = CLK_IS_CRITICAL,
1757	.ops = &clk_branch2_ops,
1758	},
1759	},
1760	};
1761
1762	static struct clk_branch gcc_camss_axi_clk = {
1763	.halt_reg = 0x58044,
1764	.halt_check = BRANCH_HALT,
1765	.clkr = {
1766	.enable_reg = 0x58044,
1767	.enable_mask = BIT(0),
1768	.hw.init = &(struct clk_init_data){
1769	.name = "gcc_camss_axi_clk",
1770	.parent_hws = (const struct clk_hw*[]) {
1771	&gcc_camss_axi_clk_src.clkr.hw,
1772	},
1773	.num_parents = 1,
1774	.flags = CLK_SET_RATE_PARENT,
1775	.ops = &clk_branch2_ops,
1776	},
1777	},
1778	};
1779
1780	static struct clk_branch gcc_camss_cci_0_clk = {
1781	.halt_reg = 0x56018,
1782	.halt_check = BRANCH_HALT,
1783	.clkr = {
1784	.enable_reg = 0x56018,
1785	.enable_mask = BIT(0),
1786	.hw.init = &(struct clk_init_data){
1787	.name = "gcc_camss_cci_0_clk",
1788	.parent_hws = (const struct clk_hw*[]) {
1789	&gcc_camss_cci_0_clk_src.clkr.hw,
1790	},
1791	.num_parents = 1,
1792	.flags = CLK_SET_RATE_PARENT,
1793	.ops = &clk_branch2_ops,
1794	},
1795	},
1796	};
1797
1798	static struct clk_branch gcc_camss_cci_1_clk = {
1799	.halt_reg = 0x5c018,
1800	.halt_check = BRANCH_HALT,
1801	.clkr = {
1802	.enable_reg = 0x5c018,
1803	.enable_mask = BIT(0),
1804	.hw.init = &(struct clk_init_data){
1805	.name = "gcc_camss_cci_1_clk",
1806	.parent_hws = (const struct clk_hw*[]) {
1807	&gcc_camss_cci_1_clk_src.clkr.hw,
1808	},
1809	.num_parents = 1,
1810	.flags = CLK_SET_RATE_PARENT,
1811	.ops = &clk_branch2_ops,
1812	},
1813	},
1814	};
1815
1816	static struct clk_branch gcc_camss_cphy_0_clk = {
1817	.halt_reg = 0x52088,
1818	.halt_check = BRANCH_HALT,
1819	.clkr = {
1820	.enable_reg = 0x52088,
1821	.enable_mask = BIT(0),
1822	.hw.init = &(struct clk_init_data){
1823	.name = "gcc_camss_cphy_0_clk",
1824	.parent_hws = (const struct clk_hw*[]) {
1825	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1826	},
1827	.num_parents = 1,
1828	.flags = CLK_SET_RATE_PARENT,
1829	.ops = &clk_branch2_ops,
1830	},
1831	},
1832	};
1833
1834	static struct clk_branch gcc_camss_cphy_1_clk = {
1835	.halt_reg = 0x5208c,
1836	.halt_check = BRANCH_HALT,
1837	.clkr = {
1838	.enable_reg = 0x5208c,
1839	.enable_mask = BIT(0),
1840	.hw.init = &(struct clk_init_data){
1841	.name = "gcc_camss_cphy_1_clk",
1842	.parent_hws = (const struct clk_hw*[]) {
1843	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1844	},
1845	.num_parents = 1,
1846	.flags = CLK_SET_RATE_PARENT,
1847	.ops = &clk_branch2_ops,
1848	},
1849	},
1850	};
1851
1852	static struct clk_branch gcc_camss_cphy_2_clk = {
1853	.halt_reg = 0x52090,
1854	.halt_check = BRANCH_HALT,
1855	.clkr = {
1856	.enable_reg = 0x52090,
1857	.enable_mask = BIT(0),
1858	.hw.init = &(struct clk_init_data){
1859	.name = "gcc_camss_cphy_2_clk",
1860	.parent_hws = (const struct clk_hw*[]) {
1861	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1862	},
1863	.num_parents = 1,
1864	.flags = CLK_SET_RATE_PARENT,
1865	.ops = &clk_branch2_ops,
1866	},
1867	},
1868	};
1869
1870	static struct clk_branch gcc_camss_cphy_3_clk = {
1871	.halt_reg = 0x520f8,
1872	.halt_check = BRANCH_HALT,
1873	.clkr = {
1874	.enable_reg = 0x520f8,
1875	.enable_mask = BIT(0),
1876	.hw.init = &(struct clk_init_data){
1877	.name = "gcc_camss_cphy_3_clk",
1878	.parent_hws = (const struct clk_hw*[]) {
1879	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1880	},
1881	.num_parents = 1,
1882	.flags = CLK_SET_RATE_PARENT,
1883	.ops = &clk_branch2_ops,
1884	},
1885	},
1886	};
1887
1888	static struct clk_branch gcc_camss_csi0phytimer_clk = {
1889	.halt_reg = 0x59018,
1890	.halt_check = BRANCH_HALT,
1891	.clkr = {
1892	.enable_reg = 0x59018,
1893	.enable_mask = BIT(0),
1894	.hw.init = &(struct clk_init_data){
1895	.name = "gcc_camss_csi0phytimer_clk",
1896	.parent_hws = (const struct clk_hw*[]) {
1897	&gcc_camss_csi0phytimer_clk_src.clkr.hw,
1898	},
1899	.num_parents = 1,
1900	.flags = CLK_SET_RATE_PARENT,
1901	.ops = &clk_branch2_ops,
1902	},
1903	},
1904	};
1905
1906	static struct clk_branch gcc_camss_csi1phytimer_clk = {
1907	.halt_reg = 0x59034,
1908	.halt_check = BRANCH_HALT,
1909	.clkr = {
1910	.enable_reg = 0x59034,
1911	.enable_mask = BIT(0),
1912	.hw.init = &(struct clk_init_data){
1913	.name = "gcc_camss_csi1phytimer_clk",
1914	.parent_hws = (const struct clk_hw*[]) {
1915	&gcc_camss_csi1phytimer_clk_src.clkr.hw,
1916	},
1917	.num_parents = 1,
1918	.flags = CLK_SET_RATE_PARENT,
1919	.ops = &clk_branch2_ops,
1920	},
1921	},
1922	};
1923
1924	static struct clk_branch gcc_camss_csi2phytimer_clk = {
1925	.halt_reg = 0x59050,
1926	.halt_check = BRANCH_HALT,
1927	.clkr = {
1928	.enable_reg = 0x59050,
1929	.enable_mask = BIT(0),
1930	.hw.init = &(struct clk_init_data){
1931	.name = "gcc_camss_csi2phytimer_clk",
1932	.parent_hws = (const struct clk_hw*[]) {
1933	&gcc_camss_csi2phytimer_clk_src.clkr.hw,
1934	},
1935	.num_parents = 1,
1936	.flags = CLK_SET_RATE_PARENT,
1937	.ops = &clk_branch2_ops,
1938	},
1939	},
1940	};
1941
1942	static struct clk_branch gcc_camss_csi3phytimer_clk = {
1943	.halt_reg = 0x5906c,
1944	.halt_check = BRANCH_HALT,
1945	.clkr = {
1946	.enable_reg = 0x5906c,
1947	.enable_mask = BIT(0),
1948	.hw.init = &(struct clk_init_data){
1949	.name = "gcc_camss_csi3phytimer_clk",
1950	.parent_hws = (const struct clk_hw*[]) {
1951	&gcc_camss_csi3phytimer_clk_src.clkr.hw,
1952	},
1953	.num_parents = 1,
1954	.flags = CLK_SET_RATE_PARENT,
1955	.ops = &clk_branch2_ops,
1956	},
1957	},
1958	};
1959
1960	static struct clk_branch gcc_camss_mclk0_clk = {
1961	.halt_reg = 0x51018,
1962	.halt_check = BRANCH_HALT,
1963	.clkr = {
1964	.enable_reg = 0x51018,
1965	.enable_mask = BIT(0),
1966	.hw.init = &(struct clk_init_data){
1967	.name = "gcc_camss_mclk0_clk",
1968	.parent_hws = (const struct clk_hw*[]) {
1969	&gcc_camss_mclk0_clk_src.clkr.hw,
1970	},
1971	.num_parents = 1,
1972	.flags = CLK_SET_RATE_PARENT,
1973	.ops = &clk_branch2_ops,
1974	},
1975	},
1976	};
1977
1978	static struct clk_branch gcc_camss_mclk1_clk = {
1979	.halt_reg = 0x51034,
1980	.halt_check = BRANCH_HALT,
1981	.clkr = {
1982	.enable_reg = 0x51034,
1983	.enable_mask = BIT(0),
1984	.hw.init = &(struct clk_init_data){
1985	.name = "gcc_camss_mclk1_clk",
1986	.parent_hws = (const struct clk_hw*[]) {
1987	&gcc_camss_mclk1_clk_src.clkr.hw,
1988	},
1989	.num_parents = 1,
1990	.flags = CLK_SET_RATE_PARENT,
1991	.ops = &clk_branch2_ops,
1992	},
1993	},
1994	};
1995
1996	static struct clk_branch gcc_camss_mclk2_clk = {
1997	.halt_reg = 0x51050,
1998	.halt_check = BRANCH_HALT,
1999	.clkr = {
2000	.enable_reg = 0x51050,
2001	.enable_mask = BIT(0),
2002	.hw.init = &(struct clk_init_data){
2003	.name = "gcc_camss_mclk2_clk",
2004	.parent_hws = (const struct clk_hw*[]) {
2005	&gcc_camss_mclk2_clk_src.clkr.hw,
2006	},
2007	.num_parents = 1,
2008	.flags = CLK_SET_RATE_PARENT,
2009	.ops = &clk_branch2_ops,
2010	},
2011	},
2012	};
2013
2014	static struct clk_branch gcc_camss_mclk3_clk = {
2015	.halt_reg = 0x5106c,
2016	.halt_check = BRANCH_HALT,
2017	.clkr = {
2018	.enable_reg = 0x5106c,
2019	.enable_mask = BIT(0),
2020	.hw.init = &(struct clk_init_data){
2021	.name = "gcc_camss_mclk3_clk",
2022	.parent_hws = (const struct clk_hw*[]) {
2023	&gcc_camss_mclk3_clk_src.clkr.hw,
2024	},
2025	.num_parents = 1,
2026	.flags = CLK_SET_RATE_PARENT,
2027	.ops = &clk_branch2_ops,
2028	},
2029	},
2030	};
2031
2032	static struct clk_branch gcc_camss_mclk4_clk = {
2033	.halt_reg = 0x51088,
2034	.halt_check = BRANCH_HALT,
2035	.clkr = {
2036	.enable_reg = 0x51088,
2037	.enable_mask = BIT(0),
2038	.hw.init = &(struct clk_init_data){
2039	.name = "gcc_camss_mclk4_clk",
2040	.parent_hws = (const struct clk_hw*[]) {
2041	&gcc_camss_mclk4_clk_src.clkr.hw,
2042	},
2043	.num_parents = 1,
2044	.flags = CLK_SET_RATE_PARENT,
2045	.ops = &clk_branch2_ops,
2046	},
2047	},
2048	};
2049
2050	static struct clk_branch gcc_camss_nrt_axi_clk = {
2051	.halt_reg = 0x58054,
2052	.halt_check = BRANCH_HALT,
2053	.clkr = {
2054	.enable_reg = 0x58054,
2055	.enable_mask = BIT(0),
2056	.hw.init = &(struct clk_init_data){
2057	.name = "gcc_camss_nrt_axi_clk",
2058	.ops = &clk_branch2_ops,
2059	},
2060	},
2061	};
2062
2063	static struct clk_branch gcc_camss_ope_ahb_clk = {
2064	.halt_reg = 0x5503c,
2065	.halt_check = BRANCH_HALT,
2066	.clkr = {
2067	.enable_reg = 0x5503c,
2068	.enable_mask = BIT(0),
2069	.hw.init = &(struct clk_init_data){
2070	.name = "gcc_camss_ope_ahb_clk",
2071	.parent_hws = (const struct clk_hw*[]) {
2072	&gcc_camss_ope_ahb_clk_src.clkr.hw,
2073	},
2074	.num_parents = 1,
2075	.flags = CLK_SET_RATE_PARENT,
2076	.ops = &clk_branch2_ops,
2077	},
2078	},
2079	};
2080
2081	static struct clk_branch gcc_camss_ope_clk = {
2082	.halt_reg = 0x5501c,
2083	.halt_check = BRANCH_HALT,
2084	.clkr = {
2085	.enable_reg = 0x5501c,
2086	.enable_mask = BIT(0),
2087	.hw.init = &(struct clk_init_data){
2088	.name = "gcc_camss_ope_clk",
2089	.parent_hws = (const struct clk_hw*[]) {
2090	&gcc_camss_ope_clk_src.clkr.hw,
2091	},
2092	.num_parents = 1,
2093	.flags = CLK_SET_RATE_PARENT,
2094	.ops = &clk_branch2_ops,
2095	},
2096	},
2097	};
2098
2099	static struct clk_branch gcc_camss_rt_axi_clk = {
2100	.halt_reg = 0x5805c,
2101	.halt_check = BRANCH_HALT,
2102	.clkr = {
2103	.enable_reg = 0x5805c,
2104	.enable_mask = BIT(0),
2105	.hw.init = &(struct clk_init_data){
2106	.name = "gcc_camss_rt_axi_clk",
2107	.ops = &clk_branch2_ops,
2108	},
2109	},
2110	};
2111
2112	static struct clk_branch gcc_camss_tfe_0_clk = {
2113	.halt_reg = 0x5201c,
2114	.halt_check = BRANCH_HALT,
2115	.clkr = {
2116	.enable_reg = 0x5201c,
2117	.enable_mask = BIT(0),
2118	.hw.init = &(struct clk_init_data){
2119	.name = "gcc_camss_tfe_0_clk",
2120	.parent_hws = (const struct clk_hw*[]) {
2121	&gcc_camss_tfe_0_clk_src.clkr.hw,
2122	},
2123	.num_parents = 1,
2124	.flags = CLK_SET_RATE_PARENT,
2125	.ops = &clk_branch2_ops,
2126	},
2127	},
2128	};
2129
2130	static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
2131	.halt_reg = 0x5207c,
2132	.halt_check = BRANCH_HALT,
2133	.clkr = {
2134	.enable_reg = 0x5207c,
2135	.enable_mask = BIT(0),
2136	.hw.init = &(struct clk_init_data){
2137	.name = "gcc_camss_tfe_0_cphy_rx_clk",
2138	.parent_hws = (const struct clk_hw*[]) {
2139	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2140	},
2141	.num_parents = 1,
2142	.flags = CLK_SET_RATE_PARENT,
2143	.ops = &clk_branch2_ops,
2144	},
2145	},
2146	};
2147
2148	static struct clk_branch gcc_camss_tfe_0_csid_clk = {
2149	.halt_reg = 0x520ac,
2150	.halt_check = BRANCH_HALT,
2151	.clkr = {
2152	.enable_reg = 0x520ac,
2153	.enable_mask = BIT(0),
2154	.hw.init = &(struct clk_init_data){
2155	.name = "gcc_camss_tfe_0_csid_clk",
2156	.parent_hws = (const struct clk_hw*[]) {
2157	&gcc_camss_tfe_0_csid_clk_src.clkr.hw,
2158	},
2159	.num_parents = 1,
2160	.flags = CLK_SET_RATE_PARENT,
2161	.ops = &clk_branch2_ops,
2162	},
2163	},
2164	};
2165
2166	static struct clk_branch gcc_camss_tfe_1_clk = {
2167	.halt_reg = 0x5203c,
2168	.halt_check = BRANCH_HALT,
2169	.clkr = {
2170	.enable_reg = 0x5203c,
2171	.enable_mask = BIT(0),
2172	.hw.init = &(struct clk_init_data){
2173	.name = "gcc_camss_tfe_1_clk",
2174	.parent_hws = (const struct clk_hw*[]) {
2175	&gcc_camss_tfe_1_clk_src.clkr.hw,
2176	},
2177	.num_parents = 1,
2178	.flags = CLK_SET_RATE_PARENT,
2179	.ops = &clk_branch2_ops,
2180	},
2181	},
2182	};
2183
2184	static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
2185	.halt_reg = 0x52080,
2186	.halt_check = BRANCH_HALT,
2187	.clkr = {
2188	.enable_reg = 0x52080,
2189	.enable_mask = BIT(0),
2190	.hw.init = &(struct clk_init_data){
2191	.name = "gcc_camss_tfe_1_cphy_rx_clk",
2192	.parent_hws = (const struct clk_hw*[]) {
2193	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2194	},
2195	.num_parents = 1,
2196	.flags = CLK_SET_RATE_PARENT,
2197	.ops = &clk_branch2_ops,
2198	},
2199	},
2200	};
2201
2202	static struct clk_branch gcc_camss_tfe_1_csid_clk = {
2203	.halt_reg = 0x520cc,
2204	.halt_check = BRANCH_HALT,
2205	.clkr = {
2206	.enable_reg = 0x520cc,
2207	.enable_mask = BIT(0),
2208	.hw.init = &(struct clk_init_data){
2209	.name = "gcc_camss_tfe_1_csid_clk",
2210	.parent_hws = (const struct clk_hw*[]) {
2211	&gcc_camss_tfe_1_csid_clk_src.clkr.hw,
2212	},
2213	.num_parents = 1,
2214	.flags = CLK_SET_RATE_PARENT,
2215	.ops = &clk_branch2_ops,
2216	},
2217	},
2218	};
2219
2220	static struct clk_branch gcc_camss_tfe_2_clk = {
2221	.halt_reg = 0x5205c,
2222	.halt_check = BRANCH_HALT,
2223	.clkr = {
2224	.enable_reg = 0x5205c,
2225	.enable_mask = BIT(0),
2226	.hw.init = &(struct clk_init_data){
2227	.name = "gcc_camss_tfe_2_clk",
2228	.parent_hws = (const struct clk_hw*[]) {
2229	&gcc_camss_tfe_2_clk_src.clkr.hw,
2230	},
2231	.num_parents = 1,
2232	.flags = CLK_SET_RATE_PARENT,
2233	.ops = &clk_branch2_ops,
2234	},
2235	},
2236	};
2237
2238	static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
2239	.halt_reg = 0x52084,
2240	.halt_check = BRANCH_HALT,
2241	.clkr = {
2242	.enable_reg = 0x52084,
2243	.enable_mask = BIT(0),
2244	.hw.init = &(struct clk_init_data){
2245	.name = "gcc_camss_tfe_2_cphy_rx_clk",
2246	.parent_hws = (const struct clk_hw*[]) {
2247	&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2248	},
2249	.num_parents = 1,
2250	.flags = CLK_SET_RATE_PARENT,
2251	.ops = &clk_branch2_ops,
2252	},
2253	},
2254	};
2255
2256	static struct clk_branch gcc_camss_tfe_2_csid_clk = {
2257	.halt_reg = 0x520ec,
2258	.halt_check = BRANCH_HALT,
2259	.clkr = {
2260	.enable_reg = 0x520ec,
2261	.enable_mask = BIT(0),
2262	.hw.init = &(struct clk_init_data){
2263	.name = "gcc_camss_tfe_2_csid_clk",
2264	.parent_hws = (const struct clk_hw*[]) {
2265	&gcc_camss_tfe_2_csid_clk_src.clkr.hw,
2266	},
2267	.num_parents = 1,
2268	.flags = CLK_SET_RATE_PARENT,
2269	.ops = &clk_branch2_ops,
2270	},
2271	},
2272	};
2273
2274	static struct clk_branch gcc_camss_top_ahb_clk = {
2275	.halt_reg = 0x58028,
2276	.halt_check = BRANCH_HALT,
2277	.clkr = {
2278	.enable_reg = 0x58028,
2279	.enable_mask = BIT(0),
2280	.hw.init = &(struct clk_init_data){
2281	.name = "gcc_camss_top_ahb_clk",
2282	.parent_hws = (const struct clk_hw*[]) {
2283	&gcc_camss_top_ahb_clk_src.clkr.hw,
2284	},
2285	.num_parents = 1,
2286	.flags = CLK_SET_RATE_PARENT,
2287	.ops = &clk_branch2_ops,
2288	},
2289	},
2290	};
2291
2292	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2293	.halt_reg = 0x1a084,
2294	.halt_check = BRANCH_HALT_VOTED,
2295	.hwcg_reg = 0x1a084,
2296	.hwcg_bit = 1,
2297	.clkr = {
2298	.enable_reg = 0x1a084,
2299	.enable_mask = BIT(0),
2300	.hw.init = &(struct clk_init_data){
2301	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2302	.parent_hws = (const struct clk_hw*[]) {
2303	&gcc_usb30_prim_master_clk_src.clkr.hw,
2304	},
2305	.num_parents = 1,
2306	.flags = CLK_SET_RATE_PARENT,
2307	.ops = &clk_branch2_ops,
2308	},
2309	},
2310	};
2311
2312	static struct clk_branch gcc_disp_ahb_clk = {
2313	.halt_reg = 0x1700c,
2314	.halt_check = BRANCH_HALT_VOTED,
2315	.hwcg_reg = 0x1700c,
2316	.hwcg_bit = 1,
2317	.clkr = {
2318	.enable_reg = 0x1700c,
2319	.enable_mask = BIT(0),
2320	.hw.init = &(struct clk_init_data){
2321	.name = "gcc_disp_ahb_clk",
2322	.flags = CLK_IS_CRITICAL,
2323	.ops = &clk_branch2_ops,
2324	},
2325	},
2326	};
2327
2328	static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
2329	.reg = 0x17058,
2330	.shift = 0,
2331	.width = 2,
2332	.clkr.hw.init = &(struct clk_init_data) {
2333	.name = "gcc_disp_gpll0_clk_src",
2334	.parent_hws = (const struct clk_hw*[]){
2335	&gpll0.clkr.hw,
2336	},
2337	.num_parents = 1,
2338	.ops = &clk_regmap_div_ops,
2339	},
2340	};
2341
2342	static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2343	.halt_check = BRANCH_HALT_DELAY,
2344	.clkr = {
2345	.enable_reg = 0x79004,
2346	.enable_mask = BIT(20),
2347	.hw.init = &(struct clk_init_data){
2348	.name = "gcc_disp_gpll0_div_clk_src",
2349	.parent_hws = (const struct clk_hw*[]) {
2350	&gcc_disp_gpll0_clk_src.clkr.hw,
2351	},
2352	.num_parents = 1,
2353	.flags = CLK_SET_RATE_PARENT,
2354	.ops = &clk_branch2_ops,
2355	},
2356	},
2357	};
2358
2359	static struct clk_branch gcc_disp_hf_axi_clk = {
2360	.halt_reg = 0x17020,
2361	.halt_check = BRANCH_VOTED,
2362	.hwcg_reg = 0x17020,
2363	.hwcg_bit = 1,
2364	.clkr = {
2365	.enable_reg = 0x17020,
2366	.enable_mask = BIT(0),
2367	.hw.init = &(struct clk_init_data){
2368	.name = "gcc_disp_hf_axi_clk",
2369	.ops = &clk_branch2_ops,
2370	},
2371	},
2372	};
2373
2374	static struct clk_branch gcc_disp_sleep_clk = {
2375	.halt_reg = 0x17074,
2376	.halt_check = BRANCH_HALT_VOTED,
2377	.hwcg_reg = 0x17074,
2378	.hwcg_bit = 1,
2379	.clkr = {
2380	.enable_reg = 0x17074,
2381	.enable_mask = BIT(0),
2382	.hw.init = &(struct clk_init_data){
2383	.name = "gcc_disp_sleep_clk",
2384	.ops = &clk_branch2_ops,
2385	},
2386	},
2387	};
2388
2389	static struct clk_branch gcc_disp_throttle_core_clk = {
2390	.halt_reg = 0x17064,
2391	.halt_check = BRANCH_HALT_VOTED,
2392	.hwcg_reg = 0x17064,
2393	.hwcg_bit = 1,
2394	.clkr = {
2395	.enable_reg = 0x7900c,
2396	.enable_mask = BIT(5),
2397	.hw.init = &(struct clk_init_data){
2398	.name = "gcc_disp_throttle_core_clk",
2399	.ops = &clk_branch2_ops,
2400	},
2401	},
2402	};
2403
2404	static struct clk_branch gcc_gp1_clk = {
2405	.halt_reg = 0x4d000,
2406	.halt_check = BRANCH_HALT,
2407	.clkr = {
2408	.enable_reg = 0x4d000,
2409	.enable_mask = BIT(0),
2410	.hw.init = &(struct clk_init_data){
2411	.name = "gcc_gp1_clk",
2412	.parent_hws = (const struct clk_hw*[]) {
2413	&gcc_gp1_clk_src.clkr.hw,
2414	},
2415	.num_parents = 1,
2416	.flags = CLK_SET_RATE_PARENT,
2417	.ops = &clk_branch2_ops,
2418	},
2419	},
2420	};
2421
2422	static struct clk_branch gcc_gp2_clk = {
2423	.halt_reg = 0x4e000,
2424	.halt_check = BRANCH_HALT,
2425	.clkr = {
2426	.enable_reg = 0x4e000,
2427	.enable_mask = BIT(0),
2428	.hw.init = &(struct clk_init_data){
2429	.name = "gcc_gp2_clk",
2430	.parent_hws = (const struct clk_hw*[]) {
2431	&gcc_gp2_clk_src.clkr.hw,
2432	},
2433	.num_parents = 1,
2434	.flags = CLK_SET_RATE_PARENT,
2435	.ops = &clk_branch2_ops,
2436	},
2437	},
2438	};
2439
2440	static struct clk_branch gcc_gp3_clk = {
2441	.halt_reg = 0x4f000,
2442	.halt_check = BRANCH_HALT,
2443	.clkr = {
2444	.enable_reg = 0x4f000,
2445	.enable_mask = BIT(0),
2446	.hw.init = &(struct clk_init_data){
2447	.name = "gcc_gp3_clk",
2448	.parent_hws = (const struct clk_hw*[]) {
2449	&gcc_gp3_clk_src.clkr.hw,
2450	},
2451	.num_parents = 1,
2452	.flags = CLK_SET_RATE_PARENT,
2453	.ops = &clk_branch2_ops,
2454	},
2455	},
2456	};
2457
2458	static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2459	.halt_reg = 0x36004,
2460	.halt_check = BRANCH_HALT_VOTED,
2461	.hwcg_reg = 0x36004,
2462	.hwcg_bit = 1,
2463	.clkr = {
2464	.enable_reg = 0x36004,
2465	.enable_mask = BIT(0),
2466	.hw.init = &(struct clk_init_data){
2467	.name = "gcc_gpu_cfg_ahb_clk",
2468	.flags = CLK_IS_CRITICAL,
2469	.ops = &clk_branch2_ops,
2470	},
2471	},
2472	};
2473
2474	static struct clk_branch gcc_gpu_gpll0_clk_src = {
2475	.halt_check = BRANCH_HALT_DELAY,
2476	.clkr = {
2477	.enable_reg = 0x79004,
2478	.enable_mask = BIT(15),
2479	.hw.init = &(struct clk_init_data){
2480	.name = "gcc_gpu_gpll0_clk_src",
2481	.parent_hws = (const struct clk_hw*[]) {
2482	&gpll0.clkr.hw,
2483	},
2484	.num_parents = 1,
2485	.flags = CLK_SET_RATE_PARENT,
2486	.ops = &clk_branch2_ops,
2487	},
2488	},
2489	};
2490
2491	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2492	.halt_check = BRANCH_HALT_DELAY,
2493	.clkr = {
2494	.enable_reg = 0x79004,
2495	.enable_mask = BIT(16),
2496	.hw.init = &(struct clk_init_data){
2497	.name = "gcc_gpu_gpll0_div_clk_src",
2498	.parent_hws = (const struct clk_hw*[]) {
2499	&gpll0_out_even.clkr.hw,
2500	},
2501	.num_parents = 1,
2502	.flags = CLK_SET_RATE_PARENT,
2503	.ops = &clk_branch2_ops,
2504	},
2505	},
2506	};
2507
2508	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2509	.halt_reg = 0x3600c,
2510	.halt_check = BRANCH_VOTED,
2511	.hwcg_reg = 0x3600c,
2512	.hwcg_bit = 1,
2513	.clkr = {
2514	.enable_reg = 0x3600c,
2515	.enable_mask = BIT(0),
2516	.hw.init = &(struct clk_init_data){
2517	.name = "gcc_gpu_memnoc_gfx_clk",
2518	.ops = &clk_branch2_ops,
2519	},
2520	},
2521	};
2522
2523	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2524	.halt_reg = 0x36018,
2525	.halt_check = BRANCH_HALT,
2526	.clkr = {
2527	.enable_reg = 0x36018,
2528	.enable_mask = BIT(0),
2529	.hw.init = &(struct clk_init_data){
2530	.name = "gcc_gpu_snoc_dvm_gfx_clk",
2531	.ops = &clk_branch2_ops,
2532	},
2533	},
2534	};
2535
2536	static struct clk_branch gcc_gpu_throttle_core_clk = {
2537	.halt_reg = 0x36048,
2538	.halt_check = BRANCH_HALT_VOTED,
2539	.hwcg_reg = 0x36048,
2540	.hwcg_bit = 1,
2541	.clkr = {
2542	.enable_reg = 0x79004,
2543	.enable_mask = BIT(31),
2544	.hw.init = &(struct clk_init_data){
2545	.name = "gcc_gpu_throttle_core_clk",
2546	.ops = &clk_branch2_ops,
2547	},
2548	},
2549	};
2550
2551	static struct clk_branch gcc_pdm2_clk = {
2552	.halt_reg = 0x2000c,
2553	.halt_check = BRANCH_HALT,
2554	.clkr = {
2555	.enable_reg = 0x2000c,
2556	.enable_mask = BIT(0),
2557	.hw.init = &(struct clk_init_data){
2558	.name = "gcc_pdm2_clk",
2559	.parent_hws = (const struct clk_hw*[]) {
2560	&gcc_pdm2_clk_src.clkr.hw,
2561	},
2562	.num_parents = 1,
2563	.flags = CLK_SET_RATE_PARENT,
2564	.ops = &clk_branch2_ops,
2565	},
2566	},
2567	};
2568
2569	static struct clk_branch gcc_pdm_ahb_clk = {
2570	.halt_reg = 0x20004,
2571	.halt_check = BRANCH_HALT_VOTED,
2572	.hwcg_reg = 0x20004,
2573	.hwcg_bit = 1,
2574	.clkr = {
2575	.enable_reg = 0x20004,
2576	.enable_mask = BIT(0),
2577	.hw.init = &(struct clk_init_data){
2578	.name = "gcc_pdm_ahb_clk",
2579	.ops = &clk_branch2_ops,
2580	},
2581	},
2582	};
2583
2584	static struct clk_branch gcc_pdm_xo4_clk = {
2585	.halt_reg = 0x20008,
2586	.halt_check = BRANCH_HALT,
2587	.clkr = {
2588	.enable_reg = 0x20008,
2589	.enable_mask = BIT(0),
2590	.hw.init = &(struct clk_init_data){
2591	.name = "gcc_pdm_xo4_clk",
2592	.ops = &clk_branch2_ops,
2593	},
2594	},
2595	};
2596
2597	static struct clk_branch gcc_prng_ahb_clk = {
2598	.halt_reg = 0x21004,
2599	.halt_check = BRANCH_HALT_VOTED,
2600	.hwcg_reg = 0x21004,
2601	.hwcg_bit = 1,
2602	.clkr = {
2603	.enable_reg = 0x79004,
2604	.enable_mask = BIT(13),
2605	.hw.init = &(struct clk_init_data){
2606	.name = "gcc_prng_ahb_clk",
2607	.ops = &clk_branch2_ops,
2608	},
2609	},
2610	};
2611
2612	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2613	.halt_reg = 0x17014,
2614	.halt_check = BRANCH_HALT_VOTED,
2615	.hwcg_reg = 0x17014,
2616	.hwcg_bit = 1,
2617	.clkr = {
2618	.enable_reg = 0x7900c,
2619	.enable_mask = BIT(0),
2620	.hw.init = &(struct clk_init_data){
2621	.name = "gcc_qmip_camera_nrt_ahb_clk",
2622	.ops = &clk_branch2_ops,
2623	},
2624	},
2625	};
2626
2627	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2628	.halt_reg = 0x17060,
2629	.halt_check = BRANCH_HALT_VOTED,
2630	.hwcg_reg = 0x17060,
2631	.hwcg_bit = 1,
2632	.clkr = {
2633	.enable_reg = 0x7900c,
2634	.enable_mask = BIT(2),
2635	.hw.init = &(struct clk_init_data){
2636	.name = "gcc_qmip_camera_rt_ahb_clk",
2637	.ops = &clk_branch2_ops,
2638	},
2639	},
2640	};
2641
2642	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2643	.halt_reg = 0x17018,
2644	.halt_check = BRANCH_HALT_VOTED,
2645	.hwcg_reg = 0x17018,
2646	.hwcg_bit = 1,
2647	.clkr = {
2648	.enable_reg = 0x7900c,
2649	.enable_mask = BIT(1),
2650	.hw.init = &(struct clk_init_data){
2651	.name = "gcc_qmip_disp_ahb_clk",
2652	.ops = &clk_branch2_ops,
2653	},
2654	},
2655	};
2656
2657	static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2658	.halt_reg = 0x36040,
2659	.halt_check = BRANCH_HALT_VOTED,
2660	.hwcg_reg = 0x36040,
2661	.hwcg_bit = 1,
2662	.clkr = {
2663	.enable_reg = 0x7900c,
2664	.enable_mask = BIT(4),
2665	.hw.init = &(struct clk_init_data){
2666	.name = "gcc_qmip_gpu_cfg_ahb_clk",
2667	.ops = &clk_branch2_ops,
2668	},
2669	},
2670	};
2671
2672	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2673	.halt_reg = 0x17010,
2674	.halt_check = BRANCH_HALT_VOTED,
2675	.hwcg_reg = 0x17010,
2676	.hwcg_bit = 1,
2677	.clkr = {
2678	.enable_reg = 0x79004,
2679	.enable_mask = BIT(25),
2680	.hw.init = &(struct clk_init_data){
2681	.name = "gcc_qmip_video_vcodec_ahb_clk",
2682	.ops = &clk_branch2_ops,
2683	},
2684	},
2685	};
2686
2687	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2688	.halt_reg = 0x1f014,
2689	.halt_check = BRANCH_HALT_VOTED,
2690	.clkr = {
2691	.enable_reg = 0x7900c,
2692	.enable_mask = BIT(9),
2693	.hw.init = &(struct clk_init_data){
2694	.name = "gcc_qupv3_wrap0_core_2x_clk",
2695	.ops = &clk_branch2_ops,
2696	},
2697	},
2698	};
2699
2700	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2701	.halt_reg = 0x1f00c,
2702	.halt_check = BRANCH_HALT_VOTED,
2703	.clkr = {
2704	.enable_reg = 0x7900c,
2705	.enable_mask = BIT(8),
2706	.hw.init = &(struct clk_init_data){
2707	.name = "gcc_qupv3_wrap0_core_clk",
2708	.ops = &clk_branch2_ops,
2709	},
2710	},
2711	};
2712
2713	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2714	.halt_reg = 0x1f144,
2715	.halt_check = BRANCH_HALT_VOTED,
2716	.clkr = {
2717	.enable_reg = 0x7900c,
2718	.enable_mask = BIT(10),
2719	.hw.init = &(struct clk_init_data){
2720	.name = "gcc_qupv3_wrap0_s0_clk",
2721	.parent_hws = (const struct clk_hw*[]) {
2722	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2723	},
2724	.num_parents = 1,
2725	.flags = CLK_SET_RATE_PARENT,
2726	.ops = &clk_branch2_ops,
2727	},
2728	},
2729	};
2730
2731	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2732	.halt_reg = 0x1f274,
2733	.halt_check = BRANCH_HALT_VOTED,
2734	.clkr = {
2735	.enable_reg = 0x7900c,
2736	.enable_mask = BIT(11),
2737	.hw.init = &(struct clk_init_data){
2738	.name = "gcc_qupv3_wrap0_s1_clk",
2739	.parent_hws = (const struct clk_hw*[]) {
2740	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2741	},
2742	.num_parents = 1,
2743	.flags = CLK_SET_RATE_PARENT,
2744	.ops = &clk_branch2_ops,
2745	},
2746	},
2747	};
2748
2749	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2750	.halt_reg = 0x1f3a4,
2751	.halt_check = BRANCH_HALT_VOTED,
2752	.clkr = {
2753	.enable_reg = 0x7900c,
2754	.enable_mask = BIT(12),
2755	.hw.init = &(struct clk_init_data){
2756	.name = "gcc_qupv3_wrap0_s2_clk",
2757	.parent_hws = (const struct clk_hw*[]) {
2758	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2759	},
2760	.num_parents = 1,
2761	.flags = CLK_SET_RATE_PARENT,
2762	.ops = &clk_branch2_ops,
2763	},
2764	},
2765	};
2766
2767	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2768	.halt_reg = 0x1f4d4,
2769	.halt_check = BRANCH_HALT_VOTED,
2770	.clkr = {
2771	.enable_reg = 0x7900c,
2772	.enable_mask = BIT(13),
2773	.hw.init = &(struct clk_init_data){
2774	.name = "gcc_qupv3_wrap0_s3_clk",
2775	.parent_hws = (const struct clk_hw*[]) {
2776	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2777	},
2778	.num_parents = 1,
2779	.flags = CLK_SET_RATE_PARENT,
2780	.ops = &clk_branch2_ops,
2781	},
2782	},
2783	};
2784
2785	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2786	.halt_reg = 0x1f604,
2787	.halt_check = BRANCH_HALT_VOTED,
2788	.clkr = {
2789	.enable_reg = 0x7900c,
2790	.enable_mask = BIT(14),
2791	.hw.init = &(struct clk_init_data){
2792	.name = "gcc_qupv3_wrap0_s4_clk",
2793	.parent_hws = (const struct clk_hw*[]) {
2794	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2795	},
2796	.num_parents = 1,
2797	.flags = CLK_SET_RATE_PARENT,
2798	.ops = &clk_branch2_ops,
2799	},
2800	},
2801	};
2802
2803	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2804	.halt_reg = 0x1f734,
2805	.halt_check = BRANCH_HALT_VOTED,
2806	.clkr = {
2807	.enable_reg = 0x7900c,
2808	.enable_mask = BIT(15),
2809	.hw.init = &(struct clk_init_data){
2810	.name = "gcc_qupv3_wrap0_s5_clk",
2811	.parent_hws = (const struct clk_hw*[]) {
2812	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2813	},
2814	.num_parents = 1,
2815	.flags = CLK_SET_RATE_PARENT,
2816	.ops = &clk_branch2_ops,
2817	},
2818	},
2819	};
2820
2821	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2822	.halt_reg = 0x53014,
2823	.halt_check = BRANCH_HALT_VOTED,
2824	.clkr = {
2825	.enable_reg = 0x7900c,
2826	.enable_mask = BIT(20),
2827	.hw.init = &(struct clk_init_data){
2828	.name = "gcc_qupv3_wrap1_core_2x_clk",
2829	.ops = &clk_branch2_ops,
2830	},
2831	},
2832	};
2833
2834	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2835	.halt_reg = 0x5300c,
2836	.halt_check = BRANCH_HALT_VOTED,
2837	.clkr = {
2838	.enable_reg = 0x7900c,
2839	.enable_mask = BIT(19),
2840	.hw.init = &(struct clk_init_data){
2841	.name = "gcc_qupv3_wrap1_core_clk",
2842	.ops = &clk_branch2_ops,
2843	},
2844	},
2845	};
2846
2847	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2848	.halt_reg = 0x53018,
2849	.halt_check = BRANCH_HALT_VOTED,
2850	.clkr = {
2851	.enable_reg = 0x7900c,
2852	.enable_mask = BIT(21),
2853	.hw.init = &(struct clk_init_data){
2854	.name = "gcc_qupv3_wrap1_s0_clk",
2855	.parent_hws = (const struct clk_hw*[]) {
2856	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2857	},
2858	.num_parents = 1,
2859	.flags = CLK_SET_RATE_PARENT,
2860	.ops = &clk_branch2_ops,
2861	},
2862	},
2863	};
2864
2865	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2866	.halt_reg = 0x53148,
2867	.halt_check = BRANCH_HALT_VOTED,
2868	.clkr = {
2869	.enable_reg = 0x7900c,
2870	.enable_mask = BIT(22),
2871	.hw.init = &(struct clk_init_data){
2872	.name = "gcc_qupv3_wrap1_s1_clk",
2873	.parent_hws = (const struct clk_hw*[]) {
2874	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2875	},
2876	.num_parents = 1,
2877	.flags = CLK_SET_RATE_PARENT,
2878	.ops = &clk_branch2_ops,
2879	},
2880	},
2881	};
2882
2883	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2884	.halt_reg = 0x53278,
2885	.halt_check = BRANCH_HALT_VOTED,
2886	.clkr = {
2887	.enable_reg = 0x7900c,
2888	.enable_mask = BIT(23),
2889	.hw.init = &(struct clk_init_data){
2890	.name = "gcc_qupv3_wrap1_s2_clk",
2891	.parent_hws = (const struct clk_hw*[]) {
2892	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2893	},
2894	.num_parents = 1,
2895	.flags = CLK_SET_RATE_PARENT,
2896	.ops = &clk_branch2_ops,
2897	},
2898	},
2899	};
2900
2901	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2902	.halt_reg = 0x533a8,
2903	.halt_check = BRANCH_HALT_VOTED,
2904	.clkr = {
2905	.enable_reg = 0x7900c,
2906	.enable_mask = BIT(24),
2907	.hw.init = &(struct clk_init_data){
2908	.name = "gcc_qupv3_wrap1_s3_clk",
2909	.parent_hws = (const struct clk_hw*[]) {
2910	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2911	},
2912	.num_parents = 1,
2913	.flags = CLK_SET_RATE_PARENT,
2914	.ops = &clk_branch2_ops,
2915	},
2916	},
2917	};
2918
2919	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2920	.halt_reg = 0x534d8,
2921	.halt_check = BRANCH_HALT_VOTED,
2922	.clkr = {
2923	.enable_reg = 0x7900c,
2924	.enable_mask = BIT(25),
2925	.hw.init = &(struct clk_init_data){
2926	.name = "gcc_qupv3_wrap1_s4_clk",
2927	.parent_hws = (const struct clk_hw*[]) {
2928	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2929	},
2930	.num_parents = 1,
2931	.flags = CLK_SET_RATE_PARENT,
2932	.ops = &clk_branch2_ops,
2933	},
2934	},
2935	};
2936
2937	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2938	.halt_reg = 0x53608,
2939	.halt_check = BRANCH_HALT_VOTED,
2940	.clkr = {
2941	.enable_reg = 0x7900c,
2942	.enable_mask = BIT(26),
2943	.hw.init = &(struct clk_init_data){
2944	.name = "gcc_qupv3_wrap1_s5_clk",
2945	.parent_hws = (const struct clk_hw*[]) {
2946	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2947	},
2948	.num_parents = 1,
2949	.flags = CLK_SET_RATE_PARENT,
2950	.ops = &clk_branch2_ops,
2951	},
2952	},
2953	};
2954
2955	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2956	.halt_reg = 0x1f004,
2957	.halt_check = BRANCH_HALT_VOTED,
2958	.hwcg_reg = 0x1f004,
2959	.hwcg_bit = 1,
2960	.clkr = {
2961	.enable_reg = 0x7900c,
2962	.enable_mask = BIT(6),
2963	.hw.init = &(struct clk_init_data){
2964	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2965	.ops = &clk_branch2_ops,
2966	},
2967	},
2968	};
2969
2970	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2971	.halt_reg = 0x1f008,
2972	.halt_check = BRANCH_HALT_VOTED,
2973	.hwcg_reg = 0x1f008,
2974	.hwcg_bit = 1,
2975	.clkr = {
2976	.enable_reg = 0x7900c,
2977	.enable_mask = BIT(7),
2978	.hw.init = &(struct clk_init_data){
2979	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2980	.ops = &clk_branch2_ops,
2981	},
2982	},
2983	};
2984
2985	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2986	.halt_reg = 0x53004,
2987	.halt_check = BRANCH_HALT_VOTED,
2988	.hwcg_reg = 0x53004,
2989	.hwcg_bit = 1,
2990	.clkr = {
2991	.enable_reg = 0x7900c,
2992	.enable_mask = BIT(17),
2993	.hw.init = &(struct clk_init_data){
2994	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2995	.ops = &clk_branch2_ops,
2996	},
2997	},
2998	};
2999
3000	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3001	.halt_reg = 0x53008,
3002	.halt_check = BRANCH_HALT_VOTED,
3003	.hwcg_reg = 0x53008,
3004	.hwcg_bit = 1,
3005	.clkr = {
3006	.enable_reg = 0x7900c,
3007	.enable_mask = BIT(18),
3008	.hw.init = &(struct clk_init_data){
3009	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
3010	.ops = &clk_branch2_ops,
3011	},
3012	},
3013	};
3014
3015	static struct clk_branch gcc_sdcc1_ahb_clk = {
3016	.halt_reg = 0x38008,
3017	.halt_check = BRANCH_HALT,
3018	.clkr = {
3019	.enable_reg = 0x38008,
3020	.enable_mask = BIT(0),
3021	.hw.init = &(struct clk_init_data){
3022	.name = "gcc_sdcc1_ahb_clk",
3023	.ops = &clk_branch2_ops,
3024	},
3025	},
3026	};
3027
3028	static struct clk_branch gcc_sdcc1_apps_clk = {
3029	.halt_reg = 0x38004,
3030	.halt_check = BRANCH_HALT,
3031	.clkr = {
3032	.enable_reg = 0x38004,
3033	.enable_mask = BIT(0),
3034	.hw.init = &(struct clk_init_data){
3035	.name = "gcc_sdcc1_apps_clk",
3036	.parent_hws = (const struct clk_hw*[]) {
3037	&gcc_sdcc1_apps_clk_src.clkr.hw,
3038	},
3039	.num_parents = 1,
3040	.flags = CLK_SET_RATE_PARENT,
3041	.ops = &clk_branch2_ops,
3042	},
3043	},
3044	};
3045
3046	static struct clk_branch gcc_sdcc1_ice_core_clk = {
3047	.halt_reg = 0x3800c,
3048	.halt_check = BRANCH_HALT_VOTED,
3049	.hwcg_reg = 0x3800c,
3050	.hwcg_bit = 1,
3051	.clkr = {
3052	.enable_reg = 0x3800c,
3053	.enable_mask = BIT(0),
3054	.hw.init = &(struct clk_init_data){
3055	.name = "gcc_sdcc1_ice_core_clk",
3056	.parent_hws = (const struct clk_hw*[]) {
3057	&gcc_sdcc1_ice_core_clk_src.clkr.hw,
3058	},
3059	.num_parents = 1,
3060	.flags = CLK_SET_RATE_PARENT,
3061	.ops = &clk_branch2_ops,
3062	},
3063	},
3064	};
3065
3066	static struct clk_branch gcc_sdcc2_ahb_clk = {
3067	.halt_reg = 0x1e008,
3068	.halt_check = BRANCH_HALT,
3069	.clkr = {
3070	.enable_reg = 0x1e008,
3071	.enable_mask = BIT(0),
3072	.hw.init = &(struct clk_init_data){
3073	.name = "gcc_sdcc2_ahb_clk",
3074	.ops = &clk_branch2_ops,
3075	},
3076	},
3077	};
3078
3079	static struct clk_branch gcc_sdcc2_apps_clk = {
3080	.halt_reg = 0x1e004,
3081	.halt_check = BRANCH_HALT,
3082	.clkr = {
3083	.enable_reg = 0x1e004,
3084	.enable_mask = BIT(0),
3085	.hw.init = &(struct clk_init_data){
3086	.name = "gcc_sdcc2_apps_clk",
3087	.parent_hws = (const struct clk_hw*[]) {
3088	&gcc_sdcc2_apps_clk_src.clkr.hw,
3089	},
3090	.num_parents = 1,
3091	.flags = CLK_SET_RATE_PARENT,
3092	.ops = &clk_branch2_ops,
3093	},
3094	},
3095	};
3096
3097	static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3098	.halt_reg = 0x2b06c,
3099	.halt_check = BRANCH_HALT_VOTED,
3100	.hwcg_reg = 0x2b06c,
3101	.hwcg_bit = 1,
3102	.clkr = {
3103	.enable_reg = 0x79004,
3104	.enable_mask = BIT(0),
3105	.hw.init = &(struct clk_init_data){
3106	.name = "gcc_sys_noc_cpuss_ahb_clk",
3107	.parent_hws = (const struct clk_hw*[]) {
3108	&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
3109	},
3110	.num_parents = 1,
3111	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
3112	.ops = &clk_branch2_ops,
3113	},
3114	},
3115	};
3116
3117	static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
3118	.halt_reg = 0x45098,
3119	.halt_check = BRANCH_HALT,
3120	.clkr = {
3121	.enable_reg = 0x45098,
3122	.enable_mask = BIT(0),
3123	.hw.init = &(struct clk_init_data){
3124	.name = "gcc_sys_noc_ufs_phy_axi_clk",
3125	.parent_hws = (const struct clk_hw*[]) {
3126	&gcc_ufs_phy_axi_clk_src.clkr.hw,
3127	},
3128	.num_parents = 1,
3129	.flags = CLK_SET_RATE_PARENT,
3130	.ops = &clk_branch2_ops,
3131	},
3132	},
3133	};
3134
3135	static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
3136	.halt_reg = 0x1a080,
3137	.halt_check = BRANCH_HALT_VOTED,
3138	.hwcg_reg = 0x1a080,
3139	.hwcg_bit = 1,
3140	.clkr = {
3141	.enable_reg = 0x1a080,
3142	.enable_mask = BIT(0),
3143	.hw.init = &(struct clk_init_data){
3144	.name = "gcc_sys_noc_usb3_prim_axi_clk",
3145	.parent_hws = (const struct clk_hw*[]) {
3146	&gcc_usb30_prim_master_clk_src.clkr.hw,
3147	},
3148	.num_parents = 1,
3149	.flags = CLK_SET_RATE_PARENT,
3150	.ops = &clk_branch2_ops,
3151	},
3152	},
3153	};
3154
3155	static struct clk_branch gcc_ufs_phy_ahb_clk = {
3156	.halt_reg = 0x45014,
3157	.halt_check = BRANCH_HALT_VOTED,
3158	.hwcg_reg = 0x45014,
3159	.hwcg_bit = 1,
3160	.clkr = {
3161	.enable_reg = 0x45014,
3162	.enable_mask = BIT(0),
3163	.hw.init = &(struct clk_init_data){
3164	.name = "gcc_ufs_phy_ahb_clk",
3165	.ops = &clk_branch2_ops,
3166	},
3167	},
3168	};
3169
3170	static struct clk_branch gcc_ufs_phy_axi_clk = {
3171	.halt_reg = 0x45010,
3172	.halt_check = BRANCH_HALT_VOTED,
3173	.hwcg_reg = 0x45010,
3174	.hwcg_bit = 1,
3175	.clkr = {
3176	.enable_reg = 0x45010,
3177	.enable_mask = BIT(0),
3178	.hw.init = &(struct clk_init_data){
3179	.name = "gcc_ufs_phy_axi_clk",
3180	.parent_hws = (const struct clk_hw*[]) {
3181	&gcc_ufs_phy_axi_clk_src.clkr.hw,
3182	},
3183	.num_parents = 1,
3184	.flags = CLK_SET_RATE_PARENT,
3185	.ops = &clk_branch2_ops,
3186	},
3187	},
3188	};
3189
3190	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3191	.halt_reg = 0x45044,
3192	.halt_check = BRANCH_HALT_VOTED,
3193	.hwcg_reg = 0x45044,
3194	.hwcg_bit = 1,
3195	.clkr = {
3196	.enable_reg = 0x45044,
3197	.enable_mask = BIT(0),
3198	.hw.init = &(struct clk_init_data){
3199	.name = "gcc_ufs_phy_ice_core_clk",
3200	.parent_hws = (const struct clk_hw*[]) {
3201	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3202	},
3203	.num_parents = 1,
3204	.flags = CLK_SET_RATE_PARENT,
3205	.ops = &clk_branch2_ops,
3206	},
3207	},
3208	};
3209
3210	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3211	.halt_reg = 0x45078,
3212	.halt_check = BRANCH_HALT_VOTED,
3213	.hwcg_reg = 0x45078,
3214	.hwcg_bit = 1,
3215	.clkr = {
3216	.enable_reg = 0x45078,
3217	.enable_mask = BIT(0),
3218	.hw.init = &(struct clk_init_data){
3219	.name = "gcc_ufs_phy_phy_aux_clk",
3220	.parent_hws = (const struct clk_hw*[]) {
3221	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3222	},
3223	.num_parents = 1,
3224	.flags = CLK_SET_RATE_PARENT,
3225	.ops = &clk_branch2_ops,
3226	},
3227	},
3228	};
3229
3230	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3231	.halt_reg = 0x4501c,
3232	.halt_check = BRANCH_HALT_SKIP,
3233	.clkr = {
3234	.enable_reg = 0x4501c,
3235	.enable_mask = BIT(0),
3236	.hw.init = &(struct clk_init_data){
3237	.name = "gcc_ufs_phy_rx_symbol_0_clk",
3238	.ops = &clk_branch2_ops,
3239	},
3240	},
3241	};
3242
3243	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3244	.halt_reg = 0x45018,
3245	.halt_check = BRANCH_HALT_SKIP,
3246	.clkr = {
3247	.enable_reg = 0x45018,
3248	.enable_mask = BIT(0),
3249	.hw.init = &(struct clk_init_data){
3250	.name = "gcc_ufs_phy_tx_symbol_0_clk",
3251	.ops = &clk_branch2_ops,
3252	},
3253	},
3254	};
3255
3256	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3257	.halt_reg = 0x45040,
3258	.halt_check = BRANCH_HALT_VOTED,
3259	.hwcg_reg = 0x45040,
3260	.hwcg_bit = 1,
3261	.clkr = {
3262	.enable_reg = 0x45040,
3263	.enable_mask = BIT(0),
3264	.hw.init = &(struct clk_init_data){
3265	.name = "gcc_ufs_phy_unipro_core_clk",
3266	.parent_hws = (const struct clk_hw*[]) {
3267	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3268	},
3269	.num_parents = 1,
3270	.flags = CLK_SET_RATE_PARENT,
3271	.ops = &clk_branch2_ops,
3272	},
3273	},
3274	};
3275
3276	static struct clk_branch gcc_usb30_prim_master_clk = {
3277	.halt_reg = 0x1a010,
3278	.halt_check = BRANCH_HALT,
3279	.clkr = {
3280	.enable_reg = 0x1a010,
3281	.enable_mask = BIT(0),
3282	.hw.init = &(struct clk_init_data){
3283	.name = "gcc_usb30_prim_master_clk",
3284	.parent_hws = (const struct clk_hw*[]) {
3285	&gcc_usb30_prim_master_clk_src.clkr.hw,
3286	},
3287	.num_parents = 1,
3288	.flags = CLK_SET_RATE_PARENT,
3289	.ops = &clk_branch2_ops,
3290	},
3291	},
3292	};
3293
3294	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3295	.halt_reg = 0x1a018,
3296	.halt_check = BRANCH_HALT,
3297	.clkr = {
3298	.enable_reg = 0x1a018,
3299	.enable_mask = BIT(0),
3300	.hw.init = &(struct clk_init_data){
3301	.name = "gcc_usb30_prim_mock_utmi_clk",
3302	.parent_hws = (const struct clk_hw*[]) {
3303	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3304	},
3305	.num_parents = 1,
3306	.flags = CLK_SET_RATE_PARENT,
3307	.ops = &clk_branch2_ops,
3308	},
3309	},
3310	};
3311
3312	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3313	.halt_reg = 0x1a014,
3314	.halt_check = BRANCH_HALT,
3315	.clkr = {
3316	.enable_reg = 0x1a014,
3317	.enable_mask = BIT(0),
3318	.hw.init = &(struct clk_init_data){
3319	.name = "gcc_usb30_prim_sleep_clk",
3320	.ops = &clk_branch2_ops,
3321	},
3322	},
3323	};
3324
3325	static struct clk_branch gcc_ufs_mem_clkref_clk = {
3326	.halt_reg = 0x8c000,
3327	.halt_check = BRANCH_HALT,
3328	.clkr = {
3329	.enable_reg = 0x8c000,
3330	.enable_mask = BIT(0),
3331	.hw.init = &(struct clk_init_data){
3332	.name = "gcc_ufs_mem_clkref_clk",
3333	.ops = &clk_branch2_ops,
3334	},
3335	},
3336	};
3337
3338	static struct clk_branch gcc_rx5_pcie_clkref_en_clk = {
3339	.halt_reg = 0x8c00c,
3340	.halt_check = BRANCH_HALT,
3341	.clkr = {
3342	.enable_reg = 0x8c00c,
3343	.enable_mask = BIT(0),
3344	.hw.init = &(struct clk_init_data){
3345	.name = "gcc_rx5_pcie_clkref_en_clk",
3346	.ops = &clk_branch2_ops,
3347	},
3348	},
3349	};
3350
3351	static struct clk_branch gcc_usb3_prim_clkref_clk = {
3352	.halt_reg = 0x8c010,
3353	.halt_check = BRANCH_HALT,
3354	.clkr = {
3355	.enable_reg = 0x8c010,
3356	.enable_mask = BIT(0),
3357	.hw.init = &(struct clk_init_data){
3358	.name = "gcc_usb3_prim_clkref_clk",
3359	.ops = &clk_branch2_ops,
3360	},
3361	},
3362	};
3363
3364	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3365	.halt_reg = 0x1a054,
3366	.halt_check = BRANCH_HALT,
3367	.clkr = {
3368	.enable_reg = 0x1a054,
3369	.enable_mask = BIT(0),
3370	.hw.init = &(struct clk_init_data){
3371	.name = "gcc_usb3_prim_phy_com_aux_clk",
3372	.parent_hws = (const struct clk_hw*[]) {
3373	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3374	},
3375	.num_parents = 1,
3376	.flags = CLK_SET_RATE_PARENT,
3377	.ops = &clk_branch2_ops,
3378	},
3379	},
3380	};
3381
3382	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3383	.halt_reg = 0x1a058,
3384	.halt_check = BRANCH_HALT_SKIP,
3385	.hwcg_reg = 0x1a058,
3386	.hwcg_bit = 1,
3387	.clkr = {
3388	.enable_reg = 0x1a058,
3389	.enable_mask = BIT(0),
3390	.hw.init = &(struct clk_init_data){
3391	.name = "gcc_usb3_prim_phy_pipe_clk",
3392	.ops = &clk_branch2_ops,
3393	},
3394	},
3395	};
3396
3397	static struct clk_branch gcc_vcodec0_axi_clk = {
3398	.halt_reg = 0x6e008,
3399	.halt_check = BRANCH_HALT,
3400	.clkr = {
3401	.enable_reg = 0x6e008,
3402	.enable_mask = BIT(0),
3403	.hw.init = &(struct clk_init_data){
3404	.name = "gcc_vcodec0_axi_clk",
3405	.ops = &clk_branch2_ops,
3406	},
3407	},
3408	};
3409
3410	static struct clk_branch gcc_venus_ahb_clk = {
3411	.halt_reg = 0x6e010,
3412	.halt_check = BRANCH_HALT,
3413	.clkr = {
3414	.enable_reg = 0x6e010,
3415	.enable_mask = BIT(0),
3416	.hw.init = &(struct clk_init_data){
3417	.name = "gcc_venus_ahb_clk",
3418	.ops = &clk_branch2_ops,
3419	},
3420	},
3421	};
3422
3423	static struct clk_branch gcc_venus_ctl_axi_clk = {
3424	.halt_reg = 0x6e004,
3425	.halt_check = BRANCH_HALT,
3426	.clkr = {
3427	.enable_reg = 0x6e004,
3428	.enable_mask = BIT(0),
3429	.hw.init = &(struct clk_init_data){
3430	.name = "gcc_venus_ctl_axi_clk",
3431	.ops = &clk_branch2_ops,
3432	},
3433	},
3434	};
3435
3436	static struct clk_branch gcc_video_ahb_clk = {
3437	.halt_reg = 0x17004,
3438	.halt_check = BRANCH_HALT_DELAY,
3439	.hwcg_reg = 0x17004,
3440	.hwcg_bit = 1,
3441	.clkr = {
3442	.enable_reg = 0x17004,
3443	.enable_mask = BIT(0),
3444	.hw.init = &(struct clk_init_data){
3445	.name = "gcc_video_ahb_clk",
3446	.flags = CLK_IS_CRITICAL,
3447	.ops = &clk_branch2_ops,
3448	},
3449	},
3450	};
3451
3452	static struct clk_branch gcc_video_axi0_clk = {
3453	.halt_reg = 0x1701c,
3454	.halt_check = BRANCH_HALT_VOTED,
3455	.hwcg_reg = 0x1701c,
3456	.hwcg_bit = 1,
3457	.clkr = {
3458	.enable_reg = 0x1701c,
3459	.enable_mask = BIT(0),
3460	.hw.init = &(struct clk_init_data){
3461	.name = "gcc_video_axi0_clk",
3462	.ops = &clk_branch2_ops,
3463	},
3464	},
3465	};
3466
3467	static struct clk_branch gcc_video_throttle_core_clk = {
3468	.halt_reg = 0x17068,
3469	.halt_check = BRANCH_HALT_VOTED,
3470	.hwcg_reg = 0x17068,
3471	.hwcg_bit = 1,
3472	.clkr = {
3473	.enable_reg = 0x79004,
3474	.enable_mask = BIT(28),
3475	.hw.init = &(struct clk_init_data){
3476	.name = "gcc_video_throttle_core_clk",
3477	.ops = &clk_branch2_ops,
3478	},
3479	},
3480	};
3481
3482	static struct clk_branch gcc_video_vcodec0_sys_clk = {
3483	.halt_reg = 0x580a4,
3484	.halt_check = BRANCH_HALT_VOTED,
3485	.hwcg_reg = 0x580a4,
3486	.hwcg_bit = 1,
3487	.clkr = {
3488	.enable_reg = 0x580a4,
3489	.enable_mask = BIT(0),
3490	.hw.init = &(struct clk_init_data){
3491	.name = "gcc_video_vcodec0_sys_clk",
3492	.parent_hws = (const struct clk_hw*[]) {
3493	&gcc_video_venus_clk_src.clkr.hw,
3494	},
3495	.num_parents = 1,
3496	.flags = CLK_SET_RATE_PARENT,
3497	.ops = &clk_branch2_ops,
3498	},
3499	},
3500	};
3501
3502	static struct clk_branch gcc_video_venus_ctl_clk = {
3503	.halt_reg = 0x5808c,
3504	.halt_check = BRANCH_HALT,
3505	.clkr = {
3506	.enable_reg = 0x5808c,
3507	.enable_mask = BIT(0),
3508	.hw.init = &(struct clk_init_data){
3509	.name = "gcc_video_venus_ctl_clk",
3510	.parent_hws = (const struct clk_hw*[]) {
3511	&gcc_video_venus_clk_src.clkr.hw,
3512	},
3513	.num_parents = 1,
3514	.flags = CLK_SET_RATE_PARENT,
3515	.ops = &clk_branch2_ops,
3516	},
3517	},
3518	};
3519
3520	static struct clk_branch gcc_video_xo_clk = {
3521	.halt_reg = 0x17024,
3522	.halt_check = BRANCH_HALT,
3523	.clkr = {
3524	.enable_reg = 0x17024,
3525	.enable_mask = BIT(0),
3526	.hw.init = &(struct clk_init_data){
3527	.name = "gcc_video_xo_clk",
3528	.ops = &clk_branch2_ops,
3529	},
3530	},
3531	};
3532
3533	static struct gdsc usb30_prim_gdsc = {
3534	.gdscr = 0x1a004,
3535	.pd = {
3536	.name = "usb30_prim_gdsc",
3537	},
3538	/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
3539	.pwrsts = PWRSTS_RET_ON,
3540	};
3541
3542	static struct gdsc ufs_phy_gdsc = {
3543	.gdscr = 0x45004,
3544	.pd = {
3545	.name = "ufs_phy_gdsc",
3546	},
3547	.pwrsts = PWRSTS_OFF_ON,
3548	};
3549
3550	static struct gdsc camss_top_gdsc = {
3551	.gdscr = 0x58004,
3552	.pd = {
3553	.name = "camss_top_gdsc",
3554	},
3555	.pwrsts = PWRSTS_OFF_ON,
3556	};
3557
3558	static struct gdsc venus_gdsc = {
3559	.gdscr = 0x5807c,
3560	.pd = {
3561	.name = "venus_gdsc",
3562	},
3563	.pwrsts = PWRSTS_OFF_ON,
3564	};
3565
3566	static struct gdsc vcodec0_gdsc = {
3567	.gdscr = 0x58098,
3568	.pd = {
3569	.name = "vcodec0_gdsc",
3570	},
3571	.pwrsts = PWRSTS_OFF_ON,
3572	.flags = HW_CTRL,
3573	};
3574
3575	static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3576	.gdscr = 0x7d074,
3577	.pd = {
3578	.name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
3579	},
3580	.pwrsts = PWRSTS_OFF_ON,
3581	.flags = VOTABLE,
3582	};
3583
3584	static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3585	.gdscr = 0x7d078,
3586	.pd = {
3587	.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
3588	},
3589	.pwrsts = PWRSTS_OFF_ON,
3590	.flags = VOTABLE,
3591	};
3592
3593	static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3594	.gdscr = 0x7d060,
3595	.pd = {
3596	.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3597	},
3598	.pwrsts = PWRSTS_OFF_ON,
3599	.flags = VOTABLE,
3600	};
3601
3602	static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3603	.gdscr = 0x7d07c,
3604	.pd = {
3605	.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3606	},
3607	.pwrsts = PWRSTS_OFF_ON,
3608	.flags = VOTABLE,
3609	};
3610
3611	static struct clk_regmap *gcc_sm6375_clocks[] = {
3612	[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3613	[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3614	[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3615	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3616	[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
3617	[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
3618	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3619	[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
3620	[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
3621	[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
3622	[GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr,
3623	[GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr,
3624	[GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr,
3625	[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
3626	[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
3627	[GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
3628	[GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr,
3629	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3630	[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3631	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3632	[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3633	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3634	[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3635	[GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr,
3636	[GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr,
3637	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3638	[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3639	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3640	[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3641	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3642	[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3643	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3644	[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3645	[GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr,
3646	[GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr,
3647	[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
3648	[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
3649	[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
3650	[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
3651	[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
3652	[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
3653	[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
3654	[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
3655	[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
3656	[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
3657	[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
3658	[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
3659	[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
3660	[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
3661	[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
3662	[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
3663	[GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
3664	[GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
3665	[GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
3666	[GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
3667	[GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
3668	[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
3669	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3670	[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
3671	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3672	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3673	[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
3674	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3675	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3676	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3677	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3678	[GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr,
3679	[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3680	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3681	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3682	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3683	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3684	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3685	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3686	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3687	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3688	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3689	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3690	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3691	[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3692	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3693	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3694	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3695	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3696	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3697	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3698	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3699	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3700	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3701	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3702	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3703	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3704	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3705	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3706	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3707	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3708	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3709	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3710	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3711	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3712	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3713	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3714	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3715	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3716	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3717	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3718	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3719	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3720	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3721	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3722	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3723	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3724	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3725	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3726	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3727	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3728	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3729	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3730	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3731	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3732	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3733	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3734	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3735	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3736	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3737	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3738	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3739	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3740	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3741	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3742	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3743	[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
3744	[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
3745	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3746	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3747	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3748	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3749	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3750	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3751	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3752	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3753	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3754	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3755	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3756	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3757	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3758	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3759	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3760	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3761	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3762	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3763	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3764	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3765	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3766	[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
3767	[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
3768	[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
3769	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3770	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3771	[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
3772	[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
3773	[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
3774	[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
3775	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3776	[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3777	[GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr,
3778	[GPLL0] = &gpll0.clkr,
3779	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3780	[GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
3781	[GPLL1] = &gpll1.clkr,
3782	[GPLL10] = &gpll10.clkr,
3783	[GPLL11] = &gpll11.clkr,
3784	[GPLL3] = &gpll3.clkr,
3785	[GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
3786	[GPLL4] = &gpll4.clkr,
3787	[GPLL5] = &gpll5.clkr,
3788	[GPLL6] = &gpll6.clkr,
3789	[GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
3790	[GPLL7] = &gpll7.clkr,
3791	[GPLL8] = &gpll8.clkr,
3792	[GPLL8_OUT_EVEN] = &gpll8_out_even.clkr,
3793	[GPLL9] = &gpll9.clkr,
3794	[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
3795	};
3796
3797	static const struct qcom_reset_map gcc_sm6375_resets[] = {
3798	[GCC_MMSS_BCR] = { 0x17000 },
3799	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
3800	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3801	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
3802	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3803	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3804	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3805	[GCC_SDCC2_BCR] = { 0x1e000 },
3806	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
3807	[GCC_PDM_BCR] = { 0x20000 },
3808	[GCC_GPU_BCR] = { 0x36000 },
3809	[GCC_SDCC1_BCR] = { 0x38000 },
3810	[GCC_UFS_PHY_BCR] = { 0x45000 },
3811	[GCC_CAMSS_TFE_BCR] = { 0x52000 },
3812	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 },
3813	[GCC_CAMSS_OPE_BCR] = { 0x55000 },
3814	[GCC_CAMSS_TOP_BCR] = { 0x58000 },
3815	[GCC_VENUS_BCR] = { 0x58078 },
3816	[GCC_VCODEC0_BCR] = { 0x58094 },
3817	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3818	};
3819
3820
3821	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3822	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3823	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3824	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3825	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3826	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3827	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3828	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3829	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3830	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3831	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3832	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3833	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3834	};
3835
3836	static struct gdsc *gcc_sm6375_gdscs[] = {
3837	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3838	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3839	[CAMSS_TOP_GDSC] = &camss_top_gdsc,
3840	[VENUS_GDSC] = &venus_gdsc,
3841	[VCODEC0_GDSC] = &vcodec0_gdsc,
3842	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3843	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3844	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3845	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3846	};
3847
3848	static const struct regmap_config gcc_sm6375_regmap_config = {
3849	.reg_bits = 32,
3850	.reg_stride = 4,
3851	.val_bits = 32,
3852	.max_register = 0xc7000,
3853	.fast_io = true,
3854	};
3855
3856	static const struct qcom_cc_desc gcc_sm6375_desc = {
3857	.config = &gcc_sm6375_regmap_config,
3858	.clks = gcc_sm6375_clocks,
3859	.num_clks = ARRAY_SIZE(gcc_sm6375_clocks),
3860	.resets = gcc_sm6375_resets,
3861	.num_resets = ARRAY_SIZE(gcc_sm6375_resets),
3862	.gdscs = gcc_sm6375_gdscs,
3863	.num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs),
3864	};
3865
3866	static const struct of_device_id gcc_sm6375_match_table[] = {
3867	{ .compatible = "qcom,sm6375-gcc" },
3868	{ }
3869	};
3870	MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table);
3871
3872	static int gcc_sm6375_probe(struct platform_device *pdev)
3873	{
3874	struct regmap *regmap;
3875	int ret;
3876
3877	regmap = qcom_cc_map(pdev, desc: &gcc_sm6375_desc);
3878	if (IS_ERR(ptr: regmap))
3879	return PTR_ERR(ptr: regmap);
3880
3881	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3882	if (ret)
3883	return ret;
3884
3885	/* Keep some clocks always-on */
3886	qcom_branch_set_clk_en(regmap, cbcr: 0x17028); /* GCC_CAMERA_XO_CLK */
3887	qcom_branch_set_clk_en(regmap, cbcr: 0x2b004); /* GCC_CPUSS_GNOC_CLK */
3888	qcom_branch_set_clk_en(regmap, cbcr: 0x1702c); /* GCC_DISP_XO_CLK */
3889
3890	clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config);
3891	clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);
3892	clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config);
3893	clk_zonda_pll_configure(pll: &gpll9, regmap, config: &gpll9_config);
3894
3895	return qcom_cc_really_probe(pdev, desc: &gcc_sm6375_desc, regmap);
3896	}
3897
3898	static struct platform_driver gcc_sm6375_driver = {
3899	.probe = gcc_sm6375_probe,
3900	.driver = {
3901	.name = "gcc-sm6375",
3902	.of_match_table = gcc_sm6375_match_table,
3903	},
3904	};
3905
3906	static int __init gcc_sm6375_init(void)
3907	{
3908	return platform_driver_register(&gcc_sm6375_driver);
3909	}
3910	subsys_initcall(gcc_sm6375_init);
3911
3912	static void __exit gcc_sm6375_exit(void)
3913	{
3914	platform_driver_unregister(&gcc_sm6375_driver);
3915	}
3916	module_exit(gcc_sm6375_exit);
3917
3918	MODULE_DESCRIPTION("QTI GCC SM6375 Driver");
3919	MODULE_LICENSE("GPL");
3920