1	// SPDX-License-Identifier: GPL-2.0
2	// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
3
4	#include <linux/kernel.h>
5	#include <linux/bitops.h>
6	#include <linux/err.h>
7	#include <linux/platform_device.h>
8	#include <linux/module.h>
9	#include <linux/of.h>
10	#include <linux/clk-provider.h>
11	#include <linux/regmap.h>
12	#include <linux/reset-controller.h>
13
14	#include <dt-bindings/clock/qcom,gcc-sm8150.h>
15
16	#include "common.h"
17	#include "clk-alpha-pll.h"
18	#include "clk-branch.h"
19	#include "clk-pll.h"
20	#include "clk-rcg.h"
21	#include "clk-regmap.h"
22	#include "reset.h"
23	#include "gdsc.h"
24
25	enum {
26	P_BI_TCXO,
27	P_AUD_REF_CLK,
28	P_GPLL0_OUT_EVEN,
29	P_GPLL0_OUT_MAIN,
30	P_GPLL7_OUT_MAIN,
31	P_GPLL9_OUT_MAIN,
32	P_SLEEP_CLK,
33	};
34
35	static struct clk_alpha_pll gpll0 = {
36	.offset = 0x0,
37	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
38	.clkr = {
39	.enable_reg = 0x52000,
40	.enable_mask = BIT(0),
41	.hw.init = &(struct clk_init_data){
42	.name = "gpll0",
43	.parent_data = &(const struct clk_parent_data){
44	.fw_name = "bi_tcxo",
45	.name = "bi_tcxo",
46	},
47	.num_parents = 1,
48	.ops = &clk_alpha_pll_fixed_trion_ops,
49	},
50	},
51	};
52
53	static const struct clk_div_table post_div_table_trion_even[] = {
54	{ 0x0, 1 },
55	{ 0x1, 2 },
56	{ 0x3, 4 },
57	{ 0x7, 8 },
58	{ }
59	};
60
61	static struct clk_alpha_pll_postdiv gpll0_out_even = {
62	.offset = 0x0,
63	.post_div_shift = 8,
64	.post_div_table = post_div_table_trion_even,
65	.num_post_div = ARRAY_SIZE(post_div_table_trion_even),
66	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
67	.width = 4,
68	.clkr.hw.init = &(struct clk_init_data){
69	.name = "gpll0_out_even",
70	.parent_hws = (const struct clk_hw*[]){
71	&gpll0.clkr.hw,
72	},
73	.num_parents = 1,
74	.ops = &clk_alpha_pll_postdiv_trion_ops,
75	},
76	};
77
78	static struct clk_alpha_pll gpll7 = {
79	.offset = 0x1a000,
80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
81	.clkr = {
82	.enable_reg = 0x52000,
83	.enable_mask = BIT(7),
84	.hw.init = &(struct clk_init_data){
85	.name = "gpll7",
86	.parent_data = &(const struct clk_parent_data){
87	.fw_name = "bi_tcxo",
88	.name = "bi_tcxo",
89	},
90	.num_parents = 1,
91	.ops = &clk_alpha_pll_fixed_trion_ops,
92	},
93	},
94	};
95
96	static struct clk_alpha_pll gpll9 = {
97	.offset = 0x1c000,
98	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
99	.clkr = {
100	.enable_reg = 0x52000,
101	.enable_mask = BIT(9),
102	.hw.init = &(struct clk_init_data){
103	.name = "gpll9",
104	.parent_data = &(const struct clk_parent_data){
105	.fw_name = "bi_tcxo",
106	.name = "bi_tcxo",
107	},
108	.num_parents = 1,
109	.ops = &clk_alpha_pll_fixed_trion_ops,
110	},
111	},
112	};
113
114	static const struct parent_map gcc_parent_map_0[] = {
115	{ P_BI_TCXO, 0 },
116	{ P_GPLL0_OUT_MAIN, 1 },
117	{ P_GPLL0_OUT_EVEN, 6 },
118	};
119
120	static const struct clk_parent_data gcc_parents_0[] = {
121	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
122	{ .hw = &gpll0.clkr.hw },
123	{ .hw = &gpll0_out_even.clkr.hw },
124	};
125
126	static const struct parent_map gcc_parent_map_1[] = {
127	{ P_BI_TCXO, 0 },
128	{ P_GPLL0_OUT_MAIN, 1 },
129	{ P_SLEEP_CLK, 5 },
130	{ P_GPLL0_OUT_EVEN, 6 },
131	};
132
133	static const struct clk_parent_data gcc_parents_1[] = {
134	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135	{ .hw = &gpll0.clkr.hw },
136	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
137	{ .hw = &gpll0_out_even.clkr.hw },
138	};
139
140	static const struct parent_map gcc_parent_map_2[] = {
141	{ P_BI_TCXO, 0 },
142	{ P_SLEEP_CLK, 5 },
143	};
144
145	static const struct clk_parent_data gcc_parents_2[] = {
146	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
147	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
148	};
149
150	static const struct parent_map gcc_parent_map_3[] = {
151	{ P_BI_TCXO, 0 },
152	{ P_GPLL0_OUT_MAIN, 1 },
153	};
154
155	static const struct clk_parent_data gcc_parents_3[] = {
156	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
157	{ .hw = &gpll0.clkr.hw },
158	};
159
160	static const struct parent_map gcc_parent_map_4[] = {
161	{ P_BI_TCXO, 0 },
162	};
163
164	static const struct clk_parent_data gcc_parents_4[] = {
165	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
166	};
167
168	static const struct parent_map gcc_parent_map_5[] = {
169	{ P_BI_TCXO, 0 },
170	{ P_GPLL0_OUT_MAIN, 1 },
171	{ P_GPLL7_OUT_MAIN, 3 },
172	{ P_GPLL0_OUT_EVEN, 6 },
173	};
174
175	static const struct clk_parent_data gcc_parents_5[] = {
176	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
177	{ .hw = &gpll0.clkr.hw },
178	{ .hw = &gpll7.clkr.hw },
179	{ .hw = &gpll0_out_even.clkr.hw },
180	};
181
182	static const struct parent_map gcc_parent_map_6[] = {
183	{ P_BI_TCXO, 0 },
184	{ P_GPLL0_OUT_MAIN, 1 },
185	{ P_GPLL9_OUT_MAIN, 2 },
186	{ P_GPLL0_OUT_EVEN, 6 },
187	};
188
189	static const struct clk_parent_data gcc_parents_6[] = {
190	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
191	{ .hw = &gpll0.clkr.hw },
192	{ .hw = &gpll9.clkr.hw },
193	{ .hw = &gpll0_out_even.clkr.hw },
194	};
195
196	static const struct parent_map gcc_parent_map_7[] = {
197	{ P_BI_TCXO, 0 },
198	{ P_GPLL0_OUT_MAIN, 1 },
199	{ P_AUD_REF_CLK, 2 },
200	{ P_GPLL0_OUT_EVEN, 6 },
201	};
202
203	static const struct clk_parent_data gcc_parents_7[] = {
204	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
205	{ .hw = &gpll0.clkr.hw },
206	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
207	{ .hw = &gpll0_out_even.clkr.hw },
208	};
209
210	static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
211	F(19200000, P_BI_TCXO, 1, 0, 0),
212	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
213	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
214	{ }
215	};
216
217	static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
218	.cmd_rcgr = 0x48014,
219	.mnd_width = 0,
220	.hid_width = 5,
221	.parent_map = gcc_parent_map_0,
222	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
223	.clkr.hw.init = &(struct clk_init_data){
224	.name = "gcc_cpuss_ahb_clk_src",
225	.parent_data = gcc_parents_0,
226	.num_parents = ARRAY_SIZE(gcc_parents_0),
227	.flags = CLK_SET_RATE_PARENT,
228	.ops = &clk_rcg2_ops,
229	},
230	};
231
232	static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
233	F(19200000, P_BI_TCXO, 1, 0, 0),
234	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
235	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
236	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
237	{ }
238	};
239
240	static struct clk_rcg2 gcc_emac_ptp_clk_src = {
241	.cmd_rcgr = 0x6038,
242	.mnd_width = 0,
243	.hid_width = 5,
244	.parent_map = gcc_parent_map_5,
245	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
246	.clkr.hw.init = &(struct clk_init_data){
247	.name = "gcc_emac_ptp_clk_src",
248	.parent_data = gcc_parents_5,
249	.num_parents = ARRAY_SIZE(gcc_parents_5),
250	.flags = CLK_SET_RATE_PARENT,
251	.ops = &clk_rcg2_ops,
252	},
253	};
254
255	static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
256	F(2500000, P_BI_TCXO, 1, 25, 192),
257	F(5000000, P_BI_TCXO, 1, 25, 96),
258	F(19200000, P_BI_TCXO, 1, 0, 0),
259	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
260	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
261	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
262	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
263	{ }
264	};
265
266	static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
267	.cmd_rcgr = 0x601c,
268	.mnd_width = 8,
269	.hid_width = 5,
270	.parent_map = gcc_parent_map_5,
271	.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
272	.clkr.hw.init = &(struct clk_init_data){
273	.name = "gcc_emac_rgmii_clk_src",
274	.parent_data = gcc_parents_5,
275	.num_parents = ARRAY_SIZE(gcc_parents_5),
276	.flags = CLK_SET_RATE_PARENT,
277	.ops = &clk_rcg2_ops,
278	},
279	};
280
281	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
282	F(19200000, P_BI_TCXO, 1, 0, 0),
283	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
284	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
285	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
286	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
287	{ }
288	};
289
290	static struct clk_rcg2 gcc_gp1_clk_src = {
291	.cmd_rcgr = 0x64004,
292	.mnd_width = 8,
293	.hid_width = 5,
294	.parent_map = gcc_parent_map_1,
295	.freq_tbl = ftbl_gcc_gp1_clk_src,
296	.clkr.hw.init = &(struct clk_init_data){
297	.name = "gcc_gp1_clk_src",
298	.parent_data = gcc_parents_1,
299	.num_parents = ARRAY_SIZE(gcc_parents_1),
300	.flags = CLK_SET_RATE_PARENT,
301	.ops = &clk_rcg2_ops,
302	},
303	};
304
305	static struct clk_rcg2 gcc_gp2_clk_src = {
306	.cmd_rcgr = 0x65004,
307	.mnd_width = 8,
308	.hid_width = 5,
309	.parent_map = gcc_parent_map_1,
310	.freq_tbl = ftbl_gcc_gp1_clk_src,
311	.clkr.hw.init = &(struct clk_init_data){
312	.name = "gcc_gp2_clk_src",
313	.parent_data = gcc_parents_1,
314	.num_parents = ARRAY_SIZE(gcc_parents_1),
315	.flags = CLK_SET_RATE_PARENT,
316	.ops = &clk_rcg2_ops,
317	},
318	};
319
320	static struct clk_rcg2 gcc_gp3_clk_src = {
321	.cmd_rcgr = 0x66004,
322	.mnd_width = 8,
323	.hid_width = 5,
324	.parent_map = gcc_parent_map_1,
325	.freq_tbl = ftbl_gcc_gp1_clk_src,
326	.clkr.hw.init = &(struct clk_init_data){
327	.name = "gcc_gp3_clk_src",
328	.parent_data = gcc_parents_1,
329	.num_parents = ARRAY_SIZE(gcc_parents_1),
330	.flags = CLK_SET_RATE_PARENT,
331	.ops = &clk_rcg2_ops,
332	},
333	};
334
335	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
336	F(9600000, P_BI_TCXO, 2, 0, 0),
337	F(19200000, P_BI_TCXO, 1, 0, 0),
338	{ }
339	};
340
341	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
342	.cmd_rcgr = 0x6b02c,
343	.mnd_width = 16,
344	.hid_width = 5,
345	.parent_map = gcc_parent_map_2,
346	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
347	.clkr.hw.init = &(struct clk_init_data){
348	.name = "gcc_pcie_0_aux_clk_src",
349	.parent_data = gcc_parents_2,
350	.num_parents = ARRAY_SIZE(gcc_parents_2),
351	.flags = CLK_SET_RATE_PARENT,
352	.ops = &clk_rcg2_ops,
353	},
354	};
355
356	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
357	.cmd_rcgr = 0x8d02c,
358	.mnd_width = 16,
359	.hid_width = 5,
360	.parent_map = gcc_parent_map_2,
361	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
362	.clkr.hw.init = &(struct clk_init_data){
363	.name = "gcc_pcie_1_aux_clk_src",
364	.parent_data = gcc_parents_2,
365	.num_parents = ARRAY_SIZE(gcc_parents_2),
366	.flags = CLK_SET_RATE_PARENT,
367	.ops = &clk_rcg2_ops,
368	},
369	};
370
371	static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
372	F(19200000, P_BI_TCXO, 1, 0, 0),
373	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
374	{ }
375	};
376
377	static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
378	.cmd_rcgr = 0x6f014,
379	.mnd_width = 0,
380	.hid_width = 5,
381	.parent_map = gcc_parent_map_0,
382	.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
383	.clkr.hw.init = &(struct clk_init_data){
384	.name = "gcc_pcie_phy_refgen_clk_src",
385	.parent_data = gcc_parents_0,
386	.num_parents = ARRAY_SIZE(gcc_parents_0),
387	.flags = CLK_SET_RATE_PARENT,
388	.ops = &clk_rcg2_ops,
389	},
390	};
391
392	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
393	F(9600000, P_BI_TCXO, 2, 0, 0),
394	F(19200000, P_BI_TCXO, 1, 0, 0),
395	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
396	{ }
397	};
398
399	static struct clk_rcg2 gcc_pdm2_clk_src = {
400	.cmd_rcgr = 0x33010,
401	.mnd_width = 0,
402	.hid_width = 5,
403	.parent_map = gcc_parent_map_0,
404	.freq_tbl = ftbl_gcc_pdm2_clk_src,
405	.clkr.hw.init = &(struct clk_init_data){
406	.name = "gcc_pdm2_clk_src",
407	.parent_data = gcc_parents_0,
408	.num_parents = ARRAY_SIZE(gcc_parents_0),
409	.flags = CLK_SET_RATE_PARENT,
410	.ops = &clk_rcg2_ops,
411	},
412	};
413
414	static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
415	F(19200000, P_BI_TCXO, 1, 0, 0),
416	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
417	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
418	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
419	{ }
420	};
421
422	static struct clk_rcg2 gcc_qspi_core_clk_src = {
423	.cmd_rcgr = 0x4b008,
424	.mnd_width = 0,
425	.hid_width = 5,
426	.parent_map = gcc_parent_map_0,
427	.freq_tbl = ftbl_gcc_qspi_core_clk_src,
428	.clkr.hw.init = &(struct clk_init_data){
429	.name = "gcc_qspi_core_clk_src",
430	.parent_data = gcc_parents_0,
431	.num_parents = ARRAY_SIZE(gcc_parents_0),
432	.flags = CLK_SET_RATE_PARENT,
433	.ops = &clk_rcg2_ops,
434	},
435	};
436
437	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
438	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
439	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
440	F(19200000, P_BI_TCXO, 1, 0, 0),
441	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
442	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
443	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
444	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
445	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
446	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
447	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
448	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
449	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
450	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
451	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
452	F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
453	{ }
454	};
455
456	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
457	.name = "gcc_qupv3_wrap0_s0_clk_src",
458	.parent_data = gcc_parents_0,
459	.num_parents = ARRAY_SIZE(gcc_parents_0),
460	.flags = CLK_SET_RATE_PARENT,
461	.ops = &clk_rcg2_ops,
462	};
463
464	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
465	.cmd_rcgr = 0x17148,
466	.mnd_width = 16,
467	.hid_width = 5,
468	.parent_map = gcc_parent_map_0,
469	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
470	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
471	};
472
473	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
474	.name = "gcc_qupv3_wrap0_s1_clk_src",
475	.parent_data = gcc_parents_0,
476	.num_parents = ARRAY_SIZE(gcc_parents_0),
477	.flags = CLK_SET_RATE_PARENT,
478	.ops = &clk_rcg2_ops,
479	};
480
481	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
482	.cmd_rcgr = 0x17278,
483	.mnd_width = 16,
484	.hid_width = 5,
485	.parent_map = gcc_parent_map_0,
486	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
487	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
488	};
489
490	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
491	.name = "gcc_qupv3_wrap0_s2_clk_src",
492	.parent_data = gcc_parents_0,
493	.num_parents = ARRAY_SIZE(gcc_parents_0),
494	.flags = CLK_SET_RATE_PARENT,
495	.ops = &clk_rcg2_ops,
496	};
497
498	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
499	.cmd_rcgr = 0x173a8,
500	.mnd_width = 16,
501	.hid_width = 5,
502	.parent_map = gcc_parent_map_0,
503	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
504	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
505	};
506
507	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
508	.name = "gcc_qupv3_wrap0_s3_clk_src",
509	.parent_data = gcc_parents_0,
510	.num_parents = ARRAY_SIZE(gcc_parents_0),
511	.flags = CLK_SET_RATE_PARENT,
512	.ops = &clk_rcg2_ops,
513	};
514
515	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
516	.cmd_rcgr = 0x174d8,
517	.mnd_width = 16,
518	.hid_width = 5,
519	.parent_map = gcc_parent_map_0,
520	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
521	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
522	};
523
524	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
525	.name = "gcc_qupv3_wrap0_s4_clk_src",
526	.parent_data = gcc_parents_0,
527	.num_parents = ARRAY_SIZE(gcc_parents_0),
528	.flags = CLK_SET_RATE_PARENT,
529	.ops = &clk_rcg2_ops,
530	};
531
532	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
533	.cmd_rcgr = 0x17608,
534	.mnd_width = 16,
535	.hid_width = 5,
536	.parent_map = gcc_parent_map_0,
537	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
538	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
539	};
540
541	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
542	.name = "gcc_qupv3_wrap0_s5_clk_src",
543	.parent_data = gcc_parents_0,
544	.num_parents = ARRAY_SIZE(gcc_parents_0),
545	.flags = CLK_SET_RATE_PARENT,
546	.ops = &clk_rcg2_ops,
547	};
548
549	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
550	.cmd_rcgr = 0x17738,
551	.mnd_width = 16,
552	.hid_width = 5,
553	.parent_map = gcc_parent_map_0,
554	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
555	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
556	};
557
558	static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
559	.name = "gcc_qupv3_wrap0_s6_clk_src",
560	.parent_data = gcc_parents_0,
561	.num_parents = ARRAY_SIZE(gcc_parents_0),
562	.flags = CLK_SET_RATE_PARENT,
563	.ops = &clk_rcg2_ops,
564	};
565
566	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
567	.cmd_rcgr = 0x17868,
568	.mnd_width = 16,
569	.hid_width = 5,
570	.parent_map = gcc_parent_map_0,
571	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
572	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
573	};
574
575	static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
576	.name = "gcc_qupv3_wrap0_s7_clk_src",
577	.parent_data = gcc_parents_0,
578	.num_parents = ARRAY_SIZE(gcc_parents_0),
579	.flags = CLK_SET_RATE_PARENT,
580	.ops = &clk_rcg2_ops,
581	};
582
583	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
584	.cmd_rcgr = 0x17998,
585	.mnd_width = 16,
586	.hid_width = 5,
587	.parent_map = gcc_parent_map_0,
588	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
589	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
590	};
591
592	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
593	.name = "gcc_qupv3_wrap1_s0_clk_src",
594	.parent_data = gcc_parents_0,
595	.num_parents = ARRAY_SIZE(gcc_parents_0),
596	.flags = CLK_SET_RATE_PARENT,
597	.ops = &clk_rcg2_ops,
598	};
599
600	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
601	.cmd_rcgr = 0x18148,
602	.mnd_width = 16,
603	.hid_width = 5,
604	.parent_map = gcc_parent_map_0,
605	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
606	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
607	};
608
609	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
610	.name = "gcc_qupv3_wrap1_s1_clk_src",
611	.parent_data = gcc_parents_0,
612	.num_parents = ARRAY_SIZE(gcc_parents_0),
613	.flags = CLK_SET_RATE_PARENT,
614	.ops = &clk_rcg2_ops,
615	};
616
617	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
618	.cmd_rcgr = 0x18278,
619	.mnd_width = 16,
620	.hid_width = 5,
621	.parent_map = gcc_parent_map_0,
622	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
623	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
624	};
625
626	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
627	.name = "gcc_qupv3_wrap1_s2_clk_src",
628	.parent_data = gcc_parents_0,
629	.num_parents = ARRAY_SIZE(gcc_parents_0),
630	.flags = CLK_SET_RATE_PARENT,
631	.ops = &clk_rcg2_ops,
632	};
633
634	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
635	.cmd_rcgr = 0x183a8,
636	.mnd_width = 16,
637	.hid_width = 5,
638	.parent_map = gcc_parent_map_0,
639	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
640	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
641	};
642
643	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
644	.name = "gcc_qupv3_wrap1_s3_clk_src",
645	.parent_data = gcc_parents_0,
646	.num_parents = ARRAY_SIZE(gcc_parents_0),
647	.flags = CLK_SET_RATE_PARENT,
648	.ops = &clk_rcg2_ops,
649	};
650
651	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
652	.cmd_rcgr = 0x184d8,
653	.mnd_width = 16,
654	.hid_width = 5,
655	.parent_map = gcc_parent_map_0,
656	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
657	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
658	};
659
660	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
661	.name = "gcc_qupv3_wrap1_s4_clk_src",
662	.parent_data = gcc_parents_0,
663	.num_parents = ARRAY_SIZE(gcc_parents_0),
664	.flags = CLK_SET_RATE_PARENT,
665	.ops = &clk_rcg2_ops,
666	};
667
668	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
669	.cmd_rcgr = 0x18608,
670	.mnd_width = 16,
671	.hid_width = 5,
672	.parent_map = gcc_parent_map_0,
673	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
674	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
675	};
676
677	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
678	.name = "gcc_qupv3_wrap1_s5_clk_src",
679	.parent_data = gcc_parents_0,
680	.num_parents = ARRAY_SIZE(gcc_parents_0),
681	.flags = CLK_SET_RATE_PARENT,
682	.ops = &clk_rcg2_ops,
683	};
684
685	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
686	.cmd_rcgr = 0x18738,
687	.mnd_width = 16,
688	.hid_width = 5,
689	.parent_map = gcc_parent_map_0,
690	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
691	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
692	};
693
694	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
695	.name = "gcc_qupv3_wrap2_s0_clk_src",
696	.parent_data = gcc_parents_0,
697	.num_parents = ARRAY_SIZE(gcc_parents_0),
698	.flags = CLK_SET_RATE_PARENT,
699	.ops = &clk_rcg2_ops,
700	};
701
702	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
703	.cmd_rcgr = 0x1e148,
704	.mnd_width = 16,
705	.hid_width = 5,
706	.parent_map = gcc_parent_map_0,
707	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
708	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
709	};
710
711	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
712	.name = "gcc_qupv3_wrap2_s1_clk_src",
713	.parent_data = gcc_parents_0,
714	.num_parents = ARRAY_SIZE(gcc_parents_0),
715	.flags = CLK_SET_RATE_PARENT,
716	.ops = &clk_rcg2_ops,
717	};
718
719	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
720	.cmd_rcgr = 0x1e278,
721	.mnd_width = 16,
722	.hid_width = 5,
723	.parent_map = gcc_parent_map_0,
724	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
725	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
726	};
727
728	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
729	.name = "gcc_qupv3_wrap2_s2_clk_src",
730	.parent_data = gcc_parents_0,
731	.num_parents = ARRAY_SIZE(gcc_parents_0),
732	.flags = CLK_SET_RATE_PARENT,
733	.ops = &clk_rcg2_ops,
734	};
735
736	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
737	.cmd_rcgr = 0x1e3a8,
738	.mnd_width = 16,
739	.hid_width = 5,
740	.parent_map = gcc_parent_map_0,
741	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
742	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
743	};
744
745	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
746	.name = "gcc_qupv3_wrap2_s3_clk_src",
747	.parent_data = gcc_parents_0,
748	.num_parents = ARRAY_SIZE(gcc_parents_0),
749	.flags = CLK_SET_RATE_PARENT,
750	.ops = &clk_rcg2_ops,
751	};
752
753	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
754	.cmd_rcgr = 0x1e4d8,
755	.mnd_width = 16,
756	.hid_width = 5,
757	.parent_map = gcc_parent_map_0,
758	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
759	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
760	};
761
762	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
763	.name = "gcc_qupv3_wrap2_s4_clk_src",
764	.parent_data = gcc_parents_0,
765	.num_parents = ARRAY_SIZE(gcc_parents_0),
766	.flags = CLK_SET_RATE_PARENT,
767	.ops = &clk_rcg2_ops,
768	};
769
770	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
771	.cmd_rcgr = 0x1e608,
772	.mnd_width = 16,
773	.hid_width = 5,
774	.parent_map = gcc_parent_map_0,
775	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
776	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
777	};
778
779	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
780	.name = "gcc_qupv3_wrap2_s5_clk_src",
781	.parent_data = gcc_parents_0,
782	.num_parents = ARRAY_SIZE(gcc_parents_0),
783	.flags = CLK_SET_RATE_PARENT,
784	.ops = &clk_rcg2_ops,
785	};
786
787	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
788	.cmd_rcgr = 0x1e738,
789	.mnd_width = 16,
790	.hid_width = 5,
791	.parent_map = gcc_parent_map_0,
792	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
793	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
794	};
795
796	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
797	F(400000, P_BI_TCXO, 12, 1, 4),
798	F(9600000, P_BI_TCXO, 2, 0, 0),
799	F(19200000, P_BI_TCXO, 1, 0, 0),
800	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
801	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
802	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
803	F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
804	{ }
805	};
806
807	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
808	.cmd_rcgr = 0x1400c,
809	.mnd_width = 8,
810	.hid_width = 5,
811	.parent_map = gcc_parent_map_6,
812	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
813	.clkr.hw.init = &(struct clk_init_data){
814	.name = "gcc_sdcc2_apps_clk_src",
815	.parent_data = gcc_parents_6,
816	.num_parents = ARRAY_SIZE(gcc_parents_6),
817	.flags = CLK_OPS_PARENT_ENABLE,
818	.ops = &clk_rcg2_floor_ops,
819	},
820	};
821
822	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
823	F(400000, P_BI_TCXO, 12, 1, 4),
824	F(9600000, P_BI_TCXO, 2, 0, 0),
825	F(19200000, P_BI_TCXO, 1, 0, 0),
826	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
827	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
828	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
829	{ }
830	};
831
832	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
833	.cmd_rcgr = 0x1600c,
834	.mnd_width = 8,
835	.hid_width = 5,
836	.parent_map = gcc_parent_map_3,
837	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
838	.clkr.hw.init = &(struct clk_init_data){
839	.name = "gcc_sdcc4_apps_clk_src",
840	.parent_data = gcc_parents_3,
841	.num_parents = ARRAY_SIZE(gcc_parents_3),
842	.flags = CLK_SET_RATE_PARENT,
843	.ops = &clk_rcg2_floor_ops,
844	},
845	};
846
847	static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
848	F(105495, P_BI_TCXO, 2, 1, 91),
849	{ }
850	};
851
852	static struct clk_rcg2 gcc_tsif_ref_clk_src = {
853	.cmd_rcgr = 0x36010,
854	.mnd_width = 8,
855	.hid_width = 5,
856	.parent_map = gcc_parent_map_7,
857	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
858	.clkr.hw.init = &(struct clk_init_data){
859	.name = "gcc_tsif_ref_clk_src",
860	.parent_data = gcc_parents_7,
861	.num_parents = ARRAY_SIZE(gcc_parents_7),
862	.flags = CLK_SET_RATE_PARENT,
863	.ops = &clk_rcg2_ops,
864	},
865	};
866
867	static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
868	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
869	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
870	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
871	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
872	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
873	{ }
874	};
875
876	static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
877	.cmd_rcgr = 0x75020,
878	.mnd_width = 8,
879	.hid_width = 5,
880	.parent_map = gcc_parent_map_0,
881	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
882	.clkr.hw.init = &(struct clk_init_data){
883	.name = "gcc_ufs_card_axi_clk_src",
884	.parent_data = gcc_parents_0,
885	.num_parents = ARRAY_SIZE(gcc_parents_0),
886	.flags = CLK_SET_RATE_PARENT,
887	.ops = &clk_rcg2_ops,
888	},
889	};
890
891	static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
892	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
893	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
894	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
895	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
896	{ }
897	};
898
899	static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
900	.cmd_rcgr = 0x75060,
901	.mnd_width = 0,
902	.hid_width = 5,
903	.parent_map = gcc_parent_map_0,
904	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
905	.clkr.hw.init = &(struct clk_init_data){
906	.name = "gcc_ufs_card_ice_core_clk_src",
907	.parent_data = gcc_parents_0,
908	.num_parents = ARRAY_SIZE(gcc_parents_0),
909	.flags = CLK_SET_RATE_PARENT,
910	.ops = &clk_rcg2_ops,
911	},
912	};
913
914	static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
915	F(19200000, P_BI_TCXO, 1, 0, 0),
916	{ }
917	};
918
919	static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
920	.cmd_rcgr = 0x75094,
921	.mnd_width = 0,
922	.hid_width = 5,
923	.parent_map = gcc_parent_map_4,
924	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
925	.clkr.hw.init = &(struct clk_init_data){
926	.name = "gcc_ufs_card_phy_aux_clk_src",
927	.parent_data = gcc_parents_4,
928	.num_parents = ARRAY_SIZE(gcc_parents_4),
929	.flags = CLK_SET_RATE_PARENT,
930	.ops = &clk_rcg2_ops,
931	},
932	};
933
934	static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
935	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
936	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
937	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
938	{ }
939	};
940
941	static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
942	.cmd_rcgr = 0x75078,
943	.mnd_width = 0,
944	.hid_width = 5,
945	.parent_map = gcc_parent_map_0,
946	.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
947	.clkr.hw.init = &(struct clk_init_data){
948	.name = "gcc_ufs_card_unipro_core_clk_src",
949	.parent_data = gcc_parents_0,
950	.num_parents = ARRAY_SIZE(gcc_parents_0),
951	.flags = CLK_SET_RATE_PARENT,
952	.ops = &clk_rcg2_ops,
953	},
954	};
955
956	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
957	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
958	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
959	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
960	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
961	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
962	{ }
963	};
964
965	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
966	.cmd_rcgr = 0x77020,
967	.mnd_width = 8,
968	.hid_width = 5,
969	.parent_map = gcc_parent_map_0,
970	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
971	.clkr.hw.init = &(struct clk_init_data){
972	.name = "gcc_ufs_phy_axi_clk_src",
973	.parent_data = gcc_parents_0,
974	.num_parents = ARRAY_SIZE(gcc_parents_0),
975	.flags = CLK_SET_RATE_PARENT,
976	.ops = &clk_rcg2_ops,
977	},
978	};
979
980	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
981	.cmd_rcgr = 0x77060,
982	.mnd_width = 0,
983	.hid_width = 5,
984	.parent_map = gcc_parent_map_0,
985	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
986	.clkr.hw.init = &(struct clk_init_data){
987	.name = "gcc_ufs_phy_ice_core_clk_src",
988	.parent_data = gcc_parents_0,
989	.num_parents = ARRAY_SIZE(gcc_parents_0),
990	.flags = CLK_SET_RATE_PARENT,
991	.ops = &clk_rcg2_ops,
992	},
993	};
994
995	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
996	.cmd_rcgr = 0x77094,
997	.mnd_width = 0,
998	.hid_width = 5,
999	.parent_map = gcc_parent_map_4,
1000	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1001	.clkr.hw.init = &(struct clk_init_data){
1002	.name = "gcc_ufs_phy_phy_aux_clk_src",
1003	.parent_data = gcc_parents_4,
1004	.num_parents = ARRAY_SIZE(gcc_parents_4),
1005	.flags = CLK_SET_RATE_PARENT,
1006	.ops = &clk_rcg2_ops,
1007	},
1008	};
1009
1010	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1011	.cmd_rcgr = 0x77078,
1012	.mnd_width = 0,
1013	.hid_width = 5,
1014	.parent_map = gcc_parent_map_0,
1015	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1016	.clkr.hw.init = &(struct clk_init_data){
1017	.name = "gcc_ufs_phy_unipro_core_clk_src",
1018	.parent_data = gcc_parents_0,
1019	.num_parents = ARRAY_SIZE(gcc_parents_0),
1020	.flags = CLK_SET_RATE_PARENT,
1021	.ops = &clk_rcg2_ops,
1022	},
1023	};
1024
1025	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1026	F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1027	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1028	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1029	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1030	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1031	{ }
1032	};
1033
1034	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1035	.cmd_rcgr = 0xf01c,
1036	.mnd_width = 8,
1037	.hid_width = 5,
1038	.parent_map = gcc_parent_map_0,
1039	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1040	.clkr.hw.init = &(struct clk_init_data){
1041	.name = "gcc_usb30_prim_master_clk_src",
1042	.parent_data = gcc_parents_0,
1043	.num_parents = ARRAY_SIZE(gcc_parents_0),
1044	.flags = CLK_SET_RATE_PARENT,
1045	.ops = &clk_rcg2_ops,
1046	},
1047	};
1048
1049	static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1050	F(19200000, P_BI_TCXO, 1, 0, 0),
1051	F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1052	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1053	{ }
1054	};
1055
1056	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1057	.cmd_rcgr = 0xf034,
1058	.mnd_width = 0,
1059	.hid_width = 5,
1060	.parent_map = gcc_parent_map_0,
1061	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1062	.clkr.hw.init = &(struct clk_init_data){
1063	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1064	.parent_data = gcc_parents_0,
1065	.num_parents = ARRAY_SIZE(gcc_parents_0),
1066	.flags = CLK_SET_RATE_PARENT,
1067	.ops = &clk_rcg2_ops,
1068	},
1069	};
1070
1071	static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1072	.cmd_rcgr = 0x1001c,
1073	.mnd_width = 8,
1074	.hid_width = 5,
1075	.parent_map = gcc_parent_map_0,
1076	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1077	.clkr.hw.init = &(struct clk_init_data){
1078	.name = "gcc_usb30_sec_master_clk_src",
1079	.parent_data = gcc_parents_0,
1080	.num_parents = ARRAY_SIZE(gcc_parents_0),
1081	.flags = CLK_SET_RATE_PARENT,
1082	.ops = &clk_rcg2_ops,
1083	},
1084	};
1085
1086	static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1087	.cmd_rcgr = 0x10034,
1088	.mnd_width = 0,
1089	.hid_width = 5,
1090	.parent_map = gcc_parent_map_0,
1091	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1092	.clkr.hw.init = &(struct clk_init_data){
1093	.name = "gcc_usb30_sec_mock_utmi_clk_src",
1094	.parent_data = gcc_parents_0,
1095	.num_parents = ARRAY_SIZE(gcc_parents_0),
1096	.flags = CLK_SET_RATE_PARENT,
1097	.ops = &clk_rcg2_ops,
1098	},
1099	};
1100
1101	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1102	.cmd_rcgr = 0xf060,
1103	.mnd_width = 0,
1104	.hid_width = 5,
1105	.parent_map = gcc_parent_map_2,
1106	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1107	.clkr.hw.init = &(struct clk_init_data){
1108	.name = "gcc_usb3_prim_phy_aux_clk_src",
1109	.parent_data = gcc_parents_2,
1110	.num_parents = ARRAY_SIZE(gcc_parents_2),
1111	.flags = CLK_SET_RATE_PARENT,
1112	.ops = &clk_rcg2_ops,
1113	},
1114	};
1115
1116	static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1117	.cmd_rcgr = 0x10060,
1118	.mnd_width = 0,
1119	.hid_width = 5,
1120	.parent_map = gcc_parent_map_2,
1121	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1122	.clkr.hw.init = &(struct clk_init_data){
1123	.name = "gcc_usb3_sec_phy_aux_clk_src",
1124	.parent_data = gcc_parents_2,
1125	.num_parents = ARRAY_SIZE(gcc_parents_2),
1126	.flags = CLK_SET_RATE_PARENT,
1127	.ops = &clk_rcg2_ops,
1128	},
1129	};
1130
1131	static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1132	.halt_reg = 0x90018,
1133	.halt_check = BRANCH_HALT,
1134	.clkr = {
1135	.enable_reg = 0x90018,
1136	.enable_mask = BIT(0),
1137	.hw.init = &(struct clk_init_data){
1138	.name = "gcc_aggre_noc_pcie_tbu_clk",
1139	.ops = &clk_branch2_ops,
1140	},
1141	},
1142	};
1143
1144	static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1145	.halt_reg = 0x750c0,
1146	.halt_check = BRANCH_HALT,
1147	.hwcg_reg = 0x750c0,
1148	.hwcg_bit = 1,
1149	.clkr = {
1150	.enable_reg = 0x750c0,
1151	.enable_mask = BIT(0),
1152	.hw.init = &(struct clk_init_data){
1153	.name = "gcc_aggre_ufs_card_axi_clk",
1154	.parent_hws = (const struct clk_hw *[]){
1155	&gcc_ufs_card_axi_clk_src.clkr.hw },
1156	.num_parents = 1,
1157	.flags = CLK_SET_RATE_PARENT,
1158	.ops = &clk_branch2_ops,
1159	},
1160	},
1161	};
1162
1163	static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1164	.halt_reg = 0x750c0,
1165	.halt_check = BRANCH_HALT,
1166	.hwcg_reg = 0x750c0,
1167	.hwcg_bit = 1,
1168	.clkr = {
1169	.enable_reg = 0x750c0,
1170	.enable_mask = BIT(1),
1171	.hw.init = &(struct clk_init_data){
1172	.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1173	.parent_hws = (const struct clk_hw *[]){
1174	&gcc_aggre_ufs_card_axi_clk.clkr.hw },
1175	.num_parents = 1,
1176	.flags = CLK_SET_RATE_PARENT,
1177	.ops = &clk_branch_simple_ops,
1178	},
1179	},
1180	};
1181
1182	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1183	.halt_reg = 0x770c0,
1184	.halt_check = BRANCH_HALT,
1185	.hwcg_reg = 0x770c0,
1186	.hwcg_bit = 1,
1187	.clkr = {
1188	.enable_reg = 0x770c0,
1189	.enable_mask = BIT(0),
1190	.hw.init = &(struct clk_init_data){
1191	.name = "gcc_aggre_ufs_phy_axi_clk",
1192	.parent_hws = (const struct clk_hw *[]){
1193	&gcc_ufs_phy_axi_clk_src.clkr.hw },
1194	.num_parents = 1,
1195	.flags = CLK_SET_RATE_PARENT,
1196	.ops = &clk_branch2_ops,
1197	},
1198	},
1199	};
1200
1201	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1202	.halt_reg = 0x770c0,
1203	.halt_check = BRANCH_HALT,
1204	.hwcg_reg = 0x770c0,
1205	.hwcg_bit = 1,
1206	.clkr = {
1207	.enable_reg = 0x770c0,
1208	.enable_mask = BIT(1),
1209	.hw.init = &(struct clk_init_data){
1210	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1211	.parent_hws = (const struct clk_hw *[]){
1212	&gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1213	.num_parents = 1,
1214	.flags = CLK_SET_RATE_PARENT,
1215	.ops = &clk_branch_simple_ops,
1216	},
1217	},
1218	};
1219
1220	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1221	.halt_reg = 0xf07c,
1222	.halt_check = BRANCH_HALT,
1223	.clkr = {
1224	.enable_reg = 0xf07c,
1225	.enable_mask = BIT(0),
1226	.hw.init = &(struct clk_init_data){
1227	.name = "gcc_aggre_usb3_prim_axi_clk",
1228	.parent_hws = (const struct clk_hw *[]){
1229	&gcc_usb30_prim_master_clk_src.clkr.hw },
1230	.num_parents = 1,
1231	.flags = CLK_SET_RATE_PARENT,
1232	.ops = &clk_branch2_ops,
1233	},
1234	},
1235	};
1236
1237	static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1238	.halt_reg = 0x1007c,
1239	.halt_check = BRANCH_HALT,
1240	.clkr = {
1241	.enable_reg = 0x1007c,
1242	.enable_mask = BIT(0),
1243	.hw.init = &(struct clk_init_data){
1244	.name = "gcc_aggre_usb3_sec_axi_clk",
1245	.parent_hws = (const struct clk_hw *[]){
1246	&gcc_usb30_sec_master_clk_src.clkr.hw },
1247	.num_parents = 1,
1248	.flags = CLK_SET_RATE_PARENT,
1249	.ops = &clk_branch2_ops,
1250	},
1251	},
1252	};
1253
1254	static struct clk_branch gcc_boot_rom_ahb_clk = {
1255	.halt_reg = 0x38004,
1256	.halt_check = BRANCH_HALT_VOTED,
1257	.hwcg_reg = 0x38004,
1258	.hwcg_bit = 1,
1259	.clkr = {
1260	.enable_reg = 0x52004,
1261	.enable_mask = BIT(10),
1262	.hw.init = &(struct clk_init_data){
1263	.name = "gcc_boot_rom_ahb_clk",
1264	.ops = &clk_branch2_ops,
1265	},
1266	},
1267	};
1268
1269	/*
1270	* Clock ON depends on external parent 'config noc', so cant poll
1271	* delay and also mark as crtitical for camss boot
1272	*/
1273	static struct clk_branch gcc_camera_ahb_clk = {
1274	.halt_reg = 0xb008,
1275	.halt_check = BRANCH_HALT_DELAY,
1276	.hwcg_reg = 0xb008,
1277	.hwcg_bit = 1,
1278	.clkr = {
1279	.enable_reg = 0xb008,
1280	.enable_mask = BIT(0),
1281	.hw.init = &(struct clk_init_data){
1282	.name = "gcc_camera_ahb_clk",
1283	.flags = CLK_IS_CRITICAL,
1284	.ops = &clk_branch2_ops,
1285	},
1286	},
1287	};
1288
1289	static struct clk_branch gcc_camera_hf_axi_clk = {
1290	.halt_reg = 0xb030,
1291	.halt_check = BRANCH_HALT,
1292	.clkr = {
1293	.enable_reg = 0xb030,
1294	.enable_mask = BIT(0),
1295	.hw.init = &(struct clk_init_data){
1296	.name = "gcc_camera_hf_axi_clk",
1297	.ops = &clk_branch2_ops,
1298	},
1299	},
1300	};
1301
1302	static struct clk_branch gcc_camera_sf_axi_clk = {
1303	.halt_reg = 0xb034,
1304	.halt_check = BRANCH_HALT,
1305	.clkr = {
1306	.enable_reg = 0xb034,
1307	.enable_mask = BIT(0),
1308	.hw.init = &(struct clk_init_data){
1309	.name = "gcc_camera_sf_axi_clk",
1310	.ops = &clk_branch2_ops,
1311	},
1312	},
1313	};
1314
1315	/* XO critical input to camss, so no need to poll */
1316	static struct clk_branch gcc_camera_xo_clk = {
1317	.halt_reg = 0xb044,
1318	.halt_check = BRANCH_HALT_DELAY,
1319	.clkr = {
1320	.enable_reg = 0xb044,
1321	.enable_mask = BIT(0),
1322	.hw.init = &(struct clk_init_data){
1323	.name = "gcc_camera_xo_clk",
1324	.flags = CLK_IS_CRITICAL,
1325	.ops = &clk_branch2_ops,
1326	},
1327	},
1328	};
1329
1330	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1331	.halt_reg = 0xf078,
1332	.halt_check = BRANCH_HALT,
1333	.clkr = {
1334	.enable_reg = 0xf078,
1335	.enable_mask = BIT(0),
1336	.hw.init = &(struct clk_init_data){
1337	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1338	.parent_hws = (const struct clk_hw *[]){
1339	&gcc_usb30_prim_master_clk_src.clkr.hw },
1340	.num_parents = 1,
1341	.flags = CLK_SET_RATE_PARENT,
1342	.ops = &clk_branch2_ops,
1343	},
1344	},
1345	};
1346
1347	static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1348	.halt_reg = 0x10078,
1349	.halt_check = BRANCH_HALT,
1350	.clkr = {
1351	.enable_reg = 0x10078,
1352	.enable_mask = BIT(0),
1353	.hw.init = &(struct clk_init_data){
1354	.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1355	.parent_hws = (const struct clk_hw *[]){
1356	&gcc_usb30_sec_master_clk_src.clkr.hw },
1357	.num_parents = 1,
1358	.flags = CLK_SET_RATE_PARENT,
1359	.ops = &clk_branch2_ops,
1360	},
1361	},
1362	};
1363
1364	static struct clk_branch gcc_cpuss_ahb_clk = {
1365	.halt_reg = 0x48000,
1366	.halt_check = BRANCH_HALT_VOTED,
1367	.clkr = {
1368	.enable_reg = 0x52004,
1369	.enable_mask = BIT(21),
1370	.hw.init = &(struct clk_init_data){
1371	.name = "gcc_cpuss_ahb_clk",
1372	.parent_hws = (const struct clk_hw *[]){
1373	&gcc_cpuss_ahb_clk_src.clkr.hw },
1374	.num_parents = 1,
1375	/* required for cpuss */
1376	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1377	.ops = &clk_branch2_ops,
1378	},
1379	},
1380	};
1381
1382	static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1383	.halt_reg = 0x48190,
1384	.halt_check = BRANCH_HALT,
1385	.clkr = {
1386	.enable_reg = 0x48190,
1387	.enable_mask = BIT(0),
1388	.hw.init = &(struct clk_init_data){
1389	.name = "gcc_cpuss_dvm_bus_clk",
1390	/* required for cpuss */
1391	.flags = CLK_IS_CRITICAL,
1392	.ops = &clk_branch2_ops,
1393	},
1394	},
1395	};
1396
1397	static struct clk_branch gcc_cpuss_gnoc_clk = {
1398	.halt_reg = 0x48004,
1399	.halt_check = BRANCH_HALT_VOTED,
1400	.hwcg_reg = 0x48004,
1401	.hwcg_bit = 1,
1402	.clkr = {
1403	.enable_reg = 0x52004,
1404	.enable_mask = BIT(22),
1405	.hw.init = &(struct clk_init_data){
1406	.name = "gcc_cpuss_gnoc_clk",
1407	/* required for cpuss */
1408	.flags = CLK_IS_CRITICAL,
1409	.ops = &clk_branch2_ops,
1410	},
1411	},
1412	};
1413
1414	static struct clk_branch gcc_cpuss_rbcpr_clk = {
1415	.halt_reg = 0x48008,
1416	.halt_check = BRANCH_HALT,
1417	.clkr = {
1418	.enable_reg = 0x48008,
1419	.enable_mask = BIT(0),
1420	.hw.init = &(struct clk_init_data){
1421	.name = "gcc_cpuss_rbcpr_clk",
1422	.ops = &clk_branch2_ops,
1423	},
1424	},
1425	};
1426
1427	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1428	.halt_reg = 0x71154,
1429	.halt_check = BRANCH_VOTED,
1430	.clkr = {
1431	.enable_reg = 0x71154,
1432	.enable_mask = BIT(0),
1433	.hw.init = &(struct clk_init_data){
1434	.name = "gcc_ddrss_gpu_axi_clk",
1435	.ops = &clk_branch2_ops,
1436	},
1437	},
1438	};
1439
1440	/*
1441	* Clock ON depends on external parent 'config noc', so cant poll
1442	* delay and also mark as crtitical for disp boot
1443	*/
1444	static struct clk_branch gcc_disp_ahb_clk = {
1445	.halt_reg = 0xb00c,
1446	.halt_check = BRANCH_HALT_DELAY,
1447	.hwcg_reg = 0xb00c,
1448	.hwcg_bit = 1,
1449	.clkr = {
1450	.enable_reg = 0xb00c,
1451	.enable_mask = BIT(0),
1452	.hw.init = &(struct clk_init_data){
1453	.name = "gcc_disp_ahb_clk",
1454	.flags = CLK_IS_CRITICAL,
1455	.ops = &clk_branch2_ops,
1456	},
1457	},
1458	};
1459
1460	static struct clk_branch gcc_disp_hf_axi_clk = {
1461	.halt_reg = 0xb038,
1462	.halt_check = BRANCH_HALT,
1463	.clkr = {
1464	.enable_reg = 0xb038,
1465	.enable_mask = BIT(0),
1466	.hw.init = &(struct clk_init_data){
1467	.name = "gcc_disp_hf_axi_clk",
1468	.ops = &clk_branch2_ops,
1469	},
1470	},
1471	};
1472
1473	static struct clk_branch gcc_disp_sf_axi_clk = {
1474	.halt_reg = 0xb03c,
1475	.halt_check = BRANCH_HALT,
1476	.clkr = {
1477	.enable_reg = 0xb03c,
1478	.enable_mask = BIT(0),
1479	.hw.init = &(struct clk_init_data){
1480	.name = "gcc_disp_sf_axi_clk",
1481	.ops = &clk_branch2_ops,
1482	},
1483	},
1484	};
1485
1486	/* XO critical input to disp, so no need to poll */
1487	static struct clk_branch gcc_disp_xo_clk = {
1488	.halt_reg = 0xb048,
1489	.halt_check = BRANCH_HALT_DELAY,
1490	.clkr = {
1491	.enable_reg = 0xb048,
1492	.enable_mask = BIT(0),
1493	.hw.init = &(struct clk_init_data){
1494	.name = "gcc_disp_xo_clk",
1495	.flags = CLK_IS_CRITICAL,
1496	.ops = &clk_branch2_ops,
1497	},
1498	},
1499	};
1500
1501	static struct clk_branch gcc_emac_axi_clk = {
1502	.halt_reg = 0x6010,
1503	.halt_check = BRANCH_HALT,
1504	.clkr = {
1505	.enable_reg = 0x6010,
1506	.enable_mask = BIT(0),
1507	.hw.init = &(struct clk_init_data){
1508	.name = "gcc_emac_axi_clk",
1509	.ops = &clk_branch2_ops,
1510	},
1511	},
1512	};
1513
1514	static struct clk_branch gcc_emac_ptp_clk = {
1515	.halt_reg = 0x6034,
1516	.halt_check = BRANCH_HALT,
1517	.clkr = {
1518	.enable_reg = 0x6034,
1519	.enable_mask = BIT(0),
1520	.hw.init = &(struct clk_init_data){
1521	.name = "gcc_emac_ptp_clk",
1522	.parent_hws = (const struct clk_hw *[]){
1523	&gcc_emac_ptp_clk_src.clkr.hw },
1524	.num_parents = 1,
1525	.flags = CLK_SET_RATE_PARENT,
1526	.ops = &clk_branch2_ops,
1527	},
1528	},
1529	};
1530
1531	static struct clk_branch gcc_emac_rgmii_clk = {
1532	.halt_reg = 0x6018,
1533	.halt_check = BRANCH_HALT,
1534	.clkr = {
1535	.enable_reg = 0x6018,
1536	.enable_mask = BIT(0),
1537	.hw.init = &(struct clk_init_data){
1538	.name = "gcc_emac_rgmii_clk",
1539	.parent_hws = (const struct clk_hw *[]){
1540	&gcc_emac_rgmii_clk_src.clkr.hw },
1541	.num_parents = 1,
1542	.flags = CLK_SET_RATE_PARENT,
1543	.ops = &clk_branch2_ops,
1544	},
1545	},
1546	};
1547
1548	static struct clk_branch gcc_emac_slv_ahb_clk = {
1549	.halt_reg = 0x6014,
1550	.halt_check = BRANCH_HALT,
1551	.hwcg_reg = 0x6014,
1552	.hwcg_bit = 1,
1553	.clkr = {
1554	.enable_reg = 0x6014,
1555	.enable_mask = BIT(0),
1556	.hw.init = &(struct clk_init_data){
1557	.name = "gcc_emac_slv_ahb_clk",
1558	.ops = &clk_branch2_ops,
1559	},
1560	},
1561	};
1562
1563	static struct clk_branch gcc_gp1_clk = {
1564	.halt_reg = 0x64000,
1565	.halt_check = BRANCH_HALT,
1566	.clkr = {
1567	.enable_reg = 0x64000,
1568	.enable_mask = BIT(0),
1569	.hw.init = &(struct clk_init_data){
1570	.name = "gcc_gp1_clk",
1571	.parent_hws = (const struct clk_hw *[]){
1572	&gcc_gp1_clk_src.clkr.hw },
1573	.num_parents = 1,
1574	.flags = CLK_SET_RATE_PARENT,
1575	.ops = &clk_branch2_ops,
1576	},
1577	},
1578	};
1579
1580	static struct clk_branch gcc_gp2_clk = {
1581	.halt_reg = 0x65000,
1582	.halt_check = BRANCH_HALT,
1583	.clkr = {
1584	.enable_reg = 0x65000,
1585	.enable_mask = BIT(0),
1586	.hw.init = &(struct clk_init_data){
1587	.name = "gcc_gp2_clk",
1588	.parent_hws = (const struct clk_hw *[]){
1589	&gcc_gp2_clk_src.clkr.hw },
1590	.num_parents = 1,
1591	.flags = CLK_SET_RATE_PARENT,
1592	.ops = &clk_branch2_ops,
1593	},
1594	},
1595	};
1596
1597	static struct clk_branch gcc_gp3_clk = {
1598	.halt_reg = 0x66000,
1599	.halt_check = BRANCH_HALT,
1600	.clkr = {
1601	.enable_reg = 0x66000,
1602	.enable_mask = BIT(0),
1603	.hw.init = &(struct clk_init_data){
1604	.name = "gcc_gp3_clk",
1605	.parent_hws = (const struct clk_hw *[]){
1606	&gcc_gp3_clk_src.clkr.hw },
1607	.num_parents = 1,
1608	.flags = CLK_SET_RATE_PARENT,
1609	.ops = &clk_branch2_ops,
1610	},
1611	},
1612	};
1613
1614	static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1615	.halt_reg = 0x71004,
1616	.halt_check = BRANCH_HALT,
1617	.hwcg_reg = 0x71004,
1618	.hwcg_bit = 1,
1619	.clkr = {
1620	.enable_reg = 0x71004,
1621	.enable_mask = BIT(0),
1622	.hw.init = &(struct clk_init_data){
1623	.name = "gcc_gpu_cfg_ahb_clk",
1624	/* required for gpu */
1625	.flags = CLK_IS_CRITICAL,
1626	.ops = &clk_branch2_ops,
1627	},
1628	},
1629	};
1630
1631	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1632	.halt_check = BRANCH_HALT_SKIP,
1633	.clkr = {
1634	.enable_reg = 0x52004,
1635	.enable_mask = BIT(15),
1636	.hw.init = &(struct clk_init_data){
1637	.name = "gcc_gpu_gpll0_clk_src",
1638	.parent_hws = (const struct clk_hw *[]){
1639	&gpll0.clkr.hw },
1640	.num_parents = 1,
1641	.flags = CLK_SET_RATE_PARENT,
1642	.ops = &clk_branch2_ops,
1643	},
1644	},
1645	};
1646
1647	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1648	.halt_check = BRANCH_HALT_SKIP,
1649	.clkr = {
1650	.enable_reg = 0x52004,
1651	.enable_mask = BIT(16),
1652	.hw.init = &(struct clk_init_data){
1653	.name = "gcc_gpu_gpll0_div_clk_src",
1654	.parent_hws = (const struct clk_hw *[]){
1655	&gpll0_out_even.clkr.hw },
1656	.num_parents = 1,
1657	.flags = CLK_SET_RATE_PARENT,
1658	.ops = &clk_branch2_ops,
1659	},
1660	},
1661	};
1662
1663	static struct clk_branch gcc_gpu_iref_clk = {
1664	.halt_reg = 0x8c010,
1665	.halt_check = BRANCH_HALT,
1666	.clkr = {
1667	.enable_reg = 0x8c010,
1668	.enable_mask = BIT(0),
1669	.hw.init = &(struct clk_init_data){
1670	.name = "gcc_gpu_iref_clk",
1671	.ops = &clk_branch2_ops,
1672	},
1673	},
1674	};
1675
1676	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1677	.halt_reg = 0x7100c,
1678	.halt_check = BRANCH_VOTED,
1679	.clkr = {
1680	.enable_reg = 0x7100c,
1681	.enable_mask = BIT(0),
1682	.hw.init = &(struct clk_init_data){
1683	.name = "gcc_gpu_memnoc_gfx_clk",
1684	.ops = &clk_branch2_ops,
1685	},
1686	},
1687	};
1688
1689	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1690	.halt_reg = 0x71018,
1691	.halt_check = BRANCH_HALT,
1692	.clkr = {
1693	.enable_reg = 0x71018,
1694	.enable_mask = BIT(0),
1695	.hw.init = &(struct clk_init_data){
1696	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1697	.ops = &clk_branch2_ops,
1698	},
1699	},
1700	};
1701
1702	static struct clk_branch gcc_npu_at_clk = {
1703	.halt_reg = 0x4d010,
1704	.halt_check = BRANCH_VOTED,
1705	.clkr = {
1706	.enable_reg = 0x4d010,
1707	.enable_mask = BIT(0),
1708	.hw.init = &(struct clk_init_data){
1709	.name = "gcc_npu_at_clk",
1710	.ops = &clk_branch2_ops,
1711	},
1712	},
1713	};
1714
1715	static struct clk_branch gcc_npu_axi_clk = {
1716	.halt_reg = 0x4d008,
1717	.halt_check = BRANCH_VOTED,
1718	.clkr = {
1719	.enable_reg = 0x4d008,
1720	.enable_mask = BIT(0),
1721	.hw.init = &(struct clk_init_data){
1722	.name = "gcc_npu_axi_clk",
1723	.ops = &clk_branch2_ops,
1724	},
1725	},
1726	};
1727
1728	static struct clk_branch gcc_npu_cfg_ahb_clk = {
1729	.halt_reg = 0x4d004,
1730	.halt_check = BRANCH_HALT,
1731	.hwcg_reg = 0x4d004,
1732	.hwcg_bit = 1,
1733	.clkr = {
1734	.enable_reg = 0x4d004,
1735	.enable_mask = BIT(0),
1736	.hw.init = &(struct clk_init_data){
1737	.name = "gcc_npu_cfg_ahb_clk",
1738	/* required for npu */
1739	.flags = CLK_IS_CRITICAL,
1740	.ops = &clk_branch2_ops,
1741	},
1742	},
1743	};
1744
1745	static struct clk_branch gcc_npu_gpll0_clk_src = {
1746	.halt_check = BRANCH_HALT_SKIP,
1747	.clkr = {
1748	.enable_reg = 0x52004,
1749	.enable_mask = BIT(18),
1750	.hw.init = &(struct clk_init_data){
1751	.name = "gcc_npu_gpll0_clk_src",
1752	.parent_hws = (const struct clk_hw *[]){
1753	&gpll0.clkr.hw },
1754	.num_parents = 1,
1755	.flags = CLK_SET_RATE_PARENT,
1756	.ops = &clk_branch2_ops,
1757	},
1758	},
1759	};
1760
1761	static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1762	.halt_check = BRANCH_HALT_SKIP,
1763	.clkr = {
1764	.enable_reg = 0x52004,
1765	.enable_mask = BIT(19),
1766	.hw.init = &(struct clk_init_data){
1767	.name = "gcc_npu_gpll0_div_clk_src",
1768	.parent_hws = (const struct clk_hw *[]){
1769	&gpll0_out_even.clkr.hw },
1770	.num_parents = 1,
1771	.flags = CLK_SET_RATE_PARENT,
1772	.ops = &clk_branch2_ops,
1773	},
1774	},
1775	};
1776
1777	static struct clk_branch gcc_npu_trig_clk = {
1778	.halt_reg = 0x4d00c,
1779	.halt_check = BRANCH_VOTED,
1780	.clkr = {
1781	.enable_reg = 0x4d00c,
1782	.enable_mask = BIT(0),
1783	.hw.init = &(struct clk_init_data){
1784	.name = "gcc_npu_trig_clk",
1785	.ops = &clk_branch2_ops,
1786	},
1787	},
1788	};
1789
1790	static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1791	.halt_reg = 0x6f02c,
1792	.halt_check = BRANCH_HALT,
1793	.clkr = {
1794	.enable_reg = 0x6f02c,
1795	.enable_mask = BIT(0),
1796	.hw.init = &(struct clk_init_data){
1797	.name = "gcc_pcie0_phy_refgen_clk",
1798	.parent_hws = (const struct clk_hw *[]){
1799	&gcc_pcie_phy_refgen_clk_src.clkr.hw },
1800	.num_parents = 1,
1801	.flags = CLK_SET_RATE_PARENT,
1802	.ops = &clk_branch2_ops,
1803	},
1804	},
1805	};
1806
1807	static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1808	.halt_reg = 0x6f030,
1809	.halt_check = BRANCH_HALT,
1810	.clkr = {
1811	.enable_reg = 0x6f030,
1812	.enable_mask = BIT(0),
1813	.hw.init = &(struct clk_init_data){
1814	.name = "gcc_pcie1_phy_refgen_clk",
1815	.parent_hws = (const struct clk_hw *[]){
1816	&gcc_pcie_phy_refgen_clk_src.clkr.hw },
1817	.num_parents = 1,
1818	.flags = CLK_SET_RATE_PARENT,
1819	.ops = &clk_branch2_ops,
1820	},
1821	},
1822	};
1823
1824	static struct clk_branch gcc_pcie_0_aux_clk = {
1825	.halt_reg = 0x6b020,
1826	.halt_check = BRANCH_HALT_VOTED,
1827	.clkr = {
1828	.enable_reg = 0x5200c,
1829	.enable_mask = BIT(3),
1830	.hw.init = &(struct clk_init_data){
1831	.name = "gcc_pcie_0_aux_clk",
1832	.parent_hws = (const struct clk_hw *[]){
1833	&gcc_pcie_0_aux_clk_src.clkr.hw },
1834	.num_parents = 1,
1835	.flags = CLK_SET_RATE_PARENT,
1836	.ops = &clk_branch2_ops,
1837	},
1838	},
1839	};
1840
1841	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1842	.halt_reg = 0x6b01c,
1843	.halt_check = BRANCH_HALT_VOTED,
1844	.hwcg_reg = 0x6b01c,
1845	.hwcg_bit = 1,
1846	.clkr = {
1847	.enable_reg = 0x5200c,
1848	.enable_mask = BIT(2),
1849	.hw.init = &(struct clk_init_data){
1850	.name = "gcc_pcie_0_cfg_ahb_clk",
1851	.ops = &clk_branch2_ops,
1852	},
1853	},
1854	};
1855
1856	static struct clk_branch gcc_pcie_0_clkref_clk = {
1857	.halt_reg = 0x8c00c,
1858	.halt_check = BRANCH_HALT,
1859	.clkr = {
1860	.enable_reg = 0x8c00c,
1861	.enable_mask = BIT(0),
1862	.hw.init = &(struct clk_init_data){
1863	.name = "gcc_pcie_0_clkref_clk",
1864	.ops = &clk_branch2_ops,
1865	},
1866	},
1867	};
1868
1869	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1870	.halt_reg = 0x6b018,
1871	.halt_check = BRANCH_HALT_VOTED,
1872	.clkr = {
1873	.enable_reg = 0x5200c,
1874	.enable_mask = BIT(1),
1875	.hw.init = &(struct clk_init_data){
1876	.name = "gcc_pcie_0_mstr_axi_clk",
1877	.ops = &clk_branch2_ops,
1878	},
1879	},
1880	};
1881
1882	/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1883	static struct clk_branch gcc_pcie_0_pipe_clk = {
1884	.halt_reg = 0x6b024,
1885	.halt_check = BRANCH_HALT_DELAY,
1886	.clkr = {
1887	.enable_reg = 0x5200c,
1888	.enable_mask = BIT(4),
1889	.hw.init = &(struct clk_init_data){
1890	.name = "gcc_pcie_0_pipe_clk",
1891	.ops = &clk_branch2_ops,
1892	},
1893	},
1894	};
1895
1896	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1897	.halt_reg = 0x6b014,
1898	.halt_check = BRANCH_HALT_VOTED,
1899	.hwcg_reg = 0x6b014,
1900	.hwcg_bit = 1,
1901	.clkr = {
1902	.enable_reg = 0x5200c,
1903	.enable_mask = BIT(0),
1904	.hw.init = &(struct clk_init_data){
1905	.name = "gcc_pcie_0_slv_axi_clk",
1906	.ops = &clk_branch2_ops,
1907	},
1908	},
1909	};
1910
1911	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1912	.halt_reg = 0x6b010,
1913	.halt_check = BRANCH_HALT_VOTED,
1914	.clkr = {
1915	.enable_reg = 0x5200c,
1916	.enable_mask = BIT(5),
1917	.hw.init = &(struct clk_init_data){
1918	.name = "gcc_pcie_0_slv_q2a_axi_clk",
1919	.ops = &clk_branch2_ops,
1920	},
1921	},
1922	};
1923
1924	static struct clk_branch gcc_pcie_1_aux_clk = {
1925	.halt_reg = 0x8d020,
1926	.halt_check = BRANCH_HALT_VOTED,
1927	.clkr = {
1928	.enable_reg = 0x52004,
1929	.enable_mask = BIT(29),
1930	.hw.init = &(struct clk_init_data){
1931	.name = "gcc_pcie_1_aux_clk",
1932	.parent_hws = (const struct clk_hw *[]){
1933	&gcc_pcie_1_aux_clk_src.clkr.hw },
1934	.num_parents = 1,
1935	.flags = CLK_SET_RATE_PARENT,
1936	.ops = &clk_branch2_ops,
1937	},
1938	},
1939	};
1940
1941	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1942	.halt_reg = 0x8d01c,
1943	.halt_check = BRANCH_HALT_VOTED,
1944	.hwcg_reg = 0x8d01c,
1945	.hwcg_bit = 1,
1946	.clkr = {
1947	.enable_reg = 0x52004,
1948	.enable_mask = BIT(28),
1949	.hw.init = &(struct clk_init_data){
1950	.name = "gcc_pcie_1_cfg_ahb_clk",
1951	.ops = &clk_branch2_ops,
1952	},
1953	},
1954	};
1955
1956	static struct clk_branch gcc_pcie_1_clkref_clk = {
1957	.halt_reg = 0x8c02c,
1958	.halt_check = BRANCH_HALT,
1959	.clkr = {
1960	.enable_reg = 0x8c02c,
1961	.enable_mask = BIT(0),
1962	.hw.init = &(struct clk_init_data){
1963	.name = "gcc_pcie_1_clkref_clk",
1964	.ops = &clk_branch2_ops,
1965	},
1966	},
1967	};
1968
1969	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1970	.halt_reg = 0x8d018,
1971	.halt_check = BRANCH_HALT_VOTED,
1972	.clkr = {
1973	.enable_reg = 0x52004,
1974	.enable_mask = BIT(27),
1975	.hw.init = &(struct clk_init_data){
1976	.name = "gcc_pcie_1_mstr_axi_clk",
1977	.ops = &clk_branch2_ops,
1978	},
1979	},
1980	};
1981
1982	/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1983	static struct clk_branch gcc_pcie_1_pipe_clk = {
1984	.halt_reg = 0x8d024,
1985	.halt_check = BRANCH_HALT_DELAY,
1986	.clkr = {
1987	.enable_reg = 0x52004,
1988	.enable_mask = BIT(30),
1989	.hw.init = &(struct clk_init_data){
1990	.name = "gcc_pcie_1_pipe_clk",
1991	.ops = &clk_branch2_ops,
1992	},
1993	},
1994	};
1995
1996	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1997	.halt_reg = 0x8d014,
1998	.halt_check = BRANCH_HALT_VOTED,
1999	.hwcg_reg = 0x8d014,
2000	.hwcg_bit = 1,
2001	.clkr = {
2002	.enable_reg = 0x52004,
2003	.enable_mask = BIT(26),
2004	.hw.init = &(struct clk_init_data){
2005	.name = "gcc_pcie_1_slv_axi_clk",
2006	.ops = &clk_branch2_ops,
2007	},
2008	},
2009	};
2010
2011	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2012	.halt_reg = 0x8d010,
2013	.halt_check = BRANCH_HALT_VOTED,
2014	.clkr = {
2015	.enable_reg = 0x52004,
2016	.enable_mask = BIT(25),
2017	.hw.init = &(struct clk_init_data){
2018	.name = "gcc_pcie_1_slv_q2a_axi_clk",
2019	.ops = &clk_branch2_ops,
2020	},
2021	},
2022	};
2023
2024	static struct clk_branch gcc_pcie_phy_aux_clk = {
2025	.halt_reg = 0x6f004,
2026	.halt_check = BRANCH_HALT,
2027	.clkr = {
2028	.enable_reg = 0x6f004,
2029	.enable_mask = BIT(0),
2030	.hw.init = &(struct clk_init_data){
2031	.name = "gcc_pcie_phy_aux_clk",
2032	.parent_hws = (const struct clk_hw *[]){
2033	&gcc_pcie_0_aux_clk_src.clkr.hw },
2034	.num_parents = 1,
2035	.flags = CLK_SET_RATE_PARENT,
2036	.ops = &clk_branch2_ops,
2037	},
2038	},
2039	};
2040
2041	static struct clk_branch gcc_pdm2_clk = {
2042	.halt_reg = 0x3300c,
2043	.halt_check = BRANCH_HALT,
2044	.clkr = {
2045	.enable_reg = 0x3300c,
2046	.enable_mask = BIT(0),
2047	.hw.init = &(struct clk_init_data){
2048	.name = "gcc_pdm2_clk",
2049	.parent_hws = (const struct clk_hw *[]){
2050	&gcc_pdm2_clk_src.clkr.hw },
2051	.num_parents = 1,
2052	.flags = CLK_SET_RATE_PARENT,
2053	.ops = &clk_branch2_ops,
2054	},
2055	},
2056	};
2057
2058	static struct clk_branch gcc_pdm_ahb_clk = {
2059	.halt_reg = 0x33004,
2060	.halt_check = BRANCH_HALT,
2061	.hwcg_reg = 0x33004,
2062	.hwcg_bit = 1,
2063	.clkr = {
2064	.enable_reg = 0x33004,
2065	.enable_mask = BIT(0),
2066	.hw.init = &(struct clk_init_data){
2067	.name = "gcc_pdm_ahb_clk",
2068	.ops = &clk_branch2_ops,
2069	},
2070	},
2071	};
2072
2073	static struct clk_branch gcc_pdm_xo4_clk = {
2074	.halt_reg = 0x33008,
2075	.halt_check = BRANCH_HALT,
2076	.clkr = {
2077	.enable_reg = 0x33008,
2078	.enable_mask = BIT(0),
2079	.hw.init = &(struct clk_init_data){
2080	.name = "gcc_pdm_xo4_clk",
2081	.ops = &clk_branch2_ops,
2082	},
2083	},
2084	};
2085
2086	static struct clk_branch gcc_prng_ahb_clk = {
2087	.halt_reg = 0x34004,
2088	.halt_check = BRANCH_HALT_VOTED,
2089	.clkr = {
2090	.enable_reg = 0x52004,
2091	.enable_mask = BIT(13),
2092	.hw.init = &(struct clk_init_data){
2093	.name = "gcc_prng_ahb_clk",
2094	.ops = &clk_branch2_ops,
2095	},
2096	},
2097	};
2098
2099	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2100	.halt_reg = 0xb018,
2101	.halt_check = BRANCH_HALT,
2102	.hwcg_reg = 0xb018,
2103	.hwcg_bit = 1,
2104	.clkr = {
2105	.enable_reg = 0xb018,
2106	.enable_mask = BIT(0),
2107	.hw.init = &(struct clk_init_data){
2108	.name = "gcc_qmip_camera_nrt_ahb_clk",
2109	.ops = &clk_branch2_ops,
2110	},
2111	},
2112	};
2113
2114	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2115	.halt_reg = 0xb01c,
2116	.halt_check = BRANCH_HALT,
2117	.hwcg_reg = 0xb01c,
2118	.hwcg_bit = 1,
2119	.clkr = {
2120	.enable_reg = 0xb01c,
2121	.enable_mask = BIT(0),
2122	.hw.init = &(struct clk_init_data){
2123	.name = "gcc_qmip_camera_rt_ahb_clk",
2124	.ops = &clk_branch2_ops,
2125	},
2126	},
2127	};
2128
2129	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2130	.halt_reg = 0xb020,
2131	.halt_check = BRANCH_HALT,
2132	.hwcg_reg = 0xb020,
2133	.hwcg_bit = 1,
2134	.clkr = {
2135	.enable_reg = 0xb020,
2136	.enable_mask = BIT(0),
2137	.hw.init = &(struct clk_init_data){
2138	.name = "gcc_qmip_disp_ahb_clk",
2139	.ops = &clk_branch2_ops,
2140	},
2141	},
2142	};
2143
2144	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2145	.halt_reg = 0xb010,
2146	.halt_check = BRANCH_HALT,
2147	.hwcg_reg = 0xb010,
2148	.hwcg_bit = 1,
2149	.clkr = {
2150	.enable_reg = 0xb010,
2151	.enable_mask = BIT(0),
2152	.hw.init = &(struct clk_init_data){
2153	.name = "gcc_qmip_video_cvp_ahb_clk",
2154	.ops = &clk_branch2_ops,
2155	},
2156	},
2157	};
2158
2159	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2160	.halt_reg = 0xb014,
2161	.halt_check = BRANCH_HALT,
2162	.hwcg_reg = 0xb014,
2163	.hwcg_bit = 1,
2164	.clkr = {
2165	.enable_reg = 0xb014,
2166	.enable_mask = BIT(0),
2167	.hw.init = &(struct clk_init_data){
2168	.name = "gcc_qmip_video_vcodec_ahb_clk",
2169	.ops = &clk_branch2_ops,
2170	},
2171	},
2172	};
2173
2174	static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2175	.halt_reg = 0x4b000,
2176	.halt_check = BRANCH_HALT,
2177	.clkr = {
2178	.enable_reg = 0x4b000,
2179	.enable_mask = BIT(0),
2180	.hw.init = &(struct clk_init_data){
2181	.name = "gcc_qspi_cnoc_periph_ahb_clk",
2182	.ops = &clk_branch2_ops,
2183	},
2184	},
2185	};
2186
2187	static struct clk_branch gcc_qspi_core_clk = {
2188	.halt_reg = 0x4b004,
2189	.halt_check = BRANCH_HALT,
2190	.clkr = {
2191	.enable_reg = 0x4b004,
2192	.enable_mask = BIT(0),
2193	.hw.init = &(struct clk_init_data){
2194	.name = "gcc_qspi_core_clk",
2195	.parent_hws = (const struct clk_hw *[]){
2196	&gcc_qspi_core_clk_src.clkr.hw },
2197	.num_parents = 1,
2198	.flags = CLK_SET_RATE_PARENT,
2199	.ops = &clk_branch2_ops,
2200	},
2201	},
2202	};
2203
2204	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2205	.halt_reg = 0x17144,
2206	.halt_check = BRANCH_HALT_VOTED,
2207	.clkr = {
2208	.enable_reg = 0x5200c,
2209	.enable_mask = BIT(10),
2210	.hw.init = &(struct clk_init_data){
2211	.name = "gcc_qupv3_wrap0_s0_clk",
2212	.parent_hws = (const struct clk_hw *[]){
2213	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2214	.num_parents = 1,
2215	.flags = CLK_SET_RATE_PARENT,
2216	.ops = &clk_branch2_ops,
2217	},
2218	},
2219	};
2220
2221	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2222	.halt_reg = 0x17274,
2223	.halt_check = BRANCH_HALT_VOTED,
2224	.clkr = {
2225	.enable_reg = 0x5200c,
2226	.enable_mask = BIT(11),
2227	.hw.init = &(struct clk_init_data){
2228	.name = "gcc_qupv3_wrap0_s1_clk",
2229	.parent_hws = (const struct clk_hw *[]){
2230	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2231	.num_parents = 1,
2232	.flags = CLK_SET_RATE_PARENT,
2233	.ops = &clk_branch2_ops,
2234	},
2235	},
2236	};
2237
2238	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2239	.halt_reg = 0x173a4,
2240	.halt_check = BRANCH_HALT_VOTED,
2241	.clkr = {
2242	.enable_reg = 0x5200c,
2243	.enable_mask = BIT(12),
2244	.hw.init = &(struct clk_init_data){
2245	.name = "gcc_qupv3_wrap0_s2_clk",
2246	.parent_hws = (const struct clk_hw *[]){
2247	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2248	.num_parents = 1,
2249	.flags = CLK_SET_RATE_PARENT,
2250	.ops = &clk_branch2_ops,
2251	},
2252	},
2253	};
2254
2255	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2256	.halt_reg = 0x174d4,
2257	.halt_check = BRANCH_HALT_VOTED,
2258	.clkr = {
2259	.enable_reg = 0x5200c,
2260	.enable_mask = BIT(13),
2261	.hw.init = &(struct clk_init_data){
2262	.name = "gcc_qupv3_wrap0_s3_clk",
2263	.parent_hws = (const struct clk_hw *[]){
2264	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2265	.num_parents = 1,
2266	.flags = CLK_SET_RATE_PARENT,
2267	.ops = &clk_branch2_ops,
2268	},
2269	},
2270	};
2271
2272	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2273	.halt_reg = 0x17604,
2274	.halt_check = BRANCH_HALT_VOTED,
2275	.clkr = {
2276	.enable_reg = 0x5200c,
2277	.enable_mask = BIT(14),
2278	.hw.init = &(struct clk_init_data){
2279	.name = "gcc_qupv3_wrap0_s4_clk",
2280	.parent_hws = (const struct clk_hw *[]){
2281	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2282	.num_parents = 1,
2283	.flags = CLK_SET_RATE_PARENT,
2284	.ops = &clk_branch2_ops,
2285	},
2286	},
2287	};
2288
2289	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2290	.halt_reg = 0x17734,
2291	.halt_check = BRANCH_HALT_VOTED,
2292	.clkr = {
2293	.enable_reg = 0x5200c,
2294	.enable_mask = BIT(15),
2295	.hw.init = &(struct clk_init_data){
2296	.name = "gcc_qupv3_wrap0_s5_clk",
2297	.parent_hws = (const struct clk_hw *[]){
2298	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2299	.num_parents = 1,
2300	.flags = CLK_SET_RATE_PARENT,
2301	.ops = &clk_branch2_ops,
2302	},
2303	},
2304	};
2305
2306	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2307	.halt_reg = 0x17864,
2308	.halt_check = BRANCH_HALT_VOTED,
2309	.clkr = {
2310	.enable_reg = 0x5200c,
2311	.enable_mask = BIT(16),
2312	.hw.init = &(struct clk_init_data){
2313	.name = "gcc_qupv3_wrap0_s6_clk",
2314	.parent_hws = (const struct clk_hw *[]){
2315	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2316	.num_parents = 1,
2317	.flags = CLK_SET_RATE_PARENT,
2318	.ops = &clk_branch2_ops,
2319	},
2320	},
2321	};
2322
2323	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2324	.halt_reg = 0x17994,
2325	.halt_check = BRANCH_HALT_VOTED,
2326	.clkr = {
2327	.enable_reg = 0x5200c,
2328	.enable_mask = BIT(17),
2329	.hw.init = &(struct clk_init_data){
2330	.name = "gcc_qupv3_wrap0_s7_clk",
2331	.parent_hws = (const struct clk_hw *[]){
2332	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2333	.num_parents = 1,
2334	.flags = CLK_SET_RATE_PARENT,
2335	.ops = &clk_branch2_ops,
2336	},
2337	},
2338	};
2339
2340	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2341	.halt_reg = 0x18144,
2342	.halt_check = BRANCH_HALT_VOTED,
2343	.clkr = {
2344	.enable_reg = 0x5200c,
2345	.enable_mask = BIT(22),
2346	.hw.init = &(struct clk_init_data){
2347	.name = "gcc_qupv3_wrap1_s0_clk",
2348	.parent_hws = (const struct clk_hw *[]){
2349	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2350	.num_parents = 1,
2351	.flags = CLK_SET_RATE_PARENT,
2352	.ops = &clk_branch2_ops,
2353	},
2354	},
2355	};
2356
2357	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2358	.halt_reg = 0x18274,
2359	.halt_check = BRANCH_HALT_VOTED,
2360	.clkr = {
2361	.enable_reg = 0x5200c,
2362	.enable_mask = BIT(23),
2363	.hw.init = &(struct clk_init_data){
2364	.name = "gcc_qupv3_wrap1_s1_clk",
2365	.parent_hws = (const struct clk_hw *[]){
2366	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2367	.num_parents = 1,
2368	.flags = CLK_SET_RATE_PARENT,
2369	.ops = &clk_branch2_ops,
2370	},
2371	},
2372	};
2373
2374	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2375	.halt_reg = 0x183a4,
2376	.halt_check = BRANCH_HALT_VOTED,
2377	.clkr = {
2378	.enable_reg = 0x5200c,
2379	.enable_mask = BIT(24),
2380	.hw.init = &(struct clk_init_data){
2381	.name = "gcc_qupv3_wrap1_s2_clk",
2382	.parent_hws = (const struct clk_hw *[]){
2383	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2384	.num_parents = 1,
2385	.flags = CLK_SET_RATE_PARENT,
2386	.ops = &clk_branch2_ops,
2387	},
2388	},
2389	};
2390
2391	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2392	.halt_reg = 0x184d4,
2393	.halt_check = BRANCH_HALT_VOTED,
2394	.clkr = {
2395	.enable_reg = 0x5200c,
2396	.enable_mask = BIT(25),
2397	.hw.init = &(struct clk_init_data){
2398	.name = "gcc_qupv3_wrap1_s3_clk",
2399	.parent_hws = (const struct clk_hw *[]){
2400	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2401	.num_parents = 1,
2402	.flags = CLK_SET_RATE_PARENT,
2403	.ops = &clk_branch2_ops,
2404	},
2405	},
2406	};
2407
2408	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2409	.halt_reg = 0x18604,
2410	.halt_check = BRANCH_HALT_VOTED,
2411	.clkr = {
2412	.enable_reg = 0x5200c,
2413	.enable_mask = BIT(26),
2414	.hw.init = &(struct clk_init_data){
2415	.name = "gcc_qupv3_wrap1_s4_clk",
2416	.parent_hws = (const struct clk_hw *[]){
2417	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2418	.num_parents = 1,
2419	.flags = CLK_SET_RATE_PARENT,
2420	.ops = &clk_branch2_ops,
2421	},
2422	},
2423	};
2424
2425	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2426	.halt_reg = 0x18734,
2427	.halt_check = BRANCH_HALT_VOTED,
2428	.clkr = {
2429	.enable_reg = 0x5200c,
2430	.enable_mask = BIT(27),
2431	.hw.init = &(struct clk_init_data){
2432	.name = "gcc_qupv3_wrap1_s5_clk",
2433	.parent_hws = (const struct clk_hw *[]){
2434	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2435	.num_parents = 1,
2436	.flags = CLK_SET_RATE_PARENT,
2437	.ops = &clk_branch2_ops,
2438	},
2439	},
2440	};
2441
2442	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2443	.halt_reg = 0x1e144,
2444	.halt_check = BRANCH_HALT_VOTED,
2445	.clkr = {
2446	.enable_reg = 0x52014,
2447	.enable_mask = BIT(4),
2448	.hw.init = &(struct clk_init_data){
2449	.name = "gcc_qupv3_wrap2_s0_clk",
2450	.parent_hws = (const struct clk_hw *[]){
2451	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2452	.num_parents = 1,
2453	.flags = CLK_SET_RATE_PARENT,
2454	.ops = &clk_branch2_ops,
2455	},
2456	},
2457	};
2458
2459	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2460	.halt_reg = 0x1e274,
2461	.halt_check = BRANCH_HALT_VOTED,
2462	.clkr = {
2463	.enable_reg = 0x52014,
2464	.enable_mask = BIT(5),
2465	.hw.init = &(struct clk_init_data){
2466	.name = "gcc_qupv3_wrap2_s1_clk",
2467	.parent_hws = (const struct clk_hw *[]){
2468	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2469	.num_parents = 1,
2470	.flags = CLK_SET_RATE_PARENT,
2471	.ops = &clk_branch2_ops,
2472	},
2473	},
2474	};
2475
2476	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2477	.halt_reg = 0x1e3a4,
2478	.halt_check = BRANCH_HALT_VOTED,
2479	.clkr = {
2480	.enable_reg = 0x52014,
2481	.enable_mask = BIT(6),
2482	.hw.init = &(struct clk_init_data){
2483	.name = "gcc_qupv3_wrap2_s2_clk",
2484	.parent_hws = (const struct clk_hw *[]){
2485	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2486	.num_parents = 1,
2487	.flags = CLK_SET_RATE_PARENT,
2488	.ops = &clk_branch2_ops,
2489	},
2490	},
2491	};
2492
2493	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2494	.halt_reg = 0x1e4d4,
2495	.halt_check = BRANCH_HALT_VOTED,
2496	.clkr = {
2497	.enable_reg = 0x52014,
2498	.enable_mask = BIT(7),
2499	.hw.init = &(struct clk_init_data){
2500	.name = "gcc_qupv3_wrap2_s3_clk",
2501	.parent_hws = (const struct clk_hw *[]){
2502	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2503	.num_parents = 1,
2504	.flags = CLK_SET_RATE_PARENT,
2505	.ops = &clk_branch2_ops,
2506	},
2507	},
2508	};
2509
2510	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2511	.halt_reg = 0x1e604,
2512	.halt_check = BRANCH_HALT_VOTED,
2513	.clkr = {
2514	.enable_reg = 0x52014,
2515	.enable_mask = BIT(8),
2516	.hw.init = &(struct clk_init_data){
2517	.name = "gcc_qupv3_wrap2_s4_clk",
2518	.parent_hws = (const struct clk_hw *[]){
2519	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2520	.num_parents = 1,
2521	.flags = CLK_SET_RATE_PARENT,
2522	.ops = &clk_branch2_ops,
2523	},
2524	},
2525	};
2526
2527	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2528	.halt_reg = 0x1e734,
2529	.halt_check = BRANCH_HALT_VOTED,
2530	.clkr = {
2531	.enable_reg = 0x52014,
2532	.enable_mask = BIT(9),
2533	.hw.init = &(struct clk_init_data){
2534	.name = "gcc_qupv3_wrap2_s5_clk",
2535	.parent_hws = (const struct clk_hw *[]){
2536	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2537	.num_parents = 1,
2538	.flags = CLK_SET_RATE_PARENT,
2539	.ops = &clk_branch2_ops,
2540	},
2541	},
2542	};
2543
2544	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2545	.halt_reg = 0x17004,
2546	.halt_check = BRANCH_HALT_VOTED,
2547	.clkr = {
2548	.enable_reg = 0x5200c,
2549	.enable_mask = BIT(6),
2550	.hw.init = &(struct clk_init_data){
2551	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2552	.ops = &clk_branch2_ops,
2553	},
2554	},
2555	};
2556
2557	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2558	.halt_reg = 0x17008,
2559	.halt_check = BRANCH_HALT_VOTED,
2560	.hwcg_reg = 0x17008,
2561	.hwcg_bit = 1,
2562	.clkr = {
2563	.enable_reg = 0x5200c,
2564	.enable_mask = BIT(7),
2565	.hw.init = &(struct clk_init_data){
2566	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2567	.ops = &clk_branch2_ops,
2568	},
2569	},
2570	};
2571
2572	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2573	.halt_reg = 0x18004,
2574	.halt_check = BRANCH_HALT_VOTED,
2575	.clkr = {
2576	.enable_reg = 0x5200c,
2577	.enable_mask = BIT(20),
2578	.hw.init = &(struct clk_init_data){
2579	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2580	.ops = &clk_branch2_ops,
2581	},
2582	},
2583	};
2584
2585	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2586	.halt_reg = 0x18008,
2587	.halt_check = BRANCH_HALT_VOTED,
2588	.hwcg_reg = 0x18008,
2589	.hwcg_bit = 1,
2590	.clkr = {
2591	.enable_reg = 0x5200c,
2592	.enable_mask = BIT(21),
2593	.hw.init = &(struct clk_init_data){
2594	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2595	.ops = &clk_branch2_ops,
2596	},
2597	},
2598	};
2599
2600	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2601	.halt_reg = 0x1e004,
2602	.halt_check = BRANCH_HALT_VOTED,
2603	.clkr = {
2604	.enable_reg = 0x52014,
2605	.enable_mask = BIT(2),
2606	.hw.init = &(struct clk_init_data){
2607	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2608	.ops = &clk_branch2_ops,
2609	},
2610	},
2611	};
2612
2613	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2614	.halt_reg = 0x1e008,
2615	.halt_check = BRANCH_HALT_VOTED,
2616	.hwcg_reg = 0x1e008,
2617	.hwcg_bit = 1,
2618	.clkr = {
2619	.enable_reg = 0x52014,
2620	.enable_mask = BIT(1),
2621	.hw.init = &(struct clk_init_data){
2622	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2623	.ops = &clk_branch2_ops,
2624	},
2625	},
2626	};
2627
2628	static struct clk_branch gcc_sdcc2_ahb_clk = {
2629	.halt_reg = 0x14008,
2630	.halt_check = BRANCH_HALT,
2631	.clkr = {
2632	.enable_reg = 0x14008,
2633	.enable_mask = BIT(0),
2634	.hw.init = &(struct clk_init_data){
2635	.name = "gcc_sdcc2_ahb_clk",
2636	.ops = &clk_branch2_ops,
2637	},
2638	},
2639	};
2640
2641	static struct clk_branch gcc_sdcc2_apps_clk = {
2642	.halt_reg = 0x14004,
2643	.halt_check = BRANCH_HALT,
2644	.clkr = {
2645	.enable_reg = 0x14004,
2646	.enable_mask = BIT(0),
2647	.hw.init = &(struct clk_init_data){
2648	.name = "gcc_sdcc2_apps_clk",
2649	.parent_hws = (const struct clk_hw *[]){
2650	&gcc_sdcc2_apps_clk_src.clkr.hw },
2651	.num_parents = 1,
2652	.flags = CLK_SET_RATE_PARENT,
2653	.ops = &clk_branch2_ops,
2654	},
2655	},
2656	};
2657
2658	static struct clk_branch gcc_sdcc4_ahb_clk = {
2659	.halt_reg = 0x16008,
2660	.halt_check = BRANCH_HALT,
2661	.clkr = {
2662	.enable_reg = 0x16008,
2663	.enable_mask = BIT(0),
2664	.hw.init = &(struct clk_init_data){
2665	.name = "gcc_sdcc4_ahb_clk",
2666	.ops = &clk_branch2_ops,
2667	},
2668	},
2669	};
2670
2671	static struct clk_branch gcc_sdcc4_apps_clk = {
2672	.halt_reg = 0x16004,
2673	.halt_check = BRANCH_HALT,
2674	.clkr = {
2675	.enable_reg = 0x16004,
2676	.enable_mask = BIT(0),
2677	.hw.init = &(struct clk_init_data){
2678	.name = "gcc_sdcc4_apps_clk",
2679	.parent_hws = (const struct clk_hw *[]){
2680	&gcc_sdcc4_apps_clk_src.clkr.hw },
2681	.num_parents = 1,
2682	.flags = CLK_SET_RATE_PARENT,
2683	.ops = &clk_branch2_ops,
2684	},
2685	},
2686	};
2687
2688	static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2689	.halt_reg = 0x4819c,
2690	.halt_check = BRANCH_HALT_VOTED,
2691	.clkr = {
2692	.enable_reg = 0x52004,
2693	.enable_mask = BIT(0),
2694	.hw.init = &(struct clk_init_data){
2695	.name = "gcc_sys_noc_cpuss_ahb_clk",
2696	.parent_hws = (const struct clk_hw *[]){
2697	&gcc_cpuss_ahb_clk_src.clkr.hw },
2698	.num_parents = 1,
2699	/* required for cpuss */
2700	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2701	.ops = &clk_branch2_ops,
2702	},
2703	},
2704	};
2705
2706	static struct clk_branch gcc_tsif_ahb_clk = {
2707	.halt_reg = 0x36004,
2708	.halt_check = BRANCH_HALT,
2709	.clkr = {
2710	.enable_reg = 0x36004,
2711	.enable_mask = BIT(0),
2712	.hw.init = &(struct clk_init_data){
2713	.name = "gcc_tsif_ahb_clk",
2714	.ops = &clk_branch2_ops,
2715	},
2716	},
2717	};
2718
2719	static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2720	.halt_reg = 0x3600c,
2721	.halt_check = BRANCH_HALT,
2722	.clkr = {
2723	.enable_reg = 0x3600c,
2724	.enable_mask = BIT(0),
2725	.hw.init = &(struct clk_init_data){
2726	.name = "gcc_tsif_inactivity_timers_clk",
2727	.ops = &clk_branch2_ops,
2728	},
2729	},
2730	};
2731
2732	static struct clk_branch gcc_tsif_ref_clk = {
2733	.halt_reg = 0x36008,
2734	.halt_check = BRANCH_HALT,
2735	.clkr = {
2736	.enable_reg = 0x36008,
2737	.enable_mask = BIT(0),
2738	.hw.init = &(struct clk_init_data){
2739	.name = "gcc_tsif_ref_clk",
2740	.parent_hws = (const struct clk_hw *[]){
2741	&gcc_tsif_ref_clk_src.clkr.hw },
2742	.num_parents = 1,
2743	.flags = CLK_SET_RATE_PARENT,
2744	.ops = &clk_branch2_ops,
2745	},
2746	},
2747	};
2748
2749	static struct clk_branch gcc_ufs_card_ahb_clk = {
2750	.halt_reg = 0x75014,
2751	.halt_check = BRANCH_HALT,
2752	.hwcg_reg = 0x75014,
2753	.hwcg_bit = 1,
2754	.clkr = {
2755	.enable_reg = 0x75014,
2756	.enable_mask = BIT(0),
2757	.hw.init = &(struct clk_init_data){
2758	.name = "gcc_ufs_card_ahb_clk",
2759	.ops = &clk_branch2_ops,
2760	},
2761	},
2762	};
2763
2764	static struct clk_branch gcc_ufs_card_axi_clk = {
2765	.halt_reg = 0x75010,
2766	.halt_check = BRANCH_HALT,
2767	.hwcg_reg = 0x75010,
2768	.hwcg_bit = 1,
2769	.clkr = {
2770	.enable_reg = 0x75010,
2771	.enable_mask = BIT(0),
2772	.hw.init = &(struct clk_init_data){
2773	.name = "gcc_ufs_card_axi_clk",
2774	.parent_hws = (const struct clk_hw *[]){
2775	&gcc_ufs_card_axi_clk_src.clkr.hw },
2776	.num_parents = 1,
2777	.flags = CLK_SET_RATE_PARENT,
2778	.ops = &clk_branch2_ops,
2779	},
2780	},
2781	};
2782
2783	static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2784	.halt_reg = 0x75010,
2785	.halt_check = BRANCH_HALT,
2786	.hwcg_reg = 0x75010,
2787	.hwcg_bit = 1,
2788	.clkr = {
2789	.enable_reg = 0x75010,
2790	.enable_mask = BIT(1),
2791	.hw.init = &(struct clk_init_data){
2792	.name = "gcc_ufs_card_axi_hw_ctl_clk",
2793	.parent_hws = (const struct clk_hw *[]){
2794	&gcc_ufs_card_axi_clk.clkr.hw },
2795	.num_parents = 1,
2796	.flags = CLK_SET_RATE_PARENT,
2797	.ops = &clk_branch_simple_ops,
2798	},
2799	},
2800	};
2801
2802	static struct clk_branch gcc_ufs_card_clkref_clk = {
2803	.halt_reg = 0x8c004,
2804	.halt_check = BRANCH_HALT,
2805	.clkr = {
2806	.enable_reg = 0x8c004,
2807	.enable_mask = BIT(0),
2808	.hw.init = &(struct clk_init_data){
2809	.name = "gcc_ufs_card_clkref_clk",
2810	.ops = &clk_branch2_ops,
2811	},
2812	},
2813	};
2814
2815	static struct clk_branch gcc_ufs_card_ice_core_clk = {
2816	.halt_reg = 0x7505c,
2817	.halt_check = BRANCH_HALT,
2818	.hwcg_reg = 0x7505c,
2819	.hwcg_bit = 1,
2820	.clkr = {
2821	.enable_reg = 0x7505c,
2822	.enable_mask = BIT(0),
2823	.hw.init = &(struct clk_init_data){
2824	.name = "gcc_ufs_card_ice_core_clk",
2825	.parent_hws = (const struct clk_hw *[]){
2826	&gcc_ufs_card_ice_core_clk_src.clkr.hw },
2827	.num_parents = 1,
2828	.flags = CLK_SET_RATE_PARENT,
2829	.ops = &clk_branch2_ops,
2830	},
2831	},
2832	};
2833
2834	static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2835	.halt_reg = 0x7505c,
2836	.halt_check = BRANCH_HALT,
2837	.hwcg_reg = 0x7505c,
2838	.hwcg_bit = 1,
2839	.clkr = {
2840	.enable_reg = 0x7505c,
2841	.enable_mask = BIT(1),
2842	.hw.init = &(struct clk_init_data){
2843	.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2844	.parent_hws = (const struct clk_hw *[]){
2845	&gcc_ufs_card_ice_core_clk.clkr.hw },
2846	.num_parents = 1,
2847	.flags = CLK_SET_RATE_PARENT,
2848	.ops = &clk_branch_simple_ops,
2849	},
2850	},
2851	};
2852
2853	static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2854	.halt_reg = 0x75090,
2855	.halt_check = BRANCH_HALT,
2856	.hwcg_reg = 0x75090,
2857	.hwcg_bit = 1,
2858	.clkr = {
2859	.enable_reg = 0x75090,
2860	.enable_mask = BIT(0),
2861	.hw.init = &(struct clk_init_data){
2862	.name = "gcc_ufs_card_phy_aux_clk",
2863	.parent_hws = (const struct clk_hw *[]){
2864	&gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2865	.num_parents = 1,
2866	.flags = CLK_SET_RATE_PARENT,
2867	.ops = &clk_branch2_ops,
2868	},
2869	},
2870	};
2871
2872	static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2873	.halt_reg = 0x75090,
2874	.halt_check = BRANCH_HALT,
2875	.hwcg_reg = 0x75090,
2876	.hwcg_bit = 1,
2877	.clkr = {
2878	.enable_reg = 0x75090,
2879	.enable_mask = BIT(1),
2880	.hw.init = &(struct clk_init_data){
2881	.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2882	.parent_hws = (const struct clk_hw *[]){
2883	&gcc_ufs_card_phy_aux_clk.clkr.hw },
2884	.num_parents = 1,
2885	.flags = CLK_SET_RATE_PARENT,
2886	.ops = &clk_branch_simple_ops,
2887	},
2888	},
2889	};
2890
2891	/* external clocks so add BRANCH_HALT_SKIP */
2892	static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2893	.halt_check = BRANCH_HALT_SKIP,
2894	.clkr = {
2895	.enable_reg = 0x7501c,
2896	.enable_mask = BIT(0),
2897	.hw.init = &(struct clk_init_data){
2898	.name = "gcc_ufs_card_rx_symbol_0_clk",
2899	.ops = &clk_branch2_ops,
2900	},
2901	},
2902	};
2903
2904	/* external clocks so add BRANCH_HALT_SKIP */
2905	static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2906	.halt_check = BRANCH_HALT_SKIP,
2907	.clkr = {
2908	.enable_reg = 0x750ac,
2909	.enable_mask = BIT(0),
2910	.hw.init = &(struct clk_init_data){
2911	.name = "gcc_ufs_card_rx_symbol_1_clk",
2912	.ops = &clk_branch2_ops,
2913	},
2914	},
2915	};
2916
2917	/* external clocks so add BRANCH_HALT_SKIP */
2918	static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2919	.halt_check = BRANCH_HALT_SKIP,
2920	.clkr = {
2921	.enable_reg = 0x75018,
2922	.enable_mask = BIT(0),
2923	.hw.init = &(struct clk_init_data){
2924	.name = "gcc_ufs_card_tx_symbol_0_clk",
2925	.ops = &clk_branch2_ops,
2926	},
2927	},
2928	};
2929
2930	static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2931	.halt_reg = 0x75058,
2932	.halt_check = BRANCH_HALT,
2933	.hwcg_reg = 0x75058,
2934	.hwcg_bit = 1,
2935	.clkr = {
2936	.enable_reg = 0x75058,
2937	.enable_mask = BIT(0),
2938	.hw.init = &(struct clk_init_data){
2939	.name = "gcc_ufs_card_unipro_core_clk",
2940	.parent_hws = (const struct clk_hw *[]){
2941	&gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2942	.num_parents = 1,
2943	.flags = CLK_SET_RATE_PARENT,
2944	.ops = &clk_branch2_ops,
2945	},
2946	},
2947	};
2948
2949	static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2950	.halt_reg = 0x75058,
2951	.halt_check = BRANCH_HALT,
2952	.hwcg_reg = 0x75058,
2953	.hwcg_bit = 1,
2954	.clkr = {
2955	.enable_reg = 0x75058,
2956	.enable_mask = BIT(1),
2957	.hw.init = &(struct clk_init_data){
2958	.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2959	.parent_hws = (const struct clk_hw *[]){
2960	&gcc_ufs_card_unipro_core_clk.clkr.hw },
2961	.num_parents = 1,
2962	.flags = CLK_SET_RATE_PARENT,
2963	.ops = &clk_branch_simple_ops,
2964	},
2965	},
2966	};
2967
2968	static struct clk_branch gcc_ufs_mem_clkref_clk = {
2969	.halt_reg = 0x8c000,
2970	.halt_check = BRANCH_HALT,
2971	.clkr = {
2972	.enable_reg = 0x8c000,
2973	.enable_mask = BIT(0),
2974	.hw.init = &(struct clk_init_data){
2975	.name = "gcc_ufs_mem_clkref_clk",
2976	.ops = &clk_branch2_ops,
2977	},
2978	},
2979	};
2980
2981	static struct clk_branch gcc_ufs_phy_ahb_clk = {
2982	.halt_reg = 0x77014,
2983	.halt_check = BRANCH_HALT,
2984	.hwcg_reg = 0x77014,
2985	.hwcg_bit = 1,
2986	.clkr = {
2987	.enable_reg = 0x77014,
2988	.enable_mask = BIT(0),
2989	.hw.init = &(struct clk_init_data){
2990	.name = "gcc_ufs_phy_ahb_clk",
2991	.ops = &clk_branch2_ops,
2992	},
2993	},
2994	};
2995
2996	static struct clk_branch gcc_ufs_phy_axi_clk = {
2997	.halt_reg = 0x77010,
2998	.halt_check = BRANCH_HALT,
2999	.hwcg_reg = 0x77010,
3000	.hwcg_bit = 1,
3001	.clkr = {
3002	.enable_reg = 0x77010,
3003	.enable_mask = BIT(0),
3004	.hw.init = &(struct clk_init_data){
3005	.name = "gcc_ufs_phy_axi_clk",
3006	.parent_hws = (const struct clk_hw *[]){
3007	&gcc_ufs_phy_axi_clk_src.clkr.hw },
3008	.num_parents = 1,
3009	.flags = CLK_SET_RATE_PARENT,
3010	.ops = &clk_branch2_ops,
3011	},
3012	},
3013	};
3014
3015	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3016	.halt_reg = 0x77010,
3017	.halt_check = BRANCH_HALT,
3018	.hwcg_reg = 0x77010,
3019	.hwcg_bit = 1,
3020	.clkr = {
3021	.enable_reg = 0x77010,
3022	.enable_mask = BIT(1),
3023	.hw.init = &(struct clk_init_data){
3024	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3025	.parent_hws = (const struct clk_hw *[]){
3026	&gcc_ufs_phy_axi_clk.clkr.hw },
3027	.num_parents = 1,
3028	.flags = CLK_SET_RATE_PARENT,
3029	.ops = &clk_branch_simple_ops,
3030	},
3031	},
3032	};
3033
3034	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3035	.halt_reg = 0x7705c,
3036	.halt_check = BRANCH_HALT,
3037	.hwcg_reg = 0x7705c,
3038	.hwcg_bit = 1,
3039	.clkr = {
3040	.enable_reg = 0x7705c,
3041	.enable_mask = BIT(0),
3042	.hw.init = &(struct clk_init_data){
3043	.name = "gcc_ufs_phy_ice_core_clk",
3044	.parent_hws = (const struct clk_hw *[]){
3045	&gcc_ufs_phy_ice_core_clk_src.clkr.hw },
3046	.num_parents = 1,
3047	.flags = CLK_SET_RATE_PARENT,
3048	.ops = &clk_branch2_ops,
3049	},
3050	},
3051	};
3052
3053	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3054	.halt_reg = 0x7705c,
3055	.halt_check = BRANCH_HALT,
3056	.hwcg_reg = 0x7705c,
3057	.hwcg_bit = 1,
3058	.clkr = {
3059	.enable_reg = 0x7705c,
3060	.enable_mask = BIT(1),
3061	.hw.init = &(struct clk_init_data){
3062	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3063	.parent_hws = (const struct clk_hw *[]){
3064	&gcc_ufs_phy_ice_core_clk.clkr.hw },
3065	.num_parents = 1,
3066	.flags = CLK_SET_RATE_PARENT,
3067	.ops = &clk_branch_simple_ops,
3068	},
3069	},
3070	};
3071
3072	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3073	.halt_reg = 0x77090,
3074	.halt_check = BRANCH_HALT,
3075	.hwcg_reg = 0x77090,
3076	.hwcg_bit = 1,
3077	.clkr = {
3078	.enable_reg = 0x77090,
3079	.enable_mask = BIT(0),
3080	.hw.init = &(struct clk_init_data){
3081	.name = "gcc_ufs_phy_phy_aux_clk",
3082	.parent_hws = (const struct clk_hw *[]){
3083	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
3084	.num_parents = 1,
3085	.flags = CLK_SET_RATE_PARENT,
3086	.ops = &clk_branch2_ops,
3087	},
3088	},
3089	};
3090
3091	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3092	.halt_reg = 0x77090,
3093	.halt_check = BRANCH_HALT,
3094	.hwcg_reg = 0x77090,
3095	.hwcg_bit = 1,
3096	.clkr = {
3097	.enable_reg = 0x77090,
3098	.enable_mask = BIT(1),
3099	.hw.init = &(struct clk_init_data){
3100	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3101	.parent_hws = (const struct clk_hw *[]){
3102	&gcc_ufs_phy_phy_aux_clk.clkr.hw },
3103	.num_parents = 1,
3104	.flags = CLK_SET_RATE_PARENT,
3105	.ops = &clk_branch_simple_ops,
3106	},
3107	},
3108	};
3109
3110	/* external clocks so add BRANCH_HALT_SKIP */
3111	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3112	.halt_check = BRANCH_HALT_SKIP,
3113	.clkr = {
3114	.enable_reg = 0x7701c,
3115	.enable_mask = BIT(0),
3116	.hw.init = &(struct clk_init_data){
3117	.name = "gcc_ufs_phy_rx_symbol_0_clk",
3118	.ops = &clk_branch2_ops,
3119	},
3120	},
3121	};
3122
3123	/* external clocks so add BRANCH_HALT_SKIP */
3124	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3125	.halt_check = BRANCH_HALT_SKIP,
3126	.clkr = {
3127	.enable_reg = 0x770ac,
3128	.enable_mask = BIT(0),
3129	.hw.init = &(struct clk_init_data){
3130	.name = "gcc_ufs_phy_rx_symbol_1_clk",
3131	.ops = &clk_branch2_ops,
3132	},
3133	},
3134	};
3135
3136	/* external clocks so add BRANCH_HALT_SKIP */
3137	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3138	.halt_check = BRANCH_HALT_SKIP,
3139	.clkr = {
3140	.enable_reg = 0x77018,
3141	.enable_mask = BIT(0),
3142	.hw.init = &(struct clk_init_data){
3143	.name = "gcc_ufs_phy_tx_symbol_0_clk",
3144	.ops = &clk_branch2_ops,
3145	},
3146	},
3147	};
3148
3149	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3150	.halt_reg = 0x77058,
3151	.halt_check = BRANCH_HALT,
3152	.hwcg_reg = 0x77058,
3153	.hwcg_bit = 1,
3154	.clkr = {
3155	.enable_reg = 0x77058,
3156	.enable_mask = BIT(0),
3157	.hw.init = &(struct clk_init_data){
3158	.name = "gcc_ufs_phy_unipro_core_clk",
3159	.parent_hws = (const struct clk_hw *[]){
3160	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3161	.num_parents = 1,
3162	.flags = CLK_SET_RATE_PARENT,
3163	.ops = &clk_branch2_ops,
3164	},
3165	},
3166	};
3167
3168	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3169	.halt_reg = 0x77058,
3170	.halt_check = BRANCH_HALT,
3171	.hwcg_reg = 0x77058,
3172	.hwcg_bit = 1,
3173	.clkr = {
3174	.enable_reg = 0x77058,
3175	.enable_mask = BIT(1),
3176	.hw.init = &(struct clk_init_data){
3177	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3178	.parent_hws = (const struct clk_hw *[]){
3179	&gcc_ufs_phy_unipro_core_clk.clkr.hw },
3180	.num_parents = 1,
3181	.flags = CLK_SET_RATE_PARENT,
3182	.ops = &clk_branch_simple_ops,
3183	},
3184	},
3185	};
3186
3187	static struct clk_branch gcc_usb30_prim_master_clk = {
3188	.halt_reg = 0xf010,
3189	.halt_check = BRANCH_HALT,
3190	.clkr = {
3191	.enable_reg = 0xf010,
3192	.enable_mask = BIT(0),
3193	.hw.init = &(struct clk_init_data){
3194	.name = "gcc_usb30_prim_master_clk",
3195	.parent_hws = (const struct clk_hw *[]){
3196	&gcc_usb30_prim_master_clk_src.clkr.hw },
3197	.num_parents = 1,
3198	.flags = CLK_SET_RATE_PARENT,
3199	.ops = &clk_branch2_ops,
3200	},
3201	},
3202	};
3203
3204	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3205	.halt_reg = 0xf018,
3206	.halt_check = BRANCH_HALT,
3207	.clkr = {
3208	.enable_reg = 0xf018,
3209	.enable_mask = BIT(0),
3210	.hw.init = &(struct clk_init_data){
3211	.name = "gcc_usb30_prim_mock_utmi_clk",
3212	.parent_hws = (const struct clk_hw *[]){
3213	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3214	.num_parents = 1,
3215	.flags = CLK_SET_RATE_PARENT,
3216	.ops = &clk_branch2_ops,
3217	},
3218	},
3219	};
3220
3221	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3222	.halt_reg = 0xf014,
3223	.halt_check = BRANCH_HALT,
3224	.clkr = {
3225	.enable_reg = 0xf014,
3226	.enable_mask = BIT(0),
3227	.hw.init = &(struct clk_init_data){
3228	.name = "gcc_usb30_prim_sleep_clk",
3229	.ops = &clk_branch2_ops,
3230	},
3231	},
3232	};
3233
3234	static struct clk_branch gcc_usb30_sec_master_clk = {
3235	.halt_reg = 0x10010,
3236	.halt_check = BRANCH_HALT,
3237	.clkr = {
3238	.enable_reg = 0x10010,
3239	.enable_mask = BIT(0),
3240	.hw.init = &(struct clk_init_data){
3241	.name = "gcc_usb30_sec_master_clk",
3242	.parent_hws = (const struct clk_hw *[]){
3243	&gcc_usb30_sec_master_clk_src.clkr.hw },
3244	.num_parents = 1,
3245	.flags = CLK_SET_RATE_PARENT,
3246	.ops = &clk_branch2_ops,
3247	},
3248	},
3249	};
3250
3251	static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3252	.halt_reg = 0x10018,
3253	.halt_check = BRANCH_HALT,
3254	.clkr = {
3255	.enable_reg = 0x10018,
3256	.enable_mask = BIT(0),
3257	.hw.init = &(struct clk_init_data){
3258	.name = "gcc_usb30_sec_mock_utmi_clk",
3259	.parent_hws = (const struct clk_hw *[]){
3260	&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3261	.num_parents = 1,
3262	.flags = CLK_SET_RATE_PARENT,
3263	.ops = &clk_branch2_ops,
3264	},
3265	},
3266	};
3267
3268	static struct clk_branch gcc_usb30_sec_sleep_clk = {
3269	.halt_reg = 0x10014,
3270	.halt_check = BRANCH_HALT,
3271	.clkr = {
3272	.enable_reg = 0x10014,
3273	.enable_mask = BIT(0),
3274	.hw.init = &(struct clk_init_data){
3275	.name = "gcc_usb30_sec_sleep_clk",
3276	.ops = &clk_branch2_ops,
3277	},
3278	},
3279	};
3280
3281	static struct clk_branch gcc_usb3_prim_clkref_clk = {
3282	.halt_reg = 0x8c008,
3283	.halt_check = BRANCH_HALT,
3284	.clkr = {
3285	.enable_reg = 0x8c008,
3286	.enable_mask = BIT(0),
3287	.hw.init = &(struct clk_init_data){
3288	.name = "gcc_usb3_prim_clkref_clk",
3289	.ops = &clk_branch2_ops,
3290	},
3291	},
3292	};
3293
3294	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3295	.halt_reg = 0xf050,
3296	.halt_check = BRANCH_HALT,
3297	.clkr = {
3298	.enable_reg = 0xf050,
3299	.enable_mask = BIT(0),
3300	.hw.init = &(struct clk_init_data){
3301	.name = "gcc_usb3_prim_phy_aux_clk",
3302	.parent_hws = (const struct clk_hw *[]){
3303	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3304	.num_parents = 1,
3305	.flags = CLK_SET_RATE_PARENT,
3306	.ops = &clk_branch2_ops,
3307	},
3308	},
3309	};
3310
3311	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3312	.halt_reg = 0xf054,
3313	.halt_check = BRANCH_HALT,
3314	.clkr = {
3315	.enable_reg = 0xf054,
3316	.enable_mask = BIT(0),
3317	.hw.init = &(struct clk_init_data){
3318	.name = "gcc_usb3_prim_phy_com_aux_clk",
3319	.parent_hws = (const struct clk_hw *[]){
3320	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3321	.num_parents = 1,
3322	.flags = CLK_SET_RATE_PARENT,
3323	.ops = &clk_branch2_ops,
3324	},
3325	},
3326	};
3327
3328	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3329	.halt_check = BRANCH_HALT_SKIP,
3330	.clkr = {
3331	.enable_reg = 0xf058,
3332	.enable_mask = BIT(0),
3333	.hw.init = &(struct clk_init_data){
3334	.name = "gcc_usb3_prim_phy_pipe_clk",
3335	.ops = &clk_branch2_ops,
3336	},
3337	},
3338	};
3339
3340	static struct clk_branch gcc_usb3_sec_clkref_clk = {
3341	.halt_reg = 0x8c028,
3342	.halt_check = BRANCH_HALT,
3343	.clkr = {
3344	.enable_reg = 0x8c028,
3345	.enable_mask = BIT(0),
3346	.hw.init = &(struct clk_init_data){
3347	.name = "gcc_usb3_sec_clkref_clk",
3348	.ops = &clk_branch2_ops,
3349	},
3350	},
3351	};
3352
3353	static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3354	.halt_reg = 0x10050,
3355	.halt_check = BRANCH_HALT,
3356	.clkr = {
3357	.enable_reg = 0x10050,
3358	.enable_mask = BIT(0),
3359	.hw.init = &(struct clk_init_data){
3360	.name = "gcc_usb3_sec_phy_aux_clk",
3361	.parent_hws = (const struct clk_hw *[]){
3362	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3363	.num_parents = 1,
3364	.flags = CLK_SET_RATE_PARENT,
3365	.ops = &clk_branch2_ops,
3366	},
3367	},
3368	};
3369
3370	static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3371	.halt_reg = 0x10054,
3372	.halt_check = BRANCH_HALT,
3373	.clkr = {
3374	.enable_reg = 0x10054,
3375	.enable_mask = BIT(0),
3376	.hw.init = &(struct clk_init_data){
3377	.name = "gcc_usb3_sec_phy_com_aux_clk",
3378	.parent_hws = (const struct clk_hw *[]){
3379	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3380	.num_parents = 1,
3381	.flags = CLK_SET_RATE_PARENT,
3382	.ops = &clk_branch2_ops,
3383	},
3384	},
3385	};
3386
3387	static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3388	.halt_check = BRANCH_HALT_SKIP,
3389	.clkr = {
3390	.enable_reg = 0x10058,
3391	.enable_mask = BIT(0),
3392	.hw.init = &(struct clk_init_data){
3393	.name = "gcc_usb3_sec_phy_pipe_clk",
3394	.ops = &clk_branch2_ops,
3395	},
3396	},
3397	};
3398
3399	/*
3400	* Clock ON depends on external parent 'config noc', so cant poll
3401	* delay and also mark as crtitical for video boot
3402	*/
3403	static struct clk_branch gcc_video_ahb_clk = {
3404	.halt_reg = 0xb004,
3405	.halt_check = BRANCH_HALT_DELAY,
3406	.hwcg_reg = 0xb004,
3407	.hwcg_bit = 1,
3408	.clkr = {
3409	.enable_reg = 0xb004,
3410	.enable_mask = BIT(0),
3411	.hw.init = &(struct clk_init_data){
3412	.name = "gcc_video_ahb_clk",
3413	.flags = CLK_IS_CRITICAL,
3414	.ops = &clk_branch2_ops,
3415	},
3416	},
3417	};
3418
3419	static struct clk_branch gcc_video_axi0_clk = {
3420	.halt_reg = 0xb024,
3421	.halt_check = BRANCH_HALT,
3422	.clkr = {
3423	.enable_reg = 0xb024,
3424	.enable_mask = BIT(0),
3425	.hw.init = &(struct clk_init_data){
3426	.name = "gcc_video_axi0_clk",
3427	.ops = &clk_branch2_ops,
3428	},
3429	},
3430	};
3431
3432	static struct clk_branch gcc_video_axi1_clk = {
3433	.halt_reg = 0xb028,
3434	.halt_check = BRANCH_HALT,
3435	.clkr = {
3436	.enable_reg = 0xb028,
3437	.enable_mask = BIT(0),
3438	.hw.init = &(struct clk_init_data){
3439	.name = "gcc_video_axi1_clk",
3440	.ops = &clk_branch2_ops,
3441	},
3442	},
3443	};
3444
3445	static struct clk_branch gcc_video_axic_clk = {
3446	.halt_reg = 0xb02c,
3447	.halt_check = BRANCH_HALT,
3448	.clkr = {
3449	.enable_reg = 0xb02c,
3450	.enable_mask = BIT(0),
3451	.hw.init = &(struct clk_init_data){
3452	.name = "gcc_video_axic_clk",
3453	.ops = &clk_branch2_ops,
3454	},
3455	},
3456	};
3457
3458	/* XO critical input to video, so no need to poll */
3459	static struct clk_branch gcc_video_xo_clk = {
3460	.halt_reg = 0xb040,
3461	.halt_check = BRANCH_HALT_DELAY,
3462	.clkr = {
3463	.enable_reg = 0xb040,
3464	.enable_mask = BIT(0),
3465	.hw.init = &(struct clk_init_data){
3466	.name = "gcc_video_xo_clk",
3467	.flags = CLK_IS_CRITICAL,
3468	.ops = &clk_branch2_ops,
3469	},
3470	},
3471	};
3472
3473	static struct gdsc pcie_0_gdsc = {
3474	.gdscr = 0x6b004,
3475	.pd = {
3476	.name = "pcie_0_gdsc",
3477	},
3478	.pwrsts = PWRSTS_OFF_ON,
3479	.flags = POLL_CFG_GDSCR,
3480	};
3481
3482	static struct gdsc pcie_1_gdsc = {
3483	.gdscr = 0x8d004,
3484	.pd = {
3485	.name = "pcie_1_gdsc",
3486	},
3487	.pwrsts = PWRSTS_OFF_ON,
3488	.flags = POLL_CFG_GDSCR,
3489	};
3490
3491	static struct gdsc ufs_card_gdsc = {
3492	.gdscr = 0x75004,
3493	.pd = {
3494	.name = "ufs_card_gdsc",
3495	},
3496	.pwrsts = PWRSTS_OFF_ON,
3497	.flags = POLL_CFG_GDSCR,
3498	};
3499
3500	static struct gdsc ufs_phy_gdsc = {
3501	.gdscr = 0x77004,
3502	.pd = {
3503	.name = "ufs_phy_gdsc",
3504	},
3505	.pwrsts = PWRSTS_OFF_ON,
3506	.flags = POLL_CFG_GDSCR,
3507	};
3508
3509	static struct gdsc emac_gdsc = {
3510	.gdscr = 0x6004,
3511	.pd = {
3512	.name = "emac_gdsc",
3513	},
3514	.pwrsts = PWRSTS_OFF_ON,
3515	.flags = POLL_CFG_GDSCR,
3516	};
3517
3518	static struct gdsc usb30_prim_gdsc = {
3519	.gdscr = 0xf004,
3520	.pd = {
3521	.name = "usb30_prim_gdsc",
3522	},
3523	.pwrsts = PWRSTS_OFF_ON,
3524	.flags = POLL_CFG_GDSCR,
3525	};
3526
3527	static struct gdsc usb30_sec_gdsc = {
3528	.gdscr = 0x10004,
3529	.pd = {
3530	.name = "usb30_sec_gdsc",
3531	},
3532	.pwrsts = PWRSTS_OFF_ON,
3533	.flags = POLL_CFG_GDSCR,
3534	};
3535
3536	static struct clk_regmap *gcc_sm8150_clocks[] = {
3537	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3538	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3539	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3540	&gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3541	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3542	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3543	&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3544	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3545	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3546	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3547	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3548	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3549	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3550	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3551	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3552	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3553	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3554	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3555	[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3556	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3557	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3558	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3559	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3560	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3561	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3562	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3563	[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3564	[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3565	[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3566	[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3567	[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3568	[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3569	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3570	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3571	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3572	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3573	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3574	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3575	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3576	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3577	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3578	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3579	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3580	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3581	[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3582	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3583	[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3584	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
3585	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
3586	[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3587	[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3588	[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3589	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3590	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3591	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3592	[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3593	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3594	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3595	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3596	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3597	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3598	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3599	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3600	[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3601	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3602	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3603	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3604	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3605	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3606	[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3607	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3608	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3609	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3610	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3611	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3612	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3613	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3614	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3615	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3616	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3617	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3618	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3619	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3620	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3621	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3622	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3623	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3624	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3625	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3626	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3627	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3628	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3629	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3630	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3631	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3632	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3633	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3634	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3635	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3636	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3637	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3638	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3639	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3640	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3641	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3642	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3643	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3644	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3645	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3646	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3647	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3648	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3649	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3650	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3651	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3652	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3653	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3654	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3655	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3656	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3657	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3658	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3659	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3660	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3661	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3662	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3663	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3664	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3665	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3666	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3667	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3668	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3669	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3670	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3671	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3672	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3673	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3674	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3675	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3676	[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3677	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3678	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3679	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3680	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3681	[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3682	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3683	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3684	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3685	&gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3686	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3687	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3688	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3689	&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3690	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3691	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3692	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3693	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3694	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3695	&gcc_ufs_card_unipro_core_clk_src.clkr,
3696	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3697	&gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3698	[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3699	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3700	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3701	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3702	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3703	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3704	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3705	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3706	&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3707	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3708	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3709	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3710	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3711	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3712	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3713	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3714	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3715	&gcc_ufs_phy_unipro_core_clk_src.clkr,
3716	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3717	&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3718	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3719	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3720	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3721	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3722	&gcc_usb30_prim_mock_utmi_clk_src.clkr,
3723	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3724	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3725	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3726	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3727	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3728	&gcc_usb30_sec_mock_utmi_clk_src.clkr,
3729	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3730	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3731	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3732	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3733	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3734	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3735	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3736	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3737	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3738	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3739	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3740	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3741	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3742	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3743	[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3744	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3745	[GPLL0] = &gpll0.clkr,
3746	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3747	[GPLL7] = &gpll7.clkr,
3748	[GPLL9] = &gpll9.clkr,
3749	};
3750
3751	static const struct qcom_reset_map gcc_sm8150_resets[] = {
3752	[GCC_EMAC_BCR] = { 0x6000 },
3753	[GCC_GPU_BCR] = { 0x71000 },
3754	[GCC_MMSS_BCR] = { 0xb000 },
3755	[GCC_NPU_BCR] = { 0x4d000 },
3756	[GCC_PCIE_0_BCR] = { 0x6b000 },
3757	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3758	[GCC_PCIE_1_BCR] = { 0x8d000 },
3759	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3760	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3761	[GCC_PDM_BCR] = { 0x33000 },
3762	[GCC_PRNG_BCR] = { 0x34000 },
3763	[GCC_QSPI_BCR] = { 0x24008 },
3764	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3765	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3766	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3767	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3768	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3769	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3770	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3771	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3772	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3773	[GCC_SDCC2_BCR] = { 0x14000 },
3774	[GCC_SDCC4_BCR] = { 0x16000 },
3775	[GCC_TSIF_BCR] = { 0x36000 },
3776	[GCC_UFS_CARD_BCR] = { 0x75000 },
3777	[GCC_UFS_PHY_BCR] = { 0x77000 },
3778	[GCC_USB30_PRIM_BCR] = { 0xf000 },
3779	[GCC_USB30_SEC_BCR] = { 0x10000 },
3780	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3781	[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
3782	[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
3783	[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
3784	};
3785
3786	static struct gdsc *gcc_sm8150_gdscs[] = {
3787	[EMAC_GDSC] = &emac_gdsc,
3788	[PCIE_0_GDSC] = &pcie_0_gdsc,
3789	[PCIE_1_GDSC] = &pcie_1_gdsc,
3790	[UFS_CARD_GDSC] = &ufs_card_gdsc,
3791	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3792	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3793	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
3794	};
3795
3796	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3797	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3798	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3799	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3800	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3801	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3802	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3803	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3804	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3805	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3806	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3807	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3808	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3809	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3810	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3811	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3812	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3813	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3814	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3815	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3816	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3817	};
3818
3819	static const struct regmap_config gcc_sm8150_regmap_config = {
3820	.reg_bits = 32,
3821	.reg_stride = 4,
3822	.val_bits = 32,
3823	.max_register = 0x9c040,
3824	.fast_io = true,
3825	};
3826
3827	static const struct qcom_cc_desc gcc_sm8150_desc = {
3828	.config = &gcc_sm8150_regmap_config,
3829	.clks = gcc_sm8150_clocks,
3830	.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3831	.resets = gcc_sm8150_resets,
3832	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3833	.gdscs = gcc_sm8150_gdscs,
3834	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
3835	};
3836
3837	static const struct of_device_id gcc_sm8150_match_table[] = {
3838	{ .compatible = "qcom,gcc-sm8150" },
3839	{ }
3840	};
3841	MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3842
3843	static int gcc_sm8150_probe(struct platform_device *pdev)
3844	{
3845	struct regmap *regmap;
3846	int ret;
3847
3848	regmap = qcom_cc_map(pdev, desc: &gcc_sm8150_desc);
3849	if (IS_ERR(ptr: regmap))
3850	return PTR_ERR(ptr: regmap);
3851
3852	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3853	regmap_update_bits(map: regmap, reg: 0x4d110, mask: 0x3, val: 0x3);
3854	regmap_update_bits(map: regmap, reg: 0x71028, mask: 0x3, val: 0x3);
3855
3856	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
3857	ARRAY_SIZE(gcc_dfs_clocks));
3858	if (ret)
3859	dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Failed to register with DFS!\n");
3860
3861	return qcom_cc_really_probe(pdev, desc: &gcc_sm8150_desc, regmap);
3862	}
3863
3864	static struct platform_driver gcc_sm8150_driver = {
3865	.probe = gcc_sm8150_probe,
3866	.driver = {
3867	.name = "gcc-sm8150",
3868	.of_match_table = gcc_sm8150_match_table,
3869	},
3870	};
3871
3872	static int __init gcc_sm8150_init(void)
3873	{
3874	return platform_driver_register(&gcc_sm8150_driver);
3875	}
3876	subsys_initcall(gcc_sm8150_init);
3877
3878	static void __exit gcc_sm8150_exit(void)
3879	{
3880	platform_driver_unregister(&gcc_sm8150_driver);
3881	}
3882	module_exit(gcc_sm8150_exit);
3883
3884	MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3885	MODULE_LICENSE("GPL v2");
3886