1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/clk-provider.h>
7	#include <linux/err.h>
8	#include <linux/kernel.h>
9	#include <linux/module.h>
10	#include <linux/of.h>
11	#include <linux/platform_device.h>
12	#include <linux/regmap.h>
13
14	#include <dt-bindings/clock/qcom,gcc-sm8250.h>
15
16	#include "clk-alpha-pll.h"
17	#include "clk-branch.h"
18	#include "clk-rcg.h"
19	#include "clk-regmap.h"
20	#include "clk-regmap-divider.h"
21	#include "common.h"
22	#include "gdsc.h"
23	#include "reset.h"
24
25	enum {
26	P_BI_TCXO,
27	P_AUD_REF_CLK,
28	P_GPLL0_OUT_EVEN,
29	P_GPLL0_OUT_MAIN,
30	P_GPLL4_OUT_MAIN,
31	P_GPLL9_OUT_MAIN,
32	P_SLEEP_CLK,
33	};
34
35	static struct clk_alpha_pll gpll0 = {
36	.offset = 0x0,
37	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
38	.clkr = {
39	.enable_reg = 0x52018,
40	.enable_mask = BIT(0),
41	.hw.init = &(struct clk_init_data){
42	.name = "gpll0",
43	.parent_data = &(const struct clk_parent_data){
44	.fw_name = "bi_tcxo",
45	},
46	.num_parents = 1,
47	.ops = &clk_alpha_pll_fixed_lucid_ops,
48	},
49	},
50	};
51
52	static const struct clk_div_table post_div_table_gpll0_out_even[] = {
53	{ 0x1, 2 },
54	{ }
55	};
56
57	static struct clk_alpha_pll_postdiv gpll0_out_even = {
58	.offset = 0x0,
59	.post_div_shift = 8,
60	.post_div_table = post_div_table_gpll0_out_even,
61	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
62	.width = 4,
63	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
64	.clkr.hw.init = &(struct clk_init_data){
65	.name = "gpll0_out_even",
66	.parent_hws = (const struct clk_hw*[]){
67	&gpll0.clkr.hw,
68	},
69	.num_parents = 1,
70	.ops = &clk_alpha_pll_postdiv_lucid_ops,
71	},
72	};
73
74	static struct clk_alpha_pll gpll4 = {
75	.offset = 0x76000,
76	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
77	.clkr = {
78	.enable_reg = 0x52018,
79	.enable_mask = BIT(4),
80	.hw.init = &(struct clk_init_data){
81	.name = "gpll4",
82	.parent_data = &(const struct clk_parent_data){
83	.fw_name = "bi_tcxo",
84	},
85	.num_parents = 1,
86	.ops = &clk_alpha_pll_fixed_lucid_ops,
87	},
88	},
89	};
90
91	static struct clk_alpha_pll gpll9 = {
92	.offset = 0x1c000,
93	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
94	.clkr = {
95	.enable_reg = 0x52018,
96	.enable_mask = BIT(9),
97	.hw.init = &(struct clk_init_data){
98	.name = "gpll9",
99	.parent_data = &(const struct clk_parent_data){
100	.fw_name = "bi_tcxo",
101	},
102	.num_parents = 1,
103	.ops = &clk_alpha_pll_fixed_lucid_ops,
104	},
105	},
106	};
107
108	static const struct parent_map gcc_parent_map_0[] = {
109	{ P_BI_TCXO, 0 },
110	{ P_GPLL0_OUT_MAIN, 1 },
111	{ P_GPLL0_OUT_EVEN, 6 },
112	};
113
114	static const struct clk_parent_data gcc_parent_data_0[] = {
115	{ .fw_name = "bi_tcxo" },
116	{ .hw = &gpll0.clkr.hw },
117	{ .hw = &gpll0_out_even.clkr.hw },
118	};
119
120	static const struct clk_parent_data gcc_parent_data_0_ao[] = {
121	{ .fw_name = "bi_tcxo_ao" },
122	{ .hw = &gpll0.clkr.hw },
123	{ .hw = &gpll0_out_even.clkr.hw },
124	};
125
126	static const struct parent_map gcc_parent_map_1[] = {
127	{ P_BI_TCXO, 0 },
128	{ P_GPLL0_OUT_MAIN, 1 },
129	{ P_SLEEP_CLK, 5 },
130	{ P_GPLL0_OUT_EVEN, 6 },
131	};
132
133	static const struct clk_parent_data gcc_parent_data_1[] = {
134	{ .fw_name = "bi_tcxo" },
135	{ .hw = &gpll0.clkr.hw },
136	{ .fw_name = "sleep_clk" },
137	{ .hw = &gpll0_out_even.clkr.hw },
138	};
139
140	static const struct parent_map gcc_parent_map_2[] = {
141	{ P_BI_TCXO, 0 },
142	{ P_SLEEP_CLK, 5 },
143	};
144
145	static const struct clk_parent_data gcc_parent_data_2[] = {
146	{ .fw_name = "bi_tcxo" },
147	{ .fw_name = "sleep_clk" },
148	};
149
150	static const struct parent_map gcc_parent_map_3[] = {
151	{ P_BI_TCXO, 0 },
152	};
153
154	static const struct clk_parent_data gcc_parent_data_3[] = {
155	{ .fw_name = "bi_tcxo" },
156	};
157
158	static const struct parent_map gcc_parent_map_4[] = {
159	{ P_BI_TCXO, 0 },
160	{ P_GPLL0_OUT_MAIN, 1 },
161	{ P_GPLL9_OUT_MAIN, 2 },
162	{ P_GPLL4_OUT_MAIN, 5 },
163	{ P_GPLL0_OUT_EVEN, 6 },
164	};
165
166	static const struct clk_parent_data gcc_parent_data_4[] = {
167	{ .fw_name = "bi_tcxo" },
168	{ .hw = &gpll0.clkr.hw },
169	{ .hw = &gpll9.clkr.hw },
170	{ .hw = &gpll4.clkr.hw },
171	{ .hw = &gpll0_out_even.clkr.hw },
172	};
173
174	static const struct parent_map gcc_parent_map_5[] = {
175	{ P_BI_TCXO, 0 },
176	{ P_GPLL0_OUT_MAIN, 1 },
177	{ P_AUD_REF_CLK, 2 },
178	{ P_GPLL0_OUT_EVEN, 6 },
179	};
180
181	static const struct clk_parent_data gcc_parent_data_5[] = {
182	{ .fw_name = "bi_tcxo" },
183	{ .hw = &gpll0.clkr.hw },
184	{ .fw_name = "aud_ref_clk" },
185	{ .hw = &gpll0_out_even.clkr.hw },
186	};
187
188	static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
189	F(19200000, P_BI_TCXO, 1, 0, 0),
190	{ }
191	};
192
193	static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
194	.cmd_rcgr = 0x48010,
195	.mnd_width = 0,
196	.hid_width = 5,
197	.parent_map = gcc_parent_map_0,
198	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
199	.clkr.hw.init = &(struct clk_init_data){
200	.name = "gcc_cpuss_ahb_clk_src",
201	.parent_data = gcc_parent_data_0_ao,
202	.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
203	.flags = CLK_SET_RATE_PARENT,
204	.ops = &clk_rcg2_ops,
205	},
206	};
207
208	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
209	F(19200000, P_BI_TCXO, 1, 0, 0),
210	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
211	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
212	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
213	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
214	{ }
215	};
216
217	static struct clk_rcg2 gcc_gp1_clk_src = {
218	.cmd_rcgr = 0x64004,
219	.mnd_width = 8,
220	.hid_width = 5,
221	.parent_map = gcc_parent_map_1,
222	.freq_tbl = ftbl_gcc_gp1_clk_src,
223	.clkr.hw.init = &(struct clk_init_data){
224	.name = "gcc_gp1_clk_src",
225	.parent_data = gcc_parent_data_1,
226	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
227	.ops = &clk_rcg2_ops,
228	},
229	};
230
231	static struct clk_rcg2 gcc_gp2_clk_src = {
232	.cmd_rcgr = 0x65004,
233	.mnd_width = 8,
234	.hid_width = 5,
235	.parent_map = gcc_parent_map_1,
236	.freq_tbl = ftbl_gcc_gp1_clk_src,
237	.clkr.hw.init = &(struct clk_init_data){
238	.name = "gcc_gp2_clk_src",
239	.parent_data = gcc_parent_data_1,
240	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
241	.ops = &clk_rcg2_ops,
242	},
243	};
244
245	static struct clk_rcg2 gcc_gp3_clk_src = {
246	.cmd_rcgr = 0x66004,
247	.mnd_width = 8,
248	.hid_width = 5,
249	.parent_map = gcc_parent_map_1,
250	.freq_tbl = ftbl_gcc_gp1_clk_src,
251	.clkr.hw.init = &(struct clk_init_data){
252	.name = "gcc_gp3_clk_src",
253	.parent_data = gcc_parent_data_1,
254	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
255	.ops = &clk_rcg2_ops,
256	},
257	};
258
259	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
260	F(9600000, P_BI_TCXO, 2, 0, 0),
261	F(19200000, P_BI_TCXO, 1, 0, 0),
262	{ }
263	};
264
265	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
266	.cmd_rcgr = 0x6b038,
267	.mnd_width = 16,
268	.hid_width = 5,
269	.parent_map = gcc_parent_map_2,
270	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
271	.clkr.hw.init = &(struct clk_init_data){
272	.name = "gcc_pcie_0_aux_clk_src",
273	.parent_data = gcc_parent_data_2,
274	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
275	.ops = &clk_rcg2_ops,
276	},
277	};
278
279	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
280	.cmd_rcgr = 0x8d038,
281	.mnd_width = 16,
282	.hid_width = 5,
283	.parent_map = gcc_parent_map_2,
284	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
285	.clkr.hw.init = &(struct clk_init_data){
286	.name = "gcc_pcie_1_aux_clk_src",
287	.parent_data = gcc_parent_data_2,
288	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
289	.ops = &clk_rcg2_ops,
290	},
291	};
292
293	static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
294	.cmd_rcgr = 0x6038,
295	.mnd_width = 16,
296	.hid_width = 5,
297	.parent_map = gcc_parent_map_2,
298	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
299	.clkr.hw.init = &(struct clk_init_data){
300	.name = "gcc_pcie_2_aux_clk_src",
301	.parent_data = gcc_parent_data_2,
302	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
303	.ops = &clk_rcg2_ops,
304	},
305	};
306
307	static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
308	F(19200000, P_BI_TCXO, 1, 0, 0),
309	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
310	{ }
311	};
312
313	static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
314	.cmd_rcgr = 0x6f014,
315	.mnd_width = 0,
316	.hid_width = 5,
317	.parent_map = gcc_parent_map_0,
318	.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
319	.clkr.hw.init = &(struct clk_init_data){
320	.name = "gcc_pcie_phy_refgen_clk_src",
321	.parent_data = gcc_parent_data_0_ao,
322	.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
323	.ops = &clk_rcg2_ops,
324	},
325	};
326
327	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
328	F(9600000, P_BI_TCXO, 2, 0, 0),
329	F(19200000, P_BI_TCXO, 1, 0, 0),
330	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
331	{ }
332	};
333
334	static struct clk_rcg2 gcc_pdm2_clk_src = {
335	.cmd_rcgr = 0x33010,
336	.mnd_width = 0,
337	.hid_width = 5,
338	.parent_map = gcc_parent_map_0,
339	.freq_tbl = ftbl_gcc_pdm2_clk_src,
340	.clkr.hw.init = &(struct clk_init_data){
341	.name = "gcc_pdm2_clk_src",
342	.parent_data = gcc_parent_data_0,
343	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
344	.ops = &clk_rcg2_ops,
345	},
346	};
347
348	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
349	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
350	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
351	F(19200000, P_BI_TCXO, 1, 0, 0),
352	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
353	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
354	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
355	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
356	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
357	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
358	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
359	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
360	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
361	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
362	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
363	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
364	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
365	{ }
366	};
367
368	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
369	.name = "gcc_qupv3_wrap0_s0_clk_src",
370	.parent_data = gcc_parent_data_0,
371	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
372	.ops = &clk_rcg2_ops,
373	};
374
375	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
376	.cmd_rcgr = 0x17010,
377	.mnd_width = 16,
378	.hid_width = 5,
379	.parent_map = gcc_parent_map_0,
380	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
381	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
382	};
383
384	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
385	.name = "gcc_qupv3_wrap0_s1_clk_src",
386	.parent_data = gcc_parent_data_0,
387	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
388	.ops = &clk_rcg2_ops,
389	};
390
391	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
392	.cmd_rcgr = 0x17140,
393	.mnd_width = 16,
394	.hid_width = 5,
395	.parent_map = gcc_parent_map_0,
396	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
397	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
398	};
399
400	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
401	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
402	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
403	F(19200000, P_BI_TCXO, 1, 0, 0),
404	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
405	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
406	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
407	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
408	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
409	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
410	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
411	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
412	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
413	{ }
414	};
415
416	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
417	.name = "gcc_qupv3_wrap0_s2_clk_src",
418	.parent_data = gcc_parent_data_0,
419	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
420	.ops = &clk_rcg2_ops,
421	};
422
423	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
424	.cmd_rcgr = 0x17270,
425	.mnd_width = 16,
426	.hid_width = 5,
427	.parent_map = gcc_parent_map_0,
428	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
429	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
430	};
431
432	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
433	.name = "gcc_qupv3_wrap0_s3_clk_src",
434	.parent_data = gcc_parent_data_0,
435	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
436	.ops = &clk_rcg2_ops,
437	};
438
439	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
440	.cmd_rcgr = 0x173a0,
441	.mnd_width = 16,
442	.hid_width = 5,
443	.parent_map = gcc_parent_map_0,
444	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
445	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
446	};
447
448	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
449	.name = "gcc_qupv3_wrap0_s4_clk_src",
450	.parent_data = gcc_parent_data_0,
451	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
452	.ops = &clk_rcg2_ops,
453	};
454
455	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
456	.cmd_rcgr = 0x174d0,
457	.mnd_width = 16,
458	.hid_width = 5,
459	.parent_map = gcc_parent_map_0,
460	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
461	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
462	};
463
464	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
465	.name = "gcc_qupv3_wrap0_s5_clk_src",
466	.parent_data = gcc_parent_data_0,
467	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
468	.ops = &clk_rcg2_ops,
469	};
470
471	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
472	.cmd_rcgr = 0x17600,
473	.mnd_width = 16,
474	.hid_width = 5,
475	.parent_map = gcc_parent_map_0,
476	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
477	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
478	};
479
480	static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
481	.name = "gcc_qupv3_wrap0_s6_clk_src",
482	.parent_data = gcc_parent_data_0,
483	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
484	.ops = &clk_rcg2_ops,
485	};
486
487	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
488	.cmd_rcgr = 0x17730,
489	.mnd_width = 16,
490	.hid_width = 5,
491	.parent_map = gcc_parent_map_0,
492	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
493	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
494	};
495
496	static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
497	.name = "gcc_qupv3_wrap0_s7_clk_src",
498	.parent_data = gcc_parent_data_0,
499	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
500	.ops = &clk_rcg2_ops,
501	};
502
503	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
504	.cmd_rcgr = 0x17860,
505	.mnd_width = 16,
506	.hid_width = 5,
507	.parent_map = gcc_parent_map_0,
508	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
509	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
510	};
511
512	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
513	.name = "gcc_qupv3_wrap1_s0_clk_src",
514	.parent_data = gcc_parent_data_0,
515	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
516	.ops = &clk_rcg2_ops,
517	};
518
519	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
520	.cmd_rcgr = 0x18010,
521	.mnd_width = 16,
522	.hid_width = 5,
523	.parent_map = gcc_parent_map_0,
524	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
525	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
526	};
527
528	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
529	.name = "gcc_qupv3_wrap1_s1_clk_src",
530	.parent_data = gcc_parent_data_0,
531	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
532	.ops = &clk_rcg2_ops,
533	};
534
535	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
536	.cmd_rcgr = 0x18140,
537	.mnd_width = 16,
538	.hid_width = 5,
539	.parent_map = gcc_parent_map_0,
540	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
541	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
542	};
543
544	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
545	.name = "gcc_qupv3_wrap1_s2_clk_src",
546	.parent_data = gcc_parent_data_0,
547	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
548	.ops = &clk_rcg2_ops,
549	};
550
551	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
552	.cmd_rcgr = 0x18270,
553	.mnd_width = 16,
554	.hid_width = 5,
555	.parent_map = gcc_parent_map_0,
556	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
557	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
558	};
559
560	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
561	.name = "gcc_qupv3_wrap1_s3_clk_src",
562	.parent_data = gcc_parent_data_0,
563	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
564	.ops = &clk_rcg2_ops,
565	};
566
567	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
568	.cmd_rcgr = 0x183a0,
569	.mnd_width = 16,
570	.hid_width = 5,
571	.parent_map = gcc_parent_map_0,
572	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
573	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
574	};
575
576	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
577	.name = "gcc_qupv3_wrap1_s4_clk_src",
578	.parent_data = gcc_parent_data_0,
579	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
580	.ops = &clk_rcg2_ops,
581	};
582
583	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
584	.cmd_rcgr = 0x184d0,
585	.mnd_width = 16,
586	.hid_width = 5,
587	.parent_map = gcc_parent_map_0,
588	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
589	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
590	};
591
592	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
593	.name = "gcc_qupv3_wrap1_s5_clk_src",
594	.parent_data = gcc_parent_data_0,
595	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
596	.ops = &clk_rcg2_ops,
597	};
598
599	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
600	.cmd_rcgr = 0x18600,
601	.mnd_width = 16,
602	.hid_width = 5,
603	.parent_map = gcc_parent_map_0,
604	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
605	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
606	};
607
608	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
609	.name = "gcc_qupv3_wrap2_s0_clk_src",
610	.parent_data = gcc_parent_data_0,
611	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
612	.ops = &clk_rcg2_ops,
613	};
614
615	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
616	.cmd_rcgr = 0x1e010,
617	.mnd_width = 16,
618	.hid_width = 5,
619	.parent_map = gcc_parent_map_0,
620	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
621	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
622	};
623
624	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
625	.name = "gcc_qupv3_wrap2_s1_clk_src",
626	.parent_data = gcc_parent_data_0,
627	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
628	.ops = &clk_rcg2_ops,
629	};
630
631	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
632	.cmd_rcgr = 0x1e140,
633	.mnd_width = 16,
634	.hid_width = 5,
635	.parent_map = gcc_parent_map_0,
636	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
637	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
638	};
639
640	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
641	.name = "gcc_qupv3_wrap2_s2_clk_src",
642	.parent_data = gcc_parent_data_0,
643	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
644	.ops = &clk_rcg2_ops,
645	};
646
647	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
648	.cmd_rcgr = 0x1e270,
649	.mnd_width = 16,
650	.hid_width = 5,
651	.parent_map = gcc_parent_map_0,
652	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
653	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
654	};
655
656	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
657	.name = "gcc_qupv3_wrap2_s3_clk_src",
658	.parent_data = gcc_parent_data_0,
659	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
660	.ops = &clk_rcg2_ops,
661	};
662
663	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
664	.cmd_rcgr = 0x1e3a0,
665	.mnd_width = 16,
666	.hid_width = 5,
667	.parent_map = gcc_parent_map_0,
668	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
669	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
670	};
671
672	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
673	.name = "gcc_qupv3_wrap2_s4_clk_src",
674	.parent_data = gcc_parent_data_0,
675	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
676	.ops = &clk_rcg2_ops,
677	};
678
679	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
680	.cmd_rcgr = 0x1e4d0,
681	.mnd_width = 16,
682	.hid_width = 5,
683	.parent_map = gcc_parent_map_0,
684	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
685	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
686	};
687
688	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
689	.name = "gcc_qupv3_wrap2_s5_clk_src",
690	.parent_data = gcc_parent_data_0,
691	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
692	.ops = &clk_rcg2_ops,
693	};
694
695	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
696	.cmd_rcgr = 0x1e600,
697	.mnd_width = 16,
698	.hid_width = 5,
699	.parent_map = gcc_parent_map_0,
700	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
701	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
702	};
703
704	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
705	F(400000, P_BI_TCXO, 12, 1, 4),
706	F(19200000, P_BI_TCXO, 1, 0, 0),
707	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
708	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
709	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
710	F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
711	{ }
712	};
713
714	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
715	.cmd_rcgr = 0x1400c,
716	.mnd_width = 8,
717	.hid_width = 5,
718	.parent_map = gcc_parent_map_4,
719	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
720	.clkr.hw.init = &(struct clk_init_data){
721	.name = "gcc_sdcc2_apps_clk_src",
722	.parent_data = gcc_parent_data_4,
723	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
724	.flags = CLK_OPS_PARENT_ENABLE,
725	.ops = &clk_rcg2_floor_ops,
726	},
727	};
728
729	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
730	F(400000, P_BI_TCXO, 12, 1, 4),
731	F(19200000, P_BI_TCXO, 1, 0, 0),
732	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
733	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
734	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
735	{ }
736	};
737
738	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
739	.cmd_rcgr = 0x1600c,
740	.mnd_width = 8,
741	.hid_width = 5,
742	.parent_map = gcc_parent_map_0,
743	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
744	.clkr.hw.init = &(struct clk_init_data){
745	.name = "gcc_sdcc4_apps_clk_src",
746	.parent_data = gcc_parent_data_0,
747	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
748	.ops = &clk_rcg2_floor_ops,
749	},
750	};
751
752	static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
753	F(105495, P_BI_TCXO, 2, 1, 91),
754	{ }
755	};
756
757	static struct clk_rcg2 gcc_tsif_ref_clk_src = {
758	.cmd_rcgr = 0x36010,
759	.mnd_width = 8,
760	.hid_width = 5,
761	.parent_map = gcc_parent_map_5,
762	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
763	.clkr.hw.init = &(struct clk_init_data){
764	.name = "gcc_tsif_ref_clk_src",
765	.parent_data = gcc_parent_data_5,
766	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
767	.ops = &clk_rcg2_ops,
768	},
769	};
770
771	static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
772	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
773	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
774	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
775	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
776	{ }
777	};
778
779	static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
780	.cmd_rcgr = 0x75024,
781	.mnd_width = 8,
782	.hid_width = 5,
783	.parent_map = gcc_parent_map_0,
784	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
785	.clkr.hw.init = &(struct clk_init_data){
786	.name = "gcc_ufs_card_axi_clk_src",
787	.parent_data = gcc_parent_data_0,
788	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
789	.ops = &clk_rcg2_ops,
790	},
791	};
792
793	static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
794	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
795	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
796	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
797	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
798	{ }
799	};
800
801	static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
802	.cmd_rcgr = 0x7506c,
803	.mnd_width = 0,
804	.hid_width = 5,
805	.parent_map = gcc_parent_map_0,
806	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
807	.clkr.hw.init = &(struct clk_init_data){
808	.name = "gcc_ufs_card_ice_core_clk_src",
809	.parent_data = gcc_parent_data_0,
810	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
811	.ops = &clk_rcg2_ops,
812	},
813	};
814
815	static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
816	F(19200000, P_BI_TCXO, 1, 0, 0),
817	{ }
818	};
819
820	static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
821	.cmd_rcgr = 0x750a0,
822	.mnd_width = 0,
823	.hid_width = 5,
824	.parent_map = gcc_parent_map_3,
825	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
826	.clkr.hw.init = &(struct clk_init_data){
827	.name = "gcc_ufs_card_phy_aux_clk_src",
828	.parent_data = gcc_parent_data_3,
829	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
830	.ops = &clk_rcg2_ops,
831	},
832	};
833
834	static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
835	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
836	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
837	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
838	{ }
839	};
840
841	static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
842	.cmd_rcgr = 0x75084,
843	.mnd_width = 0,
844	.hid_width = 5,
845	.parent_map = gcc_parent_map_0,
846	.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
847	.clkr.hw.init = &(struct clk_init_data){
848	.name = "gcc_ufs_card_unipro_core_clk_src",
849	.parent_data = gcc_parent_data_0,
850	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
851	.ops = &clk_rcg2_ops,
852	},
853	};
854
855	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
856	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
857	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
858	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
859	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
860	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
861	{ }
862	};
863
864	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
865	.cmd_rcgr = 0x77024,
866	.mnd_width = 8,
867	.hid_width = 5,
868	.parent_map = gcc_parent_map_0,
869	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
870	.clkr.hw.init = &(struct clk_init_data){
871	.name = "gcc_ufs_phy_axi_clk_src",
872	.parent_data = gcc_parent_data_0,
873	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
874	.ops = &clk_rcg2_ops,
875	},
876	};
877
878	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
879	.cmd_rcgr = 0x7706c,
880	.mnd_width = 0,
881	.hid_width = 5,
882	.parent_map = gcc_parent_map_0,
883	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
884	.clkr.hw.init = &(struct clk_init_data){
885	.name = "gcc_ufs_phy_ice_core_clk_src",
886	.parent_data = gcc_parent_data_0,
887	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888	.ops = &clk_rcg2_ops,
889	},
890	};
891
892	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
893	.cmd_rcgr = 0x770a0,
894	.mnd_width = 0,
895	.hid_width = 5,
896	.parent_map = gcc_parent_map_3,
897	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
898	.clkr.hw.init = &(struct clk_init_data){
899	.name = "gcc_ufs_phy_phy_aux_clk_src",
900	.parent_data = gcc_parent_data_3,
901	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
902	.ops = &clk_rcg2_ops,
903	},
904	};
905
906	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
907	.cmd_rcgr = 0x77084,
908	.mnd_width = 0,
909	.hid_width = 5,
910	.parent_map = gcc_parent_map_0,
911	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
912	.clkr.hw.init = &(struct clk_init_data){
913	.name = "gcc_ufs_phy_unipro_core_clk_src",
914	.parent_data = gcc_parent_data_0,
915	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
916	.ops = &clk_rcg2_ops,
917	},
918	};
919
920	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
921	F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
922	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
923	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
924	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
925	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
926	{ }
927	};
928
929	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
930	.cmd_rcgr = 0xf020,
931	.mnd_width = 8,
932	.hid_width = 5,
933	.parent_map = gcc_parent_map_0,
934	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
935	.clkr.hw.init = &(struct clk_init_data){
936	.name = "gcc_usb30_prim_master_clk_src",
937	.parent_data = gcc_parent_data_0,
938	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
939	.ops = &clk_rcg2_ops,
940	},
941	};
942
943	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
944	.cmd_rcgr = 0xf038,
945	.mnd_width = 0,
946	.hid_width = 5,
947	.parent_map = gcc_parent_map_0,
948	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
949	.clkr.hw.init = &(struct clk_init_data){
950	.name = "gcc_usb30_prim_mock_utmi_clk_src",
951	.parent_data = gcc_parent_data_0,
952	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
953	.ops = &clk_rcg2_ops,
954	},
955	};
956
957	static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
958	.cmd_rcgr = 0x10020,
959	.mnd_width = 8,
960	.hid_width = 5,
961	.parent_map = gcc_parent_map_0,
962	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
963	.clkr.hw.init = &(struct clk_init_data){
964	.name = "gcc_usb30_sec_master_clk_src",
965	.parent_data = gcc_parent_data_0,
966	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
967	.ops = &clk_rcg2_ops,
968	},
969	};
970
971	static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
972	.cmd_rcgr = 0x10038,
973	.mnd_width = 0,
974	.hid_width = 5,
975	.parent_map = gcc_parent_map_0,
976	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
977	.clkr.hw.init = &(struct clk_init_data){
978	.name = "gcc_usb30_sec_mock_utmi_clk_src",
979	.parent_data = gcc_parent_data_0,
980	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
981	.ops = &clk_rcg2_ops,
982	},
983	};
984
985	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
986	.cmd_rcgr = 0xf064,
987	.mnd_width = 0,
988	.hid_width = 5,
989	.parent_map = gcc_parent_map_2,
990	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
991	.clkr.hw.init = &(struct clk_init_data){
992	.name = "gcc_usb3_prim_phy_aux_clk_src",
993	.parent_data = gcc_parent_data_2,
994	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
995	.ops = &clk_rcg2_ops,
996	},
997	};
998
999	static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1000	.cmd_rcgr = 0x10064,
1001	.mnd_width = 0,
1002	.hid_width = 5,
1003	.parent_map = gcc_parent_map_2,
1004	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1005	.clkr.hw.init = &(struct clk_init_data){
1006	.name = "gcc_usb3_sec_phy_aux_clk_src",
1007	.parent_data = gcc_parent_data_2,
1008	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1009	.ops = &clk_rcg2_ops,
1010	},
1011	};
1012
1013	static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
1014	.reg = 0x48028,
1015	.shift = 0,
1016	.width = 4,
1017	.clkr.hw.init = &(struct clk_init_data) {
1018	.name = "gcc_cpuss_ahb_postdiv_clk_src",
1019	.parent_hws = (const struct clk_hw*[]){
1020	&gcc_cpuss_ahb_clk_src.clkr.hw,
1021	},
1022	.num_parents = 1,
1023	.flags = CLK_SET_RATE_PARENT,
1024	.ops = &clk_regmap_div_ro_ops,
1025	},
1026	};
1027
1028	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1029	.reg = 0xf050,
1030	.shift = 0,
1031	.width = 2,
1032	.clkr.hw.init = &(struct clk_init_data) {
1033	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1034	.parent_hws = (const struct clk_hw*[]){
1035	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1036	},
1037	.num_parents = 1,
1038	.flags = CLK_SET_RATE_PARENT,
1039	.ops = &clk_regmap_div_ro_ops,
1040	},
1041	};
1042
1043	static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1044	.reg = 0x10050,
1045	.shift = 0,
1046	.width = 2,
1047	.clkr.hw.init = &(struct clk_init_data) {
1048	.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1049	.parent_hws = (const struct clk_hw*[]){
1050	&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1051	},
1052	.num_parents = 1,
1053	.flags = CLK_SET_RATE_PARENT,
1054	.ops = &clk_regmap_div_ro_ops,
1055	},
1056	};
1057
1058	static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1059	.halt_reg = 0x9000c,
1060	.halt_check = BRANCH_HALT_VOTED,
1061	.clkr = {
1062	.enable_reg = 0x9000c,
1063	.enable_mask = BIT(0),
1064	.hw.init = &(struct clk_init_data){
1065	.name = "gcc_aggre_noc_pcie_tbu_clk",
1066	.ops = &clk_branch2_ops,
1067	},
1068	},
1069	};
1070
1071	static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1072	.halt_reg = 0x750cc,
1073	.halt_check = BRANCH_HALT_VOTED,
1074	.hwcg_reg = 0x750cc,
1075	.hwcg_bit = 1,
1076	.clkr = {
1077	.enable_reg = 0x750cc,
1078	.enable_mask = BIT(0),
1079	.hw.init = &(struct clk_init_data){
1080	.name = "gcc_aggre_ufs_card_axi_clk",
1081	.parent_hws = (const struct clk_hw*[]){
1082	&gcc_ufs_card_axi_clk_src.clkr.hw,
1083	},
1084	.num_parents = 1,
1085	.flags = CLK_SET_RATE_PARENT,
1086	.ops = &clk_branch2_ops,
1087	},
1088	},
1089	};
1090
1091	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1092	.halt_reg = 0x770cc,
1093	.halt_check = BRANCH_HALT_VOTED,
1094	.hwcg_reg = 0x770cc,
1095	.hwcg_bit = 1,
1096	.clkr = {
1097	.enable_reg = 0x770cc,
1098	.enable_mask = BIT(0),
1099	.hw.init = &(struct clk_init_data){
1100	.name = "gcc_aggre_ufs_phy_axi_clk",
1101	.parent_hws = (const struct clk_hw*[]){
1102	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1103	},
1104	.num_parents = 1,
1105	.flags = CLK_SET_RATE_PARENT,
1106	.ops = &clk_branch2_ops,
1107	},
1108	},
1109	};
1110
1111	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1112	.halt_reg = 0xf080,
1113	.halt_check = BRANCH_HALT_VOTED,
1114	.clkr = {
1115	.enable_reg = 0xf080,
1116	.enable_mask = BIT(0),
1117	.hw.init = &(struct clk_init_data){
1118	.name = "gcc_aggre_usb3_prim_axi_clk",
1119	.parent_hws = (const struct clk_hw*[]){
1120	&gcc_usb30_prim_master_clk_src.clkr.hw,
1121	},
1122	.num_parents = 1,
1123	.flags = CLK_SET_RATE_PARENT,
1124	.ops = &clk_branch2_ops,
1125	},
1126	},
1127	};
1128
1129	static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1130	.halt_reg = 0x10080,
1131	.halt_check = BRANCH_HALT_VOTED,
1132	.clkr = {
1133	.enable_reg = 0x10080,
1134	.enable_mask = BIT(0),
1135	.hw.init = &(struct clk_init_data){
1136	.name = "gcc_aggre_usb3_sec_axi_clk",
1137	.parent_hws = (const struct clk_hw*[]){
1138	&gcc_usb30_sec_master_clk_src.clkr.hw,
1139	},
1140	.num_parents = 1,
1141	.flags = CLK_SET_RATE_PARENT,
1142	.ops = &clk_branch2_ops,
1143	},
1144	},
1145	};
1146
1147	static struct clk_branch gcc_boot_rom_ahb_clk = {
1148	.halt_reg = 0x38004,
1149	.halt_check = BRANCH_HALT_VOTED,
1150	.hwcg_reg = 0x38004,
1151	.hwcg_bit = 1,
1152	.clkr = {
1153	.enable_reg = 0x52000,
1154	.enable_mask = BIT(10),
1155	.hw.init = &(struct clk_init_data){
1156	.name = "gcc_boot_rom_ahb_clk",
1157	.ops = &clk_branch2_ops,
1158	},
1159	},
1160	};
1161
1162	static struct clk_branch gcc_camera_hf_axi_clk = {
1163	.halt_reg = 0xb02c,
1164	.halt_check = BRANCH_HALT_VOTED,
1165	.clkr = {
1166	.enable_reg = 0xb02c,
1167	.enable_mask = BIT(0),
1168	.hw.init = &(struct clk_init_data){
1169	.name = "gcc_camera_hf_axi_clk",
1170	.ops = &clk_branch2_ops,
1171	},
1172	},
1173	};
1174
1175	static struct clk_branch gcc_camera_sf_axi_clk = {
1176	.halt_reg = 0xb030,
1177	.halt_check = BRANCH_HALT_VOTED,
1178	.clkr = {
1179	.enable_reg = 0xb030,
1180	.enable_mask = BIT(0),
1181	.hw.init = &(struct clk_init_data){
1182	.name = "gcc_camera_sf_axi_clk",
1183	.ops = &clk_branch2_ops,
1184	},
1185	},
1186	};
1187
1188	static struct clk_branch gcc_camera_xo_clk = {
1189	.halt_reg = 0xb040,
1190	.halt_check = BRANCH_HALT,
1191	.clkr = {
1192	.enable_reg = 0xb040,
1193	.enable_mask = BIT(0),
1194	.hw.init = &(struct clk_init_data){
1195	.name = "gcc_camera_xo_clk",
1196	.ops = &clk_branch2_ops,
1197	},
1198	},
1199	};
1200
1201	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1202	.halt_reg = 0xf07c,
1203	.halt_check = BRANCH_HALT_VOTED,
1204	.clkr = {
1205	.enable_reg = 0xf07c,
1206	.enable_mask = BIT(0),
1207	.hw.init = &(struct clk_init_data){
1208	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1209	.parent_hws = (const struct clk_hw*[]){
1210	&gcc_usb30_prim_master_clk_src.clkr.hw,
1211	},
1212	.num_parents = 1,
1213	.flags = CLK_SET_RATE_PARENT,
1214	.ops = &clk_branch2_ops,
1215	},
1216	},
1217	};
1218
1219	static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1220	.halt_reg = 0x1007c,
1221	.halt_check = BRANCH_HALT_VOTED,
1222	.clkr = {
1223	.enable_reg = 0x1007c,
1224	.enable_mask = BIT(0),
1225	.hw.init = &(struct clk_init_data){
1226	.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1227	.parent_hws = (const struct clk_hw*[]){
1228	&gcc_usb30_sec_master_clk_src.clkr.hw,
1229	},
1230	.num_parents = 1,
1231	.flags = CLK_SET_RATE_PARENT,
1232	.ops = &clk_branch2_ops,
1233	},
1234	},
1235	};
1236
1237	static struct clk_branch gcc_cpuss_ahb_clk = {
1238	.halt_reg = 0x48000,
1239	.halt_check = BRANCH_HALT_VOTED,
1240	.clkr = {
1241	.enable_reg = 0x52000,
1242	.enable_mask = BIT(21),
1243	.hw.init = &(struct clk_init_data){
1244	.name = "gcc_cpuss_ahb_clk",
1245	.parent_hws = (const struct clk_hw*[]){
1246	&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
1247	},
1248	.num_parents = 1,
1249	.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1250	.ops = &clk_branch2_ops,
1251	},
1252	},
1253	};
1254
1255	static struct clk_branch gcc_cpuss_rbcpr_clk = {
1256	.halt_reg = 0x48004,
1257	.halt_check = BRANCH_HALT,
1258	.clkr = {
1259	.enable_reg = 0x48004,
1260	.enable_mask = BIT(0),
1261	.hw.init = &(struct clk_init_data){
1262	.name = "gcc_cpuss_rbcpr_clk",
1263	.ops = &clk_branch2_ops,
1264	},
1265	},
1266	};
1267
1268	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1269	.halt_reg = 0x71154,
1270	.halt_check = BRANCH_HALT_VOTED,
1271	.clkr = {
1272	.enable_reg = 0x71154,
1273	.enable_mask = BIT(0),
1274	.hw.init = &(struct clk_init_data){
1275	.name = "gcc_ddrss_gpu_axi_clk",
1276	.ops = &clk_branch2_ops,
1277	},
1278	},
1279	};
1280
1281	static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1282	.halt_reg = 0x8d058,
1283	.halt_check = BRANCH_HALT_VOTED,
1284	.clkr = {
1285	.enable_reg = 0x8d058,
1286	.enable_mask = BIT(0),
1287	.hw.init = &(struct clk_init_data){
1288	.name = "gcc_ddrss_pcie_sf_tbu_clk",
1289	.ops = &clk_branch2_ops,
1290	},
1291	},
1292	};
1293
1294	static struct clk_branch gcc_disp_hf_axi_clk = {
1295	.halt_reg = 0xb034,
1296	.halt_check = BRANCH_HALT_VOTED,
1297	.clkr = {
1298	.enable_reg = 0xb034,
1299	.enable_mask = BIT(0),
1300	.hw.init = &(struct clk_init_data){
1301	.name = "gcc_disp_hf_axi_clk",
1302	.ops = &clk_branch2_ops,
1303	},
1304	},
1305	};
1306
1307	static struct clk_branch gcc_disp_sf_axi_clk = {
1308	.halt_reg = 0xb038,
1309	.halt_check = BRANCH_HALT_VOTED,
1310	.clkr = {
1311	.enable_reg = 0xb038,
1312	.enable_mask = BIT(0),
1313	.hw.init = &(struct clk_init_data){
1314	.name = "gcc_disp_sf_axi_clk",
1315	.ops = &clk_branch2_ops,
1316	},
1317	},
1318	};
1319
1320	static struct clk_branch gcc_disp_xo_clk = {
1321	.halt_reg = 0xb044,
1322	.halt_check = BRANCH_HALT,
1323	.clkr = {
1324	.enable_reg = 0xb044,
1325	.enable_mask = BIT(0),
1326	.hw.init = &(struct clk_init_data){
1327	.name = "gcc_disp_xo_clk",
1328	.ops = &clk_branch2_ops,
1329	},
1330	},
1331	};
1332
1333	static struct clk_branch gcc_gp1_clk = {
1334	.halt_reg = 0x64000,
1335	.halt_check = BRANCH_HALT,
1336	.clkr = {
1337	.enable_reg = 0x64000,
1338	.enable_mask = BIT(0),
1339	.hw.init = &(struct clk_init_data){
1340	.name = "gcc_gp1_clk",
1341	.parent_hws = (const struct clk_hw*[]){
1342	&gcc_gp1_clk_src.clkr.hw,
1343	},
1344	.num_parents = 1,
1345	.flags = CLK_SET_RATE_PARENT,
1346	.ops = &clk_branch2_ops,
1347	},
1348	},
1349	};
1350
1351	static struct clk_branch gcc_gp2_clk = {
1352	.halt_reg = 0x65000,
1353	.halt_check = BRANCH_HALT,
1354	.clkr = {
1355	.enable_reg = 0x65000,
1356	.enable_mask = BIT(0),
1357	.hw.init = &(struct clk_init_data){
1358	.name = "gcc_gp2_clk",
1359	.parent_hws = (const struct clk_hw*[]){
1360	&gcc_gp2_clk_src.clkr.hw,
1361	},
1362	.num_parents = 1,
1363	.flags = CLK_SET_RATE_PARENT,
1364	.ops = &clk_branch2_ops,
1365	},
1366	},
1367	};
1368
1369	static struct clk_branch gcc_gp3_clk = {
1370	.halt_reg = 0x66000,
1371	.halt_check = BRANCH_HALT,
1372	.clkr = {
1373	.enable_reg = 0x66000,
1374	.enable_mask = BIT(0),
1375	.hw.init = &(struct clk_init_data){
1376	.name = "gcc_gp3_clk",
1377	.parent_hws = (const struct clk_hw*[]){
1378	&gcc_gp3_clk_src.clkr.hw,
1379	},
1380	.num_parents = 1,
1381	.flags = CLK_SET_RATE_PARENT,
1382	.ops = &clk_branch2_ops,
1383	},
1384	},
1385	};
1386
1387	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1388	.halt_check = BRANCH_HALT_DELAY,
1389	.clkr = {
1390	.enable_reg = 0x52000,
1391	.enable_mask = BIT(15),
1392	.hw.init = &(struct clk_init_data){
1393	.name = "gcc_gpu_gpll0_clk_src",
1394	.parent_hws = (const struct clk_hw*[]){
1395	&gpll0.clkr.hw,
1396	},
1397	.num_parents = 1,
1398	.flags = CLK_SET_RATE_PARENT,
1399	.ops = &clk_branch2_ops,
1400	},
1401	},
1402	};
1403
1404	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1405	.halt_check = BRANCH_HALT_DELAY,
1406	.clkr = {
1407	.enable_reg = 0x52000,
1408	.enable_mask = BIT(16),
1409	.hw.init = &(struct clk_init_data){
1410	.name = "gcc_gpu_gpll0_div_clk_src",
1411	.parent_hws = (const struct clk_hw*[]){
1412	&gpll0_out_even.clkr.hw,
1413	},
1414	.num_parents = 1,
1415	.flags = CLK_SET_RATE_PARENT,
1416	.ops = &clk_branch2_ops,
1417	},
1418	},
1419	};
1420
1421	static struct clk_branch gcc_gpu_iref_en = {
1422	.halt_reg = 0x8c014,
1423	.halt_check = BRANCH_HALT,
1424	.clkr = {
1425	.enable_reg = 0x8c014,
1426	.enable_mask = BIT(0),
1427	.hw.init = &(struct clk_init_data){
1428	.name = "gcc_gpu_iref_en",
1429	.ops = &clk_branch2_ops,
1430	},
1431	},
1432	};
1433
1434	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1435	.halt_reg = 0x7100c,
1436	.halt_check = BRANCH_HALT_VOTED,
1437	.clkr = {
1438	.enable_reg = 0x7100c,
1439	.enable_mask = BIT(0),
1440	.hw.init = &(struct clk_init_data){
1441	.name = "gcc_gpu_memnoc_gfx_clk",
1442	.ops = &clk_branch2_ops,
1443	},
1444	},
1445	};
1446
1447	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1448	.halt_reg = 0x71018,
1449	.halt_check = BRANCH_HALT,
1450	.clkr = {
1451	.enable_reg = 0x71018,
1452	.enable_mask = BIT(0),
1453	.hw.init = &(struct clk_init_data){
1454	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1455	.ops = &clk_branch2_ops,
1456	},
1457	},
1458	};
1459
1460	static struct clk_branch gcc_npu_axi_clk = {
1461	.halt_reg = 0x4d008,
1462	.halt_check = BRANCH_HALT_VOTED,
1463	.clkr = {
1464	.enable_reg = 0x4d008,
1465	.enable_mask = BIT(0),
1466	.hw.init = &(struct clk_init_data){
1467	.name = "gcc_npu_axi_clk",
1468	.ops = &clk_branch2_ops,
1469	},
1470	},
1471	};
1472
1473	static struct clk_branch gcc_npu_bwmon_axi_clk = {
1474	.halt_reg = 0x73008,
1475	.halt_check = BRANCH_HALT_VOTED,
1476	.clkr = {
1477	.enable_reg = 0x73008,
1478	.enable_mask = BIT(0),
1479	.hw.init = &(struct clk_init_data){
1480	.name = "gcc_npu_bwmon_axi_clk",
1481	.ops = &clk_branch2_ops,
1482	},
1483	},
1484	};
1485
1486	static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = {
1487	.halt_reg = 0x73004,
1488	.halt_check = BRANCH_HALT,
1489	.clkr = {
1490	.enable_reg = 0x73004,
1491	.enable_mask = BIT(0),
1492	.hw.init = &(struct clk_init_data){
1493	.name = "gcc_npu_bwmon_cfg_ahb_clk",
1494	.ops = &clk_branch2_ops,
1495	},
1496	},
1497	};
1498
1499	static struct clk_branch gcc_npu_cfg_ahb_clk = {
1500	.halt_reg = 0x4d004,
1501	.halt_check = BRANCH_HALT,
1502	.hwcg_reg = 0x4d004,
1503	.hwcg_bit = 1,
1504	.clkr = {
1505	.enable_reg = 0x4d004,
1506	.enable_mask = BIT(0),
1507	.hw.init = &(struct clk_init_data){
1508	.name = "gcc_npu_cfg_ahb_clk",
1509	.ops = &clk_branch2_ops,
1510	},
1511	},
1512	};
1513
1514	static struct clk_branch gcc_npu_dma_clk = {
1515	.halt_reg = 0x4d00c,
1516	.halt_check = BRANCH_HALT_VOTED,
1517	.clkr = {
1518	.enable_reg = 0x4d00c,
1519	.enable_mask = BIT(0),
1520	.hw.init = &(struct clk_init_data){
1521	.name = "gcc_npu_dma_clk",
1522	.ops = &clk_branch2_ops,
1523	},
1524	},
1525	};
1526
1527	static struct clk_branch gcc_npu_gpll0_clk_src = {
1528	.halt_check = BRANCH_HALT_DELAY,
1529	.clkr = {
1530	.enable_reg = 0x52000,
1531	.enable_mask = BIT(18),
1532	.hw.init = &(struct clk_init_data){
1533	.name = "gcc_npu_gpll0_clk_src",
1534	.parent_hws = (const struct clk_hw*[]){
1535	&gpll0.clkr.hw,
1536	},
1537	.num_parents = 1,
1538	.flags = CLK_SET_RATE_PARENT,
1539	.ops = &clk_branch2_ops,
1540	},
1541	},
1542	};
1543
1544	static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1545	.halt_check = BRANCH_HALT_DELAY,
1546	.clkr = {
1547	.enable_reg = 0x52000,
1548	.enable_mask = BIT(19),
1549	.hw.init = &(struct clk_init_data){
1550	.name = "gcc_npu_gpll0_div_clk_src",
1551	.parent_hws = (const struct clk_hw*[]){
1552	&gpll0_out_even.clkr.hw,
1553	},
1554	.num_parents = 1,
1555	.flags = CLK_SET_RATE_PARENT,
1556	.ops = &clk_branch2_ops,
1557	},
1558	},
1559	};
1560
1561	static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1562	.halt_reg = 0x6f02c,
1563	.halt_check = BRANCH_HALT,
1564	.clkr = {
1565	.enable_reg = 0x6f02c,
1566	.enable_mask = BIT(0),
1567	.hw.init = &(struct clk_init_data){
1568	.name = "gcc_pcie0_phy_refgen_clk",
1569	.parent_hws = (const struct clk_hw*[]){
1570	&gcc_pcie_phy_refgen_clk_src.clkr.hw,
1571	},
1572	.num_parents = 1,
1573	.flags = CLK_SET_RATE_PARENT,
1574	.ops = &clk_branch2_ops,
1575	},
1576	},
1577	};
1578
1579	static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1580	.halt_reg = 0x6f030,
1581	.halt_check = BRANCH_HALT,
1582	.clkr = {
1583	.enable_reg = 0x6f030,
1584	.enable_mask = BIT(0),
1585	.hw.init = &(struct clk_init_data){
1586	.name = "gcc_pcie1_phy_refgen_clk",
1587	.parent_hws = (const struct clk_hw*[]){
1588	&gcc_pcie_phy_refgen_clk_src.clkr.hw,
1589	},
1590	.num_parents = 1,
1591	.flags = CLK_SET_RATE_PARENT,
1592	.ops = &clk_branch2_ops,
1593	},
1594	},
1595	};
1596
1597	static struct clk_branch gcc_pcie2_phy_refgen_clk = {
1598	.halt_reg = 0x6f034,
1599	.halt_check = BRANCH_HALT,
1600	.clkr = {
1601	.enable_reg = 0x6f034,
1602	.enable_mask = BIT(0),
1603	.hw.init = &(struct clk_init_data){
1604	.name = "gcc_pcie2_phy_refgen_clk",
1605	.parent_hws = (const struct clk_hw*[]){
1606	&gcc_pcie_phy_refgen_clk_src.clkr.hw,
1607	},
1608	.num_parents = 1,
1609	.flags = CLK_SET_RATE_PARENT,
1610	.ops = &clk_branch2_ops,
1611	},
1612	},
1613	};
1614
1615	static struct clk_branch gcc_pcie_0_aux_clk = {
1616	.halt_reg = 0x6b028,
1617	.halt_check = BRANCH_HALT_VOTED,
1618	.clkr = {
1619	.enable_reg = 0x52008,
1620	.enable_mask = BIT(3),
1621	.hw.init = &(struct clk_init_data){
1622	.name = "gcc_pcie_0_aux_clk",
1623	.parent_hws = (const struct clk_hw*[]){
1624	&gcc_pcie_0_aux_clk_src.clkr.hw,
1625	},
1626	.num_parents = 1,
1627	.flags = CLK_SET_RATE_PARENT,
1628	.ops = &clk_branch2_ops,
1629	},
1630	},
1631	};
1632
1633	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1634	.halt_reg = 0x6b024,
1635	.halt_check = BRANCH_HALT_VOTED,
1636	.hwcg_reg = 0x6b024,
1637	.hwcg_bit = 1,
1638	.clkr = {
1639	.enable_reg = 0x52008,
1640	.enable_mask = BIT(2),
1641	.hw.init = &(struct clk_init_data){
1642	.name = "gcc_pcie_0_cfg_ahb_clk",
1643	.ops = &clk_branch2_ops,
1644	},
1645	},
1646	};
1647
1648	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1649	.halt_reg = 0x6b01c,
1650	.halt_check = BRANCH_HALT_VOTED,
1651	.clkr = {
1652	.enable_reg = 0x52008,
1653	.enable_mask = BIT(1),
1654	.hw.init = &(struct clk_init_data){
1655	.name = "gcc_pcie_0_mstr_axi_clk",
1656	.ops = &clk_branch2_ops,
1657	},
1658	},
1659	};
1660
1661	static struct clk_branch gcc_pcie_0_pipe_clk = {
1662	.halt_reg = 0x6b02c,
1663	.halt_check = BRANCH_HALT_SKIP,
1664	.clkr = {
1665	.enable_reg = 0x52008,
1666	.enable_mask = BIT(4),
1667	.hw.init = &(struct clk_init_data){
1668	.name = "gcc_pcie_0_pipe_clk",
1669	.ops = &clk_branch2_ops,
1670	},
1671	},
1672	};
1673
1674	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1675	.halt_reg = 0x6b014,
1676	.halt_check = BRANCH_HALT_VOTED,
1677	.hwcg_reg = 0x6b014,
1678	.hwcg_bit = 1,
1679	.clkr = {
1680	.enable_reg = 0x52008,
1681	.enable_mask = BIT(0),
1682	.hw.init = &(struct clk_init_data){
1683	.name = "gcc_pcie_0_slv_axi_clk",
1684	.ops = &clk_branch2_ops,
1685	},
1686	},
1687	};
1688
1689	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1690	.halt_reg = 0x6b010,
1691	.halt_check = BRANCH_HALT_VOTED,
1692	.clkr = {
1693	.enable_reg = 0x52008,
1694	.enable_mask = BIT(5),
1695	.hw.init = &(struct clk_init_data){
1696	.name = "gcc_pcie_0_slv_q2a_axi_clk",
1697	.ops = &clk_branch2_ops,
1698	},
1699	},
1700	};
1701
1702	static struct clk_branch gcc_pcie_1_aux_clk = {
1703	.halt_reg = 0x8d028,
1704	.halt_check = BRANCH_HALT_VOTED,
1705	.clkr = {
1706	.enable_reg = 0x52000,
1707	.enable_mask = BIT(29),
1708	.hw.init = &(struct clk_init_data){
1709	.name = "gcc_pcie_1_aux_clk",
1710	.parent_hws = (const struct clk_hw*[]){
1711	&gcc_pcie_1_aux_clk_src.clkr.hw,
1712	},
1713	.num_parents = 1,
1714	.flags = CLK_SET_RATE_PARENT,
1715	.ops = &clk_branch2_ops,
1716	},
1717	},
1718	};
1719
1720	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1721	.halt_reg = 0x8d024,
1722	.halt_check = BRANCH_HALT_VOTED,
1723	.hwcg_reg = 0x8d024,
1724	.hwcg_bit = 1,
1725	.clkr = {
1726	.enable_reg = 0x52000,
1727	.enable_mask = BIT(28),
1728	.hw.init = &(struct clk_init_data){
1729	.name = "gcc_pcie_1_cfg_ahb_clk",
1730	.ops = &clk_branch2_ops,
1731	},
1732	},
1733	};
1734
1735	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1736	.halt_reg = 0x8d01c,
1737	.halt_check = BRANCH_HALT_VOTED,
1738	.clkr = {
1739	.enable_reg = 0x52000,
1740	.enable_mask = BIT(27),
1741	.hw.init = &(struct clk_init_data){
1742	.name = "gcc_pcie_1_mstr_axi_clk",
1743	.ops = &clk_branch2_ops,
1744	},
1745	},
1746	};
1747
1748	static struct clk_branch gcc_pcie_1_pipe_clk = {
1749	.halt_reg = 0x8d02c,
1750	.halt_check = BRANCH_HALT_SKIP,
1751	.clkr = {
1752	.enable_reg = 0x52000,
1753	.enable_mask = BIT(30),
1754	.hw.init = &(struct clk_init_data){
1755	.name = "gcc_pcie_1_pipe_clk",
1756	.ops = &clk_branch2_ops,
1757	},
1758	},
1759	};
1760
1761	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1762	.halt_reg = 0x8d014,
1763	.halt_check = BRANCH_HALT_VOTED,
1764	.hwcg_reg = 0x8d014,
1765	.hwcg_bit = 1,
1766	.clkr = {
1767	.enable_reg = 0x52000,
1768	.enable_mask = BIT(26),
1769	.hw.init = &(struct clk_init_data){
1770	.name = "gcc_pcie_1_slv_axi_clk",
1771	.ops = &clk_branch2_ops,
1772	},
1773	},
1774	};
1775
1776	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1777	.halt_reg = 0x8d010,
1778	.halt_check = BRANCH_HALT_VOTED,
1779	.clkr = {
1780	.enable_reg = 0x52000,
1781	.enable_mask = BIT(25),
1782	.hw.init = &(struct clk_init_data){
1783	.name = "gcc_pcie_1_slv_q2a_axi_clk",
1784	.ops = &clk_branch2_ops,
1785	},
1786	},
1787	};
1788
1789	static struct clk_branch gcc_pcie_2_aux_clk = {
1790	.halt_reg = 0x6028,
1791	.halt_check = BRANCH_HALT_VOTED,
1792	.clkr = {
1793	.enable_reg = 0x52010,
1794	.enable_mask = BIT(14),
1795	.hw.init = &(struct clk_init_data){
1796	.name = "gcc_pcie_2_aux_clk",
1797	.parent_hws = (const struct clk_hw*[]){
1798	&gcc_pcie_2_aux_clk_src.clkr.hw,
1799	},
1800	.num_parents = 1,
1801	.flags = CLK_SET_RATE_PARENT,
1802	.ops = &clk_branch2_ops,
1803	},
1804	},
1805	};
1806
1807	static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
1808	.halt_reg = 0x6024,
1809	.halt_check = BRANCH_HALT_VOTED,
1810	.hwcg_reg = 0x6024,
1811	.hwcg_bit = 1,
1812	.clkr = {
1813	.enable_reg = 0x52010,
1814	.enable_mask = BIT(13),
1815	.hw.init = &(struct clk_init_data){
1816	.name = "gcc_pcie_2_cfg_ahb_clk",
1817	.ops = &clk_branch2_ops,
1818	},
1819	},
1820	};
1821
1822	static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
1823	.halt_reg = 0x601c,
1824	.halt_check = BRANCH_HALT_VOTED,
1825	.clkr = {
1826	.enable_reg = 0x52010,
1827	.enable_mask = BIT(12),
1828	.hw.init = &(struct clk_init_data){
1829	.name = "gcc_pcie_2_mstr_axi_clk",
1830	.ops = &clk_branch2_ops,
1831	},
1832	},
1833	};
1834
1835	static struct clk_branch gcc_pcie_2_pipe_clk = {
1836	.halt_reg = 0x602c,
1837	.halt_check = BRANCH_HALT_SKIP,
1838	.clkr = {
1839	.enable_reg = 0x52010,
1840	.enable_mask = BIT(15),
1841	.hw.init = &(struct clk_init_data){
1842	.name = "gcc_pcie_2_pipe_clk",
1843	.ops = &clk_branch2_ops,
1844	},
1845	},
1846	};
1847
1848	static struct clk_branch gcc_pcie_2_slv_axi_clk = {
1849	.halt_reg = 0x6014,
1850	.halt_check = BRANCH_HALT_VOTED,
1851	.hwcg_reg = 0x6014,
1852	.hwcg_bit = 1,
1853	.clkr = {
1854	.enable_reg = 0x52010,
1855	.enable_mask = BIT(11),
1856	.hw.init = &(struct clk_init_data){
1857	.name = "gcc_pcie_2_slv_axi_clk",
1858	.ops = &clk_branch2_ops,
1859	},
1860	},
1861	};
1862
1863	static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
1864	.halt_reg = 0x6010,
1865	.halt_check = BRANCH_HALT_VOTED,
1866	.clkr = {
1867	.enable_reg = 0x52010,
1868	.enable_mask = BIT(10),
1869	.hw.init = &(struct clk_init_data){
1870	.name = "gcc_pcie_2_slv_q2a_axi_clk",
1871	.ops = &clk_branch2_ops,
1872	},
1873	},
1874	};
1875
1876	static struct clk_branch gcc_pcie_mdm_clkref_en = {
1877	.halt_reg = 0x8c00c,
1878	.halt_check = BRANCH_HALT,
1879	.clkr = {
1880	.enable_reg = 0x8c00c,
1881	.enable_mask = BIT(0),
1882	.hw.init = &(struct clk_init_data){
1883	.name = "gcc_pcie_mdm_clkref_en",
1884	.ops = &clk_branch2_ops,
1885	},
1886	},
1887	};
1888
1889	static struct clk_branch gcc_pcie_phy_aux_clk = {
1890	.halt_reg = 0x6f004,
1891	.halt_check = BRANCH_HALT,
1892	.clkr = {
1893	.enable_reg = 0x6f004,
1894	.enable_mask = BIT(0),
1895	.hw.init = &(struct clk_init_data){
1896	.name = "gcc_pcie_phy_aux_clk",
1897	.parent_hws = (const struct clk_hw*[]){
1898	&gcc_pcie_0_aux_clk_src.clkr.hw,
1899	},
1900	.num_parents = 1,
1901	.flags = CLK_SET_RATE_PARENT,
1902	.ops = &clk_branch2_ops,
1903	},
1904	},
1905	};
1906
1907	static struct clk_branch gcc_pcie_wifi_clkref_en = {
1908	.halt_reg = 0x8c004,
1909	.halt_check = BRANCH_HALT,
1910	.clkr = {
1911	.enable_reg = 0x8c004,
1912	.enable_mask = BIT(0),
1913	.hw.init = &(struct clk_init_data){
1914	.name = "gcc_pcie_wifi_clkref_en",
1915	.ops = &clk_branch2_ops,
1916	},
1917	},
1918	};
1919
1920	static struct clk_branch gcc_pcie_wigig_clkref_en = {
1921	.halt_reg = 0x8c008,
1922	.halt_check = BRANCH_HALT,
1923	.clkr = {
1924	.enable_reg = 0x8c008,
1925	.enable_mask = BIT(0),
1926	.hw.init = &(struct clk_init_data){
1927	.name = "gcc_pcie_wigig_clkref_en",
1928	.ops = &clk_branch2_ops,
1929	},
1930	},
1931	};
1932
1933	static struct clk_branch gcc_pdm2_clk = {
1934	.halt_reg = 0x3300c,
1935	.halt_check = BRANCH_HALT,
1936	.clkr = {
1937	.enable_reg = 0x3300c,
1938	.enable_mask = BIT(0),
1939	.hw.init = &(struct clk_init_data){
1940	.name = "gcc_pdm2_clk",
1941	.parent_hws = (const struct clk_hw*[]){
1942	&gcc_pdm2_clk_src.clkr.hw,
1943	},
1944	.num_parents = 1,
1945	.flags = CLK_SET_RATE_PARENT,
1946	.ops = &clk_branch2_ops,
1947	},
1948	},
1949	};
1950
1951	static struct clk_branch gcc_pdm_ahb_clk = {
1952	.halt_reg = 0x33004,
1953	.halt_check = BRANCH_HALT,
1954	.hwcg_reg = 0x33004,
1955	.hwcg_bit = 1,
1956	.clkr = {
1957	.enable_reg = 0x33004,
1958	.enable_mask = BIT(0),
1959	.hw.init = &(struct clk_init_data){
1960	.name = "gcc_pdm_ahb_clk",
1961	.ops = &clk_branch2_ops,
1962	},
1963	},
1964	};
1965
1966	static struct clk_branch gcc_pdm_xo4_clk = {
1967	.halt_reg = 0x33008,
1968	.halt_check = BRANCH_HALT,
1969	.clkr = {
1970	.enable_reg = 0x33008,
1971	.enable_mask = BIT(0),
1972	.hw.init = &(struct clk_init_data){
1973	.name = "gcc_pdm_xo4_clk",
1974	.ops = &clk_branch2_ops,
1975	},
1976	},
1977	};
1978
1979	static struct clk_branch gcc_prng_ahb_clk = {
1980	.halt_reg = 0x34004,
1981	.halt_check = BRANCH_HALT_VOTED,
1982	.clkr = {
1983	.enable_reg = 0x52000,
1984	.enable_mask = BIT(13),
1985	.hw.init = &(struct clk_init_data){
1986	.name = "gcc_prng_ahb_clk",
1987	.ops = &clk_branch2_ops,
1988	},
1989	},
1990	};
1991
1992	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1993	.halt_reg = 0xb018,
1994	.halt_check = BRANCH_HALT_VOTED,
1995	.hwcg_reg = 0xb018,
1996	.hwcg_bit = 1,
1997	.clkr = {
1998	.enable_reg = 0xb018,
1999	.enable_mask = BIT(0),
2000	.hw.init = &(struct clk_init_data){
2001	.name = "gcc_qmip_camera_nrt_ahb_clk",
2002	.ops = &clk_branch2_ops,
2003	},
2004	},
2005	};
2006
2007	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2008	.halt_reg = 0xb01c,
2009	.halt_check = BRANCH_HALT_VOTED,
2010	.hwcg_reg = 0xb01c,
2011	.hwcg_bit = 1,
2012	.clkr = {
2013	.enable_reg = 0xb01c,
2014	.enable_mask = BIT(0),
2015	.hw.init = &(struct clk_init_data){
2016	.name = "gcc_qmip_camera_rt_ahb_clk",
2017	.ops = &clk_branch2_ops,
2018	},
2019	},
2020	};
2021
2022	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2023	.halt_reg = 0xb020,
2024	.halt_check = BRANCH_HALT_VOTED,
2025	.hwcg_reg = 0xb020,
2026	.hwcg_bit = 1,
2027	.clkr = {
2028	.enable_reg = 0xb020,
2029	.enable_mask = BIT(0),
2030	.hw.init = &(struct clk_init_data){
2031	.name = "gcc_qmip_disp_ahb_clk",
2032	.ops = &clk_branch2_ops,
2033	},
2034	},
2035	};
2036
2037	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2038	.halt_reg = 0xb010,
2039	.halt_check = BRANCH_HALT_VOTED,
2040	.hwcg_reg = 0xb010,
2041	.hwcg_bit = 1,
2042	.clkr = {
2043	.enable_reg = 0xb010,
2044	.enable_mask = BIT(0),
2045	.hw.init = &(struct clk_init_data){
2046	.name = "gcc_qmip_video_cvp_ahb_clk",
2047	.ops = &clk_branch2_ops,
2048	},
2049	},
2050	};
2051
2052	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2053	.halt_reg = 0xb014,
2054	.halt_check = BRANCH_HALT_VOTED,
2055	.hwcg_reg = 0xb014,
2056	.hwcg_bit = 1,
2057	.clkr = {
2058	.enable_reg = 0xb014,
2059	.enable_mask = BIT(0),
2060	.hw.init = &(struct clk_init_data){
2061	.name = "gcc_qmip_video_vcodec_ahb_clk",
2062	.ops = &clk_branch2_ops,
2063	},
2064	},
2065	};
2066
2067	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2068	.halt_reg = 0x23008,
2069	.halt_check = BRANCH_HALT_VOTED,
2070	.clkr = {
2071	.enable_reg = 0x52008,
2072	.enable_mask = BIT(9),
2073	.hw.init = &(struct clk_init_data){
2074	.name = "gcc_qupv3_wrap0_core_2x_clk",
2075	.ops = &clk_branch2_ops,
2076	},
2077	},
2078	};
2079
2080	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2081	.halt_reg = 0x23000,
2082	.halt_check = BRANCH_HALT_VOTED,
2083	.clkr = {
2084	.enable_reg = 0x52008,
2085	.enable_mask = BIT(8),
2086	.hw.init = &(struct clk_init_data){
2087	.name = "gcc_qupv3_wrap0_core_clk",
2088	.ops = &clk_branch2_ops,
2089	},
2090	},
2091	};
2092
2093	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2094	.halt_reg = 0x1700c,
2095	.halt_check = BRANCH_HALT_VOTED,
2096	.clkr = {
2097	.enable_reg = 0x52008,
2098	.enable_mask = BIT(10),
2099	.hw.init = &(struct clk_init_data){
2100	.name = "gcc_qupv3_wrap0_s0_clk",
2101	.parent_hws = (const struct clk_hw*[]){
2102	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2103	},
2104	.num_parents = 1,
2105	.flags = CLK_SET_RATE_PARENT,
2106	.ops = &clk_branch2_ops,
2107	},
2108	},
2109	};
2110
2111	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2112	.halt_reg = 0x1713c,
2113	.halt_check = BRANCH_HALT_VOTED,
2114	.clkr = {
2115	.enable_reg = 0x52008,
2116	.enable_mask = BIT(11),
2117	.hw.init = &(struct clk_init_data){
2118	.name = "gcc_qupv3_wrap0_s1_clk",
2119	.parent_hws = (const struct clk_hw*[]){
2120	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2121	},
2122	.num_parents = 1,
2123	.flags = CLK_SET_RATE_PARENT,
2124	.ops = &clk_branch2_ops,
2125	},
2126	},
2127	};
2128
2129	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2130	.halt_reg = 0x1726c,
2131	.halt_check = BRANCH_HALT_VOTED,
2132	.clkr = {
2133	.enable_reg = 0x52008,
2134	.enable_mask = BIT(12),
2135	.hw.init = &(struct clk_init_data){
2136	.name = "gcc_qupv3_wrap0_s2_clk",
2137	.parent_hws = (const struct clk_hw*[]){
2138	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2139	},
2140	.num_parents = 1,
2141	.flags = CLK_SET_RATE_PARENT,
2142	.ops = &clk_branch2_ops,
2143	},
2144	},
2145	};
2146
2147	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2148	.halt_reg = 0x1739c,
2149	.halt_check = BRANCH_HALT_VOTED,
2150	.clkr = {
2151	.enable_reg = 0x52008,
2152	.enable_mask = BIT(13),
2153	.hw.init = &(struct clk_init_data){
2154	.name = "gcc_qupv3_wrap0_s3_clk",
2155	.parent_hws = (const struct clk_hw*[]){
2156	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2157	},
2158	.num_parents = 1,
2159	.flags = CLK_SET_RATE_PARENT,
2160	.ops = &clk_branch2_ops,
2161	},
2162	},
2163	};
2164
2165	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2166	.halt_reg = 0x174cc,
2167	.halt_check = BRANCH_HALT_VOTED,
2168	.clkr = {
2169	.enable_reg = 0x52008,
2170	.enable_mask = BIT(14),
2171	.hw.init = &(struct clk_init_data){
2172	.name = "gcc_qupv3_wrap0_s4_clk",
2173	.parent_hws = (const struct clk_hw*[]){
2174	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2175	},
2176	.num_parents = 1,
2177	.flags = CLK_SET_RATE_PARENT,
2178	.ops = &clk_branch2_ops,
2179	},
2180	},
2181	};
2182
2183	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2184	.halt_reg = 0x175fc,
2185	.halt_check = BRANCH_HALT_VOTED,
2186	.clkr = {
2187	.enable_reg = 0x52008,
2188	.enable_mask = BIT(15),
2189	.hw.init = &(struct clk_init_data){
2190	.name = "gcc_qupv3_wrap0_s5_clk",
2191	.parent_hws = (const struct clk_hw*[]){
2192	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2193	},
2194	.num_parents = 1,
2195	.flags = CLK_SET_RATE_PARENT,
2196	.ops = &clk_branch2_ops,
2197	},
2198	},
2199	};
2200
2201	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2202	.halt_reg = 0x1772c,
2203	.halt_check = BRANCH_HALT_VOTED,
2204	.clkr = {
2205	.enable_reg = 0x52008,
2206	.enable_mask = BIT(16),
2207	.hw.init = &(struct clk_init_data){
2208	.name = "gcc_qupv3_wrap0_s6_clk",
2209	.parent_hws = (const struct clk_hw*[]){
2210	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2211	},
2212	.num_parents = 1,
2213	.flags = CLK_SET_RATE_PARENT,
2214	.ops = &clk_branch2_ops,
2215	},
2216	},
2217	};
2218
2219	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2220	.halt_reg = 0x1785c,
2221	.halt_check = BRANCH_HALT_VOTED,
2222	.clkr = {
2223	.enable_reg = 0x52008,
2224	.enable_mask = BIT(17),
2225	.hw.init = &(struct clk_init_data){
2226	.name = "gcc_qupv3_wrap0_s7_clk",
2227	.parent_hws = (const struct clk_hw*[]){
2228	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2229	},
2230	.num_parents = 1,
2231	.flags = CLK_SET_RATE_PARENT,
2232	.ops = &clk_branch2_ops,
2233	},
2234	},
2235	};
2236
2237	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2238	.halt_reg = 0x23140,
2239	.halt_check = BRANCH_HALT_VOTED,
2240	.clkr = {
2241	.enable_reg = 0x52008,
2242	.enable_mask = BIT(18),
2243	.hw.init = &(struct clk_init_data){
2244	.name = "gcc_qupv3_wrap1_core_2x_clk",
2245	.ops = &clk_branch2_ops,
2246	},
2247	},
2248	};
2249
2250	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2251	.halt_reg = 0x23138,
2252	.halt_check = BRANCH_HALT_VOTED,
2253	.clkr = {
2254	.enable_reg = 0x52008,
2255	.enable_mask = BIT(19),
2256	.hw.init = &(struct clk_init_data){
2257	.name = "gcc_qupv3_wrap1_core_clk",
2258	.ops = &clk_branch2_ops,
2259	},
2260	},
2261	};
2262
2263	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2264	.halt_reg = 0x1800c,
2265	.halt_check = BRANCH_HALT_VOTED,
2266	.clkr = {
2267	.enable_reg = 0x52008,
2268	.enable_mask = BIT(22),
2269	.hw.init = &(struct clk_init_data){
2270	.name = "gcc_qupv3_wrap1_s0_clk",
2271	.parent_hws = (const struct clk_hw*[]){
2272	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2273	},
2274	.num_parents = 1,
2275	.flags = CLK_SET_RATE_PARENT,
2276	.ops = &clk_branch2_ops,
2277	},
2278	},
2279	};
2280
2281	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2282	.halt_reg = 0x1813c,
2283	.halt_check = BRANCH_HALT_VOTED,
2284	.clkr = {
2285	.enable_reg = 0x52008,
2286	.enable_mask = BIT(23),
2287	.hw.init = &(struct clk_init_data){
2288	.name = "gcc_qupv3_wrap1_s1_clk",
2289	.parent_hws = (const struct clk_hw*[]){
2290	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2291	},
2292	.num_parents = 1,
2293	.flags = CLK_SET_RATE_PARENT,
2294	.ops = &clk_branch2_ops,
2295	},
2296	},
2297	};
2298
2299	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2300	.halt_reg = 0x1826c,
2301	.halt_check = BRANCH_HALT_VOTED,
2302	.clkr = {
2303	.enable_reg = 0x52008,
2304	.enable_mask = BIT(24),
2305	.hw.init = &(struct clk_init_data){
2306	.name = "gcc_qupv3_wrap1_s2_clk",
2307	.parent_hws = (const struct clk_hw*[]){
2308	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2309	},
2310	.num_parents = 1,
2311	.flags = CLK_SET_RATE_PARENT,
2312	.ops = &clk_branch2_ops,
2313	},
2314	},
2315	};
2316
2317	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2318	.halt_reg = 0x1839c,
2319	.halt_check = BRANCH_HALT_VOTED,
2320	.clkr = {
2321	.enable_reg = 0x52008,
2322	.enable_mask = BIT(25),
2323	.hw.init = &(struct clk_init_data){
2324	.name = "gcc_qupv3_wrap1_s3_clk",
2325	.parent_hws = (const struct clk_hw*[]){
2326	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2327	},
2328	.num_parents = 1,
2329	.flags = CLK_SET_RATE_PARENT,
2330	.ops = &clk_branch2_ops,
2331	},
2332	},
2333	};
2334
2335	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2336	.halt_reg = 0x184cc,
2337	.halt_check = BRANCH_HALT_VOTED,
2338	.clkr = {
2339	.enable_reg = 0x52008,
2340	.enable_mask = BIT(26),
2341	.hw.init = &(struct clk_init_data){
2342	.name = "gcc_qupv3_wrap1_s4_clk",
2343	.parent_hws = (const struct clk_hw*[]){
2344	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2345	},
2346	.num_parents = 1,
2347	.flags = CLK_SET_RATE_PARENT,
2348	.ops = &clk_branch2_ops,
2349	},
2350	},
2351	};
2352
2353	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2354	.halt_reg = 0x185fc,
2355	.halt_check = BRANCH_HALT_VOTED,
2356	.clkr = {
2357	.enable_reg = 0x52008,
2358	.enable_mask = BIT(27),
2359	.hw.init = &(struct clk_init_data){
2360	.name = "gcc_qupv3_wrap1_s5_clk",
2361	.parent_hws = (const struct clk_hw*[]){
2362	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2363	},
2364	.num_parents = 1,
2365	.flags = CLK_SET_RATE_PARENT,
2366	.ops = &clk_branch2_ops,
2367	},
2368	},
2369	};
2370
2371	static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2372	.halt_reg = 0x23278,
2373	.halt_check = BRANCH_HALT_VOTED,
2374	.clkr = {
2375	.enable_reg = 0x52010,
2376	.enable_mask = BIT(3),
2377	.hw.init = &(struct clk_init_data){
2378	.name = "gcc_qupv3_wrap2_core_2x_clk",
2379	.ops = &clk_branch2_ops,
2380	},
2381	},
2382	};
2383
2384	static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2385	.halt_reg = 0x23270,
2386	.halt_check = BRANCH_HALT_VOTED,
2387	.clkr = {
2388	.enable_reg = 0x52010,
2389	.enable_mask = BIT(0),
2390	.hw.init = &(struct clk_init_data){
2391	.name = "gcc_qupv3_wrap2_core_clk",
2392	.ops = &clk_branch2_ops,
2393	},
2394	},
2395	};
2396
2397	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2398	.halt_reg = 0x1e00c,
2399	.halt_check = BRANCH_HALT_VOTED,
2400	.clkr = {
2401	.enable_reg = 0x52010,
2402	.enable_mask = BIT(4),
2403	.hw.init = &(struct clk_init_data){
2404	.name = "gcc_qupv3_wrap2_s0_clk",
2405	.parent_hws = (const struct clk_hw*[]){
2406	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2407	},
2408	.num_parents = 1,
2409	.flags = CLK_SET_RATE_PARENT,
2410	.ops = &clk_branch2_ops,
2411	},
2412	},
2413	};
2414
2415	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2416	.halt_reg = 0x1e13c,
2417	.halt_check = BRANCH_HALT_VOTED,
2418	.clkr = {
2419	.enable_reg = 0x52010,
2420	.enable_mask = BIT(5),
2421	.hw.init = &(struct clk_init_data){
2422	.name = "gcc_qupv3_wrap2_s1_clk",
2423	.parent_hws = (const struct clk_hw*[]){
2424	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2425	},
2426	.num_parents = 1,
2427	.flags = CLK_SET_RATE_PARENT,
2428	.ops = &clk_branch2_ops,
2429	},
2430	},
2431	};
2432
2433	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2434	.halt_reg = 0x1e26c,
2435	.halt_check = BRANCH_HALT_VOTED,
2436	.clkr = {
2437	.enable_reg = 0x52010,
2438	.enable_mask = BIT(6),
2439	.hw.init = &(struct clk_init_data){
2440	.name = "gcc_qupv3_wrap2_s2_clk",
2441	.parent_hws = (const struct clk_hw*[]){
2442	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2443	},
2444	.num_parents = 1,
2445	.flags = CLK_SET_RATE_PARENT,
2446	.ops = &clk_branch2_ops,
2447	},
2448	},
2449	};
2450
2451	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2452	.halt_reg = 0x1e39c,
2453	.halt_check = BRANCH_HALT_VOTED,
2454	.clkr = {
2455	.enable_reg = 0x52010,
2456	.enable_mask = BIT(7),
2457	.hw.init = &(struct clk_init_data){
2458	.name = "gcc_qupv3_wrap2_s3_clk",
2459	.parent_hws = (const struct clk_hw*[]){
2460	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2461	},
2462	.num_parents = 1,
2463	.flags = CLK_SET_RATE_PARENT,
2464	.ops = &clk_branch2_ops,
2465	},
2466	},
2467	};
2468
2469	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2470	.halt_reg = 0x1e4cc,
2471	.halt_check = BRANCH_HALT_VOTED,
2472	.clkr = {
2473	.enable_reg = 0x52010,
2474	.enable_mask = BIT(8),
2475	.hw.init = &(struct clk_init_data){
2476	.name = "gcc_qupv3_wrap2_s4_clk",
2477	.parent_hws = (const struct clk_hw*[]){
2478	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2479	},
2480	.num_parents = 1,
2481	.flags = CLK_SET_RATE_PARENT,
2482	.ops = &clk_branch2_ops,
2483	},
2484	},
2485	};
2486
2487	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2488	.halt_reg = 0x1e5fc,
2489	.halt_check = BRANCH_HALT_VOTED,
2490	.clkr = {
2491	.enable_reg = 0x52010,
2492	.enable_mask = BIT(9),
2493	.hw.init = &(struct clk_init_data){
2494	.name = "gcc_qupv3_wrap2_s5_clk",
2495	.parent_hws = (const struct clk_hw*[]){
2496	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2497	},
2498	.num_parents = 1,
2499	.flags = CLK_SET_RATE_PARENT,
2500	.ops = &clk_branch2_ops,
2501	},
2502	},
2503	};
2504
2505	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2506	.halt_reg = 0x17004,
2507	.halt_check = BRANCH_HALT_VOTED,
2508	.clkr = {
2509	.enable_reg = 0x52008,
2510	.enable_mask = BIT(6),
2511	.hw.init = &(struct clk_init_data){
2512	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2513	.ops = &clk_branch2_ops,
2514	},
2515	},
2516	};
2517
2518	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2519	.halt_reg = 0x17008,
2520	.halt_check = BRANCH_HALT_VOTED,
2521	.hwcg_reg = 0x17008,
2522	.hwcg_bit = 1,
2523	.clkr = {
2524	.enable_reg = 0x52008,
2525	.enable_mask = BIT(7),
2526	.hw.init = &(struct clk_init_data){
2527	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2528	.ops = &clk_branch2_ops,
2529	},
2530	},
2531	};
2532
2533	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2534	.halt_reg = 0x18004,
2535	.halt_check = BRANCH_HALT_VOTED,
2536	.clkr = {
2537	.enable_reg = 0x52008,
2538	.enable_mask = BIT(20),
2539	.hw.init = &(struct clk_init_data){
2540	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2541	.ops = &clk_branch2_ops,
2542	},
2543	},
2544	};
2545
2546	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2547	.halt_reg = 0x18008,
2548	.halt_check = BRANCH_HALT_VOTED,
2549	.hwcg_reg = 0x18008,
2550	.hwcg_bit = 1,
2551	.clkr = {
2552	.enable_reg = 0x52008,
2553	.enable_mask = BIT(21),
2554	.hw.init = &(struct clk_init_data){
2555	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2556	.ops = &clk_branch2_ops,
2557	},
2558	},
2559	};
2560
2561	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2562	.halt_reg = 0x1e004,
2563	.halt_check = BRANCH_HALT_VOTED,
2564	.clkr = {
2565	.enable_reg = 0x52010,
2566	.enable_mask = BIT(2),
2567	.hw.init = &(struct clk_init_data){
2568	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2569	.ops = &clk_branch2_ops,
2570	},
2571	},
2572	};
2573
2574	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2575	.halt_reg = 0x1e008,
2576	.halt_check = BRANCH_HALT_VOTED,
2577	.hwcg_reg = 0x1e008,
2578	.hwcg_bit = 1,
2579	.clkr = {
2580	.enable_reg = 0x52010,
2581	.enable_mask = BIT(1),
2582	.hw.init = &(struct clk_init_data){
2583	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2584	.ops = &clk_branch2_ops,
2585	},
2586	},
2587	};
2588
2589	static struct clk_branch gcc_sdcc2_ahb_clk = {
2590	.halt_reg = 0x14008,
2591	.halt_check = BRANCH_HALT,
2592	.clkr = {
2593	.enable_reg = 0x14008,
2594	.enable_mask = BIT(0),
2595	.hw.init = &(struct clk_init_data){
2596	.name = "gcc_sdcc2_ahb_clk",
2597	.ops = &clk_branch2_ops,
2598	},
2599	},
2600	};
2601
2602	static struct clk_branch gcc_sdcc2_apps_clk = {
2603	.halt_reg = 0x14004,
2604	.halt_check = BRANCH_HALT,
2605	.clkr = {
2606	.enable_reg = 0x14004,
2607	.enable_mask = BIT(0),
2608	.hw.init = &(struct clk_init_data){
2609	.name = "gcc_sdcc2_apps_clk",
2610	.parent_hws = (const struct clk_hw*[]){
2611	&gcc_sdcc2_apps_clk_src.clkr.hw,
2612	},
2613	.num_parents = 1,
2614	.flags = CLK_SET_RATE_PARENT,
2615	.ops = &clk_branch2_ops,
2616	},
2617	},
2618	};
2619
2620	static struct clk_branch gcc_sdcc4_ahb_clk = {
2621	.halt_reg = 0x16008,
2622	.halt_check = BRANCH_HALT,
2623	.clkr = {
2624	.enable_reg = 0x16008,
2625	.enable_mask = BIT(0),
2626	.hw.init = &(struct clk_init_data){
2627	.name = "gcc_sdcc4_ahb_clk",
2628	.ops = &clk_branch2_ops,
2629	},
2630	},
2631	};
2632
2633	static struct clk_branch gcc_sdcc4_apps_clk = {
2634	.halt_reg = 0x16004,
2635	.halt_check = BRANCH_HALT,
2636	.clkr = {
2637	.enable_reg = 0x16004,
2638	.enable_mask = BIT(0),
2639	.hw.init = &(struct clk_init_data){
2640	.name = "gcc_sdcc4_apps_clk",
2641	.parent_hws = (const struct clk_hw*[]){
2642	&gcc_sdcc4_apps_clk_src.clkr.hw,
2643	},
2644	.num_parents = 1,
2645	.flags = CLK_SET_RATE_PARENT,
2646	.ops = &clk_branch2_ops,
2647	},
2648	},
2649	};
2650
2651	static struct clk_branch gcc_tsif_ahb_clk = {
2652	.halt_reg = 0x36004,
2653	.halt_check = BRANCH_HALT_VOTED,
2654	.clkr = {
2655	.enable_reg = 0x36004,
2656	.enable_mask = BIT(0),
2657	.hw.init = &(struct clk_init_data){
2658	.name = "gcc_tsif_ahb_clk",
2659	.ops = &clk_branch2_ops,
2660	},
2661	},
2662	};
2663
2664	static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2665	.halt_reg = 0x3600c,
2666	.halt_check = BRANCH_HALT,
2667	.clkr = {
2668	.enable_reg = 0x3600c,
2669	.enable_mask = BIT(0),
2670	.hw.init = &(struct clk_init_data){
2671	.name = "gcc_tsif_inactivity_timers_clk",
2672	.ops = &clk_branch2_ops,
2673	},
2674	},
2675	};
2676
2677	static struct clk_branch gcc_tsif_ref_clk = {
2678	.halt_reg = 0x36008,
2679	.halt_check = BRANCH_HALT,
2680	.clkr = {
2681	.enable_reg = 0x36008,
2682	.enable_mask = BIT(0),
2683	.hw.init = &(struct clk_init_data){
2684	.name = "gcc_tsif_ref_clk",
2685	.parent_hws = (const struct clk_hw*[]){
2686	&gcc_tsif_ref_clk_src.clkr.hw,
2687	},
2688	.num_parents = 1,
2689	.flags = CLK_SET_RATE_PARENT,
2690	.ops = &clk_branch2_ops,
2691	},
2692	},
2693	};
2694
2695	static struct clk_branch gcc_ufs_1x_clkref_en = {
2696	.halt_reg = 0x8c000,
2697	.halt_check = BRANCH_HALT,
2698	.clkr = {
2699	.enable_reg = 0x8c000,
2700	.enable_mask = BIT(0),
2701	.hw.init = &(struct clk_init_data){
2702	.name = "gcc_ufs_1x_clkref_en",
2703	.ops = &clk_branch2_ops,
2704	},
2705	},
2706	};
2707
2708	static struct clk_branch gcc_ufs_card_ahb_clk = {
2709	.halt_reg = 0x75018,
2710	.halt_check = BRANCH_HALT_VOTED,
2711	.hwcg_reg = 0x75018,
2712	.hwcg_bit = 1,
2713	.clkr = {
2714	.enable_reg = 0x75018,
2715	.enable_mask = BIT(0),
2716	.hw.init = &(struct clk_init_data){
2717	.name = "gcc_ufs_card_ahb_clk",
2718	.ops = &clk_branch2_ops,
2719	},
2720	},
2721	};
2722
2723	static struct clk_branch gcc_ufs_card_axi_clk = {
2724	.halt_reg = 0x75010,
2725	.halt_check = BRANCH_HALT,
2726	.hwcg_reg = 0x75010,
2727	.hwcg_bit = 1,
2728	.clkr = {
2729	.enable_reg = 0x75010,
2730	.enable_mask = BIT(0),
2731	.hw.init = &(struct clk_init_data){
2732	.name = "gcc_ufs_card_axi_clk",
2733	.parent_hws = (const struct clk_hw*[]){
2734	&gcc_ufs_card_axi_clk_src.clkr.hw,
2735	},
2736	.num_parents = 1,
2737	.flags = CLK_SET_RATE_PARENT,
2738	.ops = &clk_branch2_ops,
2739	},
2740	},
2741	};
2742
2743	static struct clk_branch gcc_ufs_card_ice_core_clk = {
2744	.halt_reg = 0x75064,
2745	.halt_check = BRANCH_HALT_VOTED,
2746	.hwcg_reg = 0x75064,
2747	.hwcg_bit = 1,
2748	.clkr = {
2749	.enable_reg = 0x75064,
2750	.enable_mask = BIT(0),
2751	.hw.init = &(struct clk_init_data){
2752	.name = "gcc_ufs_card_ice_core_clk",
2753	.parent_hws = (const struct clk_hw*[]){
2754	&gcc_ufs_card_ice_core_clk_src.clkr.hw,
2755	},
2756	.num_parents = 1,
2757	.flags = CLK_SET_RATE_PARENT,
2758	.ops = &clk_branch2_ops,
2759	},
2760	},
2761	};
2762
2763	static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2764	.halt_reg = 0x7509c,
2765	.halt_check = BRANCH_HALT,
2766	.hwcg_reg = 0x7509c,
2767	.hwcg_bit = 1,
2768	.clkr = {
2769	.enable_reg = 0x7509c,
2770	.enable_mask = BIT(0),
2771	.hw.init = &(struct clk_init_data){
2772	.name = "gcc_ufs_card_phy_aux_clk",
2773	.parent_hws = (const struct clk_hw*[]){
2774	&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2775	},
2776	.num_parents = 1,
2777	.flags = CLK_SET_RATE_PARENT,
2778	.ops = &clk_branch2_ops,
2779	},
2780	},
2781	};
2782
2783	static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2784	.halt_reg = 0x75020,
2785	.halt_check = BRANCH_HALT_DELAY,
2786	.clkr = {
2787	.enable_reg = 0x75020,
2788	.enable_mask = BIT(0),
2789	.hw.init = &(struct clk_init_data){
2790	.name = "gcc_ufs_card_rx_symbol_0_clk",
2791	.ops = &clk_branch2_ops,
2792	},
2793	},
2794	};
2795
2796	static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2797	.halt_reg = 0x750b8,
2798	.halt_check = BRANCH_HALT_DELAY,
2799	.clkr = {
2800	.enable_reg = 0x750b8,
2801	.enable_mask = BIT(0),
2802	.hw.init = &(struct clk_init_data){
2803	.name = "gcc_ufs_card_rx_symbol_1_clk",
2804	.ops = &clk_branch2_ops,
2805	},
2806	},
2807	};
2808
2809	static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2810	.halt_reg = 0x7501c,
2811	.halt_check = BRANCH_HALT_DELAY,
2812	.clkr = {
2813	.enable_reg = 0x7501c,
2814	.enable_mask = BIT(0),
2815	.hw.init = &(struct clk_init_data){
2816	.name = "gcc_ufs_card_tx_symbol_0_clk",
2817	.ops = &clk_branch2_ops,
2818	},
2819	},
2820	};
2821
2822	static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2823	.halt_reg = 0x7505c,
2824	.halt_check = BRANCH_HALT,
2825	.hwcg_reg = 0x7505c,
2826	.hwcg_bit = 1,
2827	.clkr = {
2828	.enable_reg = 0x7505c,
2829	.enable_mask = BIT(0),
2830	.hw.init = &(struct clk_init_data){
2831	.name = "gcc_ufs_card_unipro_core_clk",
2832	.parent_hws = (const struct clk_hw*[]){
2833	&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2834	},
2835	.num_parents = 1,
2836	.flags = CLK_SET_RATE_PARENT,
2837	.ops = &clk_branch2_ops,
2838	},
2839	},
2840	};
2841
2842	static struct clk_branch gcc_ufs_phy_ahb_clk = {
2843	.halt_reg = 0x77018,
2844	.halt_check = BRANCH_HALT_VOTED,
2845	.hwcg_reg = 0x77018,
2846	.hwcg_bit = 1,
2847	.clkr = {
2848	.enable_reg = 0x77018,
2849	.enable_mask = BIT(0),
2850	.hw.init = &(struct clk_init_data){
2851	.name = "gcc_ufs_phy_ahb_clk",
2852	.ops = &clk_branch2_ops,
2853	},
2854	},
2855	};
2856
2857	static struct clk_branch gcc_ufs_phy_axi_clk = {
2858	.halt_reg = 0x77010,
2859	.halt_check = BRANCH_HALT,
2860	.hwcg_reg = 0x77010,
2861	.hwcg_bit = 1,
2862	.clkr = {
2863	.enable_reg = 0x77010,
2864	.enable_mask = BIT(0),
2865	.hw.init = &(struct clk_init_data){
2866	.name = "gcc_ufs_phy_axi_clk",
2867	.parent_hws = (const struct clk_hw*[]){
2868	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2869	},
2870	.num_parents = 1,
2871	.flags = CLK_SET_RATE_PARENT,
2872	.ops = &clk_branch2_ops,
2873	},
2874	},
2875	};
2876
2877	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2878	.halt_reg = 0x77064,
2879	.halt_check = BRANCH_HALT_VOTED,
2880	.hwcg_reg = 0x77064,
2881	.hwcg_bit = 1,
2882	.clkr = {
2883	.enable_reg = 0x77064,
2884	.enable_mask = BIT(0),
2885	.hw.init = &(struct clk_init_data){
2886	.name = "gcc_ufs_phy_ice_core_clk",
2887	.parent_hws = (const struct clk_hw*[]){
2888	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2889	},
2890	.num_parents = 1,
2891	.flags = CLK_SET_RATE_PARENT,
2892	.ops = &clk_branch2_ops,
2893	},
2894	},
2895	};
2896
2897	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2898	.halt_reg = 0x7709c,
2899	.halt_check = BRANCH_HALT,
2900	.hwcg_reg = 0x7709c,
2901	.hwcg_bit = 1,
2902	.clkr = {
2903	.enable_reg = 0x7709c,
2904	.enable_mask = BIT(0),
2905	.hw.init = &(struct clk_init_data){
2906	.name = "gcc_ufs_phy_phy_aux_clk",
2907	.parent_hws = (const struct clk_hw*[]){
2908	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2909	},
2910	.num_parents = 1,
2911	.flags = CLK_SET_RATE_PARENT,
2912	.ops = &clk_branch2_ops,
2913	},
2914	},
2915	};
2916
2917	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2918	.halt_reg = 0x77020,
2919	.halt_check = BRANCH_HALT_DELAY,
2920	.clkr = {
2921	.enable_reg = 0x77020,
2922	.enable_mask = BIT(0),
2923	.hw.init = &(struct clk_init_data){
2924	.name = "gcc_ufs_phy_rx_symbol_0_clk",
2925	.ops = &clk_branch2_ops,
2926	},
2927	},
2928	};
2929
2930	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2931	.halt_reg = 0x770b8,
2932	.halt_check = BRANCH_HALT_DELAY,
2933	.clkr = {
2934	.enable_reg = 0x770b8,
2935	.enable_mask = BIT(0),
2936	.hw.init = &(struct clk_init_data){
2937	.name = "gcc_ufs_phy_rx_symbol_1_clk",
2938	.ops = &clk_branch2_ops,
2939	},
2940	},
2941	};
2942
2943	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2944	.halt_reg = 0x7701c,
2945	.halt_check = BRANCH_HALT_DELAY,
2946	.clkr = {
2947	.enable_reg = 0x7701c,
2948	.enable_mask = BIT(0),
2949	.hw.init = &(struct clk_init_data){
2950	.name = "gcc_ufs_phy_tx_symbol_0_clk",
2951	.ops = &clk_branch2_ops,
2952	},
2953	},
2954	};
2955
2956	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2957	.halt_reg = 0x7705c,
2958	.halt_check = BRANCH_HALT,
2959	.hwcg_reg = 0x7705c,
2960	.hwcg_bit = 1,
2961	.clkr = {
2962	.enable_reg = 0x7705c,
2963	.enable_mask = BIT(0),
2964	.hw.init = &(struct clk_init_data){
2965	.name = "gcc_ufs_phy_unipro_core_clk",
2966	.parent_hws = (const struct clk_hw*[]){
2967	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2968	},
2969	.num_parents = 1,
2970	.flags = CLK_SET_RATE_PARENT,
2971	.ops = &clk_branch2_ops,
2972	},
2973	},
2974	};
2975
2976	static struct clk_branch gcc_usb30_prim_master_clk = {
2977	.halt_reg = 0xf010,
2978	.halt_check = BRANCH_HALT_VOTED,
2979	.clkr = {
2980	.enable_reg = 0xf010,
2981	.enable_mask = BIT(0),
2982	.hw.init = &(struct clk_init_data){
2983	.name = "gcc_usb30_prim_master_clk",
2984	.parent_hws = (const struct clk_hw*[]){
2985	&gcc_usb30_prim_master_clk_src.clkr.hw,
2986	},
2987	.num_parents = 1,
2988	.flags = CLK_SET_RATE_PARENT,
2989	.ops = &clk_branch2_ops,
2990	},
2991	},
2992	};
2993
2994	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2995	.halt_reg = 0xf01c,
2996	.halt_check = BRANCH_HALT,
2997	.clkr = {
2998	.enable_reg = 0xf01c,
2999	.enable_mask = BIT(0),
3000	.hw.init = &(struct clk_init_data){
3001	.name = "gcc_usb30_prim_mock_utmi_clk",
3002	.parent_hws = (const struct clk_hw*[]) {
3003	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3004	},
3005	.num_parents = 1,
3006	.flags = CLK_SET_RATE_PARENT,
3007	.ops = &clk_branch2_ops,
3008	},
3009	},
3010	};
3011
3012	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3013	.halt_reg = 0xf018,
3014	.halt_check = BRANCH_HALT,
3015	.clkr = {
3016	.enable_reg = 0xf018,
3017	.enable_mask = BIT(0),
3018	.hw.init = &(struct clk_init_data){
3019	.name = "gcc_usb30_prim_sleep_clk",
3020	.ops = &clk_branch2_ops,
3021	},
3022	},
3023	};
3024
3025	static struct clk_branch gcc_usb30_sec_master_clk = {
3026	.halt_reg = 0x10010,
3027	.halt_check = BRANCH_HALT_VOTED,
3028	.clkr = {
3029	.enable_reg = 0x10010,
3030	.enable_mask = BIT(0),
3031	.hw.init = &(struct clk_init_data){
3032	.name = "gcc_usb30_sec_master_clk",
3033	.parent_hws = (const struct clk_hw*[]){
3034	&gcc_usb30_sec_master_clk_src.clkr.hw,
3035	},
3036	.num_parents = 1,
3037	.flags = CLK_SET_RATE_PARENT,
3038	.ops = &clk_branch2_ops,
3039	},
3040	},
3041	};
3042
3043	static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3044	.halt_reg = 0x1001c,
3045	.halt_check = BRANCH_HALT,
3046	.clkr = {
3047	.enable_reg = 0x1001c,
3048	.enable_mask = BIT(0),
3049	.hw.init = &(struct clk_init_data){
3050	.name = "gcc_usb30_sec_mock_utmi_clk",
3051	.parent_hws = (const struct clk_hw*[]) {
3052	&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3053	},
3054	.num_parents = 1,
3055	.flags = CLK_SET_RATE_PARENT,
3056	.ops = &clk_branch2_ops,
3057	},
3058	},
3059	};
3060
3061	static struct clk_branch gcc_usb30_sec_sleep_clk = {
3062	.halt_reg = 0x10018,
3063	.halt_check = BRANCH_HALT,
3064	.clkr = {
3065	.enable_reg = 0x10018,
3066	.enable_mask = BIT(0),
3067	.hw.init = &(struct clk_init_data){
3068	.name = "gcc_usb30_sec_sleep_clk",
3069	.ops = &clk_branch2_ops,
3070	},
3071	},
3072	};
3073
3074	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3075	.halt_reg = 0xf054,
3076	.halt_check = BRANCH_HALT,
3077	.clkr = {
3078	.enable_reg = 0xf054,
3079	.enable_mask = BIT(0),
3080	.hw.init = &(struct clk_init_data){
3081	.name = "gcc_usb3_prim_phy_aux_clk",
3082	.parent_hws = (const struct clk_hw*[]){
3083	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3084	},
3085	.num_parents = 1,
3086	.flags = CLK_SET_RATE_PARENT,
3087	.ops = &clk_branch2_ops,
3088	},
3089	},
3090	};
3091
3092	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3093	.halt_reg = 0xf058,
3094	.halt_check = BRANCH_HALT,
3095	.clkr = {
3096	.enable_reg = 0xf058,
3097	.enable_mask = BIT(0),
3098	.hw.init = &(struct clk_init_data){
3099	.name = "gcc_usb3_prim_phy_com_aux_clk",
3100	.parent_hws = (const struct clk_hw*[]){
3101	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3102	},
3103	.num_parents = 1,
3104	.flags = CLK_SET_RATE_PARENT,
3105	.ops = &clk_branch2_ops,
3106	},
3107	},
3108	};
3109
3110	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3111	.halt_reg = 0xf05c,
3112	.halt_check = BRANCH_HALT_DELAY,
3113	.clkr = {
3114	.enable_reg = 0xf05c,
3115	.enable_mask = BIT(0),
3116	.hw.init = &(struct clk_init_data){
3117	.name = "gcc_usb3_prim_phy_pipe_clk",
3118	.ops = &clk_branch2_ops,
3119	},
3120	},
3121	};
3122
3123	static struct clk_branch gcc_usb3_sec_clkref_en = {
3124	.halt_reg = 0x8c010,
3125	.halt_check = BRANCH_HALT,
3126	.clkr = {
3127	.enable_reg = 0x8c010,
3128	.enable_mask = BIT(0),
3129	.hw.init = &(struct clk_init_data){
3130	.name = "gcc_usb3_sec_clkref_en",
3131	.ops = &clk_branch2_ops,
3132	},
3133	},
3134	};
3135
3136	static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3137	.halt_reg = 0x10054,
3138	.halt_check = BRANCH_HALT,
3139	.clkr = {
3140	.enable_reg = 0x10054,
3141	.enable_mask = BIT(0),
3142	.hw.init = &(struct clk_init_data){
3143	.name = "gcc_usb3_sec_phy_aux_clk",
3144	.parent_hws = (const struct clk_hw*[]){
3145	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3146	},
3147	.num_parents = 1,
3148	.flags = CLK_SET_RATE_PARENT,
3149	.ops = &clk_branch2_ops,
3150	},
3151	},
3152	};
3153
3154	static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3155	.halt_reg = 0x10058,
3156	.halt_check = BRANCH_HALT,
3157	.clkr = {
3158	.enable_reg = 0x10058,
3159	.enable_mask = BIT(0),
3160	.hw.init = &(struct clk_init_data){
3161	.name = "gcc_usb3_sec_phy_com_aux_clk",
3162	.parent_hws = (const struct clk_hw*[]){
3163	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3164	},
3165	.num_parents = 1,
3166	.flags = CLK_SET_RATE_PARENT,
3167	.ops = &clk_branch2_ops,
3168	},
3169	},
3170	};
3171
3172	static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3173	.halt_reg = 0x1005c,
3174	.halt_check = BRANCH_HALT_DELAY,
3175	.clkr = {
3176	.enable_reg = 0x1005c,
3177	.enable_mask = BIT(0),
3178	.hw.init = &(struct clk_init_data){
3179	.name = "gcc_usb3_sec_phy_pipe_clk",
3180	.ops = &clk_branch2_ops,
3181	},
3182	},
3183	};
3184
3185	static struct clk_branch gcc_video_axi0_clk = {
3186	.halt_reg = 0xb024,
3187	.halt_check = BRANCH_HALT_VOTED,
3188	.clkr = {
3189	.enable_reg = 0xb024,
3190	.enable_mask = BIT(0),
3191	.hw.init = &(struct clk_init_data){
3192	.name = "gcc_video_axi0_clk",
3193	.ops = &clk_branch2_ops,
3194	},
3195	},
3196	};
3197
3198	static struct clk_branch gcc_video_axi1_clk = {
3199	.halt_reg = 0xb028,
3200	.halt_check = BRANCH_HALT_VOTED,
3201	.clkr = {
3202	.enable_reg = 0xb028,
3203	.enable_mask = BIT(0),
3204	.hw.init = &(struct clk_init_data){
3205	.name = "gcc_video_axi1_clk",
3206	.ops = &clk_branch2_ops,
3207	},
3208	},
3209	};
3210
3211	static struct clk_branch gcc_video_xo_clk = {
3212	.halt_reg = 0xb03c,
3213	.halt_check = BRANCH_HALT,
3214	.clkr = {
3215	.enable_reg = 0xb03c,
3216	.enable_mask = BIT(0),
3217	.hw.init = &(struct clk_init_data){
3218	.name = "gcc_video_xo_clk",
3219	.ops = &clk_branch2_ops,
3220	},
3221	},
3222	};
3223
3224	static struct gdsc pcie_0_gdsc = {
3225	.gdscr = 0x6b004,
3226	.pd = {
3227	.name = "pcie_0_gdsc",
3228	},
3229	.pwrsts = PWRSTS_OFF_ON,
3230	};
3231
3232	static struct gdsc pcie_1_gdsc = {
3233	.gdscr = 0x8d004,
3234	.pd = {
3235	.name = "pcie_1_gdsc",
3236	},
3237	.pwrsts = PWRSTS_OFF_ON,
3238	};
3239
3240	static struct gdsc pcie_2_gdsc = {
3241	.gdscr = 0x6004,
3242	.pd = {
3243	.name = "pcie_2_gdsc",
3244	},
3245	.pwrsts = PWRSTS_OFF_ON,
3246	};
3247
3248	static struct gdsc ufs_card_gdsc = {
3249	.gdscr = 0x75004,
3250	.pd = {
3251	.name = "ufs_card_gdsc",
3252	},
3253	.pwrsts = PWRSTS_OFF_ON,
3254	};
3255
3256	static struct gdsc ufs_phy_gdsc = {
3257	.gdscr = 0x77004,
3258	.pd = {
3259	.name = "ufs_phy_gdsc",
3260	},
3261	.pwrsts = PWRSTS_OFF_ON,
3262	};
3263
3264	static struct gdsc usb30_prim_gdsc = {
3265	.gdscr = 0xf004,
3266	.pd = {
3267	.name = "usb30_prim_gdsc",
3268	},
3269	.pwrsts = PWRSTS_RET_ON,
3270	};
3271
3272	static struct gdsc usb30_sec_gdsc = {
3273	.gdscr = 0x10004,
3274	.pd = {
3275	.name = "usb30_sec_gdsc",
3276	},
3277	.pwrsts = PWRSTS_RET_ON,
3278	};
3279
3280	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3281	.gdscr = 0x7d050,
3282	.pd = {
3283	.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3284	},
3285	.pwrsts = PWRSTS_OFF_ON,
3286	.flags = VOTABLE,
3287	};
3288
3289	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3290	.gdscr = 0x7d058,
3291	.pd = {
3292	.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3293	},
3294	.pwrsts = PWRSTS_OFF_ON,
3295	.flags = VOTABLE,
3296	};
3297
3298	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3299	.gdscr = 0x7d054,
3300	.pd = {
3301	.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3302	},
3303	.pwrsts = PWRSTS_OFF_ON,
3304	.flags = VOTABLE,
3305	};
3306
3307	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3308	.gdscr = 0x7d06c,
3309	.pd = {
3310	.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3311	},
3312	.pwrsts = PWRSTS_OFF_ON,
3313	.flags = VOTABLE,
3314	};
3315
3316	static struct clk_regmap *gcc_sm8250_clocks[] = {
3317	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3318	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3319	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3320	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3321	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3322	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3323	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3324	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3325	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3326	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3327	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3328	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3329	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3330	[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
3331	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3332	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3333	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3334	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3335	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3336	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3337	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3338	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3339	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3340	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3341	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3342	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3343	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3344	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3345	[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3346	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3347	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3348	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3349	[GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
3350	[GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr,
3351	[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3352	[GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
3353	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
3354	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
3355	[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3356	[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3357	[GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
3358	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3359	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3360	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3361	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3362	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3363	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3364	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3365	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3366	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3367	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3368	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3369	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3370	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3371	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3372	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3373	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
3374	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3375	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3376	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3377	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3378	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
3379	[GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr,
3380	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3381	[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3382	[GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr,
3383	[GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr,
3384	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3385	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3386	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3387	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3388	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3389	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3390	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3391	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3392	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3393	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3394	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3395	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3396	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3397	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3398	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3399	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3400	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3401	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3402	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3403	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3404	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3405	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3406	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3407	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3408	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3409	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3410	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3411	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3412	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3413	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3414	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3415	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3416	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3417	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3418	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3419	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3420	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3421	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3422	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3423	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3424	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3425	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3426	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3427	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3428	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3429	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3430	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3431	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3432	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3433	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3434	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3435	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3436	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3437	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3438	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3439	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3440	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3441	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3442	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3443	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3444	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3445	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3446	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3447	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3448	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3449	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3450	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3451	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3452	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3453	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3454	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3455	[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3456	[GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr,
3457	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3458	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3459	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3460	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3461	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3462	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3463	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3464	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3465	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3466	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3467	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3468	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3469	&gcc_ufs_card_unipro_core_clk_src.clkr,
3470	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3471	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3472	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3473	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3474	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3475	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3476	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3477	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3478	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3479	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3480	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3481	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3482	&gcc_ufs_phy_unipro_core_clk_src.clkr,
3483	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3484	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3485	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3486	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3487	&gcc_usb30_prim_mock_utmi_clk_src.clkr,
3488	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3489	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3490	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3491	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3492	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3493	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3494	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3495	&gcc_usb30_sec_mock_utmi_clk_src.clkr,
3496	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3497	&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3498	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3499	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3500	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3501	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3502	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3503	[GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3504	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3505	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3506	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3507	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3508	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3509	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3510	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3511	[GPLL0] = &gpll0.clkr,
3512	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3513	[GPLL4] = &gpll4.clkr,
3514	[GPLL9] = &gpll9.clkr,
3515	};
3516
3517	static struct gdsc *gcc_sm8250_gdscs[] = {
3518	[PCIE_0_GDSC] = &pcie_0_gdsc,
3519	[PCIE_1_GDSC] = &pcie_1_gdsc,
3520	[PCIE_2_GDSC] = &pcie_2_gdsc,
3521	[UFS_CARD_GDSC] = &ufs_card_gdsc,
3522	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3523	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3524	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
3525	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3526	&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3527	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3528	&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3529	[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =
3530	&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3531	[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] =
3532	&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3533	};
3534
3535	static const struct qcom_reset_map gcc_sm8250_resets[] = {
3536	[GCC_GPU_BCR] = { 0x71000 },
3537	[GCC_MMSS_BCR] = { 0xb000 },
3538	[GCC_NPU_BWMON_BCR] = { 0x73000 },
3539	[GCC_NPU_BCR] = { 0x4d000 },
3540	[GCC_PCIE_0_BCR] = { 0x6b000 },
3541	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3542	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3543	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3544	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3545	[GCC_PCIE_1_BCR] = { 0x8d000 },
3546	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3547	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3548	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3549	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3550	[GCC_PCIE_2_BCR] = { 0x6000 },
3551	[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
3552	[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
3553	[GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
3554	[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
3555	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3556	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3557	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3558	[GCC_PDM_BCR] = { 0x33000 },
3559	[GCC_PRNG_BCR] = { 0x34000 },
3560	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3561	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3562	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3563	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3564	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3565	[GCC_SDCC2_BCR] = { 0x14000 },
3566	[GCC_SDCC4_BCR] = { 0x16000 },
3567	[GCC_TSIF_BCR] = { 0x36000 },
3568	[GCC_UFS_CARD_BCR] = { 0x75000 },
3569	[GCC_UFS_PHY_BCR] = { 0x77000 },
3570	[GCC_USB30_PRIM_BCR] = { 0xf000 },
3571	[GCC_USB30_SEC_BCR] = { 0x10000 },
3572	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3573	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3574	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3575	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3576	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3577	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3578	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3579	[GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 },
3580	[GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 },
3581	};
3582
3583	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3584	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3585	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3586	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3587	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3588	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3589	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3590	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3591	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3592	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3593	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3594	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3595	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3596	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3597	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3598	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3599	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3600	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3601	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3602	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3603	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3604	};
3605
3606	static const struct regmap_config gcc_sm8250_regmap_config = {
3607	.reg_bits = 32,
3608	.reg_stride = 4,
3609	.val_bits = 32,
3610	.max_register = 0x9c100,
3611	.fast_io = true,
3612	};
3613
3614	static const struct qcom_cc_desc gcc_sm8250_desc = {
3615	.config = &gcc_sm8250_regmap_config,
3616	.clks = gcc_sm8250_clocks,
3617	.num_clks = ARRAY_SIZE(gcc_sm8250_clocks),
3618	.resets = gcc_sm8250_resets,
3619	.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
3620	.gdscs = gcc_sm8250_gdscs,
3621	.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
3622	};
3623
3624	static const struct of_device_id gcc_sm8250_match_table[] = {
3625	{ .compatible = "qcom,gcc-sm8250" },
3626	{ }
3627	};
3628	MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table);
3629
3630	static int gcc_sm8250_probe(struct platform_device *pdev)
3631	{
3632	struct regmap *regmap;
3633	int ret;
3634
3635	regmap = qcom_cc_map(pdev, desc: &gcc_sm8250_desc);
3636	if (IS_ERR(ptr: regmap))
3637	return PTR_ERR(ptr: regmap);
3638
3639	/*
3640	* Disable the GPLL0 active input to NPU and GPU
3641	* via MISC registers.
3642	*/
3643	regmap_update_bits(map: regmap, reg: 0x4d110, mask: 0x3, val: 0x3);
3644	regmap_update_bits(map: regmap, reg: 0x71028, mask: 0x3, val: 0x3);
3645
3646	/* Keep some clocks always-on */
3647	qcom_branch_set_clk_en(regmap, cbcr: 0x0b004); /* GCC_VIDEO_AHB_CLK */
3648	qcom_branch_set_clk_en(regmap, cbcr: 0x0b008); /* GCC_CAMERA_AHB_CLK */
3649	qcom_branch_set_clk_en(regmap, cbcr: 0x0b00c); /* GCC_DISP_AHB_CLK */
3650	qcom_branch_set_clk_en(regmap, cbcr: 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */
3651	qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
3652	qcom_branch_set_clk_en(regmap, cbcr: 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
3653
3654	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
3655	ARRAY_SIZE(gcc_dfs_clocks));
3656	if (ret)
3657	return ret;
3658
3659	return qcom_cc_really_probe(pdev, desc: &gcc_sm8250_desc, regmap);
3660	}
3661
3662	static struct platform_driver gcc_sm8250_driver = {
3663	.probe = gcc_sm8250_probe,
3664	.driver = {
3665	.name = "gcc-sm8250",
3666	.of_match_table = gcc_sm8250_match_table,
3667	},
3668	};
3669
3670	static int __init gcc_sm8250_init(void)
3671	{
3672	return platform_driver_register(&gcc_sm8250_driver);
3673	}
3674	subsys_initcall(gcc_sm8250_init);
3675
3676	static void __exit gcc_sm8250_exit(void)
3677	{
3678	platform_driver_unregister(&gcc_sm8250_driver);
3679	}
3680	module_exit(gcc_sm8250_exit);
3681
3682	MODULE_DESCRIPTION("QTI GCC SM8250 Driver");
3683	MODULE_LICENSE("GPL v2");
3684