1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2021, Linaro Limited
5	*/
6
7	#include <linux/clk-provider.h>
8	#include <linux/module.h>
9	#include <linux/of.h>
10	#include <linux/platform_device.h>
11	#include <linux/regmap.h>
12
13	#include <dt-bindings/clock/qcom,gcc-sm8450.h>
14
15	#include "clk-alpha-pll.h"
16	#include "clk-branch.h"
17	#include "clk-rcg.h"
18	#include "clk-regmap.h"
19	#include "clk-regmap-divider.h"
20	#include "clk-regmap-mux.h"
21	#include "clk-regmap-phy-mux.h"
22	#include "gdsc.h"
23	#include "reset.h"
24
25	enum {
26	P_BI_TCXO,
27	P_GCC_GPLL0_OUT_EVEN,
28	P_GCC_GPLL0_OUT_MAIN,
29	P_GCC_GPLL4_OUT_MAIN,
30	P_GCC_GPLL9_OUT_MAIN,
31	P_PCIE_1_PHY_AUX_CLK,
32	P_SLEEP_CLK,
33	P_UFS_PHY_RX_SYMBOL_0_CLK,
34	P_UFS_PHY_RX_SYMBOL_1_CLK,
35	P_UFS_PHY_TX_SYMBOL_0_CLK,
36	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
37	};
38
39	static struct clk_alpha_pll gcc_gpll0 = {
40	.offset = 0x0,
41	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
42	.clkr = {
43	.enable_reg = 0x62018,
44	.enable_mask = BIT(0),
45	.hw.init = &(struct clk_init_data){
46	.name = "gcc_gpll0",
47	.parent_data = &(const struct clk_parent_data){
48	.fw_name = "bi_tcxo",
49	},
50	.num_parents = 1,
51	.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
52	},
53	},
54	};
55
56	static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
57	{ 0x1, 2 },
58	{ }
59	};
60
61	static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
62	.offset = 0x0,
63	.post_div_shift = 10,
64	.post_div_table = post_div_table_gcc_gpll0_out_even,
65	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
66	.width = 4,
67	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
68	.clkr.hw.init = &(struct clk_init_data){
69	.name = "gcc_gpll0_out_even",
70	.parent_hws = (const struct clk_hw*[]) {
71	&gcc_gpll0.clkr.hw,
72	},
73	.num_parents = 1,
74	.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
75	},
76	};
77
78	static struct clk_alpha_pll gcc_gpll4 = {
79	.offset = 0x4000,
80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
81	.clkr = {
82	.enable_reg = 0x62018,
83	.enable_mask = BIT(4),
84	.hw.init = &(struct clk_init_data){
85	.name = "gcc_gpll4",
86	.parent_data = &(const struct clk_parent_data){
87	.fw_name = "bi_tcxo",
88	},
89	.num_parents = 1,
90	.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
91	},
92	},
93	};
94
95	static struct clk_alpha_pll gcc_gpll9 = {
96	.offset = 0x9000,
97	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
98	.clkr = {
99	.enable_reg = 0x62018,
100	.enable_mask = BIT(9),
101	.hw.init = &(struct clk_init_data){
102	.name = "gcc_gpll9",
103	.parent_data = &(const struct clk_parent_data){
104	.fw_name = "bi_tcxo",
105	},
106	.num_parents = 1,
107	.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
108	},
109	},
110	};
111
112	static const struct parent_map gcc_parent_map_0[] = {
113	{ P_BI_TCXO, 0 },
114	{ P_GCC_GPLL0_OUT_MAIN, 1 },
115	{ P_GCC_GPLL0_OUT_EVEN, 6 },
116	};
117
118	static const struct clk_parent_data gcc_parent_data_0[] = {
119	{ .fw_name = "bi_tcxo" },
120	{ .hw = &gcc_gpll0.clkr.hw },
121	{ .hw = &gcc_gpll0_out_even.clkr.hw },
122	};
123
124	static const struct parent_map gcc_parent_map_1[] = {
125	{ P_BI_TCXO, 0 },
126	{ P_GCC_GPLL0_OUT_MAIN, 1 },
127	{ P_SLEEP_CLK, 5 },
128	{ P_GCC_GPLL0_OUT_EVEN, 6 },
129	};
130
131	static const struct clk_parent_data gcc_parent_data_1[] = {
132	{ .fw_name = "bi_tcxo" },
133	{ .hw = &gcc_gpll0.clkr.hw },
134	{ .fw_name = "sleep_clk" },
135	{ .hw = &gcc_gpll0_out_even.clkr.hw },
136	};
137
138	static const struct parent_map gcc_parent_map_2[] = {
139	{ P_BI_TCXO, 0 },
140	{ P_SLEEP_CLK, 5 },
141	};
142
143	static const struct clk_parent_data gcc_parent_data_2[] = {
144	{ .fw_name = "bi_tcxo" },
145	{ .fw_name = "sleep_clk" },
146	};
147
148	static const struct parent_map gcc_parent_map_3[] = {
149	{ P_BI_TCXO, 0 },
150	};
151
152	static const struct clk_parent_data gcc_parent_data_3[] = {
153	{ .fw_name = "bi_tcxo" },
154	};
155
156	static const struct parent_map gcc_parent_map_5[] = {
157	{ P_PCIE_1_PHY_AUX_CLK, 0 },
158	{ P_BI_TCXO, 2 },
159	};
160
161	static const struct clk_parent_data gcc_parent_data_5[] = {
162	{ .fw_name = "pcie_1_phy_aux_clk" },
163	{ .fw_name = "bi_tcxo" },
164	};
165
166	static const struct parent_map gcc_parent_map_7[] = {
167	{ P_BI_TCXO, 0 },
168	{ P_GCC_GPLL0_OUT_MAIN, 1 },
169	{ P_GCC_GPLL9_OUT_MAIN, 2 },
170	{ P_GCC_GPLL4_OUT_MAIN, 5 },
171	{ P_GCC_GPLL0_OUT_EVEN, 6 },
172	};
173
174	static const struct clk_parent_data gcc_parent_data_7[] = {
175	{ .fw_name = "bi_tcxo" },
176	{ .hw = &gcc_gpll0.clkr.hw },
177	{ .hw = &gcc_gpll9.clkr.hw },
178	{ .hw = &gcc_gpll4.clkr.hw },
179	{ .hw = &gcc_gpll0_out_even.clkr.hw },
180	};
181
182	static const struct parent_map gcc_parent_map_8[] = {
183	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
184	{ P_BI_TCXO, 2 },
185	};
186
187	static const struct clk_parent_data gcc_parent_data_8[] = {
188	{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
189	{ .fw_name = "bi_tcxo" },
190	};
191
192	static const struct parent_map gcc_parent_map_9[] = {
193	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
194	{ P_BI_TCXO, 2 },
195	};
196
197	static const struct clk_parent_data gcc_parent_data_9[] = {
198	{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
199	{ .fw_name = "bi_tcxo" },
200	};
201
202	static const struct parent_map gcc_parent_map_10[] = {
203	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
204	{ P_BI_TCXO, 2 },
205	};
206
207	static const struct clk_parent_data gcc_parent_data_10[] = {
208	{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
209	{ .fw_name = "bi_tcxo" },
210	};
211
212	static const struct parent_map gcc_parent_map_11[] = {
213	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
214	{ P_BI_TCXO, 2 },
215	};
216
217	static const struct clk_parent_data gcc_parent_data_11[] = {
218	{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
219	{ .fw_name = "bi_tcxo" },
220	};
221
222	static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
223	.reg = 0x7b060,
224	.clkr = {
225	.hw.init = &(struct clk_init_data){
226	.name = "gcc_pcie_0_pipe_clk_src",
227	.parent_data = &(const struct clk_parent_data){
228	.fw_name = "pcie_0_pipe_clk",
229	},
230	.num_parents = 1,
231	.ops = &clk_regmap_phy_mux_ops,
232	},
233	},
234	};
235
236	static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
237	.reg = 0x9d080,
238	.shift = 0,
239	.width = 2,
240	.parent_map = gcc_parent_map_5,
241	.clkr = {
242	.hw.init = &(struct clk_init_data){
243	.name = "gcc_pcie_1_phy_aux_clk_src",
244	.parent_data = gcc_parent_data_5,
245	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
246	.ops = &clk_regmap_mux_closest_ops,
247	},
248	},
249	};
250
251	static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
252	.reg = 0x9d064,
253	.clkr = {
254	.hw.init = &(struct clk_init_data){
255	.name = "gcc_pcie_1_pipe_clk_src",
256	.parent_data = &(const struct clk_parent_data){
257	.fw_name = "pcie_1_pipe_clk",
258	},
259	.num_parents = 1,
260	.ops = &clk_regmap_phy_mux_ops,
261	},
262	},
263	};
264
265	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
266	.reg = 0x87060,
267	.shift = 0,
268	.width = 2,
269	.parent_map = gcc_parent_map_8,
270	.clkr = {
271	.hw.init = &(struct clk_init_data){
272	.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
273	.parent_data = gcc_parent_data_8,
274	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
275	.ops = &clk_regmap_mux_closest_ops,
276	},
277	},
278	};
279
280	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
281	.reg = 0x870d0,
282	.shift = 0,
283	.width = 2,
284	.parent_map = gcc_parent_map_9,
285	.clkr = {
286	.hw.init = &(struct clk_init_data){
287	.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
288	.parent_data = gcc_parent_data_9,
289	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
290	.ops = &clk_regmap_mux_closest_ops,
291	},
292	},
293	};
294
295	static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
296	.reg = 0x87050,
297	.shift = 0,
298	.width = 2,
299	.parent_map = gcc_parent_map_10,
300	.clkr = {
301	.hw.init = &(struct clk_init_data){
302	.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
303	.parent_data = gcc_parent_data_10,
304	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
305	.ops = &clk_regmap_mux_closest_ops,
306	},
307	},
308	};
309
310	static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
311	.reg = 0x49068,
312	.shift = 0,
313	.width = 2,
314	.parent_map = gcc_parent_map_11,
315	.clkr = {
316	.hw.init = &(struct clk_init_data){
317	.name = "gcc_usb3_prim_phy_pipe_clk_src",
318	.parent_data = gcc_parent_data_11,
319	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
320	.ops = &clk_regmap_mux_closest_ops,
321	},
322	},
323	};
324
325	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
326	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
327	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
328	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
329	{ }
330	};
331
332	static struct clk_rcg2 gcc_gp1_clk_src = {
333	.cmd_rcgr = 0x74004,
334	.mnd_width = 8,
335	.hid_width = 5,
336	.parent_map = gcc_parent_map_1,
337	.freq_tbl = ftbl_gcc_gp1_clk_src,
338	.hw_clk_ctrl = true,
339	.clkr.hw.init = &(struct clk_init_data){
340	.name = "gcc_gp1_clk_src",
341	.parent_data = gcc_parent_data_1,
342	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
343	.flags = CLK_SET_RATE_PARENT,
344	.ops = &clk_rcg2_ops,
345	},
346	};
347
348	static struct clk_rcg2 gcc_gp2_clk_src = {
349	.cmd_rcgr = 0x75004,
350	.mnd_width = 8,
351	.hid_width = 5,
352	.parent_map = gcc_parent_map_1,
353	.freq_tbl = ftbl_gcc_gp1_clk_src,
354	.hw_clk_ctrl = true,
355	.clkr.hw.init = &(struct clk_init_data){
356	.name = "gcc_gp2_clk_src",
357	.parent_data = gcc_parent_data_1,
358	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
359	.flags = CLK_SET_RATE_PARENT,
360	.ops = &clk_rcg2_ops,
361	},
362	};
363
364	static struct clk_rcg2 gcc_gp3_clk_src = {
365	.cmd_rcgr = 0x76004,
366	.mnd_width = 8,
367	.hid_width = 5,
368	.parent_map = gcc_parent_map_1,
369	.freq_tbl = ftbl_gcc_gp1_clk_src,
370	.hw_clk_ctrl = true,
371	.clkr.hw.init = &(struct clk_init_data){
372	.name = "gcc_gp3_clk_src",
373	.parent_data = gcc_parent_data_1,
374	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
375	.flags = CLK_SET_RATE_PARENT,
376	.ops = &clk_rcg2_ops,
377	},
378	};
379
380	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
381	F(19200000, P_BI_TCXO, 1, 0, 0),
382	{ }
383	};
384
385	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
386	.cmd_rcgr = 0x7b064,
387	.mnd_width = 16,
388	.hid_width = 5,
389	.parent_map = gcc_parent_map_2,
390	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
391	.hw_clk_ctrl = true,
392	.clkr.hw.init = &(struct clk_init_data){
393	.name = "gcc_pcie_0_aux_clk_src",
394	.parent_data = gcc_parent_data_2,
395	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
396	.flags = CLK_SET_RATE_PARENT,
397	.ops = &clk_rcg2_ops,
398	},
399	};
400
401	static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
402	F(19200000, P_BI_TCXO, 1, 0, 0),
403	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
404	{ }
405	};
406
407	static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
408	.cmd_rcgr = 0x7b048,
409	.mnd_width = 0,
410	.hid_width = 5,
411	.parent_map = gcc_parent_map_0,
412	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
413	.hw_clk_ctrl = true,
414	.clkr.hw.init = &(struct clk_init_data){
415	.name = "gcc_pcie_0_phy_rchng_clk_src",
416	.parent_data = gcc_parent_data_0,
417	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
418	.flags = CLK_SET_RATE_PARENT,
419	.ops = &clk_rcg2_ops,
420	},
421	};
422
423	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
424	.cmd_rcgr = 0x9d068,
425	.mnd_width = 16,
426	.hid_width = 5,
427	.parent_map = gcc_parent_map_2,
428	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
429	.hw_clk_ctrl = true,
430	.clkr.hw.init = &(struct clk_init_data){
431	.name = "gcc_pcie_1_aux_clk_src",
432	.parent_data = gcc_parent_data_2,
433	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
434	.flags = CLK_SET_RATE_PARENT,
435	.ops = &clk_rcg2_ops,
436	},
437	};
438
439	static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
440	.cmd_rcgr = 0x9d04c,
441	.mnd_width = 0,
442	.hid_width = 5,
443	.parent_map = gcc_parent_map_0,
444	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
445	.hw_clk_ctrl = true,
446	.clkr.hw.init = &(struct clk_init_data){
447	.name = "gcc_pcie_1_phy_rchng_clk_src",
448	.parent_data = gcc_parent_data_0,
449	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
450	.flags = CLK_SET_RATE_PARENT,
451	.ops = &clk_rcg2_ops,
452	},
453	};
454
455	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
456	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
457	{ }
458	};
459
460	static struct clk_rcg2 gcc_pdm2_clk_src = {
461	.cmd_rcgr = 0x43010,
462	.mnd_width = 0,
463	.hid_width = 5,
464	.parent_map = gcc_parent_map_0,
465	.freq_tbl = ftbl_gcc_pdm2_clk_src,
466	.hw_clk_ctrl = true,
467	.clkr.hw.init = &(struct clk_init_data){
468	.name = "gcc_pdm2_clk_src",
469	.parent_data = gcc_parent_data_0,
470	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
471	.flags = CLK_SET_RATE_PARENT,
472	.ops = &clk_rcg2_ops,
473	},
474	};
475
476	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
477	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
478	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
479	F(19200000, P_BI_TCXO, 1, 0, 0),
480	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
481	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
482	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
483	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
484	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
485	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
486	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
487	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
488	{ }
489	};
490
491	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
492	.name = "gcc_qupv3_wrap0_s0_clk_src",
493	.parent_data = gcc_parent_data_0,
494	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
495	.flags = CLK_SET_RATE_PARENT,
496	.ops = &clk_rcg2_ops,
497	};
498
499	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
500	.cmd_rcgr = 0x27014,
501	.mnd_width = 16,
502	.hid_width = 5,
503	.parent_map = gcc_parent_map_0,
504	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
505	.hw_clk_ctrl = true,
506	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
507	};
508
509	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
510	.name = "gcc_qupv3_wrap0_s1_clk_src",
511	.parent_data = gcc_parent_data_0,
512	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
513	.flags = CLK_SET_RATE_PARENT,
514	.ops = &clk_rcg2_ops,
515	};
516
517	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
518	.cmd_rcgr = 0x27148,
519	.mnd_width = 16,
520	.hid_width = 5,
521	.parent_map = gcc_parent_map_0,
522	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
523	.hw_clk_ctrl = true,
524	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
525	};
526
527	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
528	.name = "gcc_qupv3_wrap0_s2_clk_src",
529	.parent_data = gcc_parent_data_0,
530	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
531	.flags = CLK_SET_RATE_PARENT,
532	.ops = &clk_rcg2_ops,
533	};
534
535	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
536	.cmd_rcgr = 0x2727c,
537	.mnd_width = 16,
538	.hid_width = 5,
539	.parent_map = gcc_parent_map_0,
540	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
541	.hw_clk_ctrl = true,
542	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
543	};
544
545	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
546	.name = "gcc_qupv3_wrap0_s3_clk_src",
547	.parent_data = gcc_parent_data_0,
548	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
549	.flags = CLK_SET_RATE_PARENT,
550	.ops = &clk_rcg2_ops,
551	};
552
553	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
554	.cmd_rcgr = 0x273b0,
555	.mnd_width = 16,
556	.hid_width = 5,
557	.parent_map = gcc_parent_map_0,
558	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
559	.hw_clk_ctrl = true,
560	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
561	};
562
563	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
564	.name = "gcc_qupv3_wrap0_s4_clk_src",
565	.parent_data = gcc_parent_data_0,
566	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
567	.flags = CLK_SET_RATE_PARENT,
568	.ops = &clk_rcg2_ops,
569	};
570
571	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
572	.cmd_rcgr = 0x274e4,
573	.mnd_width = 16,
574	.hid_width = 5,
575	.parent_map = gcc_parent_map_0,
576	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
577	.hw_clk_ctrl = true,
578	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
579	};
580
581	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
582	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
583	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
584	F(19200000, P_BI_TCXO, 1, 0, 0),
585	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
586	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
587	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
588	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
589	F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
590	{ }
591	};
592
593	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
594	.name = "gcc_qupv3_wrap0_s5_clk_src",
595	.parent_data = gcc_parent_data_0,
596	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
597	.flags = CLK_SET_RATE_PARENT,
598	.ops = &clk_rcg2_ops,
599	};
600
601	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
602	.cmd_rcgr = 0x27618,
603	.mnd_width = 16,
604	.hid_width = 5,
605	.parent_map = gcc_parent_map_0,
606	.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
607	.hw_clk_ctrl = true,
608	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
609	};
610
611	static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
612	.name = "gcc_qupv3_wrap0_s6_clk_src",
613	.parent_data = gcc_parent_data_0,
614	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
615	.flags = CLK_SET_RATE_PARENT,
616	.ops = &clk_rcg2_ops,
617	};
618
619	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
620	.cmd_rcgr = 0x2774c,
621	.mnd_width = 16,
622	.hid_width = 5,
623	.parent_map = gcc_parent_map_0,
624	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
625	.hw_clk_ctrl = true,
626	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
627	};
628
629	static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
630	.name = "gcc_qupv3_wrap0_s7_clk_src",
631	.parent_data = gcc_parent_data_0,
632	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
633	.flags = CLK_SET_RATE_PARENT,
634	.ops = &clk_rcg2_ops,
635	};
636
637	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
638	.cmd_rcgr = 0x27880,
639	.mnd_width = 16,
640	.hid_width = 5,
641	.parent_map = gcc_parent_map_0,
642	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
643	.hw_clk_ctrl = true,
644	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
645	};
646
647	static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
648	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
649	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
650	F(19200000, P_BI_TCXO, 1, 0, 0),
651	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
652	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
653	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
654	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
655	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
656	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
657	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
658	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
659	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
660	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
661	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
662	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
663	{ }
664	};
665
666	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
667	.name = "gcc_qupv3_wrap1_s0_clk_src",
668	.parent_data = gcc_parent_data_0,
669	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
670	.flags = CLK_SET_RATE_PARENT,
671	.ops = &clk_rcg2_ops,
672	};
673
674	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
675	.cmd_rcgr = 0x28014,
676	.mnd_width = 16,
677	.hid_width = 5,
678	.parent_map = gcc_parent_map_0,
679	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
680	.hw_clk_ctrl = true,
681	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
682	};
683
684	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
685	.name = "gcc_qupv3_wrap1_s1_clk_src",
686	.parent_data = gcc_parent_data_0,
687	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
688	.flags = CLK_SET_RATE_PARENT,
689	.ops = &clk_rcg2_ops,
690	};
691
692	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
693	.cmd_rcgr = 0x28148,
694	.mnd_width = 16,
695	.hid_width = 5,
696	.parent_map = gcc_parent_map_0,
697	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
698	.hw_clk_ctrl = true,
699	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
700	};
701
702	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
703	.name = "gcc_qupv3_wrap1_s2_clk_src",
704	.parent_data = gcc_parent_data_0,
705	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
706	.flags = CLK_SET_RATE_PARENT,
707	.ops = &clk_rcg2_ops,
708	};
709
710	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
711	.cmd_rcgr = 0x2827c,
712	.mnd_width = 16,
713	.hid_width = 5,
714	.parent_map = gcc_parent_map_0,
715	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
716	.hw_clk_ctrl = true,
717	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
718	};
719
720	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
721	.name = "gcc_qupv3_wrap1_s3_clk_src",
722	.parent_data = gcc_parent_data_0,
723	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
724	.flags = CLK_SET_RATE_PARENT,
725	.ops = &clk_rcg2_ops,
726	};
727
728	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
729	.cmd_rcgr = 0x283b0,
730	.mnd_width = 16,
731	.hid_width = 5,
732	.parent_map = gcc_parent_map_0,
733	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
734	.hw_clk_ctrl = true,
735	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
736	};
737
738	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
739	.name = "gcc_qupv3_wrap1_s4_clk_src",
740	.parent_data = gcc_parent_data_0,
741	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
742	.flags = CLK_SET_RATE_PARENT,
743	.ops = &clk_rcg2_ops,
744	};
745
746	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
747	.cmd_rcgr = 0x284e4,
748	.mnd_width = 16,
749	.hid_width = 5,
750	.parent_map = gcc_parent_map_0,
751	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
752	.hw_clk_ctrl = true,
753	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
754	};
755
756	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
757	.name = "gcc_qupv3_wrap1_s5_clk_src",
758	.parent_data = gcc_parent_data_0,
759	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
760	.flags = CLK_SET_RATE_PARENT,
761	.ops = &clk_rcg2_ops,
762	};
763
764	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
765	.cmd_rcgr = 0x28618,
766	.mnd_width = 16,
767	.hid_width = 5,
768	.parent_map = gcc_parent_map_0,
769	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
770	.hw_clk_ctrl = true,
771	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
772	};
773
774	static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
775	.name = "gcc_qupv3_wrap1_s6_clk_src",
776	.parent_data = gcc_parent_data_0,
777	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
778	.flags = CLK_SET_RATE_PARENT,
779	.ops = &clk_rcg2_ops,
780	};
781
782	static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
783	.cmd_rcgr = 0x2874c,
784	.mnd_width = 16,
785	.hid_width = 5,
786	.parent_map = gcc_parent_map_0,
787	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
788	.hw_clk_ctrl = true,
789	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
790	};
791
792	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
793	.name = "gcc_qupv3_wrap2_s0_clk_src",
794	.parent_data = gcc_parent_data_0,
795	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
796	.flags = CLK_SET_RATE_PARENT,
797	.ops = &clk_rcg2_ops,
798	};
799
800	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
801	.cmd_rcgr = 0x2e014,
802	.mnd_width = 16,
803	.hid_width = 5,
804	.parent_map = gcc_parent_map_0,
805	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
806	.hw_clk_ctrl = true,
807	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
808	};
809
810	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
811	.name = "gcc_qupv3_wrap2_s1_clk_src",
812	.parent_data = gcc_parent_data_0,
813	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
814	.flags = CLK_SET_RATE_PARENT,
815	.ops = &clk_rcg2_ops,
816	};
817
818	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
819	.cmd_rcgr = 0x2e148,
820	.mnd_width = 16,
821	.hid_width = 5,
822	.parent_map = gcc_parent_map_0,
823	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
824	.hw_clk_ctrl = true,
825	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
826	};
827
828	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
829	.name = "gcc_qupv3_wrap2_s2_clk_src",
830	.parent_data = gcc_parent_data_0,
831	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
832	.flags = CLK_SET_RATE_PARENT,
833	.ops = &clk_rcg2_ops,
834	};
835
836	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
837	.cmd_rcgr = 0x2e27c,
838	.mnd_width = 16,
839	.hid_width = 5,
840	.parent_map = gcc_parent_map_0,
841	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
842	.hw_clk_ctrl = true,
843	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
844	};
845
846	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
847	.name = "gcc_qupv3_wrap2_s3_clk_src",
848	.parent_data = gcc_parent_data_0,
849	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
850	.flags = CLK_SET_RATE_PARENT,
851	.ops = &clk_rcg2_ops,
852	};
853
854	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
855	.cmd_rcgr = 0x2e3b0,
856	.mnd_width = 16,
857	.hid_width = 5,
858	.parent_map = gcc_parent_map_0,
859	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
860	.hw_clk_ctrl = true,
861	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
862	};
863
864	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
865	.name = "gcc_qupv3_wrap2_s4_clk_src",
866	.parent_data = gcc_parent_data_0,
867	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
868	.flags = CLK_SET_RATE_PARENT,
869	.ops = &clk_rcg2_ops,
870	};
871
872	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
873	.cmd_rcgr = 0x2e4e4,
874	.mnd_width = 16,
875	.hid_width = 5,
876	.parent_map = gcc_parent_map_0,
877	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
878	.hw_clk_ctrl = true,
879	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
880	};
881
882	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
883	.name = "gcc_qupv3_wrap2_s5_clk_src",
884	.parent_data = gcc_parent_data_0,
885	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
886	.flags = CLK_SET_RATE_PARENT,
887	.ops = &clk_rcg2_ops,
888	};
889
890	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
891	.cmd_rcgr = 0x2e618,
892	.mnd_width = 16,
893	.hid_width = 5,
894	.parent_map = gcc_parent_map_0,
895	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
896	.hw_clk_ctrl = true,
897	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
898	};
899
900	static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
901	.name = "gcc_qupv3_wrap2_s6_clk_src",
902	.parent_data = gcc_parent_data_0,
903	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
904	.flags = CLK_SET_RATE_PARENT,
905	.ops = &clk_rcg2_ops,
906	};
907
908	static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
909	.cmd_rcgr = 0x2e74c,
910	.mnd_width = 16,
911	.hid_width = 5,
912	.parent_map = gcc_parent_map_0,
913	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
914	.hw_clk_ctrl = true,
915	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
916	};
917
918	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
919	F(400000, P_BI_TCXO, 12, 1, 4),
920	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
921	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
922	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
923	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
924	{ }
925	};
926
927	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
928	.cmd_rcgr = 0x24014,
929	.mnd_width = 8,
930	.hid_width = 5,
931	.parent_map = gcc_parent_map_7,
932	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
933	.hw_clk_ctrl = true,
934	.clkr.hw.init = &(struct clk_init_data){
935	.name = "gcc_sdcc2_apps_clk_src",
936	.parent_data = gcc_parent_data_7,
937	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
938	.flags = CLK_SET_RATE_PARENT,
939	.ops = &clk_rcg2_floor_ops,
940	},
941	};
942
943	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
944	F(400000, P_BI_TCXO, 12, 1, 4),
945	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
946	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
947	{ }
948	};
949
950	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
951	.cmd_rcgr = 0x26014,
952	.mnd_width = 8,
953	.hid_width = 5,
954	.parent_map = gcc_parent_map_0,
955	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
956	.hw_clk_ctrl = true,
957	.clkr.hw.init = &(struct clk_init_data){
958	.name = "gcc_sdcc4_apps_clk_src",
959	.parent_data = gcc_parent_data_0,
960	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
961	.flags = CLK_SET_RATE_PARENT,
962	.ops = &clk_rcg2_floor_ops,
963	},
964	};
965
966	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
967	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
968	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
969	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
970	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
971	{ }
972	};
973
974	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
975	.cmd_rcgr = 0x8702c,
976	.mnd_width = 8,
977	.hid_width = 5,
978	.parent_map = gcc_parent_map_0,
979	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
980	.hw_clk_ctrl = true,
981	.clkr.hw.init = &(struct clk_init_data){
982	.name = "gcc_ufs_phy_axi_clk_src",
983	.parent_data = gcc_parent_data_0,
984	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
985	.flags = CLK_SET_RATE_PARENT,
986	.ops = &clk_rcg2_ops,
987	},
988	};
989
990	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
991	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
992	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
993	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
994	{ }
995	};
996
997	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
998	.cmd_rcgr = 0x87074,
999	.mnd_width = 0,
1000	.hid_width = 5,
1001	.parent_map = gcc_parent_map_0,
1002	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1003	.hw_clk_ctrl = true,
1004	.clkr.hw.init = &(struct clk_init_data){
1005	.name = "gcc_ufs_phy_ice_core_clk_src",
1006	.parent_data = gcc_parent_data_0,
1007	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1008	.flags = CLK_SET_RATE_PARENT,
1009	.ops = &clk_rcg2_ops,
1010	},
1011	};
1012
1013	static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1014	F(9600000, P_BI_TCXO, 2, 0, 0),
1015	F(19200000, P_BI_TCXO, 1, 0, 0),
1016	{ }
1017	};
1018
1019	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1020	.cmd_rcgr = 0x870a8,
1021	.mnd_width = 0,
1022	.hid_width = 5,
1023	.parent_map = gcc_parent_map_3,
1024	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1025	.hw_clk_ctrl = true,
1026	.clkr.hw.init = &(struct clk_init_data){
1027	.name = "gcc_ufs_phy_phy_aux_clk_src",
1028	.parent_data = gcc_parent_data_3,
1029	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1030	.flags = CLK_SET_RATE_PARENT,
1031	.ops = &clk_rcg2_ops,
1032	},
1033	};
1034
1035	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1036	.cmd_rcgr = 0x8708c,
1037	.mnd_width = 0,
1038	.hid_width = 5,
1039	.parent_map = gcc_parent_map_0,
1040	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1041	.hw_clk_ctrl = true,
1042	.clkr.hw.init = &(struct clk_init_data){
1043	.name = "gcc_ufs_phy_unipro_core_clk_src",
1044	.parent_data = gcc_parent_data_0,
1045	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1046	.flags = CLK_SET_RATE_PARENT,
1047	.ops = &clk_rcg2_ops,
1048	},
1049	};
1050
1051	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1052	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1053	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1054	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1055	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1056	{ }
1057	};
1058
1059	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1060	.cmd_rcgr = 0x49028,
1061	.mnd_width = 8,
1062	.hid_width = 5,
1063	.parent_map = gcc_parent_map_0,
1064	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1065	.hw_clk_ctrl = true,
1066	.clkr.hw.init = &(struct clk_init_data){
1067	.name = "gcc_usb30_prim_master_clk_src",
1068	.parent_data = gcc_parent_data_0,
1069	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070	.flags = CLK_SET_RATE_PARENT,
1071	.ops = &clk_rcg2_ops,
1072	},
1073	};
1074
1075	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1076	.cmd_rcgr = 0x49040,
1077	.mnd_width = 0,
1078	.hid_width = 5,
1079	.parent_map = gcc_parent_map_0,
1080	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1081	.hw_clk_ctrl = true,
1082	.clkr.hw.init = &(struct clk_init_data){
1083	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1084	.parent_data = gcc_parent_data_0,
1085	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1086	.flags = CLK_SET_RATE_PARENT,
1087	.ops = &clk_rcg2_ops,
1088	},
1089	};
1090
1091	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1092	.cmd_rcgr = 0x4906c,
1093	.mnd_width = 0,
1094	.hid_width = 5,
1095	.parent_map = gcc_parent_map_2,
1096	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1097	.hw_clk_ctrl = true,
1098	.clkr.hw.init = &(struct clk_init_data){
1099	.name = "gcc_usb3_prim_phy_aux_clk_src",
1100	.parent_data = gcc_parent_data_2,
1101	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1102	.flags = CLK_SET_RATE_PARENT,
1103	.ops = &clk_rcg2_ops,
1104	},
1105	};
1106
1107	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1108	.reg = 0x49058,
1109	.shift = 0,
1110	.width = 4,
1111	.clkr.hw.init = &(struct clk_init_data) {
1112	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1113	.parent_hws = (const struct clk_hw*[]) {
1114	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1115	},
1116	.num_parents = 1,
1117	.flags = CLK_SET_RATE_PARENT,
1118	.ops = &clk_regmap_div_ro_ops,
1119	},
1120	};
1121
1122	static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1123	.halt_reg = 0x7b08c,
1124	.halt_check = BRANCH_HALT_SKIP,
1125	.hwcg_reg = 0x7b08c,
1126	.hwcg_bit = 1,
1127	.clkr = {
1128	.enable_reg = 0x62000,
1129	.enable_mask = BIT(12),
1130	.hw.init = &(struct clk_init_data){
1131	.name = "gcc_aggre_noc_pcie_0_axi_clk",
1132	.ops = &clk_branch2_ops,
1133	},
1134	},
1135	};
1136
1137	static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1138	.halt_reg = 0x9d098,
1139	.halt_check = BRANCH_HALT_SKIP,
1140	.hwcg_reg = 0x9d098,
1141	.hwcg_bit = 1,
1142	.clkr = {
1143	.enable_reg = 0x62000,
1144	.enable_mask = BIT(11),
1145	.hw.init = &(struct clk_init_data){
1146	.name = "gcc_aggre_noc_pcie_1_axi_clk",
1147	.ops = &clk_branch2_ops,
1148	},
1149	},
1150	};
1151
1152	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1153	.halt_reg = 0x870d4,
1154	.halt_check = BRANCH_HALT_VOTED,
1155	.hwcg_reg = 0x870d4,
1156	.hwcg_bit = 1,
1157	.clkr = {
1158	.enable_reg = 0x870d4,
1159	.enable_mask = BIT(0),
1160	.hw.init = &(struct clk_init_data){
1161	.name = "gcc_aggre_ufs_phy_axi_clk",
1162	.parent_hws = (const struct clk_hw*[]) {
1163	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1164	},
1165	.num_parents = 1,
1166	.flags = CLK_SET_RATE_PARENT,
1167	.ops = &clk_branch2_ops,
1168	},
1169	},
1170	};
1171
1172	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1173	.halt_reg = 0x870d4,
1174	.halt_check = BRANCH_HALT_VOTED,
1175	.hwcg_reg = 0x870d4,
1176	.hwcg_bit = 1,
1177	.clkr = {
1178	.enable_reg = 0x870d4,
1179	.enable_mask = BIT(1),
1180	.hw.init = &(struct clk_init_data){
1181	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1182	.parent_hws = (const struct clk_hw*[]) {
1183	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1184	},
1185	.num_parents = 1,
1186	.flags = CLK_SET_RATE_PARENT,
1187	.ops = &clk_branch2_ops,
1188	},
1189	},
1190	};
1191
1192	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1193	.halt_reg = 0x49088,
1194	.halt_check = BRANCH_HALT_VOTED,
1195	.hwcg_reg = 0x49088,
1196	.hwcg_bit = 1,
1197	.clkr = {
1198	.enable_reg = 0x49088,
1199	.enable_mask = BIT(0),
1200	.hw.init = &(struct clk_init_data){
1201	.name = "gcc_aggre_usb3_prim_axi_clk",
1202	.parent_hws = (const struct clk_hw*[]) {
1203	&gcc_usb30_prim_master_clk_src.clkr.hw,
1204	},
1205	.num_parents = 1,
1206	.flags = CLK_SET_RATE_PARENT,
1207	.ops = &clk_branch2_ops,
1208	},
1209	},
1210	};
1211
1212	static struct clk_branch gcc_boot_rom_ahb_clk = {
1213	.halt_reg = 0x48004,
1214	.halt_check = BRANCH_HALT_VOTED,
1215	.hwcg_reg = 0x48004,
1216	.hwcg_bit = 1,
1217	.clkr = {
1218	.enable_reg = 0x62000,
1219	.enable_mask = BIT(10),
1220	.hw.init = &(struct clk_init_data){
1221	.name = "gcc_boot_rom_ahb_clk",
1222	.ops = &clk_branch2_ops,
1223	},
1224	},
1225	};
1226
1227	static struct clk_branch gcc_camera_hf_axi_clk = {
1228	.halt_reg = 0x36010,
1229	.halt_check = BRANCH_HALT_SKIP,
1230	.hwcg_reg = 0x36010,
1231	.hwcg_bit = 1,
1232	.clkr = {
1233	.enable_reg = 0x36010,
1234	.enable_mask = BIT(0),
1235	.hw.init = &(struct clk_init_data){
1236	.name = "gcc_camera_hf_axi_clk",
1237	.ops = &clk_branch2_ops,
1238	},
1239	},
1240	};
1241
1242	static struct clk_branch gcc_camera_sf_axi_clk = {
1243	.halt_reg = 0x36018,
1244	.halt_check = BRANCH_HALT_SKIP,
1245	.hwcg_reg = 0x36018,
1246	.hwcg_bit = 1,
1247	.clkr = {
1248	.enable_reg = 0x36018,
1249	.enable_mask = BIT(0),
1250	.hw.init = &(struct clk_init_data){
1251	.name = "gcc_camera_sf_axi_clk",
1252	.ops = &clk_branch2_ops,
1253	},
1254	},
1255	};
1256
1257	static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1258	.halt_reg = 0x20030,
1259	.halt_check = BRANCH_HALT_VOTED,
1260	.hwcg_reg = 0x20030,
1261	.hwcg_bit = 1,
1262	.clkr = {
1263	.enable_reg = 0x62000,
1264	.enable_mask = BIT(20),
1265	.hw.init = &(struct clk_init_data){
1266	.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1267	.ops = &clk_branch2_ops,
1268	},
1269	},
1270	};
1271
1272	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1273	.halt_reg = 0x49084,
1274	.halt_check = BRANCH_HALT_VOTED,
1275	.hwcg_reg = 0x49084,
1276	.hwcg_bit = 1,
1277	.clkr = {
1278	.enable_reg = 0x49084,
1279	.enable_mask = BIT(0),
1280	.hw.init = &(struct clk_init_data){
1281	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1282	.parent_hws = (const struct clk_hw*[]) {
1283	&gcc_usb30_prim_master_clk_src.clkr.hw,
1284	},
1285	.num_parents = 1,
1286	.flags = CLK_SET_RATE_PARENT,
1287	.ops = &clk_branch2_ops,
1288	},
1289	},
1290	};
1291
1292	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1293	.halt_reg = 0x81154,
1294	.halt_check = BRANCH_HALT_SKIP,
1295	.hwcg_reg = 0x81154,
1296	.hwcg_bit = 1,
1297	.clkr = {
1298	.enable_reg = 0x81154,
1299	.enable_mask = BIT(0),
1300	.hw.init = &(struct clk_init_data){
1301	.name = "gcc_ddrss_gpu_axi_clk",
1302	.ops = &clk_branch2_aon_ops,
1303	},
1304	},
1305	};
1306
1307	static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1308	.halt_reg = 0x9d094,
1309	.halt_check = BRANCH_HALT_SKIP,
1310	.hwcg_reg = 0x9d094,
1311	.hwcg_bit = 1,
1312	.clkr = {
1313	.enable_reg = 0x62000,
1314	.enable_mask = BIT(19),
1315	.hw.init = &(struct clk_init_data){
1316	.name = "gcc_ddrss_pcie_sf_tbu_clk",
1317	.ops = &clk_branch2_ops,
1318	},
1319	},
1320	};
1321
1322	static struct clk_branch gcc_disp_hf_axi_clk = {
1323	.halt_reg = 0x3700c,
1324	.halt_check = BRANCH_HALT_SKIP,
1325	.hwcg_reg = 0x3700c,
1326	.hwcg_bit = 1,
1327	.clkr = {
1328	.enable_reg = 0x3700c,
1329	.enable_mask = BIT(0),
1330	.hw.init = &(struct clk_init_data){
1331	.name = "gcc_disp_hf_axi_clk",
1332	.ops = &clk_branch2_ops,
1333	},
1334	},
1335	};
1336
1337	static struct clk_branch gcc_disp_sf_axi_clk = {
1338	.halt_reg = 0x37014,
1339	.halt_check = BRANCH_HALT_SKIP,
1340	.hwcg_reg = 0x37014,
1341	.hwcg_bit = 1,
1342	.clkr = {
1343	.enable_reg = 0x37014,
1344	.enable_mask = BIT(0),
1345	.hw.init = &(struct clk_init_data){
1346	.name = "gcc_disp_sf_axi_clk",
1347	.ops = &clk_branch2_ops,
1348	},
1349	},
1350	};
1351
1352	static struct clk_branch gcc_eusb3_0_clkref_en = {
1353	.halt_reg = 0x9c00c,
1354	.halt_check = BRANCH_HALT,
1355	.clkr = {
1356	.enable_reg = 0x9c00c,
1357	.enable_mask = BIT(0),
1358	.hw.init = &(struct clk_init_data){
1359	.name = "gcc_eusb3_0_clkref_en",
1360	.ops = &clk_branch2_ops,
1361	},
1362	},
1363	};
1364
1365	static struct clk_branch gcc_gp1_clk = {
1366	.halt_reg = 0x74000,
1367	.halt_check = BRANCH_HALT,
1368	.clkr = {
1369	.enable_reg = 0x74000,
1370	.enable_mask = BIT(0),
1371	.hw.init = &(struct clk_init_data){
1372	.name = "gcc_gp1_clk",
1373	.parent_hws = (const struct clk_hw*[]) {
1374	&gcc_gp1_clk_src.clkr.hw,
1375	},
1376	.num_parents = 1,
1377	.flags = CLK_SET_RATE_PARENT,
1378	.ops = &clk_branch2_ops,
1379	},
1380	},
1381	};
1382
1383	static struct clk_branch gcc_gp2_clk = {
1384	.halt_reg = 0x75000,
1385	.halt_check = BRANCH_HALT,
1386	.clkr = {
1387	.enable_reg = 0x75000,
1388	.enable_mask = BIT(0),
1389	.hw.init = &(struct clk_init_data){
1390	.name = "gcc_gp2_clk",
1391	.parent_hws = (const struct clk_hw*[]) {
1392	&gcc_gp2_clk_src.clkr.hw,
1393	},
1394	.num_parents = 1,
1395	.flags = CLK_SET_RATE_PARENT,
1396	.ops = &clk_branch2_ops,
1397	},
1398	},
1399	};
1400
1401	static struct clk_branch gcc_gp3_clk = {
1402	.halt_reg = 0x76000,
1403	.halt_check = BRANCH_HALT,
1404	.clkr = {
1405	.enable_reg = 0x76000,
1406	.enable_mask = BIT(0),
1407	.hw.init = &(struct clk_init_data){
1408	.name = "gcc_gp3_clk",
1409	.parent_hws = (const struct clk_hw*[]) {
1410	&gcc_gp3_clk_src.clkr.hw,
1411	},
1412	.num_parents = 1,
1413	.flags = CLK_SET_RATE_PARENT,
1414	.ops = &clk_branch2_ops,
1415	},
1416	},
1417	};
1418
1419	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1420	.halt_check = BRANCH_HALT_DELAY,
1421	.clkr = {
1422	.enable_reg = 0x62000,
1423	.enable_mask = BIT(15),
1424	.hw.init = &(struct clk_init_data){
1425	.name = "gcc_gpu_gpll0_clk_src",
1426	.parent_hws = (const struct clk_hw*[]) {
1427	&gcc_gpll0.clkr.hw,
1428	},
1429	.num_parents = 1,
1430	.flags = CLK_SET_RATE_PARENT,
1431	.ops = &clk_branch2_ops,
1432	},
1433	},
1434	};
1435
1436	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1437	.halt_check = BRANCH_HALT_DELAY,
1438	.clkr = {
1439	.enable_reg = 0x62000,
1440	.enable_mask = BIT(16),
1441	.hw.init = &(struct clk_init_data){
1442	.name = "gcc_gpu_gpll0_div_clk_src",
1443	.parent_hws = (const struct clk_hw*[]) {
1444	&gcc_gpll0_out_even.clkr.hw,
1445	},
1446	.num_parents = 1,
1447	.flags = CLK_SET_RATE_PARENT,
1448	.ops = &clk_branch2_ops,
1449	},
1450	},
1451	};
1452
1453	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1454	.halt_reg = 0x81010,
1455	.halt_check = BRANCH_HALT_VOTED,
1456	.hwcg_reg = 0x81010,
1457	.hwcg_bit = 1,
1458	.clkr = {
1459	.enable_reg = 0x81010,
1460	.enable_mask = BIT(0),
1461	.hw.init = &(struct clk_init_data){
1462	.name = "gcc_gpu_memnoc_gfx_clk",
1463	.ops = &clk_branch2_ops,
1464	},
1465	},
1466	};
1467
1468	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1469	.halt_reg = 0x81018,
1470	.halt_check = BRANCH_HALT_DELAY,
1471	.clkr = {
1472	.enable_reg = 0x81018,
1473	.enable_mask = BIT(0),
1474	.hw.init = &(struct clk_init_data){
1475	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1476	.ops = &clk_branch2_ops,
1477	},
1478	},
1479	};
1480
1481	static struct clk_branch gcc_pcie_0_aux_clk = {
1482	.halt_reg = 0x7b034,
1483	.halt_check = BRANCH_HALT_VOTED,
1484	.clkr = {
1485	.enable_reg = 0x62008,
1486	.enable_mask = BIT(3),
1487	.hw.init = &(struct clk_init_data){
1488	.name = "gcc_pcie_0_aux_clk",
1489	.parent_hws = (const struct clk_hw*[]) {
1490	&gcc_pcie_0_aux_clk_src.clkr.hw,
1491	},
1492	.num_parents = 1,
1493	.flags = CLK_SET_RATE_PARENT,
1494	.ops = &clk_branch2_ops,
1495	},
1496	},
1497	};
1498
1499	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1500	.halt_reg = 0x7b030,
1501	.halt_check = BRANCH_HALT_VOTED,
1502	.hwcg_reg = 0x7b030,
1503	.hwcg_bit = 1,
1504	.clkr = {
1505	.enable_reg = 0x62008,
1506	.enable_mask = BIT(2),
1507	.hw.init = &(struct clk_init_data){
1508	.name = "gcc_pcie_0_cfg_ahb_clk",
1509	.ops = &clk_branch2_ops,
1510	},
1511	},
1512	};
1513
1514	static struct clk_branch gcc_pcie_0_clkref_en = {
1515	.halt_reg = 0x9c004,
1516	.halt_check = BRANCH_HALT,
1517	.clkr = {
1518	.enable_reg = 0x9c004,
1519	.enable_mask = BIT(0),
1520	.hw.init = &(struct clk_init_data){
1521	.name = "gcc_pcie_0_clkref_en",
1522	.ops = &clk_branch2_ops,
1523	},
1524	},
1525	};
1526
1527	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1528	.halt_reg = 0x7b028,
1529	.halt_check = BRANCH_HALT_SKIP,
1530	.clkr = {
1531	.enable_reg = 0x62008,
1532	.enable_mask = BIT(1),
1533	.hw.init = &(struct clk_init_data){
1534	.name = "gcc_pcie_0_mstr_axi_clk",
1535	.ops = &clk_branch2_ops,
1536	},
1537	},
1538	};
1539
1540	static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1541	.halt_reg = 0x7b044,
1542	.halt_check = BRANCH_HALT_VOTED,
1543	.clkr = {
1544	.enable_reg = 0x62000,
1545	.enable_mask = BIT(22),
1546	.hw.init = &(struct clk_init_data){
1547	.name = "gcc_pcie_0_phy_rchng_clk",
1548	.parent_hws = (const struct clk_hw*[]) {
1549	&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1550	},
1551	.num_parents = 1,
1552	.flags = CLK_SET_RATE_PARENT,
1553	.ops = &clk_branch2_ops,
1554	},
1555	},
1556	};
1557
1558	static struct clk_branch gcc_pcie_0_pipe_clk = {
1559	.halt_reg = 0x7b03c,
1560	.halt_check = BRANCH_HALT_SKIP,
1561	.clkr = {
1562	.enable_reg = 0x62008,
1563	.enable_mask = BIT(4),
1564	.hw.init = &(struct clk_init_data){
1565	.name = "gcc_pcie_0_pipe_clk",
1566	.parent_hws = (const struct clk_hw*[]) {
1567	&gcc_pcie_0_pipe_clk_src.clkr.hw,
1568	},
1569	.num_parents = 1,
1570	.flags = CLK_SET_RATE_PARENT,
1571	.ops = &clk_branch2_ops,
1572	},
1573	},
1574	};
1575
1576	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1577	.halt_reg = 0x7b020,
1578	.halt_check = BRANCH_HALT_VOTED,
1579	.hwcg_reg = 0x7b020,
1580	.hwcg_bit = 1,
1581	.clkr = {
1582	.enable_reg = 0x62008,
1583	.enable_mask = BIT(0),
1584	.hw.init = &(struct clk_init_data){
1585	.name = "gcc_pcie_0_slv_axi_clk",
1586	.ops = &clk_branch2_ops,
1587	},
1588	},
1589	};
1590
1591	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1592	.halt_reg = 0x7b01c,
1593	.halt_check = BRANCH_HALT_VOTED,
1594	.clkr = {
1595	.enable_reg = 0x62008,
1596	.enable_mask = BIT(5),
1597	.hw.init = &(struct clk_init_data){
1598	.name = "gcc_pcie_0_slv_q2a_axi_clk",
1599	.ops = &clk_branch2_ops,
1600	},
1601	},
1602	};
1603
1604	static struct clk_branch gcc_pcie_1_aux_clk = {
1605	.halt_reg = 0x9d030,
1606	.halt_check = BRANCH_HALT_VOTED,
1607	.clkr = {
1608	.enable_reg = 0x62000,
1609	.enable_mask = BIT(29),
1610	.hw.init = &(struct clk_init_data){
1611	.name = "gcc_pcie_1_aux_clk",
1612	.parent_hws = (const struct clk_hw*[]) {
1613	&gcc_pcie_1_aux_clk_src.clkr.hw,
1614	},
1615	.num_parents = 1,
1616	.flags = CLK_SET_RATE_PARENT,
1617	.ops = &clk_branch2_ops,
1618	},
1619	},
1620	};
1621
1622	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1623	.halt_reg = 0x9d02c,
1624	.halt_check = BRANCH_HALT_VOTED,
1625	.hwcg_reg = 0x9d02c,
1626	.hwcg_bit = 1,
1627	.clkr = {
1628	.enable_reg = 0x62000,
1629	.enable_mask = BIT(28),
1630	.hw.init = &(struct clk_init_data){
1631	.name = "gcc_pcie_1_cfg_ahb_clk",
1632	.ops = &clk_branch2_ops,
1633	},
1634	},
1635	};
1636
1637	static struct clk_branch gcc_pcie_1_clkref_en = {
1638	.halt_reg = 0x9c008,
1639	.halt_check = BRANCH_HALT,
1640	.clkr = {
1641	.enable_reg = 0x9c008,
1642	.enable_mask = BIT(0),
1643	.hw.init = &(struct clk_init_data){
1644	.name = "gcc_pcie_1_clkref_en",
1645	.ops = &clk_branch2_ops,
1646	},
1647	},
1648	};
1649
1650	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1651	.halt_reg = 0x9d024,
1652	.halt_check = BRANCH_HALT_SKIP,
1653	.clkr = {
1654	.enable_reg = 0x62000,
1655	.enable_mask = BIT(27),
1656	.hw.init = &(struct clk_init_data){
1657	.name = "gcc_pcie_1_mstr_axi_clk",
1658	.ops = &clk_branch2_ops,
1659	},
1660	},
1661	};
1662
1663	static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1664	.halt_reg = 0x9d038,
1665	.halt_check = BRANCH_HALT_VOTED,
1666	.clkr = {
1667	.enable_reg = 0x62000,
1668	.enable_mask = BIT(24),
1669	.hw.init = &(struct clk_init_data){
1670	.name = "gcc_pcie_1_phy_aux_clk",
1671	.parent_hws = (const struct clk_hw*[]) {
1672	&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1673	},
1674	.num_parents = 1,
1675	.flags = CLK_SET_RATE_PARENT,
1676	.ops = &clk_branch2_ops,
1677	},
1678	},
1679	};
1680
1681	static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1682	.halt_reg = 0x9d048,
1683	.halt_check = BRANCH_HALT_VOTED,
1684	.clkr = {
1685	.enable_reg = 0x62000,
1686	.enable_mask = BIT(23),
1687	.hw.init = &(struct clk_init_data){
1688	.name = "gcc_pcie_1_phy_rchng_clk",
1689	.parent_hws = (const struct clk_hw*[]) {
1690	&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1691	},
1692	.num_parents = 1,
1693	.flags = CLK_SET_RATE_PARENT,
1694	.ops = &clk_branch2_ops,
1695	},
1696	},
1697	};
1698
1699	static struct clk_branch gcc_pcie_1_pipe_clk = {
1700	.halt_reg = 0x9d040,
1701	.halt_check = BRANCH_HALT_SKIP,
1702	.clkr = {
1703	.enable_reg = 0x62000,
1704	.enable_mask = BIT(30),
1705	.hw.init = &(struct clk_init_data){
1706	.name = "gcc_pcie_1_pipe_clk",
1707	.parent_hws = (const struct clk_hw*[]) {
1708	&gcc_pcie_1_pipe_clk_src.clkr.hw,
1709	},
1710	.num_parents = 1,
1711	.flags = CLK_SET_RATE_PARENT,
1712	.ops = &clk_branch2_ops,
1713	},
1714	},
1715	};
1716
1717	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1718	.halt_reg = 0x9d01c,
1719	.halt_check = BRANCH_HALT_VOTED,
1720	.hwcg_reg = 0x9d01c,
1721	.hwcg_bit = 1,
1722	.clkr = {
1723	.enable_reg = 0x62000,
1724	.enable_mask = BIT(26),
1725	.hw.init = &(struct clk_init_data){
1726	.name = "gcc_pcie_1_slv_axi_clk",
1727	.ops = &clk_branch2_ops,
1728	},
1729	},
1730	};
1731
1732	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1733	.halt_reg = 0x9d018,
1734	.halt_check = BRANCH_HALT_VOTED,
1735	.clkr = {
1736	.enable_reg = 0x62000,
1737	.enable_mask = BIT(25),
1738	.hw.init = &(struct clk_init_data){
1739	.name = "gcc_pcie_1_slv_q2a_axi_clk",
1740	.ops = &clk_branch2_ops,
1741	},
1742	},
1743	};
1744
1745	static struct clk_branch gcc_pdm2_clk = {
1746	.halt_reg = 0x4300c,
1747	.halt_check = BRANCH_HALT,
1748	.clkr = {
1749	.enable_reg = 0x4300c,
1750	.enable_mask = BIT(0),
1751	.hw.init = &(struct clk_init_data){
1752	.name = "gcc_pdm2_clk",
1753	.parent_hws = (const struct clk_hw*[]) {
1754	&gcc_pdm2_clk_src.clkr.hw,
1755	},
1756	.num_parents = 1,
1757	.flags = CLK_SET_RATE_PARENT,
1758	.ops = &clk_branch2_ops,
1759	},
1760	},
1761	};
1762
1763	static struct clk_branch gcc_pdm_ahb_clk = {
1764	.halt_reg = 0x43004,
1765	.halt_check = BRANCH_HALT_VOTED,
1766	.hwcg_reg = 0x43004,
1767	.hwcg_bit = 1,
1768	.clkr = {
1769	.enable_reg = 0x43004,
1770	.enable_mask = BIT(0),
1771	.hw.init = &(struct clk_init_data){
1772	.name = "gcc_pdm_ahb_clk",
1773	.ops = &clk_branch2_ops,
1774	},
1775	},
1776	};
1777
1778	static struct clk_branch gcc_pdm_xo4_clk = {
1779	.halt_reg = 0x43008,
1780	.halt_check = BRANCH_HALT,
1781	.clkr = {
1782	.enable_reg = 0x43008,
1783	.enable_mask = BIT(0),
1784	.hw.init = &(struct clk_init_data){
1785	.name = "gcc_pdm_xo4_clk",
1786	.ops = &clk_branch2_ops,
1787	},
1788	},
1789	};
1790
1791	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1792	.halt_reg = 0x36008,
1793	.halt_check = BRANCH_HALT_VOTED,
1794	.hwcg_reg = 0x36008,
1795	.hwcg_bit = 1,
1796	.clkr = {
1797	.enable_reg = 0x36008,
1798	.enable_mask = BIT(0),
1799	.hw.init = &(struct clk_init_data){
1800	.name = "gcc_qmip_camera_nrt_ahb_clk",
1801	.ops = &clk_branch2_ops,
1802	},
1803	},
1804	};
1805
1806	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1807	.halt_reg = 0x3600c,
1808	.halt_check = BRANCH_HALT_VOTED,
1809	.hwcg_reg = 0x3600c,
1810	.hwcg_bit = 1,
1811	.clkr = {
1812	.enable_reg = 0x3600c,
1813	.enable_mask = BIT(0),
1814	.hw.init = &(struct clk_init_data){
1815	.name = "gcc_qmip_camera_rt_ahb_clk",
1816	.ops = &clk_branch2_ops,
1817	},
1818	},
1819	};
1820
1821	static struct clk_branch gcc_qmip_disp_ahb_clk = {
1822	.halt_reg = 0x37008,
1823	.halt_check = BRANCH_HALT_VOTED,
1824	.hwcg_reg = 0x37008,
1825	.hwcg_bit = 1,
1826	.clkr = {
1827	.enable_reg = 0x37008,
1828	.enable_mask = BIT(0),
1829	.hw.init = &(struct clk_init_data){
1830	.name = "gcc_qmip_disp_ahb_clk",
1831	.ops = &clk_branch2_ops,
1832	},
1833	},
1834	};
1835
1836	static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1837	.halt_reg = 0x81008,
1838	.halt_check = BRANCH_HALT_VOTED,
1839	.hwcg_reg = 0x81008,
1840	.hwcg_bit = 1,
1841	.clkr = {
1842	.enable_reg = 0x81008,
1843	.enable_mask = BIT(0),
1844	.hw.init = &(struct clk_init_data){
1845	.name = "gcc_qmip_gpu_ahb_clk",
1846	.ops = &clk_branch2_ops,
1847	},
1848	},
1849	};
1850
1851	static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1852	.halt_reg = 0x7b018,
1853	.halt_check = BRANCH_HALT_VOTED,
1854	.hwcg_reg = 0x7b018,
1855	.hwcg_bit = 1,
1856	.clkr = {
1857	.enable_reg = 0x7b018,
1858	.enable_mask = BIT(0),
1859	.hw.init = &(struct clk_init_data){
1860	.name = "gcc_qmip_pcie_ahb_clk",
1861	.ops = &clk_branch2_ops,
1862	},
1863	},
1864	};
1865
1866	static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1867	.halt_reg = 0x42014,
1868	.halt_check = BRANCH_HALT_VOTED,
1869	.hwcg_reg = 0x42014,
1870	.hwcg_bit = 1,
1871	.clkr = {
1872	.enable_reg = 0x42014,
1873	.enable_mask = BIT(0),
1874	.hw.init = &(struct clk_init_data){
1875	.name = "gcc_qmip_video_cv_cpu_ahb_clk",
1876	.ops = &clk_branch2_ops,
1877	},
1878	},
1879	};
1880
1881	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1882	.halt_reg = 0x42008,
1883	.halt_check = BRANCH_HALT_VOTED,
1884	.hwcg_reg = 0x42008,
1885	.hwcg_bit = 1,
1886	.clkr = {
1887	.enable_reg = 0x42008,
1888	.enable_mask = BIT(0),
1889	.hw.init = &(struct clk_init_data){
1890	.name = "gcc_qmip_video_cvp_ahb_clk",
1891	.ops = &clk_branch2_ops,
1892	},
1893	},
1894	};
1895
1896	static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1897	.halt_reg = 0x42010,
1898	.halt_check = BRANCH_HALT_VOTED,
1899	.hwcg_reg = 0x42010,
1900	.hwcg_bit = 1,
1901	.clkr = {
1902	.enable_reg = 0x42010,
1903	.enable_mask = BIT(0),
1904	.hw.init = &(struct clk_init_data){
1905	.name = "gcc_qmip_video_v_cpu_ahb_clk",
1906	.ops = &clk_branch2_ops,
1907	},
1908	},
1909	};
1910
1911	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1912	.halt_reg = 0x4200c,
1913	.halt_check = BRANCH_HALT_VOTED,
1914	.hwcg_reg = 0x4200c,
1915	.hwcg_bit = 1,
1916	.clkr = {
1917	.enable_reg = 0x4200c,
1918	.enable_mask = BIT(0),
1919	.hw.init = &(struct clk_init_data){
1920	.name = "gcc_qmip_video_vcodec_ahb_clk",
1921	.ops = &clk_branch2_ops,
1922	},
1923	},
1924	};
1925
1926	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1927	.halt_reg = 0x3300c,
1928	.halt_check = BRANCH_HALT_VOTED,
1929	.clkr = {
1930	.enable_reg = 0x62008,
1931	.enable_mask = BIT(9),
1932	.hw.init = &(struct clk_init_data){
1933	.name = "gcc_qupv3_wrap0_core_2x_clk",
1934	.ops = &clk_branch2_ops,
1935	},
1936	},
1937	};
1938
1939	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1940	.halt_reg = 0x33000,
1941	.halt_check = BRANCH_HALT_VOTED,
1942	.clkr = {
1943	.enable_reg = 0x62008,
1944	.enable_mask = BIT(8),
1945	.hw.init = &(struct clk_init_data){
1946	.name = "gcc_qupv3_wrap0_core_clk",
1947	.ops = &clk_branch2_ops,
1948	},
1949	},
1950	};
1951
1952	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1953	.halt_reg = 0x2700c,
1954	.halt_check = BRANCH_HALT_VOTED,
1955	.clkr = {
1956	.enable_reg = 0x62008,
1957	.enable_mask = BIT(10),
1958	.hw.init = &(struct clk_init_data){
1959	.name = "gcc_qupv3_wrap0_s0_clk",
1960	.parent_hws = (const struct clk_hw*[]) {
1961	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1962	},
1963	.num_parents = 1,
1964	.flags = CLK_SET_RATE_PARENT,
1965	.ops = &clk_branch2_ops,
1966	},
1967	},
1968	};
1969
1970	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1971	.halt_reg = 0x27140,
1972	.halt_check = BRANCH_HALT_VOTED,
1973	.clkr = {
1974	.enable_reg = 0x62008,
1975	.enable_mask = BIT(11),
1976	.hw.init = &(struct clk_init_data){
1977	.name = "gcc_qupv3_wrap0_s1_clk",
1978	.parent_hws = (const struct clk_hw*[]) {
1979	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1980	},
1981	.num_parents = 1,
1982	.flags = CLK_SET_RATE_PARENT,
1983	.ops = &clk_branch2_ops,
1984	},
1985	},
1986	};
1987
1988	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1989	.halt_reg = 0x27274,
1990	.halt_check = BRANCH_HALT_VOTED,
1991	.clkr = {
1992	.enable_reg = 0x62008,
1993	.enable_mask = BIT(12),
1994	.hw.init = &(struct clk_init_data){
1995	.name = "gcc_qupv3_wrap0_s2_clk",
1996	.parent_hws = (const struct clk_hw*[]) {
1997	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1998	},
1999	.num_parents = 1,
2000	.flags = CLK_SET_RATE_PARENT,
2001	.ops = &clk_branch2_ops,
2002	},
2003	},
2004	};
2005
2006	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2007	.halt_reg = 0x273a8,
2008	.halt_check = BRANCH_HALT_VOTED,
2009	.clkr = {
2010	.enable_reg = 0x62008,
2011	.enable_mask = BIT(13),
2012	.hw.init = &(struct clk_init_data){
2013	.name = "gcc_qupv3_wrap0_s3_clk",
2014	.parent_hws = (const struct clk_hw*[]) {
2015	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2016	},
2017	.num_parents = 1,
2018	.flags = CLK_SET_RATE_PARENT,
2019	.ops = &clk_branch2_ops,
2020	},
2021	},
2022	};
2023
2024	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2025	.halt_reg = 0x274dc,
2026	.halt_check = BRANCH_HALT_VOTED,
2027	.clkr = {
2028	.enable_reg = 0x62008,
2029	.enable_mask = BIT(14),
2030	.hw.init = &(struct clk_init_data){
2031	.name = "gcc_qupv3_wrap0_s4_clk",
2032	.parent_hws = (const struct clk_hw*[]) {
2033	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2034	},
2035	.num_parents = 1,
2036	.flags = CLK_SET_RATE_PARENT,
2037	.ops = &clk_branch2_ops,
2038	},
2039	},
2040	};
2041
2042	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2043	.halt_reg = 0x27610,
2044	.halt_check = BRANCH_HALT_VOTED,
2045	.clkr = {
2046	.enable_reg = 0x62008,
2047	.enable_mask = BIT(15),
2048	.hw.init = &(struct clk_init_data){
2049	.name = "gcc_qupv3_wrap0_s5_clk",
2050	.parent_hws = (const struct clk_hw*[]) {
2051	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2052	},
2053	.num_parents = 1,
2054	.flags = CLK_SET_RATE_PARENT,
2055	.ops = &clk_branch2_ops,
2056	},
2057	},
2058	};
2059
2060	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2061	.halt_reg = 0x27744,
2062	.halt_check = BRANCH_HALT_VOTED,
2063	.clkr = {
2064	.enable_reg = 0x62008,
2065	.enable_mask = BIT(16),
2066	.hw.init = &(struct clk_init_data){
2067	.name = "gcc_qupv3_wrap0_s6_clk",
2068	.parent_hws = (const struct clk_hw*[]) {
2069	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2070	},
2071	.num_parents = 1,
2072	.flags = CLK_SET_RATE_PARENT,
2073	.ops = &clk_branch2_ops,
2074	},
2075	},
2076	};
2077
2078	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2079	.halt_reg = 0x27878,
2080	.halt_check = BRANCH_HALT_VOTED,
2081	.clkr = {
2082	.enable_reg = 0x62008,
2083	.enable_mask = BIT(17),
2084	.hw.init = &(struct clk_init_data){
2085	.name = "gcc_qupv3_wrap0_s7_clk",
2086	.parent_hws = (const struct clk_hw*[]) {
2087	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2088	},
2089	.num_parents = 1,
2090	.flags = CLK_SET_RATE_PARENT,
2091	.ops = &clk_branch2_ops,
2092	},
2093	},
2094	};
2095
2096	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2097	.halt_reg = 0x3314c,
2098	.halt_check = BRANCH_HALT_VOTED,
2099	.clkr = {
2100	.enable_reg = 0x62008,
2101	.enable_mask = BIT(18),
2102	.hw.init = &(struct clk_init_data){
2103	.name = "gcc_qupv3_wrap1_core_2x_clk",
2104	.ops = &clk_branch2_ops,
2105	},
2106	},
2107	};
2108
2109	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2110	.halt_reg = 0x33140,
2111	.halt_check = BRANCH_HALT_VOTED,
2112	.clkr = {
2113	.enable_reg = 0x62008,
2114	.enable_mask = BIT(19),
2115	.hw.init = &(struct clk_init_data){
2116	.name = "gcc_qupv3_wrap1_core_clk",
2117	.ops = &clk_branch2_ops,
2118	},
2119	},
2120	};
2121
2122	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2123	.halt_reg = 0x2800c,
2124	.halt_check = BRANCH_HALT_VOTED,
2125	.clkr = {
2126	.enable_reg = 0x62008,
2127	.enable_mask = BIT(22),
2128	.hw.init = &(struct clk_init_data){
2129	.name = "gcc_qupv3_wrap1_s0_clk",
2130	.parent_hws = (const struct clk_hw*[]) {
2131	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2132	},
2133	.num_parents = 1,
2134	.flags = CLK_SET_RATE_PARENT,
2135	.ops = &clk_branch2_ops,
2136	},
2137	},
2138	};
2139
2140	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2141	.halt_reg = 0x28140,
2142	.halt_check = BRANCH_HALT_VOTED,
2143	.clkr = {
2144	.enable_reg = 0x62008,
2145	.enable_mask = BIT(23),
2146	.hw.init = &(struct clk_init_data){
2147	.name = "gcc_qupv3_wrap1_s1_clk",
2148	.parent_hws = (const struct clk_hw*[]) {
2149	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2150	},
2151	.num_parents = 1,
2152	.flags = CLK_SET_RATE_PARENT,
2153	.ops = &clk_branch2_ops,
2154	},
2155	},
2156	};
2157
2158	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2159	.halt_reg = 0x28274,
2160	.halt_check = BRANCH_HALT_VOTED,
2161	.clkr = {
2162	.enable_reg = 0x62008,
2163	.enable_mask = BIT(24),
2164	.hw.init = &(struct clk_init_data){
2165	.name = "gcc_qupv3_wrap1_s2_clk",
2166	.parent_hws = (const struct clk_hw*[]) {
2167	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2168	},
2169	.num_parents = 1,
2170	.flags = CLK_SET_RATE_PARENT,
2171	.ops = &clk_branch2_ops,
2172	},
2173	},
2174	};
2175
2176	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2177	.halt_reg = 0x283a8,
2178	.halt_check = BRANCH_HALT_VOTED,
2179	.clkr = {
2180	.enable_reg = 0x62008,
2181	.enable_mask = BIT(25),
2182	.hw.init = &(struct clk_init_data){
2183	.name = "gcc_qupv3_wrap1_s3_clk",
2184	.parent_hws = (const struct clk_hw*[]) {
2185	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2186	},
2187	.num_parents = 1,
2188	.flags = CLK_SET_RATE_PARENT,
2189	.ops = &clk_branch2_ops,
2190	},
2191	},
2192	};
2193
2194	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2195	.halt_reg = 0x284dc,
2196	.halt_check = BRANCH_HALT_VOTED,
2197	.clkr = {
2198	.enable_reg = 0x62008,
2199	.enable_mask = BIT(26),
2200	.hw.init = &(struct clk_init_data){
2201	.name = "gcc_qupv3_wrap1_s4_clk",
2202	.parent_hws = (const struct clk_hw*[]) {
2203	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2204	},
2205	.num_parents = 1,
2206	.flags = CLK_SET_RATE_PARENT,
2207	.ops = &clk_branch2_ops,
2208	},
2209	},
2210	};
2211
2212	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2213	.halt_reg = 0x28610,
2214	.halt_check = BRANCH_HALT_VOTED,
2215	.clkr = {
2216	.enable_reg = 0x62008,
2217	.enable_mask = BIT(27),
2218	.hw.init = &(struct clk_init_data){
2219	.name = "gcc_qupv3_wrap1_s5_clk",
2220	.parent_hws = (const struct clk_hw*[]) {
2221	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2222	},
2223	.num_parents = 1,
2224	.flags = CLK_SET_RATE_PARENT,
2225	.ops = &clk_branch2_ops,
2226	},
2227	},
2228	};
2229
2230	static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2231	.halt_reg = 0x28744,
2232	.halt_check = BRANCH_HALT_VOTED,
2233	.clkr = {
2234	.enable_reg = 0x62008,
2235	.enable_mask = BIT(28),
2236	.hw.init = &(struct clk_init_data){
2237	.name = "gcc_qupv3_wrap1_s6_clk",
2238	.parent_hws = (const struct clk_hw*[]) {
2239	&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2240	},
2241	.num_parents = 1,
2242	.flags = CLK_SET_RATE_PARENT,
2243	.ops = &clk_branch2_ops,
2244	},
2245	},
2246	};
2247
2248	static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2249	.halt_reg = 0x3328c,
2250	.halt_check = BRANCH_HALT_VOTED,
2251	.clkr = {
2252	.enable_reg = 0x62010,
2253	.enable_mask = BIT(3),
2254	.hw.init = &(struct clk_init_data){
2255	.name = "gcc_qupv3_wrap2_core_2x_clk",
2256	.ops = &clk_branch2_ops,
2257	},
2258	},
2259	};
2260
2261	static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2262	.halt_reg = 0x33280,
2263	.halt_check = BRANCH_HALT_VOTED,
2264	.clkr = {
2265	.enable_reg = 0x62010,
2266	.enable_mask = BIT(0),
2267	.hw.init = &(struct clk_init_data){
2268	.name = "gcc_qupv3_wrap2_core_clk",
2269	.ops = &clk_branch2_ops,
2270	},
2271	},
2272	};
2273
2274	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2275	.halt_reg = 0x2e00c,
2276	.halt_check = BRANCH_HALT_VOTED,
2277	.clkr = {
2278	.enable_reg = 0x62010,
2279	.enable_mask = BIT(4),
2280	.hw.init = &(struct clk_init_data){
2281	.name = "gcc_qupv3_wrap2_s0_clk",
2282	.parent_hws = (const struct clk_hw*[]) {
2283	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2284	},
2285	.num_parents = 1,
2286	.flags = CLK_SET_RATE_PARENT,
2287	.ops = &clk_branch2_ops,
2288	},
2289	},
2290	};
2291
2292	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2293	.halt_reg = 0x2e140,
2294	.halt_check = BRANCH_HALT_VOTED,
2295	.clkr = {
2296	.enable_reg = 0x62010,
2297	.enable_mask = BIT(5),
2298	.hw.init = &(struct clk_init_data){
2299	.name = "gcc_qupv3_wrap2_s1_clk",
2300	.parent_hws = (const struct clk_hw*[]) {
2301	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2302	},
2303	.num_parents = 1,
2304	.flags = CLK_SET_RATE_PARENT,
2305	.ops = &clk_branch2_ops,
2306	},
2307	},
2308	};
2309
2310	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2311	.halt_reg = 0x2e274,
2312	.halt_check = BRANCH_HALT_VOTED,
2313	.clkr = {
2314	.enable_reg = 0x62010,
2315	.enable_mask = BIT(6),
2316	.hw.init = &(struct clk_init_data){
2317	.name = "gcc_qupv3_wrap2_s2_clk",
2318	.parent_hws = (const struct clk_hw*[]) {
2319	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2320	},
2321	.num_parents = 1,
2322	.flags = CLK_SET_RATE_PARENT,
2323	.ops = &clk_branch2_ops,
2324	},
2325	},
2326	};
2327
2328	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2329	.halt_reg = 0x2e3a8,
2330	.halt_check = BRANCH_HALT_VOTED,
2331	.clkr = {
2332	.enable_reg = 0x62010,
2333	.enable_mask = BIT(7),
2334	.hw.init = &(struct clk_init_data){
2335	.name = "gcc_qupv3_wrap2_s3_clk",
2336	.parent_hws = (const struct clk_hw*[]) {
2337	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2338	},
2339	.num_parents = 1,
2340	.flags = CLK_SET_RATE_PARENT,
2341	.ops = &clk_branch2_ops,
2342	},
2343	},
2344	};
2345
2346	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2347	.halt_reg = 0x2e4dc,
2348	.halt_check = BRANCH_HALT_VOTED,
2349	.clkr = {
2350	.enable_reg = 0x62010,
2351	.enable_mask = BIT(8),
2352	.hw.init = &(struct clk_init_data){
2353	.name = "gcc_qupv3_wrap2_s4_clk",
2354	.parent_hws = (const struct clk_hw*[]) {
2355	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2356	},
2357	.num_parents = 1,
2358	.flags = CLK_SET_RATE_PARENT,
2359	.ops = &clk_branch2_ops,
2360	},
2361	},
2362	};
2363
2364	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2365	.halt_reg = 0x2e610,
2366	.halt_check = BRANCH_HALT_VOTED,
2367	.clkr = {
2368	.enable_reg = 0x62010,
2369	.enable_mask = BIT(9),
2370	.hw.init = &(struct clk_init_data){
2371	.name = "gcc_qupv3_wrap2_s5_clk",
2372	.parent_hws = (const struct clk_hw*[]) {
2373	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2374	},
2375	.num_parents = 1,
2376	.flags = CLK_SET_RATE_PARENT,
2377	.ops = &clk_branch2_ops,
2378	},
2379	},
2380	};
2381
2382	static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2383	.halt_reg = 0x2e744,
2384	.halt_check = BRANCH_HALT_VOTED,
2385	.clkr = {
2386	.enable_reg = 0x62010,
2387	.enable_mask = BIT(10),
2388	.hw.init = &(struct clk_init_data){
2389	.name = "gcc_qupv3_wrap2_s6_clk",
2390	.parent_hws = (const struct clk_hw*[]) {
2391	&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2392	},
2393	.num_parents = 1,
2394	.flags = CLK_SET_RATE_PARENT,
2395	.ops = &clk_branch2_ops,
2396	},
2397	},
2398	};
2399
2400	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2401	.halt_reg = 0x27004,
2402	.halt_check = BRANCH_HALT_VOTED,
2403	.hwcg_reg = 0x27004,
2404	.hwcg_bit = 1,
2405	.clkr = {
2406	.enable_reg = 0x62008,
2407	.enable_mask = BIT(6),
2408	.hw.init = &(struct clk_init_data){
2409	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2410	.ops = &clk_branch2_ops,
2411	},
2412	},
2413	};
2414
2415	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2416	.halt_reg = 0x27008,
2417	.halt_check = BRANCH_HALT_VOTED,
2418	.hwcg_reg = 0x27008,
2419	.hwcg_bit = 1,
2420	.clkr = {
2421	.enable_reg = 0x62008,
2422	.enable_mask = BIT(7),
2423	.hw.init = &(struct clk_init_data){
2424	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2425	.ops = &clk_branch2_ops,
2426	},
2427	},
2428	};
2429
2430	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2431	.halt_reg = 0x28004,
2432	.halt_check = BRANCH_HALT_VOTED,
2433	.hwcg_reg = 0x28004,
2434	.hwcg_bit = 1,
2435	.clkr = {
2436	.enable_reg = 0x62008,
2437	.enable_mask = BIT(20),
2438	.hw.init = &(struct clk_init_data){
2439	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2440	.ops = &clk_branch2_ops,
2441	},
2442	},
2443	};
2444
2445	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2446	.halt_reg = 0x28008,
2447	.halt_check = BRANCH_HALT_VOTED,
2448	.hwcg_reg = 0x28008,
2449	.hwcg_bit = 1,
2450	.clkr = {
2451	.enable_reg = 0x62008,
2452	.enable_mask = BIT(21),
2453	.hw.init = &(struct clk_init_data){
2454	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2455	.ops = &clk_branch2_ops,
2456	},
2457	},
2458	};
2459
2460	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2461	.halt_reg = 0x2e004,
2462	.halt_check = BRANCH_HALT_VOTED,
2463	.hwcg_reg = 0x2e004,
2464	.hwcg_bit = 1,
2465	.clkr = {
2466	.enable_reg = 0x62010,
2467	.enable_mask = BIT(2),
2468	.hw.init = &(struct clk_init_data){
2469	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2470	.ops = &clk_branch2_ops,
2471	},
2472	},
2473	};
2474
2475	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2476	.halt_reg = 0x2e008,
2477	.halt_check = BRANCH_HALT_VOTED,
2478	.hwcg_reg = 0x2e008,
2479	.hwcg_bit = 1,
2480	.clkr = {
2481	.enable_reg = 0x62010,
2482	.enable_mask = BIT(1),
2483	.hw.init = &(struct clk_init_data){
2484	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2485	.ops = &clk_branch2_ops,
2486	},
2487	},
2488	};
2489
2490	static struct clk_branch gcc_sdcc2_ahb_clk = {
2491	.halt_reg = 0x2400c,
2492	.halt_check = BRANCH_HALT,
2493	.clkr = {
2494	.enable_reg = 0x2400c,
2495	.enable_mask = BIT(0),
2496	.hw.init = &(struct clk_init_data){
2497	.name = "gcc_sdcc2_ahb_clk",
2498	.ops = &clk_branch2_ops,
2499	},
2500	},
2501	};
2502
2503	static struct clk_branch gcc_sdcc2_apps_clk = {
2504	.halt_reg = 0x24004,
2505	.halt_check = BRANCH_HALT,
2506	.clkr = {
2507	.enable_reg = 0x24004,
2508	.enable_mask = BIT(0),
2509	.hw.init = &(struct clk_init_data){
2510	.name = "gcc_sdcc2_apps_clk",
2511	.parent_hws = (const struct clk_hw*[]) {
2512	&gcc_sdcc2_apps_clk_src.clkr.hw,
2513	},
2514	.num_parents = 1,
2515	.flags = CLK_SET_RATE_PARENT,
2516	.ops = &clk_branch2_ops,
2517	},
2518	},
2519	};
2520
2521	static struct clk_branch gcc_sdcc2_at_clk = {
2522	.halt_reg = 0x24010,
2523	.halt_check = BRANCH_HALT_VOTED,
2524	.hwcg_reg = 0x24010,
2525	.hwcg_bit = 1,
2526	.clkr = {
2527	.enable_reg = 0x24010,
2528	.enable_mask = BIT(0),
2529	.hw.init = &(struct clk_init_data){
2530	.name = "gcc_sdcc2_at_clk",
2531	.ops = &clk_branch2_ops,
2532	},
2533	},
2534	};
2535
2536	static struct clk_branch gcc_sdcc4_ahb_clk = {
2537	.halt_reg = 0x2600c,
2538	.halt_check = BRANCH_HALT,
2539	.clkr = {
2540	.enable_reg = 0x2600c,
2541	.enable_mask = BIT(0),
2542	.hw.init = &(struct clk_init_data){
2543	.name = "gcc_sdcc4_ahb_clk",
2544	.ops = &clk_branch2_ops,
2545	},
2546	},
2547	};
2548
2549	static struct clk_branch gcc_sdcc4_apps_clk = {
2550	.halt_reg = 0x26004,
2551	.halt_check = BRANCH_HALT,
2552	.clkr = {
2553	.enable_reg = 0x26004,
2554	.enable_mask = BIT(0),
2555	.hw.init = &(struct clk_init_data){
2556	.name = "gcc_sdcc4_apps_clk",
2557	.parent_hws = (const struct clk_hw*[]) {
2558	&gcc_sdcc4_apps_clk_src.clkr.hw,
2559	},
2560	.num_parents = 1,
2561	.flags = CLK_SET_RATE_PARENT,
2562	.ops = &clk_branch2_ops,
2563	},
2564	},
2565	};
2566
2567	static struct clk_branch gcc_sdcc4_at_clk = {
2568	.halt_reg = 0x26010,
2569	.halt_check = BRANCH_HALT_VOTED,
2570	.hwcg_reg = 0x26010,
2571	.hwcg_bit = 1,
2572	.clkr = {
2573	.enable_reg = 0x26010,
2574	.enable_mask = BIT(0),
2575	.hw.init = &(struct clk_init_data){
2576	.name = "gcc_sdcc4_at_clk",
2577	.ops = &clk_branch2_ops,
2578	},
2579	},
2580	};
2581
2582	static struct clk_branch gcc_ufs_0_clkref_en = {
2583	.halt_reg = 0x9c000,
2584	.halt_check = BRANCH_HALT,
2585	.clkr = {
2586	.enable_reg = 0x9c000,
2587	.enable_mask = BIT(0),
2588	.hw.init = &(struct clk_init_data){
2589	.name = "gcc_ufs_0_clkref_en",
2590	.ops = &clk_branch2_ops,
2591	},
2592	},
2593	};
2594
2595	static struct clk_branch gcc_ufs_phy_ahb_clk = {
2596	.halt_reg = 0x87020,
2597	.halt_check = BRANCH_HALT_VOTED,
2598	.hwcg_reg = 0x87020,
2599	.hwcg_bit = 1,
2600	.clkr = {
2601	.enable_reg = 0x87020,
2602	.enable_mask = BIT(0),
2603	.hw.init = &(struct clk_init_data){
2604	.name = "gcc_ufs_phy_ahb_clk",
2605	.ops = &clk_branch2_ops,
2606	},
2607	},
2608	};
2609
2610	static struct clk_branch gcc_ufs_phy_axi_clk = {
2611	.halt_reg = 0x87018,
2612	.halt_check = BRANCH_HALT_VOTED,
2613	.hwcg_reg = 0x87018,
2614	.hwcg_bit = 1,
2615	.clkr = {
2616	.enable_reg = 0x87018,
2617	.enable_mask = BIT(0),
2618	.hw.init = &(struct clk_init_data){
2619	.name = "gcc_ufs_phy_axi_clk",
2620	.parent_hws = (const struct clk_hw*[]) {
2621	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2622	},
2623	.num_parents = 1,
2624	.flags = CLK_SET_RATE_PARENT,
2625	.ops = &clk_branch2_ops,
2626	},
2627	},
2628	};
2629
2630	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2631	.halt_reg = 0x87018,
2632	.halt_check = BRANCH_HALT_VOTED,
2633	.hwcg_reg = 0x87018,
2634	.hwcg_bit = 1,
2635	.clkr = {
2636	.enable_reg = 0x87018,
2637	.enable_mask = BIT(1),
2638	.hw.init = &(struct clk_init_data){
2639	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2640	.parent_hws = (const struct clk_hw*[]) {
2641	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2642	},
2643	.num_parents = 1,
2644	.flags = CLK_SET_RATE_PARENT,
2645	.ops = &clk_branch2_ops,
2646	},
2647	},
2648	};
2649
2650	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2651	.halt_reg = 0x8706c,
2652	.halt_check = BRANCH_HALT_VOTED,
2653	.hwcg_reg = 0x8706c,
2654	.hwcg_bit = 1,
2655	.clkr = {
2656	.enable_reg = 0x8706c,
2657	.enable_mask = BIT(0),
2658	.hw.init = &(struct clk_init_data){
2659	.name = "gcc_ufs_phy_ice_core_clk",
2660	.parent_hws = (const struct clk_hw*[]) {
2661	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2662	},
2663	.num_parents = 1,
2664	.flags = CLK_SET_RATE_PARENT,
2665	.ops = &clk_branch2_ops,
2666	},
2667	},
2668	};
2669
2670	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2671	.halt_reg = 0x8706c,
2672	.halt_check = BRANCH_HALT_VOTED,
2673	.hwcg_reg = 0x8706c,
2674	.hwcg_bit = 1,
2675	.clkr = {
2676	.enable_reg = 0x8706c,
2677	.enable_mask = BIT(1),
2678	.hw.init = &(struct clk_init_data){
2679	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2680	.parent_hws = (const struct clk_hw*[]) {
2681	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2682	},
2683	.num_parents = 1,
2684	.flags = CLK_SET_RATE_PARENT,
2685	.ops = &clk_branch2_ops,
2686	},
2687	},
2688	};
2689
2690	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2691	.halt_reg = 0x870a4,
2692	.halt_check = BRANCH_HALT_VOTED,
2693	.hwcg_reg = 0x870a4,
2694	.hwcg_bit = 1,
2695	.clkr = {
2696	.enable_reg = 0x870a4,
2697	.enable_mask = BIT(0),
2698	.hw.init = &(struct clk_init_data){
2699	.name = "gcc_ufs_phy_phy_aux_clk",
2700	.parent_hws = (const struct clk_hw*[]) {
2701	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2702	},
2703	.num_parents = 1,
2704	.flags = CLK_SET_RATE_PARENT,
2705	.ops = &clk_branch2_ops,
2706	},
2707	},
2708	};
2709
2710	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2711	.halt_reg = 0x870a4,
2712	.halt_check = BRANCH_HALT_VOTED,
2713	.hwcg_reg = 0x870a4,
2714	.hwcg_bit = 1,
2715	.clkr = {
2716	.enable_reg = 0x870a4,
2717	.enable_mask = BIT(1),
2718	.hw.init = &(struct clk_init_data){
2719	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2720	.parent_hws = (const struct clk_hw*[]) {
2721	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2722	},
2723	.num_parents = 1,
2724	.flags = CLK_SET_RATE_PARENT,
2725	.ops = &clk_branch2_ops,
2726	},
2727	},
2728	};
2729
2730	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2731	.halt_reg = 0x87028,
2732	.halt_check = BRANCH_HALT_DELAY,
2733	.clkr = {
2734	.enable_reg = 0x87028,
2735	.enable_mask = BIT(0),
2736	.hw.init = &(struct clk_init_data){
2737	.name = "gcc_ufs_phy_rx_symbol_0_clk",
2738	.parent_hws = (const struct clk_hw*[]) {
2739	&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2740	},
2741	.num_parents = 1,
2742	.flags = CLK_SET_RATE_PARENT,
2743	.ops = &clk_branch2_ops,
2744	},
2745	},
2746	};
2747
2748	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2749	.halt_reg = 0x870c0,
2750	.halt_check = BRANCH_HALT_DELAY,
2751	.clkr = {
2752	.enable_reg = 0x870c0,
2753	.enable_mask = BIT(0),
2754	.hw.init = &(struct clk_init_data){
2755	.name = "gcc_ufs_phy_rx_symbol_1_clk",
2756	.parent_hws = (const struct clk_hw*[]) {
2757	&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2758	},
2759	.num_parents = 1,
2760	.flags = CLK_SET_RATE_PARENT,
2761	.ops = &clk_branch2_ops,
2762	},
2763	},
2764	};
2765
2766	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2767	.halt_reg = 0x87024,
2768	.halt_check = BRANCH_HALT_DELAY,
2769	.clkr = {
2770	.enable_reg = 0x87024,
2771	.enable_mask = BIT(0),
2772	.hw.init = &(struct clk_init_data){
2773	.name = "gcc_ufs_phy_tx_symbol_0_clk",
2774	.parent_hws = (const struct clk_hw*[]) {
2775	&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2776	},
2777	.num_parents = 1,
2778	.flags = CLK_SET_RATE_PARENT,
2779	.ops = &clk_branch2_ops,
2780	},
2781	},
2782	};
2783
2784	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2785	.halt_reg = 0x87064,
2786	.halt_check = BRANCH_HALT_VOTED,
2787	.hwcg_reg = 0x87064,
2788	.hwcg_bit = 1,
2789	.clkr = {
2790	.enable_reg = 0x87064,
2791	.enable_mask = BIT(0),
2792	.hw.init = &(struct clk_init_data){
2793	.name = "gcc_ufs_phy_unipro_core_clk",
2794	.parent_hws = (const struct clk_hw*[]) {
2795	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2796	},
2797	.num_parents = 1,
2798	.flags = CLK_SET_RATE_PARENT,
2799	.ops = &clk_branch2_ops,
2800	},
2801	},
2802	};
2803
2804	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2805	.halt_reg = 0x87064,
2806	.halt_check = BRANCH_HALT_VOTED,
2807	.hwcg_reg = 0x87064,
2808	.hwcg_bit = 1,
2809	.clkr = {
2810	.enable_reg = 0x87064,
2811	.enable_mask = BIT(1),
2812	.hw.init = &(struct clk_init_data){
2813	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2814	.parent_hws = (const struct clk_hw*[]) {
2815	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2816	},
2817	.num_parents = 1,
2818	.flags = CLK_SET_RATE_PARENT,
2819	.ops = &clk_branch2_ops,
2820	},
2821	},
2822	};
2823
2824	static struct clk_branch gcc_usb30_prim_master_clk = {
2825	.halt_reg = 0x49018,
2826	.halt_check = BRANCH_HALT,
2827	.clkr = {
2828	.enable_reg = 0x49018,
2829	.enable_mask = BIT(0),
2830	.hw.init = &(struct clk_init_data){
2831	.name = "gcc_usb30_prim_master_clk",
2832	.parent_hws = (const struct clk_hw*[]) {
2833	&gcc_usb30_prim_master_clk_src.clkr.hw,
2834	},
2835	.num_parents = 1,
2836	.flags = CLK_SET_RATE_PARENT,
2837	.ops = &clk_branch2_ops,
2838	},
2839	},
2840	};
2841
2842	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2843	.halt_reg = 0x49024,
2844	.halt_check = BRANCH_HALT,
2845	.clkr = {
2846	.enable_reg = 0x49024,
2847	.enable_mask = BIT(0),
2848	.hw.init = &(struct clk_init_data){
2849	.name = "gcc_usb30_prim_mock_utmi_clk",
2850	.parent_hws = (const struct clk_hw*[]) {
2851	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2852	},
2853	.num_parents = 1,
2854	.flags = CLK_SET_RATE_PARENT,
2855	.ops = &clk_branch2_ops,
2856	},
2857	},
2858	};
2859
2860	static struct clk_branch gcc_usb30_prim_sleep_clk = {
2861	.halt_reg = 0x49020,
2862	.halt_check = BRANCH_HALT,
2863	.clkr = {
2864	.enable_reg = 0x49020,
2865	.enable_mask = BIT(0),
2866	.hw.init = &(struct clk_init_data){
2867	.name = "gcc_usb30_prim_sleep_clk",
2868	.ops = &clk_branch2_ops,
2869	},
2870	},
2871	};
2872
2873	static struct clk_branch gcc_usb3_0_clkref_en = {
2874	.halt_reg = 0x9c010,
2875	.halt_check = BRANCH_HALT,
2876	.clkr = {
2877	.enable_reg = 0x9c010,
2878	.enable_mask = BIT(0),
2879	.hw.init = &(struct clk_init_data){
2880	.name = "gcc_usb3_0_clkref_en",
2881	.ops = &clk_branch2_ops,
2882	},
2883	},
2884	};
2885
2886	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2887	.halt_reg = 0x4905c,
2888	.halt_check = BRANCH_HALT,
2889	.clkr = {
2890	.enable_reg = 0x4905c,
2891	.enable_mask = BIT(0),
2892	.hw.init = &(struct clk_init_data){
2893	.name = "gcc_usb3_prim_phy_aux_clk",
2894	.parent_hws = (const struct clk_hw*[]) {
2895	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2896	},
2897	.num_parents = 1,
2898	.flags = CLK_SET_RATE_PARENT,
2899	.ops = &clk_branch2_ops,
2900	},
2901	},
2902	};
2903
2904	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2905	.halt_reg = 0x49060,
2906	.halt_check = BRANCH_HALT,
2907	.clkr = {
2908	.enable_reg = 0x49060,
2909	.enable_mask = BIT(0),
2910	.hw.init = &(struct clk_init_data){
2911	.name = "gcc_usb3_prim_phy_com_aux_clk",
2912	.parent_hws = (const struct clk_hw*[]) {
2913	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2914	},
2915	.num_parents = 1,
2916	.flags = CLK_SET_RATE_PARENT,
2917	.ops = &clk_branch2_ops,
2918	},
2919	},
2920	};
2921
2922	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2923	.halt_reg = 0x49064,
2924	.halt_check = BRANCH_HALT_DELAY,
2925	.hwcg_reg = 0x49064,
2926	.hwcg_bit = 1,
2927	.clkr = {
2928	.enable_reg = 0x49064,
2929	.enable_mask = BIT(0),
2930	.hw.init = &(struct clk_init_data){
2931	.name = "gcc_usb3_prim_phy_pipe_clk",
2932	.parent_hws = (const struct clk_hw*[]) {
2933	&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2934	},
2935	.num_parents = 1,
2936	.flags = CLK_SET_RATE_PARENT,
2937	.ops = &clk_branch2_ops,
2938	},
2939	},
2940	};
2941
2942	static struct clk_branch gcc_video_axi0_clk = {
2943	.halt_reg = 0x42018,
2944	.halt_check = BRANCH_HALT_SKIP,
2945	.hwcg_reg = 0x42018,
2946	.hwcg_bit = 1,
2947	.clkr = {
2948	.enable_reg = 0x42018,
2949	.enable_mask = BIT(0),
2950	.hw.init = &(struct clk_init_data){
2951	.name = "gcc_video_axi0_clk",
2952	.ops = &clk_branch2_ops,
2953	},
2954	},
2955	};
2956
2957	static struct clk_branch gcc_video_axi1_clk = {
2958	.halt_reg = 0x42020,
2959	.halt_check = BRANCH_HALT_SKIP,
2960	.hwcg_reg = 0x42020,
2961	.hwcg_bit = 1,
2962	.clkr = {
2963	.enable_reg = 0x42020,
2964	.enable_mask = BIT(0),
2965	.hw.init = &(struct clk_init_data){
2966	.name = "gcc_video_axi1_clk",
2967	.ops = &clk_branch2_ops,
2968	},
2969	},
2970	};
2971
2972	static struct gdsc pcie_0_gdsc = {
2973	.gdscr = 0x7b004,
2974	.pd = {
2975	.name = "pcie_0_gdsc",
2976	},
2977	.pwrsts = PWRSTS_OFF_ON,
2978	};
2979
2980	static struct gdsc pcie_1_gdsc = {
2981	.gdscr = 0x9d004,
2982	.pd = {
2983	.name = "pcie_1_gdsc",
2984	},
2985	.pwrsts = PWRSTS_OFF_ON,
2986	};
2987
2988	static struct gdsc ufs_phy_gdsc = {
2989	.gdscr = 0x87004,
2990	.pd = {
2991	.name = "ufs_phy_gdsc",
2992	},
2993	.pwrsts = PWRSTS_OFF_ON,
2994	};
2995
2996	static struct gdsc usb30_prim_gdsc = {
2997	.gdscr = 0x49004,
2998	.pd = {
2999	.name = "usb30_prim_gdsc",
3000	},
3001	.pwrsts = PWRSTS_OFF_ON,
3002	};
3003
3004	static struct clk_regmap *gcc_sm8450_clocks[] = {
3005	[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3006	[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3007	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3008	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3009	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3010	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3011	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3012	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3013	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
3014	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3015	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3016	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3017	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3018	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3019	[GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
3020	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3021	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3022	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3023	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3024	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3025	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3026	[GCC_GPLL0] = &gcc_gpll0.clkr,
3027	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3028	[GCC_GPLL4] = &gcc_gpll4.clkr,
3029	[GCC_GPLL9] = &gcc_gpll9.clkr,
3030	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3031	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3032	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3033	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3034	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3035	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3036	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3037	[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3038	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3039	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3040	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3041	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3042	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3043	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3044	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3045	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3046	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3047	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3048	[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3049	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3050	[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3051	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3052	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3053	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3054	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3055	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3056	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3057	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3058	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3059	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3060	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3061	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3062	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3063	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3064	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3065	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3066	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3067	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3068	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3069	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3070	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3071	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3072	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3073	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3074	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3075	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3076	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3077	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3078	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3079	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3080	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3081	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3082	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3083	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3084	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3085	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3086	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3087	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3088	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3089	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3090	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3091	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3092	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3093	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3094	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3095	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3096	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3097	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3098	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3099	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3100	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3101	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3102	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3103	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3104	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3105	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3106	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3107	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3108	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3109	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3110	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3111	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3112	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3113	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3114	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3115	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3116	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3117	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3118	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3119	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3120	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3121	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3122	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3123	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3124	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3125	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3126	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3127	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3128	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3129	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3130	[GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
3131	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3132	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3133	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3134	[GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
3135	[GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
3136	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3137	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3138	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3139	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3140	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3141	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3142	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3143	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3144	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3145	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3146	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3147	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3148	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3149	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3150	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3151	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3152	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3153	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3154	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3155	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3156	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3157	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3158	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3159	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3160	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3161	[GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
3162	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3163	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3164	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3165	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3166	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3167	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3168	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3169	};
3170
3171	static const struct qcom_reset_map gcc_sm8450_resets[] = {
3172	[GCC_CAMERA_BCR] = { 0x36000 },
3173	[GCC_DISPLAY_BCR] = { 0x37000 },
3174	[GCC_GPU_BCR] = { 0x81000 },
3175	[GCC_PCIE_0_BCR] = { 0x7b000 },
3176	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3177	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3178	[GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3179	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3180	[GCC_PCIE_1_BCR] = { 0x9d000 },
3181	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3182	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3183	[GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3184	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3185	[GCC_PCIE_PHY_BCR] = { 0x7f000 },
3186	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3187	[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3188	[GCC_PDM_BCR] = { 0x43000 },
3189	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3190	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3191	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3192	[GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3193	[GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3194	[GCC_SDCC2_BCR] = { 0x24000 },
3195	[GCC_SDCC4_BCR] = { 0x26000 },
3196	[GCC_UFS_PHY_BCR] = { 0x87000 },
3197	[GCC_USB30_PRIM_BCR] = { 0x49000 },
3198	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3199	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3200	[GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3201	[GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3202	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3203	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3204	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3205	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
3206	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
3207	[GCC_VIDEO_BCR] = { 0x42000 },
3208	};
3209
3210	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3211	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3212	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3213	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3214	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3215	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3216	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3217	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3218	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3219	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3220	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3221	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3222	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3223	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3224	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3225	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3226	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3227	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3228	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3229	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3230	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3231	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3232	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3233	};
3234
3235	static struct gdsc *gcc_sm8450_gdscs[] = {
3236	[PCIE_0_GDSC] = &pcie_0_gdsc,
3237	[PCIE_1_GDSC] = &pcie_1_gdsc,
3238	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3239	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3240	};
3241
3242	static const struct regmap_config gcc_sm8450_regmap_config = {
3243	.reg_bits = 32,
3244	.reg_stride = 4,
3245	.val_bits = 32,
3246	.max_register = 0x1f1030,
3247	.fast_io = true,
3248	};
3249
3250	static const struct qcom_cc_desc gcc_sm8450_desc = {
3251	.config = &gcc_sm8450_regmap_config,
3252	.clks = gcc_sm8450_clocks,
3253	.num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
3254	.resets = gcc_sm8450_resets,
3255	.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
3256	.gdscs = gcc_sm8450_gdscs,
3257	.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
3258	};
3259
3260	static const struct of_device_id gcc_sm8450_match_table[] = {
3261	{ .compatible = "qcom,gcc-sm8450" },
3262	{ }
3263	};
3264	MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
3265
3266	static int gcc_sm8450_probe(struct platform_device *pdev)
3267	{
3268	struct regmap *regmap;
3269	int ret;
3270
3271	regmap = qcom_cc_map(pdev, desc: &gcc_sm8450_desc);
3272	if (IS_ERR(ptr: regmap))
3273	return PTR_ERR(ptr: regmap);
3274
3275	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
3276	ARRAY_SIZE(gcc_dfs_clocks));
3277	if (ret)
3278	return ret;
3279
3280	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3281	regmap_update_bits(map: regmap, reg: gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3282
3283	/* Keep some clocks always-on */
3284	qcom_branch_set_clk_en(regmap, cbcr: 0x36004); /* GCC_CAMERA_AHB_CLK */
3285	qcom_branch_set_clk_en(regmap, cbcr: 0x36020); /* GCC_CAMERA_XO_CLK */
3286	qcom_branch_set_clk_en(regmap, cbcr: 0x37004); /* GCC_DISP_AHB_CLK */
3287	qcom_branch_set_clk_en(regmap, cbcr: 0x3701c); /* GCC_DISP_XO_CLK */
3288	qcom_branch_set_clk_en(regmap, cbcr: 0x81004); /* GCC_GPU_CFG_AHB_CLK */
3289	qcom_branch_set_clk_en(regmap, cbcr: 0x42004); /* GCC_VIDEO_AHB_CLK */
3290	qcom_branch_set_clk_en(regmap, cbcr: 0x42028); /* GCC_VIDEO_XO_CLK */
3291
3292	return qcom_cc_really_probe(pdev, desc: &gcc_sm8450_desc, regmap);
3293	}
3294
3295	static struct platform_driver gcc_sm8450_driver = {
3296	.probe = gcc_sm8450_probe,
3297	.driver = {
3298	.name = "gcc-sm8450",
3299	.of_match_table = gcc_sm8450_match_table,
3300	},
3301	};
3302
3303	static int __init gcc_sm8450_init(void)
3304	{
3305	return platform_driver_register(&gcc_sm8450_driver);
3306	}
3307	subsys_initcall(gcc_sm8450_init);
3308
3309	static void __exit gcc_sm8450_exit(void)
3310	{
3311	platform_driver_unregister(&gcc_sm8450_driver);
3312	}
3313	module_exit(gcc_sm8450_exit);
3314
3315	MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
3316	MODULE_LICENSE("GPL v2");
3317