1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5	* Copyright (c) 2022, Linaro Limited
6	*/
7
8	#include <linux/clk-provider.h>
9	#include <linux/module.h>
10	#include <linux/of.h>
11	#include <linux/platform_device.h>
12	#include <linux/regmap.h>
13
14	#include <dt-bindings/clock/qcom,sm8550-gcc.h>
15
16	#include "clk-alpha-pll.h"
17	#include "clk-branch.h"
18	#include "clk-rcg.h"
19	#include "clk-regmap.h"
20	#include "clk-regmap-divider.h"
21	#include "clk-regmap-mux.h"
22	#include "clk-regmap-phy-mux.h"
23	#include "gdsc.h"
24	#include "reset.h"
25
26	enum {
27	DT_BI_TCXO,
28	DT_SLEEP_CLK,
29	DT_PCIE_0_PIPE,
30	DT_PCIE_1_PIPE,
31	DT_PCIE_1_PHY_AUX,
32	DT_UFS_PHY_RX_SYMBOL_0,
33	DT_UFS_PHY_RX_SYMBOL_1,
34	DT_UFS_PHY_TX_SYMBOL_0,
35	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
36	};
37
38	enum {
39	P_BI_TCXO,
40	P_GCC_GPLL0_OUT_EVEN,
41	P_GCC_GPLL0_OUT_MAIN,
42	P_GCC_GPLL4_OUT_MAIN,
43	P_GCC_GPLL7_OUT_MAIN,
44	P_GCC_GPLL9_OUT_MAIN,
45	P_PCIE_0_PIPE_CLK,
46	P_PCIE_1_PHY_AUX_CLK,
47	P_PCIE_1_PIPE_CLK,
48	P_SLEEP_CLK,
49	P_UFS_PHY_RX_SYMBOL_0_CLK,
50	P_UFS_PHY_RX_SYMBOL_1_CLK,
51	P_UFS_PHY_TX_SYMBOL_0_CLK,
52	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
53	};
54
55	static struct clk_alpha_pll gcc_gpll0 = {
56	.offset = 0x0,
57	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
58	.clkr = {
59	.enable_reg = 0x52018,
60	.enable_mask = BIT(0),
61	.hw.init = &(struct clk_init_data){
62	.name = "gcc_gpll0",
63	.parent_data = &(const struct clk_parent_data){
64	.index = DT_BI_TCXO,
65	},
66	.num_parents = 1,
67	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
68	},
69	},
70	};
71
72	static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
73	{ 0x1, 2 },
74	{ }
75	};
76
77	static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
78	.offset = 0x0,
79	.post_div_shift = 10,
80	.post_div_table = post_div_table_gcc_gpll0_out_even,
81	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
82	.width = 4,
83	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
84	.clkr.hw.init = &(struct clk_init_data){
85	.name = "gcc_gpll0_out_even",
86	.parent_hws = (const struct clk_hw*[]) {
87	&gcc_gpll0.clkr.hw,
88	},
89	.num_parents = 1,
90	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
91	},
92	};
93
94	static struct clk_alpha_pll gcc_gpll4 = {
95	.offset = 0x4000,
96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
97	.clkr = {
98	.enable_reg = 0x52018,
99	.enable_mask = BIT(4),
100	.hw.init = &(struct clk_init_data){
101	.name = "gcc_gpll4",
102	.parent_data = &(const struct clk_parent_data){
103	.index = DT_BI_TCXO,
104	},
105	.num_parents = 1,
106	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
107	},
108	},
109	};
110
111	static struct clk_alpha_pll gcc_gpll7 = {
112	.offset = 0x7000,
113	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
114	.clkr = {
115	.enable_reg = 0x52018,
116	.enable_mask = BIT(7),
117	.hw.init = &(struct clk_init_data){
118	.name = "gcc_gpll7",
119	.parent_data = &(const struct clk_parent_data){
120	.index = DT_BI_TCXO,
121	},
122	.num_parents = 1,
123	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
124	},
125	},
126	};
127
128	static struct clk_alpha_pll gcc_gpll9 = {
129	.offset = 0x9000,
130	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
131	.clkr = {
132	.enable_reg = 0x52018,
133	.enable_mask = BIT(9),
134	.hw.init = &(struct clk_init_data){
135	.name = "gcc_gpll9",
136	.parent_data = &(const struct clk_parent_data){
137	.index = DT_BI_TCXO,
138	},
139	.num_parents = 1,
140	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
141	},
142	},
143	};
144
145	static const struct parent_map gcc_parent_map_0[] = {
146	{ P_BI_TCXO, 0 },
147	{ P_GCC_GPLL0_OUT_MAIN, 1 },
148	{ P_GCC_GPLL0_OUT_EVEN, 6 },
149	};
150
151	static const struct clk_parent_data gcc_parent_data_0[] = {
152	{ .index = DT_BI_TCXO },
153	{ .hw = &gcc_gpll0.clkr.hw },
154	{ .hw = &gcc_gpll0_out_even.clkr.hw },
155	};
156
157	static const struct parent_map gcc_parent_map_1[] = {
158	{ P_BI_TCXO, 0 },
159	{ P_GCC_GPLL0_OUT_MAIN, 1 },
160	{ P_SLEEP_CLK, 5 },
161	{ P_GCC_GPLL0_OUT_EVEN, 6 },
162	};
163
164	static const struct clk_parent_data gcc_parent_data_1[] = {
165	{ .index = DT_BI_TCXO },
166	{ .hw = &gcc_gpll0.clkr.hw },
167	{ .index = DT_SLEEP_CLK },
168	{ .hw = &gcc_gpll0_out_even.clkr.hw },
169	};
170
171	static const struct parent_map gcc_parent_map_2[] = {
172	{ P_BI_TCXO, 0 },
173	{ P_SLEEP_CLK, 5 },
174	};
175
176	static const struct clk_parent_data gcc_parent_data_2[] = {
177	{ .index = DT_BI_TCXO },
178	{ .index = DT_SLEEP_CLK },
179	};
180
181	static const struct parent_map gcc_parent_map_3[] = {
182	{ P_BI_TCXO, 0 },
183	{ P_GCC_GPLL0_OUT_MAIN, 1 },
184	{ P_GCC_GPLL4_OUT_MAIN, 5 },
185	{ P_GCC_GPLL0_OUT_EVEN, 6 },
186	};
187
188	static const struct clk_parent_data gcc_parent_data_3[] = {
189	{ .index = DT_BI_TCXO },
190	{ .hw = &gcc_gpll0.clkr.hw },
191	{ .hw = &gcc_gpll4.clkr.hw },
192	{ .hw = &gcc_gpll0_out_even.clkr.hw },
193	};
194
195	static const struct parent_map gcc_parent_map_4[] = {
196	{ P_BI_TCXO, 0 },
197	};
198
199	static const struct clk_parent_data gcc_parent_data_4[] = {
200	{ .index = DT_BI_TCXO },
201	};
202
203	static const struct parent_map gcc_parent_map_6[] = {
204	{ P_PCIE_1_PHY_AUX_CLK, 0 },
205	{ P_BI_TCXO, 2 },
206	};
207
208	static const struct clk_parent_data gcc_parent_data_6[] = {
209	{ .index = DT_PCIE_1_PHY_AUX },
210	{ .index = DT_BI_TCXO },
211	};
212
213	static const struct parent_map gcc_parent_map_8[] = {
214	{ P_BI_TCXO, 0 },
215	{ P_GCC_GPLL0_OUT_MAIN, 1 },
216	{ P_GCC_GPLL7_OUT_MAIN, 2 },
217	{ P_GCC_GPLL0_OUT_EVEN, 6 },
218	};
219
220	static const struct clk_parent_data gcc_parent_data_8[] = {
221	{ .index = DT_BI_TCXO },
222	{ .hw = &gcc_gpll0.clkr.hw },
223	{ .hw = &gcc_gpll7.clkr.hw },
224	{ .hw = &gcc_gpll0_out_even.clkr.hw },
225	};
226
227	static const struct parent_map gcc_parent_map_9[] = {
228	{ P_BI_TCXO, 0 },
229	{ P_GCC_GPLL0_OUT_MAIN, 1 },
230	{ P_GCC_GPLL9_OUT_MAIN, 2 },
231	{ P_GCC_GPLL4_OUT_MAIN, 5 },
232	{ P_GCC_GPLL0_OUT_EVEN, 6 },
233	};
234
235	static const struct clk_parent_data gcc_parent_data_9[] = {
236	{ .index = DT_BI_TCXO },
237	{ .hw = &gcc_gpll0.clkr.hw },
238	{ .hw = &gcc_gpll9.clkr.hw },
239	{ .hw = &gcc_gpll4.clkr.hw },
240	{ .hw = &gcc_gpll0_out_even.clkr.hw },
241	};
242
243	static const struct parent_map gcc_parent_map_10[] = {
244	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
245	{ P_BI_TCXO, 2 },
246	};
247
248	static const struct clk_parent_data gcc_parent_data_10[] = {
249	{ .index = DT_UFS_PHY_RX_SYMBOL_0 },
250	{ .index = DT_BI_TCXO },
251	};
252
253	static const struct parent_map gcc_parent_map_11[] = {
254	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
255	{ P_BI_TCXO, 2 },
256	};
257
258	static const struct clk_parent_data gcc_parent_data_11[] = {
259	{ .index = DT_UFS_PHY_RX_SYMBOL_1 },
260	{ .index = DT_BI_TCXO },
261	};
262
263	static const struct parent_map gcc_parent_map_12[] = {
264	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
265	{ P_BI_TCXO, 2 },
266	};
267
268	static const struct clk_parent_data gcc_parent_data_12[] = {
269	{ .index = DT_UFS_PHY_TX_SYMBOL_0 },
270	{ .index = DT_BI_TCXO },
271	};
272
273	static const struct parent_map gcc_parent_map_13[] = {
274	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
275	{ P_BI_TCXO, 2 },
276	};
277
278	static const struct clk_parent_data gcc_parent_data_13[] = {
279	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
280	{ .index = DT_BI_TCXO },
281	};
282
283	static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
284	.reg = 0x6b070,
285	.clkr = {
286	.hw.init = &(struct clk_init_data){
287	.name = "gcc_pcie_0_pipe_clk_src",
288	.parent_data = &(const struct clk_parent_data){
289	.index = DT_PCIE_0_PIPE,
290	},
291	.num_parents = 1,
292	.ops = &clk_regmap_phy_mux_ops,
293	},
294	},
295	};
296
297	static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
298	.reg = 0x8d094,
299	.shift = 0,
300	.width = 2,
301	.parent_map = gcc_parent_map_6,
302	.clkr = {
303	.hw.init = &(struct clk_init_data){
304	.name = "gcc_pcie_1_phy_aux_clk_src",
305	.parent_data = gcc_parent_data_6,
306	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
307	.ops = &clk_regmap_mux_closest_ops,
308	},
309	},
310	};
311
312	static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
313	.reg = 0x8d078,
314	.clkr = {
315	.hw.init = &(struct clk_init_data){
316	.name = "gcc_pcie_1_pipe_clk_src",
317	.parent_data = &(const struct clk_parent_data){
318	.index = DT_PCIE_1_PIPE,
319	},
320	.num_parents = 1,
321	.ops = &clk_regmap_phy_mux_ops,
322	},
323	},
324	};
325
326	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
327	.reg = 0x77064,
328	.shift = 0,
329	.width = 2,
330	.parent_map = gcc_parent_map_10,
331	.clkr = {
332	.hw.init = &(struct clk_init_data){
333	.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
334	.parent_data = gcc_parent_data_10,
335	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
336	.ops = &clk_regmap_mux_closest_ops,
337	},
338	},
339	};
340
341	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
342	.reg = 0x770e0,
343	.shift = 0,
344	.width = 2,
345	.parent_map = gcc_parent_map_11,
346	.clkr = {
347	.hw.init = &(struct clk_init_data){
348	.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
349	.parent_data = gcc_parent_data_11,
350	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
351	.ops = &clk_regmap_mux_closest_ops,
352	},
353	},
354	};
355
356	static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
357	.reg = 0x77054,
358	.shift = 0,
359	.width = 2,
360	.parent_map = gcc_parent_map_12,
361	.clkr = {
362	.hw.init = &(struct clk_init_data){
363	.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
364	.parent_data = gcc_parent_data_12,
365	.num_parents = ARRAY_SIZE(gcc_parent_data_12),
366	.ops = &clk_regmap_mux_closest_ops,
367	},
368	},
369	};
370
371	static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
372	.reg = 0x3906c,
373	.shift = 0,
374	.width = 2,
375	.parent_map = gcc_parent_map_13,
376	.clkr = {
377	.hw.init = &(struct clk_init_data){
378	.name = "gcc_usb3_prim_phy_pipe_clk_src",
379	.parent_data = gcc_parent_data_13,
380	.num_parents = ARRAY_SIZE(gcc_parent_data_13),
381	.ops = &clk_regmap_mux_closest_ops,
382	},
383	},
384	};
385
386	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
387	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
388	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
389	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
390	{ }
391	};
392
393	static struct clk_rcg2 gcc_gp1_clk_src = {
394	.cmd_rcgr = 0x64004,
395	.mnd_width = 16,
396	.hid_width = 5,
397	.parent_map = gcc_parent_map_1,
398	.freq_tbl = ftbl_gcc_gp1_clk_src,
399	.clkr.hw.init = &(struct clk_init_data){
400	.name = "gcc_gp1_clk_src",
401	.parent_data = gcc_parent_data_1,
402	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
403	.flags = CLK_SET_RATE_PARENT,
404	.ops = &clk_rcg2_shared_ops,
405	},
406	};
407
408	static struct clk_rcg2 gcc_gp2_clk_src = {
409	.cmd_rcgr = 0x65004,
410	.mnd_width = 16,
411	.hid_width = 5,
412	.parent_map = gcc_parent_map_1,
413	.freq_tbl = ftbl_gcc_gp1_clk_src,
414	.clkr.hw.init = &(struct clk_init_data){
415	.name = "gcc_gp2_clk_src",
416	.parent_data = gcc_parent_data_1,
417	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
418	.flags = CLK_SET_RATE_PARENT,
419	.ops = &clk_rcg2_shared_ops,
420	},
421	};
422
423	static struct clk_rcg2 gcc_gp3_clk_src = {
424	.cmd_rcgr = 0x66004,
425	.mnd_width = 16,
426	.hid_width = 5,
427	.parent_map = gcc_parent_map_1,
428	.freq_tbl = ftbl_gcc_gp1_clk_src,
429	.clkr.hw.init = &(struct clk_init_data){
430	.name = "gcc_gp3_clk_src",
431	.parent_data = gcc_parent_data_1,
432	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
433	.flags = CLK_SET_RATE_PARENT,
434	.ops = &clk_rcg2_shared_ops,
435	},
436	};
437
438	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
439	F(19200000, P_BI_TCXO, 1, 0, 0),
440	{ }
441	};
442
443	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
444	.cmd_rcgr = 0x6b074,
445	.mnd_width = 16,
446	.hid_width = 5,
447	.parent_map = gcc_parent_map_2,
448	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
449	.clkr.hw.init = &(struct clk_init_data){
450	.name = "gcc_pcie_0_aux_clk_src",
451	.parent_data = gcc_parent_data_2,
452	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
453	.flags = CLK_SET_RATE_PARENT,
454	.ops = &clk_rcg2_shared_ops,
455	},
456	};
457
458	static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
459	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
460	{ }
461	};
462
463	static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
464	.cmd_rcgr = 0x6b058,
465	.mnd_width = 0,
466	.hid_width = 5,
467	.parent_map = gcc_parent_map_0,
468	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
469	.clkr.hw.init = &(struct clk_init_data){
470	.name = "gcc_pcie_0_phy_rchng_clk_src",
471	.parent_data = gcc_parent_data_0,
472	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
473	.flags = CLK_SET_RATE_PARENT,
474	.ops = &clk_rcg2_shared_ops,
475	},
476	};
477
478	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
479	.cmd_rcgr = 0x8d07c,
480	.mnd_width = 16,
481	.hid_width = 5,
482	.parent_map = gcc_parent_map_2,
483	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
484	.clkr.hw.init = &(struct clk_init_data){
485	.name = "gcc_pcie_1_aux_clk_src",
486	.parent_data = gcc_parent_data_2,
487	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
488	.flags = CLK_SET_RATE_PARENT,
489	.ops = &clk_rcg2_shared_ops,
490	},
491	};
492
493	static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
494	.cmd_rcgr = 0x8d060,
495	.mnd_width = 0,
496	.hid_width = 5,
497	.parent_map = gcc_parent_map_0,
498	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
499	.clkr.hw.init = &(struct clk_init_data){
500	.name = "gcc_pcie_1_phy_rchng_clk_src",
501	.parent_data = gcc_parent_data_0,
502	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
503	.flags = CLK_SET_RATE_PARENT,
504	.ops = &clk_rcg2_shared_ops,
505	},
506	};
507
508	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
509	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
510	{ }
511	};
512
513	static struct clk_rcg2 gcc_pdm2_clk_src = {
514	.cmd_rcgr = 0x33010,
515	.mnd_width = 0,
516	.hid_width = 5,
517	.parent_map = gcc_parent_map_0,
518	.freq_tbl = ftbl_gcc_pdm2_clk_src,
519	.clkr.hw.init = &(struct clk_init_data){
520	.name = "gcc_pdm2_clk_src",
521	.parent_data = gcc_parent_data_0,
522	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
523	.flags = CLK_SET_RATE_PARENT,
524	.ops = &clk_rcg2_shared_ops,
525	},
526	};
527
528	static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
529	.cmd_rcgr = 0x17008,
530	.mnd_width = 0,
531	.hid_width = 5,
532	.parent_map = gcc_parent_map_0,
533	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
534	.clkr.hw.init = &(struct clk_init_data){
535	.name = "gcc_qupv3_i2c_s0_clk_src",
536	.parent_data = gcc_parent_data_0,
537	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
538	.flags = CLK_SET_RATE_PARENT,
539	.ops = &clk_rcg2_shared_ops,
540	},
541	};
542
543	static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
544	.cmd_rcgr = 0x17024,
545	.mnd_width = 0,
546	.hid_width = 5,
547	.parent_map = gcc_parent_map_0,
548	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
549	.clkr.hw.init = &(struct clk_init_data){
550	.name = "gcc_qupv3_i2c_s1_clk_src",
551	.parent_data = gcc_parent_data_0,
552	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
553	.flags = CLK_SET_RATE_PARENT,
554	.ops = &clk_rcg2_shared_ops,
555	},
556	};
557
558	static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
559	.cmd_rcgr = 0x17040,
560	.mnd_width = 0,
561	.hid_width = 5,
562	.parent_map = gcc_parent_map_0,
563	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
564	.clkr.hw.init = &(struct clk_init_data){
565	.name = "gcc_qupv3_i2c_s2_clk_src",
566	.parent_data = gcc_parent_data_0,
567	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
568	.flags = CLK_SET_RATE_PARENT,
569	.ops = &clk_rcg2_shared_ops,
570	},
571	};
572
573	static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
574	.cmd_rcgr = 0x1705c,
575	.mnd_width = 0,
576	.hid_width = 5,
577	.parent_map = gcc_parent_map_0,
578	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
579	.clkr.hw.init = &(struct clk_init_data){
580	.name = "gcc_qupv3_i2c_s3_clk_src",
581	.parent_data = gcc_parent_data_0,
582	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
583	.flags = CLK_SET_RATE_PARENT,
584	.ops = &clk_rcg2_shared_ops,
585	},
586	};
587
588	static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
589	.cmd_rcgr = 0x17078,
590	.mnd_width = 0,
591	.hid_width = 5,
592	.parent_map = gcc_parent_map_0,
593	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
594	.clkr.hw.init = &(struct clk_init_data){
595	.name = "gcc_qupv3_i2c_s4_clk_src",
596	.parent_data = gcc_parent_data_0,
597	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
598	.flags = CLK_SET_RATE_PARENT,
599	.ops = &clk_rcg2_shared_ops,
600	},
601	};
602
603	static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
604	.cmd_rcgr = 0x17094,
605	.mnd_width = 0,
606	.hid_width = 5,
607	.parent_map = gcc_parent_map_0,
608	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
609	.clkr.hw.init = &(struct clk_init_data){
610	.name = "gcc_qupv3_i2c_s5_clk_src",
611	.parent_data = gcc_parent_data_0,
612	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613	.flags = CLK_SET_RATE_PARENT,
614	.ops = &clk_rcg2_shared_ops,
615	},
616	};
617
618	static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
619	.cmd_rcgr = 0x170b0,
620	.mnd_width = 0,
621	.hid_width = 5,
622	.parent_map = gcc_parent_map_0,
623	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
624	.clkr.hw.init = &(struct clk_init_data){
625	.name = "gcc_qupv3_i2c_s6_clk_src",
626	.parent_data = gcc_parent_data_0,
627	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
628	.flags = CLK_SET_RATE_PARENT,
629	.ops = &clk_rcg2_shared_ops,
630	},
631	};
632
633	static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
634	.cmd_rcgr = 0x170cc,
635	.mnd_width = 0,
636	.hid_width = 5,
637	.parent_map = gcc_parent_map_0,
638	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
639	.clkr.hw.init = &(struct clk_init_data){
640	.name = "gcc_qupv3_i2c_s7_clk_src",
641	.parent_data = gcc_parent_data_0,
642	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
643	.flags = CLK_SET_RATE_PARENT,
644	.ops = &clk_rcg2_shared_ops,
645	},
646	};
647
648	static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
649	.cmd_rcgr = 0x170e8,
650	.mnd_width = 0,
651	.hid_width = 5,
652	.parent_map = gcc_parent_map_0,
653	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
654	.clkr.hw.init = &(struct clk_init_data){
655	.name = "gcc_qupv3_i2c_s8_clk_src",
656	.parent_data = gcc_parent_data_0,
657	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
658	.flags = CLK_SET_RATE_PARENT,
659	.ops = &clk_rcg2_shared_ops,
660	},
661	};
662
663	static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
664	.cmd_rcgr = 0x17104,
665	.mnd_width = 0,
666	.hid_width = 5,
667	.parent_map = gcc_parent_map_0,
668	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
669	.clkr.hw.init = &(struct clk_init_data){
670	.name = "gcc_qupv3_i2c_s9_clk_src",
671	.parent_data = gcc_parent_data_0,
672	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
673	.flags = CLK_SET_RATE_PARENT,
674	.ops = &clk_rcg2_shared_ops,
675	},
676	};
677
678	static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
679	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
680	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
681	F(19200000, P_BI_TCXO, 1, 0, 0),
682	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
683	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
684	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
685	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
686	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
687	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
688	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
689	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
690	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
691	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
692	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
693	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
694	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
695	{ }
696	};
697
698	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
699	.name = "gcc_qupv3_wrap1_s0_clk_src",
700	.parent_data = gcc_parent_data_0,
701	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
702	.flags = CLK_SET_RATE_PARENT,
703	.ops = &clk_rcg2_shared_ops,
704	};
705
706	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
707	.cmd_rcgr = 0x18010,
708	.mnd_width = 16,
709	.hid_width = 5,
710	.parent_map = gcc_parent_map_0,
711	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
712	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
713	};
714
715	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
716	.name = "gcc_qupv3_wrap1_s1_clk_src",
717	.parent_data = gcc_parent_data_0,
718	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
719	.flags = CLK_SET_RATE_PARENT,
720	.ops = &clk_rcg2_shared_ops,
721	};
722
723	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
724	.cmd_rcgr = 0x18148,
725	.mnd_width = 16,
726	.hid_width = 5,
727	.parent_map = gcc_parent_map_0,
728	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
729	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
730	};
731
732	static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
733	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
734	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
735	F(19200000, P_BI_TCXO, 1, 0, 0),
736	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
737	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
738	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
739	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
740	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
741	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
742	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
743	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
744	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
745	{ }
746	};
747
748	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
749	.name = "gcc_qupv3_wrap1_s2_clk_src",
750	.parent_data = gcc_parent_data_0,
751	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
752	.flags = CLK_SET_RATE_PARENT,
753	.ops = &clk_rcg2_shared_ops,
754	};
755
756	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
757	.cmd_rcgr = 0x18280,
758	.mnd_width = 16,
759	.hid_width = 5,
760	.parent_map = gcc_parent_map_0,
761	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
762	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
763	};
764
765	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
766	.name = "gcc_qupv3_wrap1_s3_clk_src",
767	.parent_data = gcc_parent_data_0,
768	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
769	.flags = CLK_SET_RATE_PARENT,
770	.ops = &clk_rcg2_shared_ops,
771	};
772
773	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
774	.cmd_rcgr = 0x183b8,
775	.mnd_width = 16,
776	.hid_width = 5,
777	.parent_map = gcc_parent_map_0,
778	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
779	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
780	};
781
782	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
783	.name = "gcc_qupv3_wrap1_s4_clk_src",
784	.parent_data = gcc_parent_data_0,
785	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
786	.flags = CLK_SET_RATE_PARENT,
787	.ops = &clk_rcg2_shared_ops,
788	};
789
790	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
791	.cmd_rcgr = 0x184f0,
792	.mnd_width = 16,
793	.hid_width = 5,
794	.parent_map = gcc_parent_map_0,
795	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
796	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
797	};
798
799	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
800	.name = "gcc_qupv3_wrap1_s5_clk_src",
801	.parent_data = gcc_parent_data_0,
802	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
803	.flags = CLK_SET_RATE_PARENT,
804	.ops = &clk_rcg2_shared_ops,
805	};
806
807	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
808	.cmd_rcgr = 0x18628,
809	.mnd_width = 16,
810	.hid_width = 5,
811	.parent_map = gcc_parent_map_0,
812	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
813	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
814	};
815
816	static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
817	.name = "gcc_qupv3_wrap1_s6_clk_src",
818	.parent_data = gcc_parent_data_0,
819	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
820	.flags = CLK_SET_RATE_PARENT,
821	.ops = &clk_rcg2_shared_ops,
822	};
823
824	static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
825	.cmd_rcgr = 0x18760,
826	.mnd_width = 16,
827	.hid_width = 5,
828	.parent_map = gcc_parent_map_0,
829	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
830	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
831	};
832
833	static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
834	.name = "gcc_qupv3_wrap1_s7_clk_src",
835	.parent_data = gcc_parent_data_0,
836	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
837	.flags = CLK_SET_RATE_PARENT,
838	.ops = &clk_rcg2_shared_ops,
839	};
840
841	static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
842	.cmd_rcgr = 0x18898,
843	.mnd_width = 16,
844	.hid_width = 5,
845	.parent_map = gcc_parent_map_0,
846	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
847	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
848	};
849
850	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
851	.name = "gcc_qupv3_wrap2_s0_clk_src",
852	.parent_data = gcc_parent_data_0,
853	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
854	.flags = CLK_SET_RATE_PARENT,
855	.ops = &clk_rcg2_shared_ops,
856	};
857
858	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
859	.cmd_rcgr = 0x1e010,
860	.mnd_width = 16,
861	.hid_width = 5,
862	.parent_map = gcc_parent_map_0,
863	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
864	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
865	};
866
867	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
868	.name = "gcc_qupv3_wrap2_s1_clk_src",
869	.parent_data = gcc_parent_data_0,
870	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
871	.flags = CLK_SET_RATE_PARENT,
872	.ops = &clk_rcg2_shared_ops,
873	};
874
875	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
876	.cmd_rcgr = 0x1e148,
877	.mnd_width = 16,
878	.hid_width = 5,
879	.parent_map = gcc_parent_map_0,
880	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
881	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
882	};
883
884	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
885	.name = "gcc_qupv3_wrap2_s2_clk_src",
886	.parent_data = gcc_parent_data_0,
887	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888	.flags = CLK_SET_RATE_PARENT,
889	.ops = &clk_rcg2_shared_ops,
890	};
891
892	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
893	.cmd_rcgr = 0x1e280,
894	.mnd_width = 16,
895	.hid_width = 5,
896	.parent_map = gcc_parent_map_0,
897	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
898	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
899	};
900
901	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
902	.name = "gcc_qupv3_wrap2_s3_clk_src",
903	.parent_data = gcc_parent_data_0,
904	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
905	.flags = CLK_SET_RATE_PARENT,
906	.ops = &clk_rcg2_shared_ops,
907	};
908
909	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
910	.cmd_rcgr = 0x1e3b8,
911	.mnd_width = 16,
912	.hid_width = 5,
913	.parent_map = gcc_parent_map_0,
914	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
915	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
916	};
917
918	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
919	.name = "gcc_qupv3_wrap2_s4_clk_src",
920	.parent_data = gcc_parent_data_0,
921	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
922	.flags = CLK_SET_RATE_PARENT,
923	.ops = &clk_rcg2_shared_ops,
924	};
925
926	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
927	.cmd_rcgr = 0x1e4f0,
928	.mnd_width = 16,
929	.hid_width = 5,
930	.parent_map = gcc_parent_map_0,
931	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
932	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
933	};
934
935	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
936	.name = "gcc_qupv3_wrap2_s5_clk_src",
937	.parent_data = gcc_parent_data_0,
938	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
939	.flags = CLK_SET_RATE_PARENT,
940	.ops = &clk_rcg2_shared_ops,
941	};
942
943	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
944	.cmd_rcgr = 0x1e628,
945	.mnd_width = 16,
946	.hid_width = 5,
947	.parent_map = gcc_parent_map_0,
948	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
949	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
950	};
951
952	static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {
953	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
954	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
955	F(19200000, P_BI_TCXO, 1, 0, 0),
956	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
957	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
958	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
959	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
960	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
961	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
962	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
963	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
964	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
965	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
966	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
967	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
968	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
969	F(125000000, P_GCC_GPLL0_OUT_MAIN, 1, 5, 24),
970	{ }
971	};
972
973	static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
974	.name = "gcc_qupv3_wrap2_s6_clk_src",
975	.parent_data = gcc_parent_data_8,
976	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
977	.flags = CLK_SET_RATE_PARENT,
978	.ops = &clk_rcg2_shared_ops,
979	};
980
981	static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
982	.cmd_rcgr = 0x1e760,
983	.mnd_width = 16,
984	.hid_width = 5,
985	.parent_map = gcc_parent_map_8,
986	.freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,
987	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
988	};
989
990	static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
991	.name = "gcc_qupv3_wrap2_s7_clk_src",
992	.parent_data = gcc_parent_data_0,
993	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
994	.flags = CLK_SET_RATE_PARENT,
995	.ops = &clk_rcg2_shared_ops,
996	};
997
998	static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
999	.cmd_rcgr = 0x1e898,
1000	.mnd_width = 16,
1001	.hid_width = 5,
1002	.parent_map = gcc_parent_map_0,
1003	.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
1004	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1005	};
1006
1007	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1008	F(400000, P_BI_TCXO, 12, 1, 4),
1009	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1010	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1011	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1012	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1013	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1014	{ }
1015	};
1016
1017	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1018	.cmd_rcgr = 0x14018,
1019	.mnd_width = 8,
1020	.hid_width = 5,
1021	.parent_map = gcc_parent_map_9,
1022	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1023	.clkr.hw.init = &(struct clk_init_data){
1024	.name = "gcc_sdcc2_apps_clk_src",
1025	.parent_data = gcc_parent_data_9,
1026	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
1027	.flags = CLK_SET_RATE_PARENT,
1028	.ops = &clk_rcg2_shared_ops,
1029	},
1030	};
1031
1032	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1033	F(400000, P_BI_TCXO, 12, 1, 4),
1034	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1035	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1036	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1037	{ }
1038	};
1039
1040	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1041	.cmd_rcgr = 0x16018,
1042	.mnd_width = 8,
1043	.hid_width = 5,
1044	.parent_map = gcc_parent_map_0,
1045	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1046	.clkr.hw.init = &(struct clk_init_data){
1047	.name = "gcc_sdcc4_apps_clk_src",
1048	.parent_data = gcc_parent_data_0,
1049	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1050	.flags = CLK_SET_RATE_PARENT,
1051	.ops = &clk_rcg2_shared_ops,
1052	},
1053	};
1054
1055	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1056	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1057	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1058	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1059	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1060	{ }
1061	};
1062
1063	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1064	.cmd_rcgr = 0x77030,
1065	.mnd_width = 8,
1066	.hid_width = 5,
1067	.parent_map = gcc_parent_map_0,
1068	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1069	.clkr.hw.init = &(struct clk_init_data){
1070	.name = "gcc_ufs_phy_axi_clk_src",
1071	.parent_data = gcc_parent_data_0,
1072	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1073	.flags = CLK_SET_RATE_PARENT,
1074	.ops = &clk_rcg2_shared_ops,
1075	},
1076	};
1077
1078	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1079	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1080	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1081	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1082	{ }
1083	};
1084
1085	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1086	.cmd_rcgr = 0x77080,
1087	.mnd_width = 0,
1088	.hid_width = 5,
1089	.parent_map = gcc_parent_map_3,
1090	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1091	.clkr.hw.init = &(struct clk_init_data){
1092	.name = "gcc_ufs_phy_ice_core_clk_src",
1093	.parent_data = gcc_parent_data_3,
1094	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1095	.flags = CLK_SET_RATE_PARENT,
1096	.ops = &clk_rcg2_shared_ops,
1097	},
1098	};
1099
1100	static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1101	F(9600000, P_BI_TCXO, 2, 0, 0),
1102	F(19200000, P_BI_TCXO, 1, 0, 0),
1103	{ }
1104	};
1105
1106	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1107	.cmd_rcgr = 0x770b4,
1108	.mnd_width = 0,
1109	.hid_width = 5,
1110	.parent_map = gcc_parent_map_4,
1111	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1112	.clkr.hw.init = &(struct clk_init_data){
1113	.name = "gcc_ufs_phy_phy_aux_clk_src",
1114	.parent_data = gcc_parent_data_4,
1115	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1116	.flags = CLK_SET_RATE_PARENT,
1117	.ops = &clk_rcg2_shared_ops,
1118	},
1119	};
1120
1121	static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1122	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1123	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1124	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1125	{ }
1126	};
1127
1128	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1129	.cmd_rcgr = 0x77098,
1130	.mnd_width = 0,
1131	.hid_width = 5,
1132	.parent_map = gcc_parent_map_0,
1133	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1134	.clkr.hw.init = &(struct clk_init_data){
1135	.name = "gcc_ufs_phy_unipro_core_clk_src",
1136	.parent_data = gcc_parent_data_0,
1137	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1138	.flags = CLK_SET_RATE_PARENT,
1139	.ops = &clk_rcg2_shared_ops,
1140	},
1141	};
1142
1143	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1144	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1145	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1146	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1147	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1148	{ }
1149	};
1150
1151	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1152	.cmd_rcgr = 0x3902c,
1153	.mnd_width = 8,
1154	.hid_width = 5,
1155	.parent_map = gcc_parent_map_0,
1156	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1157	.clkr.hw.init = &(struct clk_init_data){
1158	.name = "gcc_usb30_prim_master_clk_src",
1159	.parent_data = gcc_parent_data_0,
1160	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1161	.flags = CLK_SET_RATE_PARENT,
1162	.ops = &clk_rcg2_shared_ops,
1163	},
1164	};
1165
1166	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1167	.cmd_rcgr = 0x39044,
1168	.mnd_width = 0,
1169	.hid_width = 5,
1170	.parent_map = gcc_parent_map_0,
1171	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1172	.clkr.hw.init = &(struct clk_init_data){
1173	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1174	.parent_data = gcc_parent_data_0,
1175	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1176	.flags = CLK_SET_RATE_PARENT,
1177	.ops = &clk_rcg2_shared_ops,
1178	},
1179	};
1180
1181	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1182	.cmd_rcgr = 0x39070,
1183	.mnd_width = 0,
1184	.hid_width = 5,
1185	.parent_map = gcc_parent_map_2,
1186	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1187	.clkr.hw.init = &(struct clk_init_data){
1188	.name = "gcc_usb3_prim_phy_aux_clk_src",
1189	.parent_data = gcc_parent_data_2,
1190	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1191	.flags = CLK_SET_RATE_PARENT,
1192	.ops = &clk_rcg2_shared_ops,
1193	},
1194	};
1195
1196	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1197	.reg = 0x3905c,
1198	.shift = 0,
1199	.width = 4,
1200	.clkr.hw.init = &(struct clk_init_data) {
1201	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1202	.parent_hws = (const struct clk_hw*[]) {
1203	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1204	},
1205	.num_parents = 1,
1206	.flags = CLK_SET_RATE_PARENT,
1207	.ops = &clk_regmap_div_ro_ops,
1208	},
1209	};
1210
1211	static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
1212	.halt_reg = 0x1003c,
1213	.halt_check = BRANCH_HALT_SKIP,
1214	.hwcg_reg = 0x1003c,
1215	.hwcg_bit = 1,
1216	.clkr = {
1217	.enable_reg = 0x52000,
1218	.enable_mask = BIT(12),
1219	.hw.init = &(struct clk_init_data){
1220	.name = "gcc_aggre_noc_pcie_axi_clk",
1221	.ops = &clk_branch2_ops,
1222	},
1223	},
1224	};
1225
1226	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1227	.halt_reg = 0x770e4,
1228	.halt_check = BRANCH_HALT_VOTED,
1229	.hwcg_reg = 0x770e4,
1230	.hwcg_bit = 1,
1231	.clkr = {
1232	.enable_reg = 0x770e4,
1233	.enable_mask = BIT(0),
1234	.hw.init = &(struct clk_init_data){
1235	.name = "gcc_aggre_ufs_phy_axi_clk",
1236	.parent_hws = (const struct clk_hw*[]) {
1237	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1238	},
1239	.num_parents = 1,
1240	.flags = CLK_SET_RATE_PARENT,
1241	.ops = &clk_branch2_ops,
1242	},
1243	},
1244	};
1245
1246	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1247	.halt_reg = 0x770e4,
1248	.halt_check = BRANCH_HALT_VOTED,
1249	.hwcg_reg = 0x770e4,
1250	.hwcg_bit = 1,
1251	.clkr = {
1252	.enable_reg = 0x770e4,
1253	.enable_mask = BIT(1),
1254	.hw.init = &(struct clk_init_data){
1255	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1256	.parent_hws = (const struct clk_hw*[]) {
1257	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1258	},
1259	.num_parents = 1,
1260	.flags = CLK_SET_RATE_PARENT,
1261	.ops = &clk_branch2_ops,
1262	},
1263	},
1264	};
1265
1266	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1267	.halt_reg = 0x3908c,
1268	.halt_check = BRANCH_HALT_VOTED,
1269	.hwcg_reg = 0x3908c,
1270	.hwcg_bit = 1,
1271	.clkr = {
1272	.enable_reg = 0x3908c,
1273	.enable_mask = BIT(0),
1274	.hw.init = &(struct clk_init_data){
1275	.name = "gcc_aggre_usb3_prim_axi_clk",
1276	.parent_hws = (const struct clk_hw*[]) {
1277	&gcc_usb30_prim_master_clk_src.clkr.hw,
1278	},
1279	.num_parents = 1,
1280	.flags = CLK_SET_RATE_PARENT,
1281	.ops = &clk_branch2_ops,
1282	},
1283	},
1284	};
1285
1286	static struct clk_branch gcc_boot_rom_ahb_clk = {
1287	.halt_reg = 0x38004,
1288	.halt_check = BRANCH_HALT_VOTED,
1289	.hwcg_reg = 0x38004,
1290	.hwcg_bit = 1,
1291	.clkr = {
1292	.enable_reg = 0x52000,
1293	.enable_mask = BIT(10),
1294	.hw.init = &(struct clk_init_data){
1295	.name = "gcc_boot_rom_ahb_clk",
1296	.ops = &clk_branch2_ops,
1297	},
1298	},
1299	};
1300
1301	static struct clk_branch gcc_camera_hf_axi_clk = {
1302	.halt_reg = 0x26010,
1303	.halt_check = BRANCH_HALT_SKIP,
1304	.hwcg_reg = 0x26010,
1305	.hwcg_bit = 1,
1306	.clkr = {
1307	.enable_reg = 0x26010,
1308	.enable_mask = BIT(0),
1309	.hw.init = &(struct clk_init_data){
1310	.name = "gcc_camera_hf_axi_clk",
1311	.ops = &clk_branch2_ops,
1312	},
1313	},
1314	};
1315
1316	static struct clk_branch gcc_camera_sf_axi_clk = {
1317	.halt_reg = 0x2601c,
1318	.halt_check = BRANCH_HALT_SKIP,
1319	.hwcg_reg = 0x2601c,
1320	.hwcg_bit = 1,
1321	.clkr = {
1322	.enable_reg = 0x2601c,
1323	.enable_mask = BIT(0),
1324	.hw.init = &(struct clk_init_data){
1325	.name = "gcc_camera_sf_axi_clk",
1326	.ops = &clk_branch2_ops,
1327	},
1328	},
1329	};
1330
1331	static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1332	.halt_reg = 0x10028,
1333	.halt_check = BRANCH_HALT_SKIP,
1334	.hwcg_reg = 0x10028,
1335	.hwcg_bit = 1,
1336	.clkr = {
1337	.enable_reg = 0x52000,
1338	.enable_mask = BIT(20),
1339	.hw.init = &(struct clk_init_data){
1340	.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1341	.ops = &clk_branch2_ops,
1342	},
1343	},
1344	};
1345
1346	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1347	.halt_reg = 0x39088,
1348	.halt_check = BRANCH_HALT_VOTED,
1349	.hwcg_reg = 0x39088,
1350	.hwcg_bit = 1,
1351	.clkr = {
1352	.enable_reg = 0x39088,
1353	.enable_mask = BIT(0),
1354	.hw.init = &(struct clk_init_data){
1355	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1356	.parent_hws = (const struct clk_hw*[]) {
1357	&gcc_usb30_prim_master_clk_src.clkr.hw,
1358	},
1359	.num_parents = 1,
1360	.flags = CLK_SET_RATE_PARENT,
1361	.ops = &clk_branch2_ops,
1362	},
1363	},
1364	};
1365
1366	static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
1367	.halt_reg = 0x10030,
1368	.halt_check = BRANCH_HALT_VOTED,
1369	.hwcg_reg = 0x10030,
1370	.hwcg_bit = 1,
1371	.clkr = {
1372	.enable_reg = 0x52008,
1373	.enable_mask = BIT(6),
1374	.hw.init = &(struct clk_init_data){
1375	.name = "gcc_cnoc_pcie_sf_axi_clk",
1376	.ops = &clk_branch2_ops,
1377	},
1378	},
1379	};
1380
1381	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1382	.halt_reg = 0x71154,
1383	.halt_check = BRANCH_HALT_SKIP,
1384	.hwcg_reg = 0x71154,
1385	.hwcg_bit = 1,
1386	.clkr = {
1387	.enable_reg = 0x71154,
1388	.enable_mask = BIT(0),
1389	.hw.init = &(struct clk_init_data){
1390	.name = "gcc_ddrss_gpu_axi_clk",
1391	.ops = &clk_branch2_aon_ops,
1392	},
1393	},
1394	};
1395
1396	static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
1397	.halt_reg = 0x1004c,
1398	.halt_check = BRANCH_HALT_SKIP,
1399	.hwcg_reg = 0x1004c,
1400	.hwcg_bit = 1,
1401	.clkr = {
1402	.enable_reg = 0x52000,
1403	.enable_mask = BIT(19),
1404	.hw.init = &(struct clk_init_data){
1405	.name = "gcc_ddrss_pcie_sf_qtb_clk",
1406	.ops = &clk_branch2_ops,
1407	},
1408	},
1409	};
1410
1411	static struct clk_branch gcc_disp_hf_axi_clk = {
1412	.halt_reg = 0x2700c,
1413	.halt_check = BRANCH_HALT_SKIP,
1414	.hwcg_reg = 0x2700c,
1415	.hwcg_bit = 1,
1416	.clkr = {
1417	.enable_reg = 0x2700c,
1418	.enable_mask = BIT(0),
1419	.hw.init = &(struct clk_init_data){
1420	.name = "gcc_disp_hf_axi_clk",
1421	.ops = &clk_branch2_ops,
1422	},
1423	},
1424	};
1425
1426	static struct clk_branch gcc_gp1_clk = {
1427	.halt_reg = 0x64000,
1428	.halt_check = BRANCH_HALT,
1429	.clkr = {
1430	.enable_reg = 0x64000,
1431	.enable_mask = BIT(0),
1432	.hw.init = &(struct clk_init_data){
1433	.name = "gcc_gp1_clk",
1434	.parent_hws = (const struct clk_hw*[]) {
1435	&gcc_gp1_clk_src.clkr.hw,
1436	},
1437	.num_parents = 1,
1438	.flags = CLK_SET_RATE_PARENT,
1439	.ops = &clk_branch2_ops,
1440	},
1441	},
1442	};
1443
1444	static struct clk_branch gcc_gp2_clk = {
1445	.halt_reg = 0x65000,
1446	.halt_check = BRANCH_HALT,
1447	.clkr = {
1448	.enable_reg = 0x65000,
1449	.enable_mask = BIT(0),
1450	.hw.init = &(struct clk_init_data){
1451	.name = "gcc_gp2_clk",
1452	.parent_hws = (const struct clk_hw*[]) {
1453	&gcc_gp2_clk_src.clkr.hw,
1454	},
1455	.num_parents = 1,
1456	.flags = CLK_SET_RATE_PARENT,
1457	.ops = &clk_branch2_ops,
1458	},
1459	},
1460	};
1461
1462	static struct clk_branch gcc_gp3_clk = {
1463	.halt_reg = 0x66000,
1464	.halt_check = BRANCH_HALT,
1465	.clkr = {
1466	.enable_reg = 0x66000,
1467	.enable_mask = BIT(0),
1468	.hw.init = &(struct clk_init_data){
1469	.name = "gcc_gp3_clk",
1470	.parent_hws = (const struct clk_hw*[]) {
1471	&gcc_gp3_clk_src.clkr.hw,
1472	},
1473	.num_parents = 1,
1474	.flags = CLK_SET_RATE_PARENT,
1475	.ops = &clk_branch2_ops,
1476	},
1477	},
1478	};
1479
1480	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1481	.halt_check = BRANCH_HALT_DELAY,
1482	.clkr = {
1483	.enable_reg = 0x52000,
1484	.enable_mask = BIT(15),
1485	.hw.init = &(struct clk_init_data){
1486	.name = "gcc_gpu_gpll0_clk_src",
1487	.parent_hws = (const struct clk_hw*[]) {
1488	&gcc_gpll0.clkr.hw,
1489	},
1490	.num_parents = 1,
1491	.flags = CLK_SET_RATE_PARENT,
1492	.ops = &clk_branch2_ops,
1493	},
1494	},
1495	};
1496
1497	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1498	.halt_check = BRANCH_HALT_DELAY,
1499	.clkr = {
1500	.enable_reg = 0x52000,
1501	.enable_mask = BIT(16),
1502	.hw.init = &(struct clk_init_data){
1503	.name = "gcc_gpu_gpll0_div_clk_src",
1504	.parent_hws = (const struct clk_hw*[]) {
1505	&gcc_gpll0_out_even.clkr.hw,
1506	},
1507	.num_parents = 1,
1508	.flags = CLK_SET_RATE_PARENT,
1509	.ops = &clk_branch2_ops,
1510	},
1511	},
1512	};
1513
1514	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1515	.halt_reg = 0x71010,
1516	.halt_check = BRANCH_HALT_VOTED,
1517	.hwcg_reg = 0x71010,
1518	.hwcg_bit = 1,
1519	.clkr = {
1520	.enable_reg = 0x71010,
1521	.enable_mask = BIT(0),
1522	.hw.init = &(struct clk_init_data){
1523	.name = "gcc_gpu_memnoc_gfx_clk",
1524	.ops = &clk_branch2_ops,
1525	},
1526	},
1527	};
1528
1529	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1530	.halt_reg = 0x71018,
1531	.halt_check = BRANCH_HALT_DELAY,
1532	.clkr = {
1533	.enable_reg = 0x71018,
1534	.enable_mask = BIT(0),
1535	.hw.init = &(struct clk_init_data){
1536	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1537	.ops = &clk_branch2_ops,
1538	},
1539	},
1540	};
1541
1542	static struct clk_branch gcc_pcie_0_aux_clk = {
1543	.halt_reg = 0x6b03c,
1544	.halt_check = BRANCH_HALT_VOTED,
1545	.clkr = {
1546	.enable_reg = 0x52008,
1547	.enable_mask = BIT(3),
1548	.hw.init = &(struct clk_init_data){
1549	.name = "gcc_pcie_0_aux_clk",
1550	.parent_hws = (const struct clk_hw*[]) {
1551	&gcc_pcie_0_aux_clk_src.clkr.hw,
1552	},
1553	.num_parents = 1,
1554	.flags = CLK_SET_RATE_PARENT,
1555	.ops = &clk_branch2_ops,
1556	},
1557	},
1558	};
1559
1560	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1561	.halt_reg = 0x6b038,
1562	.halt_check = BRANCH_HALT_VOTED,
1563	.hwcg_reg = 0x6b038,
1564	.hwcg_bit = 1,
1565	.clkr = {
1566	.enable_reg = 0x52008,
1567	.enable_mask = BIT(2),
1568	.hw.init = &(struct clk_init_data){
1569	.name = "gcc_pcie_0_cfg_ahb_clk",
1570	.ops = &clk_branch2_ops,
1571	},
1572	},
1573	};
1574
1575	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1576	.halt_reg = 0x6b02c,
1577	.halt_check = BRANCH_HALT_SKIP,
1578	.hwcg_reg = 0x6b02c,
1579	.hwcg_bit = 1,
1580	.clkr = {
1581	.enable_reg = 0x52008,
1582	.enable_mask = BIT(1),
1583	.hw.init = &(struct clk_init_data){
1584	.name = "gcc_pcie_0_mstr_axi_clk",
1585	.ops = &clk_branch2_ops,
1586	},
1587	},
1588	};
1589
1590	static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1591	.halt_reg = 0x6b054,
1592	.halt_check = BRANCH_HALT_VOTED,
1593	.clkr = {
1594	.enable_reg = 0x52000,
1595	.enable_mask = BIT(22),
1596	.hw.init = &(struct clk_init_data){
1597	.name = "gcc_pcie_0_phy_rchng_clk",
1598	.parent_hws = (const struct clk_hw*[]) {
1599	&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1600	},
1601	.num_parents = 1,
1602	.flags = CLK_SET_RATE_PARENT,
1603	.ops = &clk_branch2_ops,
1604	},
1605	},
1606	};
1607
1608	static struct clk_branch gcc_pcie_0_pipe_clk = {
1609	.halt_reg = 0x6b048,
1610	.halt_check = BRANCH_HALT_SKIP,
1611	.clkr = {
1612	.enable_reg = 0x52008,
1613	.enable_mask = BIT(4),
1614	.hw.init = &(struct clk_init_data){
1615	.name = "gcc_pcie_0_pipe_clk",
1616	.parent_hws = (const struct clk_hw*[]) {
1617	&gcc_pcie_0_pipe_clk_src.clkr.hw,
1618	},
1619	.num_parents = 1,
1620	.flags = CLK_SET_RATE_PARENT,
1621	.ops = &clk_branch2_ops,
1622	},
1623	},
1624	};
1625
1626	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1627	.halt_reg = 0x6b020,
1628	.halt_check = BRANCH_HALT_VOTED,
1629	.hwcg_reg = 0x6b020,
1630	.hwcg_bit = 1,
1631	.clkr = {
1632	.enable_reg = 0x52008,
1633	.enable_mask = BIT(0),
1634	.hw.init = &(struct clk_init_data){
1635	.name = "gcc_pcie_0_slv_axi_clk",
1636	.ops = &clk_branch2_ops,
1637	},
1638	},
1639	};
1640
1641	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1642	.halt_reg = 0x6b01c,
1643	.halt_check = BRANCH_HALT_VOTED,
1644	.clkr = {
1645	.enable_reg = 0x52008,
1646	.enable_mask = BIT(5),
1647	.hw.init = &(struct clk_init_data){
1648	.name = "gcc_pcie_0_slv_q2a_axi_clk",
1649	.ops = &clk_branch2_ops,
1650	},
1651	},
1652	};
1653
1654	static struct clk_branch gcc_pcie_1_aux_clk = {
1655	.halt_reg = 0x8d038,
1656	.halt_check = BRANCH_HALT_VOTED,
1657	.clkr = {
1658	.enable_reg = 0x52000,
1659	.enable_mask = BIT(29),
1660	.hw.init = &(struct clk_init_data){
1661	.name = "gcc_pcie_1_aux_clk",
1662	.parent_hws = (const struct clk_hw*[]) {
1663	&gcc_pcie_1_aux_clk_src.clkr.hw,
1664	},
1665	.num_parents = 1,
1666	.flags = CLK_SET_RATE_PARENT,
1667	.ops = &clk_branch2_ops,
1668	},
1669	},
1670	};
1671
1672	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1673	.halt_reg = 0x8d034,
1674	.halt_check = BRANCH_HALT_VOTED,
1675	.hwcg_reg = 0x8d034,
1676	.hwcg_bit = 1,
1677	.clkr = {
1678	.enable_reg = 0x52000,
1679	.enable_mask = BIT(28),
1680	.hw.init = &(struct clk_init_data){
1681	.name = "gcc_pcie_1_cfg_ahb_clk",
1682	.ops = &clk_branch2_ops,
1683	},
1684	},
1685	};
1686
1687	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1688	.halt_reg = 0x8d028,
1689	.halt_check = BRANCH_HALT_SKIP,
1690	.hwcg_reg = 0x8d028,
1691	.hwcg_bit = 1,
1692	.clkr = {
1693	.enable_reg = 0x52000,
1694	.enable_mask = BIT(27),
1695	.hw.init = &(struct clk_init_data){
1696	.name = "gcc_pcie_1_mstr_axi_clk",
1697	.ops = &clk_branch2_ops,
1698	},
1699	},
1700	};
1701
1702	static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1703	.halt_reg = 0x8d044,
1704	.halt_check = BRANCH_HALT_VOTED,
1705	.clkr = {
1706	.enable_reg = 0x52000,
1707	.enable_mask = BIT(24),
1708	.hw.init = &(struct clk_init_data){
1709	.name = "gcc_pcie_1_phy_aux_clk",
1710	.parent_hws = (const struct clk_hw*[]) {
1711	&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1712	},
1713	.num_parents = 1,
1714	.flags = CLK_SET_RATE_PARENT,
1715	.ops = &clk_branch2_ops,
1716	},
1717	},
1718	};
1719
1720	static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1721	.halt_reg = 0x8d05c,
1722	.halt_check = BRANCH_HALT_VOTED,
1723	.clkr = {
1724	.enable_reg = 0x52000,
1725	.enable_mask = BIT(23),
1726	.hw.init = &(struct clk_init_data){
1727	.name = "gcc_pcie_1_phy_rchng_clk",
1728	.parent_hws = (const struct clk_hw*[]) {
1729	&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1730	},
1731	.num_parents = 1,
1732	.flags = CLK_SET_RATE_PARENT,
1733	.ops = &clk_branch2_ops,
1734	},
1735	},
1736	};
1737
1738	static struct clk_branch gcc_pcie_1_pipe_clk = {
1739	.halt_reg = 0x8d050,
1740	.halt_check = BRANCH_HALT_SKIP,
1741	.clkr = {
1742	.enable_reg = 0x52000,
1743	.enable_mask = BIT(30),
1744	.hw.init = &(struct clk_init_data){
1745	.name = "gcc_pcie_1_pipe_clk",
1746	.parent_hws = (const struct clk_hw*[]) {
1747	&gcc_pcie_1_pipe_clk_src.clkr.hw,
1748	},
1749	.num_parents = 1,
1750	.flags = CLK_SET_RATE_PARENT,
1751	.ops = &clk_branch2_ops,
1752	},
1753	},
1754	};
1755
1756	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1757	.halt_reg = 0x8d01c,
1758	.halt_check = BRANCH_HALT_VOTED,
1759	.hwcg_reg = 0x8d01c,
1760	.hwcg_bit = 1,
1761	.clkr = {
1762	.enable_reg = 0x52000,
1763	.enable_mask = BIT(26),
1764	.hw.init = &(struct clk_init_data){
1765	.name = "gcc_pcie_1_slv_axi_clk",
1766	.ops = &clk_branch2_ops,
1767	},
1768	},
1769	};
1770
1771	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1772	.halt_reg = 0x8d018,
1773	.halt_check = BRANCH_HALT_VOTED,
1774	.clkr = {
1775	.enable_reg = 0x52000,
1776	.enable_mask = BIT(25),
1777	.hw.init = &(struct clk_init_data){
1778	.name = "gcc_pcie_1_slv_q2a_axi_clk",
1779	.ops = &clk_branch2_ops,
1780	},
1781	},
1782	};
1783
1784	static struct clk_branch gcc_pdm2_clk = {
1785	.halt_reg = 0x3300c,
1786	.halt_check = BRANCH_HALT,
1787	.clkr = {
1788	.enable_reg = 0x3300c,
1789	.enable_mask = BIT(0),
1790	.hw.init = &(struct clk_init_data){
1791	.name = "gcc_pdm2_clk",
1792	.parent_hws = (const struct clk_hw*[]) {
1793	&gcc_pdm2_clk_src.clkr.hw,
1794	},
1795	.num_parents = 1,
1796	.flags = CLK_SET_RATE_PARENT,
1797	.ops = &clk_branch2_ops,
1798	},
1799	},
1800	};
1801
1802	static struct clk_branch gcc_pdm_ahb_clk = {
1803	.halt_reg = 0x33004,
1804	.halt_check = BRANCH_HALT_VOTED,
1805	.hwcg_reg = 0x33004,
1806	.hwcg_bit = 1,
1807	.clkr = {
1808	.enable_reg = 0x33004,
1809	.enable_mask = BIT(0),
1810	.hw.init = &(struct clk_init_data){
1811	.name = "gcc_pdm_ahb_clk",
1812	.ops = &clk_branch2_ops,
1813	},
1814	},
1815	};
1816
1817	static struct clk_branch gcc_pdm_xo4_clk = {
1818	.halt_reg = 0x33008,
1819	.halt_check = BRANCH_HALT,
1820	.clkr = {
1821	.enable_reg = 0x33008,
1822	.enable_mask = BIT(0),
1823	.hw.init = &(struct clk_init_data){
1824	.name = "gcc_pdm_xo4_clk",
1825	.ops = &clk_branch2_ops,
1826	},
1827	},
1828	};
1829
1830	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1831	.halt_reg = 0x26008,
1832	.halt_check = BRANCH_HALT_VOTED,
1833	.hwcg_reg = 0x26008,
1834	.hwcg_bit = 1,
1835	.clkr = {
1836	.enable_reg = 0x26008,
1837	.enable_mask = BIT(0),
1838	.hw.init = &(struct clk_init_data){
1839	.name = "gcc_qmip_camera_nrt_ahb_clk",
1840	.ops = &clk_branch2_ops,
1841	},
1842	},
1843	};
1844
1845	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1846	.halt_reg = 0x2600c,
1847	.halt_check = BRANCH_HALT_VOTED,
1848	.hwcg_reg = 0x2600c,
1849	.hwcg_bit = 1,
1850	.clkr = {
1851	.enable_reg = 0x2600c,
1852	.enable_mask = BIT(0),
1853	.hw.init = &(struct clk_init_data){
1854	.name = "gcc_qmip_camera_rt_ahb_clk",
1855	.ops = &clk_branch2_ops,
1856	},
1857	},
1858	};
1859
1860	static struct clk_branch gcc_qmip_disp_ahb_clk = {
1861	.halt_reg = 0x27008,
1862	.halt_check = BRANCH_HALT_VOTED,
1863	.hwcg_reg = 0x27008,
1864	.hwcg_bit = 1,
1865	.clkr = {
1866	.enable_reg = 0x27008,
1867	.enable_mask = BIT(0),
1868	.hw.init = &(struct clk_init_data){
1869	.name = "gcc_qmip_disp_ahb_clk",
1870	.ops = &clk_branch2_ops,
1871	},
1872	},
1873	};
1874
1875	static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1876	.halt_reg = 0x71008,
1877	.halt_check = BRANCH_HALT_VOTED,
1878	.hwcg_reg = 0x71008,
1879	.hwcg_bit = 1,
1880	.clkr = {
1881	.enable_reg = 0x71008,
1882	.enable_mask = BIT(0),
1883	.hw.init = &(struct clk_init_data){
1884	.name = "gcc_qmip_gpu_ahb_clk",
1885	.ops = &clk_branch2_ops,
1886	},
1887	},
1888	};
1889
1890	static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1891	.halt_reg = 0x6b018,
1892	.halt_check = BRANCH_HALT_VOTED,
1893	.hwcg_reg = 0x6b018,
1894	.hwcg_bit = 1,
1895	.clkr = {
1896	.enable_reg = 0x52000,
1897	.enable_mask = BIT(11),
1898	.hw.init = &(struct clk_init_data){
1899	.name = "gcc_qmip_pcie_ahb_clk",
1900	.ops = &clk_branch2_ops,
1901	},
1902	},
1903	};
1904
1905	static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1906	.halt_reg = 0x32014,
1907	.halt_check = BRANCH_HALT_VOTED,
1908	.hwcg_reg = 0x32014,
1909	.hwcg_bit = 1,
1910	.clkr = {
1911	.enable_reg = 0x32014,
1912	.enable_mask = BIT(0),
1913	.hw.init = &(struct clk_init_data){
1914	.name = "gcc_qmip_video_cv_cpu_ahb_clk",
1915	.ops = &clk_branch2_ops,
1916	},
1917	},
1918	};
1919
1920	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1921	.halt_reg = 0x32008,
1922	.halt_check = BRANCH_HALT_VOTED,
1923	.hwcg_reg = 0x32008,
1924	.hwcg_bit = 1,
1925	.clkr = {
1926	.enable_reg = 0x32008,
1927	.enable_mask = BIT(0),
1928	.hw.init = &(struct clk_init_data){
1929	.name = "gcc_qmip_video_cvp_ahb_clk",
1930	.ops = &clk_branch2_ops,
1931	},
1932	},
1933	};
1934
1935	static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1936	.halt_reg = 0x32010,
1937	.halt_check = BRANCH_HALT_VOTED,
1938	.hwcg_reg = 0x32010,
1939	.hwcg_bit = 1,
1940	.clkr = {
1941	.enable_reg = 0x32010,
1942	.enable_mask = BIT(0),
1943	.hw.init = &(struct clk_init_data){
1944	.name = "gcc_qmip_video_v_cpu_ahb_clk",
1945	.ops = &clk_branch2_ops,
1946	},
1947	},
1948	};
1949
1950	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1951	.halt_reg = 0x3200c,
1952	.halt_check = BRANCH_HALT_VOTED,
1953	.hwcg_reg = 0x3200c,
1954	.hwcg_bit = 1,
1955	.clkr = {
1956	.enable_reg = 0x3200c,
1957	.enable_mask = BIT(0),
1958	.hw.init = &(struct clk_init_data){
1959	.name = "gcc_qmip_video_vcodec_ahb_clk",
1960	.ops = &clk_branch2_ops,
1961	},
1962	},
1963	};
1964
1965	static struct clk_branch gcc_qupv3_i2c_core_clk = {
1966	.halt_reg = 0x23144,
1967	.halt_check = BRANCH_HALT_VOTED,
1968	.clkr = {
1969	.enable_reg = 0x52008,
1970	.enable_mask = BIT(8),
1971	.hw.init = &(struct clk_init_data){
1972	.name = "gcc_qupv3_i2c_core_clk",
1973	.ops = &clk_branch2_ops,
1974	},
1975	},
1976	};
1977
1978	static struct clk_branch gcc_qupv3_i2c_s0_clk = {
1979	.halt_reg = 0x17004,
1980	.halt_check = BRANCH_HALT_VOTED,
1981	.clkr = {
1982	.enable_reg = 0x52008,
1983	.enable_mask = BIT(10),
1984	.hw.init = &(struct clk_init_data){
1985	.name = "gcc_qupv3_i2c_s0_clk",
1986	.parent_hws = (const struct clk_hw*[]) {
1987	&gcc_qupv3_i2c_s0_clk_src.clkr.hw,
1988	},
1989	.num_parents = 1,
1990	.flags = CLK_SET_RATE_PARENT,
1991	.ops = &clk_branch2_ops,
1992	},
1993	},
1994	};
1995
1996	static struct clk_branch gcc_qupv3_i2c_s1_clk = {
1997	.halt_reg = 0x17020,
1998	.halt_check = BRANCH_HALT_VOTED,
1999	.clkr = {
2000	.enable_reg = 0x52008,
2001	.enable_mask = BIT(11),
2002	.hw.init = &(struct clk_init_data){
2003	.name = "gcc_qupv3_i2c_s1_clk",
2004	.parent_hws = (const struct clk_hw*[]) {
2005	&gcc_qupv3_i2c_s1_clk_src.clkr.hw,
2006	},
2007	.num_parents = 1,
2008	.flags = CLK_SET_RATE_PARENT,
2009	.ops = &clk_branch2_ops,
2010	},
2011	},
2012	};
2013
2014	static struct clk_branch gcc_qupv3_i2c_s2_clk = {
2015	.halt_reg = 0x1703c,
2016	.halt_check = BRANCH_HALT_VOTED,
2017	.clkr = {
2018	.enable_reg = 0x52008,
2019	.enable_mask = BIT(12),
2020	.hw.init = &(struct clk_init_data){
2021	.name = "gcc_qupv3_i2c_s2_clk",
2022	.parent_hws = (const struct clk_hw*[]) {
2023	&gcc_qupv3_i2c_s2_clk_src.clkr.hw,
2024	},
2025	.num_parents = 1,
2026	.flags = CLK_SET_RATE_PARENT,
2027	.ops = &clk_branch2_ops,
2028	},
2029	},
2030	};
2031
2032	static struct clk_branch gcc_qupv3_i2c_s3_clk = {
2033	.halt_reg = 0x17058,
2034	.halt_check = BRANCH_HALT_VOTED,
2035	.clkr = {
2036	.enable_reg = 0x52008,
2037	.enable_mask = BIT(13),
2038	.hw.init = &(struct clk_init_data){
2039	.name = "gcc_qupv3_i2c_s3_clk",
2040	.parent_hws = (const struct clk_hw*[]) {
2041	&gcc_qupv3_i2c_s3_clk_src.clkr.hw,
2042	},
2043	.num_parents = 1,
2044	.flags = CLK_SET_RATE_PARENT,
2045	.ops = &clk_branch2_ops,
2046	},
2047	},
2048	};
2049
2050	static struct clk_branch gcc_qupv3_i2c_s4_clk = {
2051	.halt_reg = 0x17074,
2052	.halt_check = BRANCH_HALT_VOTED,
2053	.clkr = {
2054	.enable_reg = 0x52008,
2055	.enable_mask = BIT(14),
2056	.hw.init = &(struct clk_init_data){
2057	.name = "gcc_qupv3_i2c_s4_clk",
2058	.parent_hws = (const struct clk_hw*[]) {
2059	&gcc_qupv3_i2c_s4_clk_src.clkr.hw,
2060	},
2061	.num_parents = 1,
2062	.flags = CLK_SET_RATE_PARENT,
2063	.ops = &clk_branch2_ops,
2064	},
2065	},
2066	};
2067
2068	static struct clk_branch gcc_qupv3_i2c_s5_clk = {
2069	.halt_reg = 0x17090,
2070	.halt_check = BRANCH_HALT_VOTED,
2071	.clkr = {
2072	.enable_reg = 0x52008,
2073	.enable_mask = BIT(15),
2074	.hw.init = &(struct clk_init_data){
2075	.name = "gcc_qupv3_i2c_s5_clk",
2076	.parent_hws = (const struct clk_hw*[]) {
2077	&gcc_qupv3_i2c_s5_clk_src.clkr.hw,
2078	},
2079	.num_parents = 1,
2080	.flags = CLK_SET_RATE_PARENT,
2081	.ops = &clk_branch2_ops,
2082	},
2083	},
2084	};
2085
2086	static struct clk_branch gcc_qupv3_i2c_s6_clk = {
2087	.halt_reg = 0x170ac,
2088	.halt_check = BRANCH_HALT_VOTED,
2089	.clkr = {
2090	.enable_reg = 0x52008,
2091	.enable_mask = BIT(16),
2092	.hw.init = &(struct clk_init_data){
2093	.name = "gcc_qupv3_i2c_s6_clk",
2094	.parent_hws = (const struct clk_hw*[]) {
2095	&gcc_qupv3_i2c_s6_clk_src.clkr.hw,
2096	},
2097	.num_parents = 1,
2098	.flags = CLK_SET_RATE_PARENT,
2099	.ops = &clk_branch2_ops,
2100	},
2101	},
2102	};
2103
2104	static struct clk_branch gcc_qupv3_i2c_s7_clk = {
2105	.halt_reg = 0x170c8,
2106	.halt_check = BRANCH_HALT_VOTED,
2107	.clkr = {
2108	.enable_reg = 0x52008,
2109	.enable_mask = BIT(17),
2110	.hw.init = &(struct clk_init_data){
2111	.name = "gcc_qupv3_i2c_s7_clk",
2112	.parent_hws = (const struct clk_hw*[]) {
2113	&gcc_qupv3_i2c_s7_clk_src.clkr.hw,
2114	},
2115	.num_parents = 1,
2116	.flags = CLK_SET_RATE_PARENT,
2117	.ops = &clk_branch2_ops,
2118	},
2119	},
2120	};
2121
2122	static struct clk_branch gcc_qupv3_i2c_s8_clk = {
2123	.halt_reg = 0x170e4,
2124	.halt_check = BRANCH_HALT_VOTED,
2125	.clkr = {
2126	.enable_reg = 0x52010,
2127	.enable_mask = BIT(14),
2128	.hw.init = &(struct clk_init_data){
2129	.name = "gcc_qupv3_i2c_s8_clk",
2130	.parent_hws = (const struct clk_hw*[]) {
2131	&gcc_qupv3_i2c_s8_clk_src.clkr.hw,
2132	},
2133	.num_parents = 1,
2134	.flags = CLK_SET_RATE_PARENT,
2135	.ops = &clk_branch2_ops,
2136	},
2137	},
2138	};
2139
2140	static struct clk_branch gcc_qupv3_i2c_s9_clk = {
2141	.halt_reg = 0x17100,
2142	.halt_check = BRANCH_HALT_VOTED,
2143	.clkr = {
2144	.enable_reg = 0x52010,
2145	.enable_mask = BIT(15),
2146	.hw.init = &(struct clk_init_data){
2147	.name = "gcc_qupv3_i2c_s9_clk",
2148	.parent_hws = (const struct clk_hw*[]) {
2149	&gcc_qupv3_i2c_s9_clk_src.clkr.hw,
2150	},
2151	.num_parents = 1,
2152	.flags = CLK_SET_RATE_PARENT,
2153	.ops = &clk_branch2_ops,
2154	},
2155	},
2156	};
2157
2158	static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {
2159	.halt_reg = 0x23140,
2160	.halt_check = BRANCH_HALT_VOTED,
2161	.hwcg_reg = 0x23140,
2162	.hwcg_bit = 1,
2163	.clkr = {
2164	.enable_reg = 0x52008,
2165	.enable_mask = BIT(7),
2166	.hw.init = &(struct clk_init_data){
2167	.name = "gcc_qupv3_i2c_s_ahb_clk",
2168	.ops = &clk_branch2_ops,
2169	},
2170	},
2171	};
2172
2173	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2174	.halt_reg = 0x23294,
2175	.halt_check = BRANCH_HALT_VOTED,
2176	.clkr = {
2177	.enable_reg = 0x52008,
2178	.enable_mask = BIT(18),
2179	.hw.init = &(struct clk_init_data){
2180	.name = "gcc_qupv3_wrap1_core_2x_clk",
2181	.ops = &clk_branch2_ops,
2182	},
2183	},
2184	};
2185
2186	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2187	.halt_reg = 0x23284,
2188	.halt_check = BRANCH_HALT_VOTED,
2189	.clkr = {
2190	.enable_reg = 0x52008,
2191	.enable_mask = BIT(19),
2192	.hw.init = &(struct clk_init_data){
2193	.name = "gcc_qupv3_wrap1_core_clk",
2194	.ops = &clk_branch2_ops,
2195	},
2196	},
2197	};
2198
2199	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2200	.halt_reg = 0x18004,
2201	.halt_check = BRANCH_HALT_VOTED,
2202	.clkr = {
2203	.enable_reg = 0x52008,
2204	.enable_mask = BIT(22),
2205	.hw.init = &(struct clk_init_data){
2206	.name = "gcc_qupv3_wrap1_s0_clk",
2207	.parent_hws = (const struct clk_hw*[]) {
2208	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2209	},
2210	.num_parents = 1,
2211	.flags = CLK_SET_RATE_PARENT,
2212	.ops = &clk_branch2_ops,
2213	},
2214	},
2215	};
2216
2217	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2218	.halt_reg = 0x1813c,
2219	.halt_check = BRANCH_HALT_VOTED,
2220	.clkr = {
2221	.enable_reg = 0x52008,
2222	.enable_mask = BIT(23),
2223	.hw.init = &(struct clk_init_data){
2224	.name = "gcc_qupv3_wrap1_s1_clk",
2225	.parent_hws = (const struct clk_hw*[]) {
2226	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2227	},
2228	.num_parents = 1,
2229	.flags = CLK_SET_RATE_PARENT,
2230	.ops = &clk_branch2_ops,
2231	},
2232	},
2233	};
2234
2235	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2236	.halt_reg = 0x18274,
2237	.halt_check = BRANCH_HALT_VOTED,
2238	.clkr = {
2239	.enable_reg = 0x52008,
2240	.enable_mask = BIT(24),
2241	.hw.init = &(struct clk_init_data){
2242	.name = "gcc_qupv3_wrap1_s2_clk",
2243	.parent_hws = (const struct clk_hw*[]) {
2244	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2245	},
2246	.num_parents = 1,
2247	.flags = CLK_SET_RATE_PARENT,
2248	.ops = &clk_branch2_ops,
2249	},
2250	},
2251	};
2252
2253	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2254	.halt_reg = 0x183ac,
2255	.halt_check = BRANCH_HALT_VOTED,
2256	.clkr = {
2257	.enable_reg = 0x52008,
2258	.enable_mask = BIT(25),
2259	.hw.init = &(struct clk_init_data){
2260	.name = "gcc_qupv3_wrap1_s3_clk",
2261	.parent_hws = (const struct clk_hw*[]) {
2262	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2263	},
2264	.num_parents = 1,
2265	.flags = CLK_SET_RATE_PARENT,
2266	.ops = &clk_branch2_ops,
2267	},
2268	},
2269	};
2270
2271	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2272	.halt_reg = 0x184e4,
2273	.halt_check = BRANCH_HALT_VOTED,
2274	.clkr = {
2275	.enable_reg = 0x52008,
2276	.enable_mask = BIT(26),
2277	.hw.init = &(struct clk_init_data){
2278	.name = "gcc_qupv3_wrap1_s4_clk",
2279	.parent_hws = (const struct clk_hw*[]) {
2280	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2281	},
2282	.num_parents = 1,
2283	.flags = CLK_SET_RATE_PARENT,
2284	.ops = &clk_branch2_ops,
2285	},
2286	},
2287	};
2288
2289	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2290	.halt_reg = 0x1861c,
2291	.halt_check = BRANCH_HALT_VOTED,
2292	.clkr = {
2293	.enable_reg = 0x52008,
2294	.enable_mask = BIT(27),
2295	.hw.init = &(struct clk_init_data){
2296	.name = "gcc_qupv3_wrap1_s5_clk",
2297	.parent_hws = (const struct clk_hw*[]) {
2298	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2299	},
2300	.num_parents = 1,
2301	.flags = CLK_SET_RATE_PARENT,
2302	.ops = &clk_branch2_ops,
2303	},
2304	},
2305	};
2306
2307	static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2308	.halt_reg = 0x18754,
2309	.halt_check = BRANCH_HALT_VOTED,
2310	.clkr = {
2311	.enable_reg = 0x52008,
2312	.enable_mask = BIT(28),
2313	.hw.init = &(struct clk_init_data){
2314	.name = "gcc_qupv3_wrap1_s6_clk",
2315	.parent_hws = (const struct clk_hw*[]) {
2316	&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2317	},
2318	.num_parents = 1,
2319	.flags = CLK_SET_RATE_PARENT,
2320	.ops = &clk_branch2_ops,
2321	},
2322	},
2323	};
2324
2325	static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2326	.halt_reg = 0x1888c,
2327	.halt_check = BRANCH_HALT_VOTED,
2328	.clkr = {
2329	.enable_reg = 0x52010,
2330	.enable_mask = BIT(16),
2331	.hw.init = &(struct clk_init_data){
2332	.name = "gcc_qupv3_wrap1_s7_clk",
2333	.parent_hws = (const struct clk_hw*[]) {
2334	&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2335	},
2336	.num_parents = 1,
2337	.flags = CLK_SET_RATE_PARENT,
2338	.ops = &clk_branch2_ops,
2339	},
2340	},
2341	};
2342
2343	static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2344	.halt_reg = 0x23004,
2345	.halt_check = BRANCH_HALT_VOTED,
2346	.clkr = {
2347	.enable_reg = 0x52010,
2348	.enable_mask = BIT(3),
2349	.hw.init = &(struct clk_init_data){
2350	.name = "gcc_qupv3_wrap2_core_2x_clk",
2351	.ops = &clk_branch2_ops,
2352	},
2353	},
2354	};
2355
2356	static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2357	.halt_reg = 0x233d4,
2358	.halt_check = BRANCH_HALT_VOTED,
2359	.clkr = {
2360	.enable_reg = 0x52010,
2361	.enable_mask = BIT(0),
2362	.hw.init = &(struct clk_init_data){
2363	.name = "gcc_qupv3_wrap2_core_clk",
2364	.ops = &clk_branch2_ops,
2365	},
2366	},
2367	};
2368
2369	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2370	.halt_reg = 0x1e004,
2371	.halt_check = BRANCH_HALT_VOTED,
2372	.clkr = {
2373	.enable_reg = 0x52010,
2374	.enable_mask = BIT(4),
2375	.hw.init = &(struct clk_init_data){
2376	.name = "gcc_qupv3_wrap2_s0_clk",
2377	.parent_hws = (const struct clk_hw*[]) {
2378	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2379	},
2380	.num_parents = 1,
2381	.flags = CLK_SET_RATE_PARENT,
2382	.ops = &clk_branch2_ops,
2383	},
2384	},
2385	};
2386
2387	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2388	.halt_reg = 0x1e13c,
2389	.halt_check = BRANCH_HALT_VOTED,
2390	.clkr = {
2391	.enable_reg = 0x52010,
2392	.enable_mask = BIT(5),
2393	.hw.init = &(struct clk_init_data){
2394	.name = "gcc_qupv3_wrap2_s1_clk",
2395	.parent_hws = (const struct clk_hw*[]) {
2396	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2397	},
2398	.num_parents = 1,
2399	.flags = CLK_SET_RATE_PARENT,
2400	.ops = &clk_branch2_ops,
2401	},
2402	},
2403	};
2404
2405	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2406	.halt_reg = 0x1e274,
2407	.halt_check = BRANCH_HALT_VOTED,
2408	.clkr = {
2409	.enable_reg = 0x52010,
2410	.enable_mask = BIT(6),
2411	.hw.init = &(struct clk_init_data){
2412	.name = "gcc_qupv3_wrap2_s2_clk",
2413	.parent_hws = (const struct clk_hw*[]) {
2414	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2415	},
2416	.num_parents = 1,
2417	.flags = CLK_SET_RATE_PARENT,
2418	.ops = &clk_branch2_ops,
2419	},
2420	},
2421	};
2422
2423	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2424	.halt_reg = 0x1e3ac,
2425	.halt_check = BRANCH_HALT_VOTED,
2426	.clkr = {
2427	.enable_reg = 0x52010,
2428	.enable_mask = BIT(7),
2429	.hw.init = &(struct clk_init_data){
2430	.name = "gcc_qupv3_wrap2_s3_clk",
2431	.parent_hws = (const struct clk_hw*[]) {
2432	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2433	},
2434	.num_parents = 1,
2435	.flags = CLK_SET_RATE_PARENT,
2436	.ops = &clk_branch2_ops,
2437	},
2438	},
2439	};
2440
2441	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2442	.halt_reg = 0x1e4e4,
2443	.halt_check = BRANCH_HALT_VOTED,
2444	.clkr = {
2445	.enable_reg = 0x52010,
2446	.enable_mask = BIT(8),
2447	.hw.init = &(struct clk_init_data){
2448	.name = "gcc_qupv3_wrap2_s4_clk",
2449	.parent_hws = (const struct clk_hw*[]) {
2450	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2451	},
2452	.num_parents = 1,
2453	.flags = CLK_SET_RATE_PARENT,
2454	.ops = &clk_branch2_ops,
2455	},
2456	},
2457	};
2458
2459	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2460	.halt_reg = 0x1e61c,
2461	.halt_check = BRANCH_HALT_VOTED,
2462	.clkr = {
2463	.enable_reg = 0x52010,
2464	.enable_mask = BIT(9),
2465	.hw.init = &(struct clk_init_data){
2466	.name = "gcc_qupv3_wrap2_s5_clk",
2467	.parent_hws = (const struct clk_hw*[]) {
2468	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2469	},
2470	.num_parents = 1,
2471	.flags = CLK_SET_RATE_PARENT,
2472	.ops = &clk_branch2_ops,
2473	},
2474	},
2475	};
2476
2477	static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2478	.halt_reg = 0x1e754,
2479	.halt_check = BRANCH_HALT_VOTED,
2480	.clkr = {
2481	.enable_reg = 0x52010,
2482	.enable_mask = BIT(10),
2483	.hw.init = &(struct clk_init_data){
2484	.name = "gcc_qupv3_wrap2_s6_clk",
2485	.parent_hws = (const struct clk_hw*[]) {
2486	&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2487	},
2488	.num_parents = 1,
2489	.flags = CLK_SET_RATE_PARENT,
2490	.ops = &clk_branch2_ops,
2491	},
2492	},
2493	};
2494
2495	static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
2496	.halt_reg = 0x1e88c,
2497	.halt_check = BRANCH_HALT_VOTED,
2498	.clkr = {
2499	.enable_reg = 0x52010,
2500	.enable_mask = BIT(17),
2501	.hw.init = &(struct clk_init_data){
2502	.name = "gcc_qupv3_wrap2_s7_clk",
2503	.parent_hws = (const struct clk_hw*[]) {
2504	&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
2505	},
2506	.num_parents = 1,
2507	.flags = CLK_SET_RATE_PARENT,
2508	.ops = &clk_branch2_ops,
2509	},
2510	},
2511	};
2512
2513	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2514	.halt_reg = 0x2327c,
2515	.halt_check = BRANCH_HALT_VOTED,
2516	.hwcg_reg = 0x2327c,
2517	.hwcg_bit = 1,
2518	.clkr = {
2519	.enable_reg = 0x52008,
2520	.enable_mask = BIT(20),
2521	.hw.init = &(struct clk_init_data){
2522	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2523	.ops = &clk_branch2_ops,
2524	},
2525	},
2526	};
2527
2528	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2529	.halt_reg = 0x23280,
2530	.halt_check = BRANCH_HALT_VOTED,
2531	.hwcg_reg = 0x23280,
2532	.hwcg_bit = 1,
2533	.clkr = {
2534	.enable_reg = 0x52008,
2535	.enable_mask = BIT(21),
2536	.hw.init = &(struct clk_init_data){
2537	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2538	.ops = &clk_branch2_ops,
2539	},
2540	},
2541	};
2542
2543	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2544	.halt_reg = 0x233cc,
2545	.halt_check = BRANCH_HALT_VOTED,
2546	.hwcg_reg = 0x233cc,
2547	.hwcg_bit = 1,
2548	.clkr = {
2549	.enable_reg = 0x52010,
2550	.enable_mask = BIT(2),
2551	.hw.init = &(struct clk_init_data){
2552	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2553	.ops = &clk_branch2_ops,
2554	},
2555	},
2556	};
2557
2558	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2559	.halt_reg = 0x233d0,
2560	.halt_check = BRANCH_HALT_VOTED,
2561	.hwcg_reg = 0x233d0,
2562	.hwcg_bit = 1,
2563	.clkr = {
2564	.enable_reg = 0x52010,
2565	.enable_mask = BIT(1),
2566	.hw.init = &(struct clk_init_data){
2567	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2568	.ops = &clk_branch2_ops,
2569	},
2570	},
2571	};
2572
2573	static struct clk_branch gcc_sdcc2_ahb_clk = {
2574	.halt_reg = 0x14010,
2575	.halt_check = BRANCH_HALT,
2576	.clkr = {
2577	.enable_reg = 0x14010,
2578	.enable_mask = BIT(0),
2579	.hw.init = &(struct clk_init_data){
2580	.name = "gcc_sdcc2_ahb_clk",
2581	.ops = &clk_branch2_ops,
2582	},
2583	},
2584	};
2585
2586	static struct clk_branch gcc_sdcc2_apps_clk = {
2587	.halt_reg = 0x14004,
2588	.halt_check = BRANCH_HALT,
2589	.clkr = {
2590	.enable_reg = 0x14004,
2591	.enable_mask = BIT(0),
2592	.hw.init = &(struct clk_init_data){
2593	.name = "gcc_sdcc2_apps_clk",
2594	.parent_hws = (const struct clk_hw*[]) {
2595	&gcc_sdcc2_apps_clk_src.clkr.hw,
2596	},
2597	.num_parents = 1,
2598	.flags = CLK_SET_RATE_PARENT,
2599	.ops = &clk_branch2_ops,
2600	},
2601	},
2602	};
2603
2604	static struct clk_branch gcc_sdcc4_ahb_clk = {
2605	.halt_reg = 0x16010,
2606	.halt_check = BRANCH_HALT,
2607	.clkr = {
2608	.enable_reg = 0x16010,
2609	.enable_mask = BIT(0),
2610	.hw.init = &(struct clk_init_data){
2611	.name = "gcc_sdcc4_ahb_clk",
2612	.ops = &clk_branch2_ops,
2613	},
2614	},
2615	};
2616
2617	static struct clk_branch gcc_sdcc4_apps_clk = {
2618	.halt_reg = 0x16004,
2619	.halt_check = BRANCH_HALT,
2620	.clkr = {
2621	.enable_reg = 0x16004,
2622	.enable_mask = BIT(0),
2623	.hw.init = &(struct clk_init_data){
2624	.name = "gcc_sdcc4_apps_clk",
2625	.parent_hws = (const struct clk_hw*[]) {
2626	&gcc_sdcc4_apps_clk_src.clkr.hw,
2627	},
2628	.num_parents = 1,
2629	.flags = CLK_SET_RATE_PARENT,
2630	.ops = &clk_branch2_ops,
2631	},
2632	},
2633	};
2634
2635	static struct clk_branch gcc_ufs_phy_ahb_clk = {
2636	.halt_reg = 0x77024,
2637	.halt_check = BRANCH_HALT_VOTED,
2638	.hwcg_reg = 0x77024,
2639	.hwcg_bit = 1,
2640	.clkr = {
2641	.enable_reg = 0x77024,
2642	.enable_mask = BIT(0),
2643	.hw.init = &(struct clk_init_data){
2644	.name = "gcc_ufs_phy_ahb_clk",
2645	.ops = &clk_branch2_ops,
2646	},
2647	},
2648	};
2649
2650	static struct clk_branch gcc_ufs_phy_axi_clk = {
2651	.halt_reg = 0x77018,
2652	.halt_check = BRANCH_HALT_VOTED,
2653	.hwcg_reg = 0x77018,
2654	.hwcg_bit = 1,
2655	.clkr = {
2656	.enable_reg = 0x77018,
2657	.enable_mask = BIT(0),
2658	.hw.init = &(struct clk_init_data){
2659	.name = "gcc_ufs_phy_axi_clk",
2660	.parent_hws = (const struct clk_hw*[]) {
2661	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2662	},
2663	.num_parents = 1,
2664	.flags = CLK_SET_RATE_PARENT,
2665	.ops = &clk_branch2_ops,
2666	},
2667	},
2668	};
2669
2670	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2671	.halt_reg = 0x77018,
2672	.halt_check = BRANCH_HALT_VOTED,
2673	.hwcg_reg = 0x77018,
2674	.hwcg_bit = 1,
2675	.clkr = {
2676	.enable_reg = 0x77018,
2677	.enable_mask = BIT(1),
2678	.hw.init = &(struct clk_init_data){
2679	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2680	.parent_hws = (const struct clk_hw*[]) {
2681	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2682	},
2683	.num_parents = 1,
2684	.flags = CLK_SET_RATE_PARENT,
2685	.ops = &clk_branch2_ops,
2686	},
2687	},
2688	};
2689
2690	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2691	.halt_reg = 0x77074,
2692	.halt_check = BRANCH_HALT_VOTED,
2693	.hwcg_reg = 0x77074,
2694	.hwcg_bit = 1,
2695	.clkr = {
2696	.enable_reg = 0x77074,
2697	.enable_mask = BIT(0),
2698	.hw.init = &(struct clk_init_data){
2699	.name = "gcc_ufs_phy_ice_core_clk",
2700	.parent_hws = (const struct clk_hw*[]) {
2701	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2702	},
2703	.num_parents = 1,
2704	.flags = CLK_SET_RATE_PARENT,
2705	.ops = &clk_branch2_ops,
2706	},
2707	},
2708	};
2709
2710	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2711	.halt_reg = 0x77074,
2712	.halt_check = BRANCH_HALT_VOTED,
2713	.hwcg_reg = 0x77074,
2714	.hwcg_bit = 1,
2715	.clkr = {
2716	.enable_reg = 0x77074,
2717	.enable_mask = BIT(1),
2718	.hw.init = &(struct clk_init_data){
2719	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2720	.parent_hws = (const struct clk_hw*[]) {
2721	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2722	},
2723	.num_parents = 1,
2724	.flags = CLK_SET_RATE_PARENT,
2725	.ops = &clk_branch2_ops,
2726	},
2727	},
2728	};
2729
2730	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2731	.halt_reg = 0x770b0,
2732	.halt_check = BRANCH_HALT_VOTED,
2733	.hwcg_reg = 0x770b0,
2734	.hwcg_bit = 1,
2735	.clkr = {
2736	.enable_reg = 0x770b0,
2737	.enable_mask = BIT(0),
2738	.hw.init = &(struct clk_init_data){
2739	.name = "gcc_ufs_phy_phy_aux_clk",
2740	.parent_hws = (const struct clk_hw*[]) {
2741	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2742	},
2743	.num_parents = 1,
2744	.flags = CLK_SET_RATE_PARENT,
2745	.ops = &clk_branch2_ops,
2746	},
2747	},
2748	};
2749
2750	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2751	.halt_reg = 0x770b0,
2752	.halt_check = BRANCH_HALT_VOTED,
2753	.hwcg_reg = 0x770b0,
2754	.hwcg_bit = 1,
2755	.clkr = {
2756	.enable_reg = 0x770b0,
2757	.enable_mask = BIT(1),
2758	.hw.init = &(struct clk_init_data){
2759	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2760	.parent_hws = (const struct clk_hw*[]) {
2761	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2762	},
2763	.num_parents = 1,
2764	.flags = CLK_SET_RATE_PARENT,
2765	.ops = &clk_branch2_ops,
2766	},
2767	},
2768	};
2769
2770	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2771	.halt_reg = 0x7702c,
2772	.halt_check = BRANCH_HALT_DELAY,
2773	.clkr = {
2774	.enable_reg = 0x7702c,
2775	.enable_mask = BIT(0),
2776	.hw.init = &(struct clk_init_data){
2777	.name = "gcc_ufs_phy_rx_symbol_0_clk",
2778	.parent_hws = (const struct clk_hw*[]) {
2779	&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2780	},
2781	.num_parents = 1,
2782	.flags = CLK_SET_RATE_PARENT,
2783	.ops = &clk_branch2_ops,
2784	},
2785	},
2786	};
2787
2788	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2789	.halt_reg = 0x770cc,
2790	.halt_check = BRANCH_HALT_DELAY,
2791	.clkr = {
2792	.enable_reg = 0x770cc,
2793	.enable_mask = BIT(0),
2794	.hw.init = &(struct clk_init_data){
2795	.name = "gcc_ufs_phy_rx_symbol_1_clk",
2796	.parent_hws = (const struct clk_hw*[]) {
2797	&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2798	},
2799	.num_parents = 1,
2800	.flags = CLK_SET_RATE_PARENT,
2801	.ops = &clk_branch2_ops,
2802	},
2803	},
2804	};
2805
2806	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2807	.halt_reg = 0x77028,
2808	.halt_check = BRANCH_HALT_DELAY,
2809	.clkr = {
2810	.enable_reg = 0x77028,
2811	.enable_mask = BIT(0),
2812	.hw.init = &(struct clk_init_data){
2813	.name = "gcc_ufs_phy_tx_symbol_0_clk",
2814	.parent_hws = (const struct clk_hw*[]) {
2815	&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2816	},
2817	.num_parents = 1,
2818	.flags = CLK_SET_RATE_PARENT,
2819	.ops = &clk_branch2_ops,
2820	},
2821	},
2822	};
2823
2824	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2825	.halt_reg = 0x77068,
2826	.halt_check = BRANCH_HALT_VOTED,
2827	.hwcg_reg = 0x77068,
2828	.hwcg_bit = 1,
2829	.clkr = {
2830	.enable_reg = 0x77068,
2831	.enable_mask = BIT(0),
2832	.hw.init = &(struct clk_init_data){
2833	.name = "gcc_ufs_phy_unipro_core_clk",
2834	.parent_hws = (const struct clk_hw*[]) {
2835	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2836	},
2837	.num_parents = 1,
2838	.flags = CLK_SET_RATE_PARENT,
2839	.ops = &clk_branch2_ops,
2840	},
2841	},
2842	};
2843
2844	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2845	.halt_reg = 0x77068,
2846	.halt_check = BRANCH_HALT_VOTED,
2847	.hwcg_reg = 0x77068,
2848	.hwcg_bit = 1,
2849	.clkr = {
2850	.enable_reg = 0x77068,
2851	.enable_mask = BIT(1),
2852	.hw.init = &(struct clk_init_data){
2853	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2854	.parent_hws = (const struct clk_hw*[]) {
2855	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2856	},
2857	.num_parents = 1,
2858	.flags = CLK_SET_RATE_PARENT,
2859	.ops = &clk_branch2_ops,
2860	},
2861	},
2862	};
2863
2864	static struct clk_branch gcc_usb30_prim_master_clk = {
2865	.halt_reg = 0x39018,
2866	.halt_check = BRANCH_HALT,
2867	.clkr = {
2868	.enable_reg = 0x39018,
2869	.enable_mask = BIT(0),
2870	.hw.init = &(struct clk_init_data){
2871	.name = "gcc_usb30_prim_master_clk",
2872	.parent_hws = (const struct clk_hw*[]) {
2873	&gcc_usb30_prim_master_clk_src.clkr.hw,
2874	},
2875	.num_parents = 1,
2876	.flags = CLK_SET_RATE_PARENT,
2877	.ops = &clk_branch2_ops,
2878	},
2879	},
2880	};
2881
2882	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2883	.halt_reg = 0x39028,
2884	.halt_check = BRANCH_HALT,
2885	.clkr = {
2886	.enable_reg = 0x39028,
2887	.enable_mask = BIT(0),
2888	.hw.init = &(struct clk_init_data){
2889	.name = "gcc_usb30_prim_mock_utmi_clk",
2890	.parent_hws = (const struct clk_hw*[]) {
2891	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2892	},
2893	.num_parents = 1,
2894	.flags = CLK_SET_RATE_PARENT,
2895	.ops = &clk_branch2_ops,
2896	},
2897	},
2898	};
2899
2900	static struct clk_branch gcc_usb30_prim_sleep_clk = {
2901	.halt_reg = 0x39024,
2902	.halt_check = BRANCH_HALT,
2903	.clkr = {
2904	.enable_reg = 0x39024,
2905	.enable_mask = BIT(0),
2906	.hw.init = &(struct clk_init_data){
2907	.name = "gcc_usb30_prim_sleep_clk",
2908	.ops = &clk_branch2_ops,
2909	},
2910	},
2911	};
2912
2913	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2914	.halt_reg = 0x39060,
2915	.halt_check = BRANCH_HALT,
2916	.clkr = {
2917	.enable_reg = 0x39060,
2918	.enable_mask = BIT(0),
2919	.hw.init = &(struct clk_init_data){
2920	.name = "gcc_usb3_prim_phy_aux_clk",
2921	.parent_hws = (const struct clk_hw*[]) {
2922	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2923	},
2924	.num_parents = 1,
2925	.flags = CLK_SET_RATE_PARENT,
2926	.ops = &clk_branch2_ops,
2927	},
2928	},
2929	};
2930
2931	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2932	.halt_reg = 0x39064,
2933	.halt_check = BRANCH_HALT,
2934	.clkr = {
2935	.enable_reg = 0x39064,
2936	.enable_mask = BIT(0),
2937	.hw.init = &(struct clk_init_data){
2938	.name = "gcc_usb3_prim_phy_com_aux_clk",
2939	.parent_hws = (const struct clk_hw*[]) {
2940	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2941	},
2942	.num_parents = 1,
2943	.flags = CLK_SET_RATE_PARENT,
2944	.ops = &clk_branch2_ops,
2945	},
2946	},
2947	};
2948
2949	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2950	.halt_reg = 0x39068,
2951	.halt_check = BRANCH_HALT_DELAY,
2952	.hwcg_reg = 0x39068,
2953	.hwcg_bit = 1,
2954	.clkr = {
2955	.enable_reg = 0x39068,
2956	.enable_mask = BIT(0),
2957	.hw.init = &(struct clk_init_data){
2958	.name = "gcc_usb3_prim_phy_pipe_clk",
2959	.parent_hws = (const struct clk_hw*[]) {
2960	&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2961	},
2962	.num_parents = 1,
2963	.flags = CLK_SET_RATE_PARENT,
2964	.ops = &clk_branch2_ops,
2965	},
2966	},
2967	};
2968
2969	static struct clk_branch gcc_video_axi0_clk = {
2970	.halt_reg = 0x32018,
2971	.halt_check = BRANCH_HALT_SKIP,
2972	.hwcg_reg = 0x32018,
2973	.hwcg_bit = 1,
2974	.clkr = {
2975	.enable_reg = 0x32018,
2976	.enable_mask = BIT(0),
2977	.hw.init = &(struct clk_init_data){
2978	.name = "gcc_video_axi0_clk",
2979	.ops = &clk_branch2_ops,
2980	},
2981	},
2982	};
2983
2984	static struct clk_branch gcc_video_axi1_clk = {
2985	.halt_reg = 0x32024,
2986	.halt_check = BRANCH_HALT_SKIP,
2987	.hwcg_reg = 0x32024,
2988	.hwcg_bit = 1,
2989	.clkr = {
2990	.enable_reg = 0x32024,
2991	.enable_mask = BIT(0),
2992	.hw.init = &(struct clk_init_data){
2993	.name = "gcc_video_axi1_clk",
2994	.ops = &clk_branch2_ops,
2995	},
2996	},
2997	};
2998
2999	static struct gdsc pcie_0_gdsc = {
3000	.gdscr = 0x6b004,
3001	.collapse_ctrl = 0x52020,
3002	.collapse_mask = BIT(0),
3003	.pd = {
3004	.name = "pcie_0_gdsc",
3005	},
3006	.pwrsts = PWRSTS_OFF_ON,
3007	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3008	};
3009
3010	static struct gdsc pcie_0_phy_gdsc = {
3011	.gdscr = 0x6c000,
3012	.collapse_ctrl = 0x52020,
3013	.collapse_mask = BIT(3),
3014	.pd = {
3015	.name = "pcie_0_phy_gdsc",
3016	},
3017	.pwrsts = PWRSTS_OFF_ON,
3018	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3019	};
3020
3021	static struct gdsc pcie_1_gdsc = {
3022	.gdscr = 0x8d004,
3023	.collapse_ctrl = 0x52020,
3024	.collapse_mask = BIT(1),
3025	.pd = {
3026	.name = "pcie_1_gdsc",
3027	},
3028	.pwrsts = PWRSTS_OFF_ON,
3029	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3030	};
3031
3032	static struct gdsc pcie_1_phy_gdsc = {
3033	.gdscr = 0x8e000,
3034	.collapse_ctrl = 0x52020,
3035	.collapse_mask = BIT(4),
3036	.pd = {
3037	.name = "pcie_1_phy_gdsc",
3038	},
3039	.pwrsts = PWRSTS_OFF_ON,
3040	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3041	};
3042
3043	static struct gdsc ufs_phy_gdsc = {
3044	.gdscr = 0x77004,
3045	.pd = {
3046	.name = "ufs_phy_gdsc",
3047	},
3048	.pwrsts = PWRSTS_OFF_ON,
3049	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3050	};
3051
3052	static struct gdsc ufs_mem_phy_gdsc = {
3053	.gdscr = 0x9e000,
3054	.pd = {
3055	.name = "ufs_mem_phy_gdsc",
3056	},
3057	.pwrsts = PWRSTS_OFF_ON,
3058	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3059	};
3060
3061	static struct gdsc usb30_prim_gdsc = {
3062	.gdscr = 0x39004,
3063	.pd = {
3064	.name = "usb30_prim_gdsc",
3065	},
3066	.pwrsts = PWRSTS_OFF_ON,
3067	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3068	};
3069
3070	static struct gdsc usb3_phy_gdsc = {
3071	.gdscr = 0x50018,
3072	.pd = {
3073	.name = "usb3_phy_gdsc",
3074	},
3075	.pwrsts = PWRSTS_OFF_ON,
3076	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3077	};
3078
3079	static struct clk_regmap *gcc_sm8550_clocks[] = {
3080	[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
3081	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3082	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3083	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3084	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3085	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3086	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3087	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
3088	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3089	[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
3090	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3091	[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
3092	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3093	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3094	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3095	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3096	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3097	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3098	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3099	[GCC_GPLL0] = &gcc_gpll0.clkr,
3100	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3101	[GCC_GPLL4] = &gcc_gpll4.clkr,
3102	[GCC_GPLL7] = &gcc_gpll7.clkr,
3103	[GCC_GPLL9] = &gcc_gpll9.clkr,
3104	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3105	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3106	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3107	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3108	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3109	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3110	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3111	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3112	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3113	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3114	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3115	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3116	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3117	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3118	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3119	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3120	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3121	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3122	[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3123	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3124	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3125	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3126	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3127	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3128	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3129	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3130	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3131	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3132	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3133	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3134	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3135	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3136	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3137	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3138	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3139	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3140	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3141	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3142	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3143	[GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr,
3144	[GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr,
3145	[GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr,
3146	[GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr,
3147	[GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr,
3148	[GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr,
3149	[GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr,
3150	[GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr,
3151	[GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr,
3152	[GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr,
3153	[GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr,
3154	[GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr,
3155	[GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr,
3156	[GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr,
3157	[GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr,
3158	[GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr,
3159	[GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr,
3160	[GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr,
3161	[GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr,
3162	[GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr,
3163	[GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr,
3164	[GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr,
3165	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3166	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3167	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3168	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3169	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3170	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3171	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3172	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3173	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3174	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3175	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3176	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3177	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3178	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3179	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3180	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3181	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3182	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3183	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3184	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3185	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3186	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3187	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3188	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3189	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3190	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3191	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3192	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3193	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3194	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3195	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3196	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3197	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3198	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3199	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
3200	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
3201	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3202	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3203	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3204	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3205	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3206	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3207	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3208	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3209	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3210	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3211	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3212	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3213	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3214	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3215	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3216	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3217	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3218	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3219	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3220	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3221	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3222	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3223	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3224	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3225	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3226	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3227	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3228	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3229	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3230	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3231	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3232	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3233	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3234	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3235	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3236	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3237	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3238	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3239	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3240	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3241	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3242	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3243	};
3244
3245	static const struct qcom_reset_map gcc_sm8550_resets[] = {
3246	[GCC_CAMERA_BCR] = { 0x26000 },
3247	[GCC_DISPLAY_BCR] = { 0x27000 },
3248	[GCC_GPU_BCR] = { 0x71000 },
3249	[GCC_PCIE_0_BCR] = { 0x6b000 },
3250	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3251	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3252	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3253	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3254	[GCC_PCIE_1_BCR] = { 0x8d000 },
3255	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3256	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3257	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3258	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
3259	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3260	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3261	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3262	[GCC_PDM_BCR] = { 0x33000 },
3263	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3264	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3265	[GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3266	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3267	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3268	[GCC_SDCC2_BCR] = { 0x14000 },
3269	[GCC_SDCC4_BCR] = { 0x16000 },
3270	[GCC_UFS_PHY_BCR] = { 0x77000 },
3271	[GCC_USB30_PRIM_BCR] = { 0x39000 },
3272	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3273	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3274	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3275	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3276	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3277	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3278	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3279	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
3280	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
3281	[GCC_VIDEO_BCR] = { 0x32000 },
3282	};
3283
3284	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3285	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3286	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3287	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3288	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3289	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3290	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3291	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3292	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3293	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3294	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3295	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3296	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3297	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3298	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3299	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3300	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
3301	};
3302
3303	static struct gdsc *gcc_sm8550_gdscs[] = {
3304	[PCIE_0_GDSC] = &pcie_0_gdsc,
3305	[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
3306	[PCIE_1_GDSC] = &pcie_1_gdsc,
3307	[PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
3308	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3309	[UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc,
3310	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3311	[USB3_PHY_GDSC] = &usb3_phy_gdsc,
3312	};
3313
3314	static const struct regmap_config gcc_sm8550_regmap_config = {
3315	.reg_bits = 32,
3316	.reg_stride = 4,
3317	.val_bits = 32,
3318	.max_register = 0x1f41f0,
3319	.fast_io = true,
3320	};
3321
3322	static const struct qcom_cc_desc gcc_sm8550_desc = {
3323	.config = &gcc_sm8550_regmap_config,
3324	.clks = gcc_sm8550_clocks,
3325	.num_clks = ARRAY_SIZE(gcc_sm8550_clocks),
3326	.resets = gcc_sm8550_resets,
3327	.num_resets = ARRAY_SIZE(gcc_sm8550_resets),
3328	.gdscs = gcc_sm8550_gdscs,
3329	.num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
3330	};
3331
3332	static const struct of_device_id gcc_sm8550_match_table[] = {
3333	{ .compatible = "qcom,sm8550-gcc" },
3334	{ }
3335	};
3336	MODULE_DEVICE_TABLE(of, gcc_sm8550_match_table);
3337
3338	static int gcc_sm8550_probe(struct platform_device *pdev)
3339	{
3340	struct regmap *regmap;
3341	int ret;
3342
3343	regmap = qcom_cc_map(pdev, desc: &gcc_sm8550_desc);
3344	if (IS_ERR(ptr: regmap))
3345	return PTR_ERR(ptr: regmap);
3346
3347	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
3348	ARRAY_SIZE(gcc_dfs_clocks));
3349	if (ret)
3350	return ret;
3351
3352	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3353	regmap_update_bits(map: regmap, reg: gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3354
3355	/* Keep some clocks always-on */
3356	qcom_branch_set_clk_en(regmap, cbcr: 0x26004); /* GCC_CAMERA_AHB_CLK */
3357	qcom_branch_set_clk_en(regmap, cbcr: 0x26028); /* GCC_CAMERA_XO_CLK */
3358	qcom_branch_set_clk_en(regmap, cbcr: 0x27004); /* GCC_DISP_AHB_CLK */
3359	qcom_branch_set_clk_en(regmap, cbcr: 0x27018); /* GCC_DISP_XO_CLK */
3360	qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
3361	qcom_branch_set_clk_en(regmap, cbcr: 0x32004); /* GCC_VIDEO_AHB_CLK */
3362	qcom_branch_set_clk_en(regmap, cbcr: 0x32030); /* GCC_VIDEO_XO_CLK */
3363
3364	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
3365	regmap_write(map: regmap, reg: 0x52024, val: 0x0);
3366
3367	return qcom_cc_really_probe(pdev, desc: &gcc_sm8550_desc, regmap);
3368	}
3369
3370	static struct platform_driver gcc_sm8550_driver = {
3371	.probe = gcc_sm8550_probe,
3372	.driver = {
3373	.name = "gcc-sm8550",
3374	.of_match_table = gcc_sm8550_match_table,
3375	},
3376	};
3377
3378	static int __init gcc_sm8550_init(void)
3379	{
3380	return platform_driver_register(&gcc_sm8550_driver);
3381	}
3382	subsys_initcall(gcc_sm8550_init);
3383
3384	static void __exit gcc_sm8550_exit(void)
3385	{
3386	platform_driver_unregister(&gcc_sm8550_driver);
3387	}
3388	module_exit(gcc_sm8550_exit);
3389
3390	MODULE_DESCRIPTION("QTI GCC SM8550 Driver");
3391	MODULE_LICENSE("GPL");
3392