1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (c) 2014 MundoReader S.L. |
4 | * Author: Heiko Stuebner <heiko@sntech.de> |
5 | * |
6 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. |
7 | * Author: Xing Zheng <zhengxing@rock-chips.com> |
8 | */ |
9 | |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/io.h> |
12 | #include <linux/of.h> |
13 | #include <linux/of_address.h> |
14 | #include <linux/syscore_ops.h> |
15 | #include <dt-bindings/clock/rk3036-cru.h> |
16 | #include "clk.h" |
17 | |
18 | #define RK3036_GRF_SOC_STATUS0 0x14c |
19 | |
20 | enum rk3036_plls { |
21 | apll, dpll, gpll, |
22 | }; |
23 | |
24 | static struct rockchip_pll_rate_table rk3036_pll_rates[] = { |
25 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
26 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), |
27 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), |
28 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), |
29 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), |
30 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), |
31 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), |
32 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), |
33 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), |
34 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), |
35 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), |
36 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), |
37 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), |
38 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), |
39 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), |
40 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), |
41 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), |
42 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), |
43 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), |
44 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), |
45 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), |
46 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), |
47 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), |
48 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), |
49 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), |
50 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), |
51 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), |
52 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), |
53 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), |
54 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), |
55 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), |
56 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), |
57 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), |
58 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), |
59 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), |
60 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), |
61 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), |
62 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), |
63 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), |
64 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |
65 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), |
66 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), |
67 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), |
68 | { /* sentinel */ }, |
69 | }; |
70 | |
71 | #define RK3036_DIV_CPU_MASK 0x1f |
72 | #define RK3036_DIV_CPU_SHIFT 8 |
73 | |
74 | #define RK3036_DIV_PERI_MASK 0xf |
75 | #define RK3036_DIV_PERI_SHIFT 0 |
76 | #define RK3036_DIV_ACLK_MASK 0x7 |
77 | #define RK3036_DIV_ACLK_SHIFT 4 |
78 | #define RK3036_DIV_HCLK_MASK 0x3 |
79 | #define RK3036_DIV_HCLK_SHIFT 8 |
80 | #define RK3036_DIV_PCLK_MASK 0x7 |
81 | #define RK3036_DIV_PCLK_SHIFT 12 |
82 | |
83 | #define RK3036_CLKSEL1(_core_periph_div) \ |
84 | { \ |
85 | .reg = RK2928_CLKSEL_CON(1), \ |
86 | .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \ |
87 | RK3036_DIV_PERI_SHIFT) \ |
88 | } |
89 | |
90 | #define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \ |
91 | { \ |
92 | .prate = _prate, \ |
93 | .divs = { \ |
94 | RK3036_CLKSEL1(_core_periph_div), \ |
95 | }, \ |
96 | } |
97 | |
98 | static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = { |
99 | RK3036_CPUCLK_RATE(816000000, 4), |
100 | RK3036_CPUCLK_RATE(600000000, 4), |
101 | RK3036_CPUCLK_RATE(312000000, 4), |
102 | }; |
103 | |
104 | static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { |
105 | .core_reg[0] = RK2928_CLKSEL_CON(0), |
106 | .div_core_shift[0] = 0, |
107 | .div_core_mask[0] = 0x1f, |
108 | .num_cores = 1, |
109 | .mux_core_alt = 1, |
110 | .mux_core_main = 0, |
111 | .mux_core_shift = 7, |
112 | .mux_core_mask = 0x1, |
113 | }; |
114 | |
115 | PNAME(mux_pll_p) = { "xin24m" , "xin24m" }; |
116 | |
117 | PNAME(mux_armclk_p) = { "apll" , "gpll_armclk" }; |
118 | PNAME(mux_busclk_p) = { "apll" , "dpll_cpu" , "gpll_cpu" }; |
119 | PNAME(mux_ddrphy_p) = { "dpll_ddr" , "gpll_ddr" }; |
120 | PNAME(mux_pll_src_3plls_p) = { "apll" , "dpll" , "gpll" }; |
121 | PNAME(mux_timer_p) = { "xin24m" , "pclk_peri_src" }; |
122 | |
123 | PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll" , "dpll" , "gpll" , "usb480m" }; |
124 | PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll" , "dpll" , "gpll" , "xin24m" }; |
125 | |
126 | PNAME(mux_mmc_src_p) = { "apll" , "dpll" , "gpll" , "xin24m" }; |
127 | PNAME(mux_i2s_pre_p) = { "i2s_src" , "i2s_frac" , "ext_i2s" , "xin12m" }; |
128 | PNAME(mux_i2s_clkout_p) = { "i2s_pre" , "xin12m" }; |
129 | PNAME(mux_spdif_p) = { "spdif_src" , "spdif_frac" , "xin12m" }; |
130 | PNAME(mux_uart0_p) = { "uart0_src" , "uart0_frac" , "xin24m" }; |
131 | PNAME(mux_uart1_p) = { "uart1_src" , "uart1_frac" , "xin24m" }; |
132 | PNAME(mux_uart2_p) = { "uart2_src" , "uart2_frac" , "xin24m" }; |
133 | PNAME(mux_mac_p) = { "mac_pll_src" , "rmii_clkin" }; |
134 | PNAME(mux_dclk_p) = { "dclk_lcdc" , "dclk_cru" }; |
135 | |
136 | static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { |
137 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll" , mux_pll_p, 0, RK2928_PLL_CON(0), |
138 | RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates), |
139 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll" , mux_pll_p, 0, RK2928_PLL_CON(4), |
140 | RK2928_MODE_CON, 4, 4, 0, NULL), |
141 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll" , mux_pll_p, 0, RK2928_PLL_CON(12), |
142 | RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates), |
143 | }; |
144 | |
145 | #define MFLAGS CLK_MUX_HIWORD_MASK |
146 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
147 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
148 | |
149 | static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata = |
150 | MUX(SCLK_UART0, "sclk_uart0" , mux_uart0_p, CLK_SET_RATE_PARENT, |
151 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); |
152 | |
153 | static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata = |
154 | MUX(SCLK_UART1, "sclk_uart1" , mux_uart1_p, CLK_SET_RATE_PARENT, |
155 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); |
156 | |
157 | static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata = |
158 | MUX(SCLK_UART2, "sclk_uart2" , mux_uart2_p, CLK_SET_RATE_PARENT, |
159 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); |
160 | |
161 | static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata = |
162 | MUX(0, "i2s_pre" , mux_i2s_pre_p, CLK_SET_RATE_PARENT, |
163 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); |
164 | |
165 | static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata = |
166 | MUX(SCLK_SPDIF, "sclk_spdif" , mux_spdif_p, 0, |
167 | RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); |
168 | |
169 | static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { |
170 | /* |
171 | * Clock-Architecture Diagram 1 |
172 | */ |
173 | |
174 | GATE(0, "gpll_armclk" , "gpll" , CLK_IGNORE_UNUSED, |
175 | RK2928_CLKGATE_CON(0), 6, GFLAGS), |
176 | |
177 | FACTOR(0, "xin12m" , "xin24m" , 0, 1, 2), |
178 | |
179 | /* |
180 | * Clock-Architecture Diagram 2 |
181 | */ |
182 | |
183 | GATE(0, "dpll_ddr" , "dpll" , CLK_IGNORE_UNUSED, |
184 | RK2928_CLKGATE_CON(0), 2, GFLAGS), |
185 | GATE(0, "gpll_ddr" , "gpll" , CLK_IGNORE_UNUSED, |
186 | RK2928_CLKGATE_CON(0), 8, GFLAGS), |
187 | COMPOSITE_NOGATE(0, "ddrphy2x" , mux_ddrphy_p, CLK_IGNORE_UNUSED, |
188 | RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), |
189 | FACTOR(0, "ddrphy" , "ddrphy2x" , 0, 1, 2), |
190 | |
191 | COMPOSITE_NOMUX(0, "pclk_dbg" , "armclk" , CLK_IGNORE_UNUSED, |
192 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, |
193 | RK2928_CLKGATE_CON(0), 7, GFLAGS), |
194 | COMPOSITE_NOMUX(0, "aclk_core_pre" , "armclk" , CLK_IGNORE_UNUSED, |
195 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
196 | RK2928_CLKGATE_CON(0), 7, GFLAGS), |
197 | |
198 | GATE(0, "dpll_cpu" , "dpll" , 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), |
199 | GATE(0, "gpll_cpu" , "gpll" , 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), |
200 | COMPOSITE_NOGATE(0, "aclk_cpu_src" , mux_busclk_p, 0, |
201 | RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS), |
202 | GATE(ACLK_CPU, "aclk_cpu" , "aclk_cpu_src" , CLK_IGNORE_UNUSED, |
203 | RK2928_CLKGATE_CON(0), 3, GFLAGS), |
204 | COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu" , "aclk_cpu_src" , CLK_IGNORE_UNUSED, |
205 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
206 | RK2928_CLKGATE_CON(0), 5, GFLAGS), |
207 | COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu" , "aclk_cpu_src" , CLK_IGNORE_UNUSED, |
208 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, |
209 | RK2928_CLKGATE_CON(0), 4, GFLAGS), |
210 | |
211 | COMPOSITE(0, "aclk_peri_src" , mux_pll_src_3plls_p, 0, |
212 | RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, |
213 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
214 | |
215 | GATE(ACLK_PERI, "aclk_peri" , "aclk_peri_src" , 0, |
216 | RK2928_CLKGATE_CON(2), 1, GFLAGS), |
217 | DIV(0, "pclk_peri_src" , "aclk_peri_src" , CLK_IGNORE_UNUSED, |
218 | RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), |
219 | GATE(PCLK_PERI, "pclk_peri" , "pclk_peri_src" , 0, |
220 | RK2928_CLKGATE_CON(2), 3, GFLAGS), |
221 | DIV(0, "hclk_peri_src" , "aclk_peri_src" , CLK_IGNORE_UNUSED, |
222 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), |
223 | GATE(HCLK_PERI, "hclk_peri" , "hclk_peri_src" , 0, |
224 | RK2928_CLKGATE_CON(2), 2, GFLAGS), |
225 | |
226 | COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0" , mux_timer_p, CLK_IGNORE_UNUSED, |
227 | RK2928_CLKSEL_CON(2), 4, 1, MFLAGS, |
228 | RK2928_CLKGATE_CON(1), 0, GFLAGS), |
229 | COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1" , mux_timer_p, CLK_IGNORE_UNUSED, |
230 | RK2928_CLKSEL_CON(2), 5, 1, MFLAGS, |
231 | RK2928_CLKGATE_CON(1), 1, GFLAGS), |
232 | COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2" , mux_timer_p, CLK_IGNORE_UNUSED, |
233 | RK2928_CLKSEL_CON(2), 6, 1, MFLAGS, |
234 | RK2928_CLKGATE_CON(2), 4, GFLAGS), |
235 | COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3" , mux_timer_p, CLK_IGNORE_UNUSED, |
236 | RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, |
237 | RK2928_CLKGATE_CON(2), 5, GFLAGS), |
238 | |
239 | MUX(0, "uart_pll_clk" , mux_pll_src_apll_dpll_gpll_usb480m_p, 0, |
240 | RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), |
241 | COMPOSITE_NOMUX(0, "uart0_src" , "uart_pll_clk" , 0, |
242 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, |
243 | RK2928_CLKGATE_CON(1), 8, GFLAGS), |
244 | COMPOSITE_NOMUX(0, "uart1_src" , "uart_pll_clk" , 0, |
245 | RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, |
246 | RK2928_CLKGATE_CON(1), 10, GFLAGS), |
247 | COMPOSITE_NOMUX(0, "uart2_src" , "uart_pll_clk" , 0, |
248 | RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, |
249 | RK2928_CLKGATE_CON(1), 12, GFLAGS), |
250 | COMPOSITE_FRACMUX(0, "uart0_frac" , "uart0_src" , CLK_SET_RATE_PARENT, |
251 | RK2928_CLKSEL_CON(17), 0, |
252 | RK2928_CLKGATE_CON(1), 9, GFLAGS, |
253 | &rk3036_uart0_fracmux), |
254 | COMPOSITE_FRACMUX(0, "uart1_frac" , "uart1_src" , CLK_SET_RATE_PARENT, |
255 | RK2928_CLKSEL_CON(18), 0, |
256 | RK2928_CLKGATE_CON(1), 11, GFLAGS, |
257 | &rk3036_uart1_fracmux), |
258 | COMPOSITE_FRACMUX(0, "uart2_frac" , "uart2_src" , CLK_SET_RATE_PARENT, |
259 | RK2928_CLKSEL_CON(19), 0, |
260 | RK2928_CLKGATE_CON(1), 13, GFLAGS, |
261 | &rk3036_uart2_fracmux), |
262 | |
263 | COMPOSITE(ACLK_VCODEC, "aclk_vcodec" , mux_pll_src_3plls_p, 0, |
264 | RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, |
265 | RK2928_CLKGATE_CON(3), 11, GFLAGS), |
266 | FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec" , "aclk_vcodec" , 0, 1, 4, |
267 | RK2928_CLKGATE_CON(3), 12, GFLAGS), |
268 | |
269 | COMPOSITE(0, "aclk_hvec" , mux_pll_src_3plls_p, 0, |
270 | RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, |
271 | RK2928_CLKGATE_CON(10), 6, GFLAGS), |
272 | |
273 | COMPOSITE(0, "aclk_disp1_pre" , mux_pll_src_3plls_p, 0, |
274 | RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, |
275 | RK2928_CLKGATE_CON(1), 4, GFLAGS), |
276 | COMPOSITE(0, "hclk_disp_pre" , mux_pll_src_3plls_p, 0, |
277 | RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, |
278 | RK2928_CLKGATE_CON(0), 11, GFLAGS), |
279 | COMPOSITE(SCLK_LCDC, "dclk_lcdc" , mux_pll_src_3plls_p, 0, |
280 | RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, |
281 | RK2928_CLKGATE_CON(3), 2, GFLAGS), |
282 | |
283 | COMPOSITE_NODIV(0, "sclk_sdmmc_src" , mux_mmc_src_p, 0, |
284 | RK2928_CLKSEL_CON(12), 8, 2, MFLAGS, |
285 | RK2928_CLKGATE_CON(2), 11, GFLAGS), |
286 | DIV(SCLK_SDMMC, "sclk_sdmmc" , "sclk_sdmmc_src" , 0, |
287 | RK2928_CLKSEL_CON(11), 0, 7, DFLAGS), |
288 | |
289 | COMPOSITE_NODIV(0, "sclk_sdio_src" , mux_mmc_src_p, 0, |
290 | RK2928_CLKSEL_CON(12), 10, 2, MFLAGS, |
291 | RK2928_CLKGATE_CON(2), 13, GFLAGS), |
292 | DIV(SCLK_SDIO, "sclk_sdio" , "sclk_sdio_src" , 0, |
293 | RK2928_CLKSEL_CON(11), 8, 7, DFLAGS), |
294 | |
295 | COMPOSITE(SCLK_EMMC, "sclk_emmc" , mux_mmc_src_p, 0, |
296 | RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS, |
297 | RK2928_CLKGATE_CON(2), 14, GFLAGS), |
298 | |
299 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv" , "sclk_sdmmc" , RK3036_SDMMC_CON0, 1), |
300 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample" , "sclk_sdmmc" , RK3036_SDMMC_CON1, 0), |
301 | |
302 | MMC(SCLK_SDIO_DRV, "sdio_drv" , "sclk_sdio" , RK3036_SDIO_CON0, 1), |
303 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample" , "sclk_sdio" , RK3036_SDIO_CON1, 0), |
304 | |
305 | MMC(SCLK_EMMC_DRV, "emmc_drv" , "sclk_emmc" , RK3036_EMMC_CON0, 1), |
306 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample" , "sclk_emmc" , RK3036_EMMC_CON1, 0), |
307 | |
308 | COMPOSITE(0, "i2s_src" , mux_pll_src_3plls_p, 0, |
309 | RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, |
310 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
311 | COMPOSITE_FRACMUX(0, "i2s_frac" , "i2s_src" , CLK_SET_RATE_PARENT, |
312 | RK2928_CLKSEL_CON(7), 0, |
313 | RK2928_CLKGATE_CON(0), 10, GFLAGS, |
314 | &rk3036_i2s_fracmux), |
315 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout" , mux_i2s_clkout_p, 0, |
316 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, |
317 | RK2928_CLKGATE_CON(0), 13, GFLAGS), |
318 | GATE(SCLK_I2S, "sclk_i2s" , "i2s_pre" , CLK_SET_RATE_PARENT, |
319 | RK2928_CLKGATE_CON(0), 14, GFLAGS), |
320 | |
321 | COMPOSITE(0, "spdif_src" , mux_pll_src_3plls_p, 0, |
322 | RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS, |
323 | RK2928_CLKGATE_CON(2), 10, GFLAGS), |
324 | COMPOSITE_FRACMUX(0, "spdif_frac" , "spdif_src" , 0, |
325 | RK2928_CLKSEL_CON(9), 0, |
326 | RK2928_CLKGATE_CON(2), 12, GFLAGS, |
327 | &rk3036_spdif_fracmux), |
328 | |
329 | GATE(SCLK_OTGPHY0, "sclk_otgphy0" , "xin12m" , CLK_IGNORE_UNUSED, |
330 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
331 | |
332 | COMPOSITE(SCLK_GPU, "sclk_gpu" , mux_pll_src_3plls_p, 0, |
333 | RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS, |
334 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
335 | |
336 | COMPOSITE(SCLK_SPI, "sclk_spi" , mux_pll_src_3plls_p, 0, |
337 | RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, |
338 | RK2928_CLKGATE_CON(2), 9, GFLAGS), |
339 | |
340 | COMPOSITE(SCLK_NANDC, "sclk_nandc" , mux_pll_src_3plls_p, 0, |
341 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, |
342 | RK2928_CLKGATE_CON(10), 4, GFLAGS), |
343 | |
344 | COMPOSITE(SCLK_SFC, "sclk_sfc" , mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0, |
345 | RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, |
346 | RK2928_CLKGATE_CON(10), 5, GFLAGS), |
347 | |
348 | COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src" , mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT, |
349 | RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), |
350 | MUX(SCLK_MACREF, "mac_clk_ref" , mux_mac_p, CLK_SET_RATE_PARENT, |
351 | RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), |
352 | |
353 | COMPOSITE_NOMUX(SCLK_MAC, "mac_clk" , "mac_clk_ref" , 0, |
354 | RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, |
355 | RK2928_CLKGATE_CON(2), 6, GFLAGS), |
356 | FACTOR(0, "sclk_macref_out" , "hclk_peri_src" , 0, 1, 2), |
357 | |
358 | MUX(SCLK_HDMI, "dclk_hdmi" , mux_dclk_p, 0, |
359 | RK2928_CLKSEL_CON(31), 0, 1, MFLAGS), |
360 | |
361 | /* |
362 | * Clock-Architecture Diagram 3 |
363 | */ |
364 | |
365 | /* aclk_cpu gates */ |
366 | GATE(0, "sclk_intmem" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), |
367 | GATE(0, "aclk_strc_sys" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), |
368 | |
369 | /* hclk_cpu gates */ |
370 | GATE(HCLK_ROM, "hclk_rom" , "hclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), |
371 | |
372 | /* pclk_cpu gates */ |
373 | GATE(PCLK_GRF, "pclk_grf" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), |
374 | GATE(PCLK_DDRUPCTL, "pclk_ddrupctl" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), |
375 | GATE(PCLK_ACODEC, "pclk_acodec" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), |
376 | GATE(PCLK_HDMI, "pclk_hdmi" , "pclk_cpu" , 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), |
377 | |
378 | /* aclk_vio gates */ |
379 | GATE(ACLK_VIO, "aclk_vio" , "aclk_disp1_pre" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), |
380 | GATE(ACLK_LCDC, "aclk_lcdc" , "aclk_disp1_pre" , 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), |
381 | |
382 | GATE(HCLK_VIO_BUS, "hclk_vio_bus" , "hclk_disp_pre" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS), |
383 | GATE(HCLK_LCDC, "hclk_lcdc" , "hclk_disp_pre" , 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), |
384 | |
385 | |
386 | /* xin24m gates */ |
387 | GATE(SCLK_PVTM_CORE, "sclk_pvtm_core" , "xin24m" , 0, RK2928_CLKGATE_CON(10), 0, GFLAGS), |
388 | GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu" , "xin24m" , 0, RK2928_CLKGATE_CON(10), 1, GFLAGS), |
389 | |
390 | /* aclk_peri gates */ |
391 | GATE(0, "aclk_peri_axi_matrix" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), |
392 | GATE(0, "aclk_cpu_peri" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), |
393 | GATE(ACLK_DMAC2, "aclk_dmac2" , "aclk_peri" , 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), |
394 | GATE(0, "aclk_peri_niu" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), |
395 | |
396 | /* hclk_peri gates */ |
397 | GATE(0, "hclk_peri_matrix" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), |
398 | GATE(0, "hclk_usb_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), |
399 | GATE(0, "hclk_peri_arbi" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), |
400 | GATE(HCLK_NANDC, "hclk_nandc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), |
401 | GATE(HCLK_SDMMC, "hclk_sdmmc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), |
402 | GATE(HCLK_SDIO, "hclk_sdio" , "hclk_peri" , 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), |
403 | GATE(HCLK_EMMC, "hclk_emmc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), |
404 | GATE(HCLK_OTG0, "hclk_otg0" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), |
405 | GATE(HCLK_OTG1, "hclk_otg1" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), |
406 | GATE(HCLK_I2S, "hclk_i2s" , "hclk_peri" , 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), |
407 | GATE(HCLK_SFC, "hclk_sfc" , "hclk_peri" , 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), |
408 | GATE(HCLK_MAC, "hclk_mac" , "hclk_peri" , 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), |
409 | |
410 | /* pclk_peri gates */ |
411 | GATE(0, "pclk_peri_matrix" , "pclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), |
412 | GATE(0, "pclk_efuse" , "pclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS), |
413 | GATE(PCLK_TIMER, "pclk_timer" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), |
414 | GATE(PCLK_PWM, "pclk_pwm" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), |
415 | GATE(PCLK_SPI, "pclk_spi" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), |
416 | GATE(PCLK_WDT, "pclk_wdt" , "pclk_peri" , 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), |
417 | GATE(PCLK_UART0, "pclk_uart0" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), |
418 | GATE(PCLK_UART1, "pclk_uart1" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), |
419 | GATE(PCLK_UART2, "pclk_uart2" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), |
420 | GATE(PCLK_I2C0, "pclk_i2c0" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), |
421 | GATE(PCLK_I2C1, "pclk_i2c1" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), |
422 | GATE(PCLK_I2C2, "pclk_i2c2" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), |
423 | GATE(PCLK_GPIO0, "pclk_gpio0" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), |
424 | GATE(PCLK_GPIO1, "pclk_gpio1" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), |
425 | GATE(PCLK_GPIO2, "pclk_gpio2" , "pclk_peri" , 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), |
426 | }; |
427 | |
428 | static const char *const rk3036_critical_clocks[] __initconst = { |
429 | "aclk_cpu" , |
430 | "aclk_peri" , |
431 | "hclk_peri" , |
432 | "pclk_peri" , |
433 | "pclk_ddrupctl" , |
434 | }; |
435 | |
436 | static void __init rk3036_clk_init(struct device_node *np) |
437 | { |
438 | struct rockchip_clk_provider *ctx; |
439 | void __iomem *reg_base; |
440 | struct clk *clk; |
441 | |
442 | reg_base = of_iomap(node: np, index: 0); |
443 | if (!reg_base) { |
444 | pr_err("%s: could not map cru region\n" , __func__); |
445 | return; |
446 | } |
447 | |
448 | /* |
449 | * Make uart_pll_clk a child of the gpll, as all other sources are |
450 | * not that usable / stable. |
451 | */ |
452 | writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), |
453 | reg_base + RK2928_CLKSEL_CON(13)); |
454 | |
455 | ctx = rockchip_clk_init(np, base: reg_base, CLK_NR_CLKS); |
456 | if (IS_ERR(ptr: ctx)) { |
457 | pr_err("%s: rockchip clk init failed\n" , __func__); |
458 | iounmap(addr: reg_base); |
459 | return; |
460 | } |
461 | |
462 | clk = clk_register_fixed_factor(NULL, name: "usb480m" , parent_name: "xin24m" , flags: 0, mult: 20, div: 1); |
463 | if (IS_ERR(ptr: clk)) |
464 | pr_warn("%s: could not register clock usb480m: %ld\n" , |
465 | __func__, PTR_ERR(clk)); |
466 | |
467 | rockchip_clk_register_plls(ctx, pll_list: rk3036_pll_clks, |
468 | ARRAY_SIZE(rk3036_pll_clks), |
469 | RK3036_GRF_SOC_STATUS0); |
470 | rockchip_clk_register_branches(ctx, list: rk3036_clk_branches, |
471 | ARRAY_SIZE(rk3036_clk_branches)); |
472 | rockchip_clk_protect_critical(clocks: rk3036_critical_clocks, |
473 | ARRAY_SIZE(rk3036_critical_clocks)); |
474 | |
475 | rockchip_clk_register_armclk(ctx, ARMCLK, name: "armclk" , |
476 | parent_names: mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
477 | reg_data: &rk3036_cpuclk_data, rates: rk3036_cpuclk_rates, |
478 | ARRAY_SIZE(rk3036_cpuclk_rates)); |
479 | |
480 | rockchip_register_softrst(np, num_regs: 9, base: reg_base + RK2928_SOFTRST_CON(0), |
481 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
482 | |
483 | rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); |
484 | |
485 | rockchip_clk_of_add_provider(np, ctx); |
486 | } |
487 | CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru" , rk3036_clk_init); |
488 | |