1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
4 | * Author: Xing Zheng <zhengxing@rock-chips.com> |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/module.h> |
9 | #include <linux/io.h> |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/property.h> |
14 | #include <linux/regmap.h> |
15 | #include <dt-bindings/clock/rk3399-cru.h> |
16 | #include "clk.h" |
17 | |
18 | enum rk3399_plls { |
19 | lpll, bpll, dpll, cpll, gpll, npll, vpll, |
20 | }; |
21 | |
22 | enum rk3399_pmu_plls { |
23 | ppll, |
24 | }; |
25 | |
26 | static struct rockchip_pll_rate_table rk3399_pll_rates[] = { |
27 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
28 | RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), |
29 | RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), |
30 | RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), |
31 | RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), |
32 | RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), |
33 | RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), |
34 | RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), |
35 | RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), |
36 | RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), |
37 | RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), |
38 | RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), |
39 | RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), |
40 | RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), |
41 | RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), |
42 | RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), |
43 | RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), |
44 | RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), |
45 | RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), |
46 | RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), |
47 | RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), |
48 | RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), |
49 | RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), |
50 | RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), |
51 | RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), |
52 | RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), |
53 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), |
54 | RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), |
55 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), |
56 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), |
57 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), |
58 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), |
59 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), |
60 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), |
61 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), |
62 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), |
63 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), |
64 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), |
65 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), |
66 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), |
67 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), |
68 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), |
69 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), |
70 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), |
71 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), |
72 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), |
73 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), |
74 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), |
75 | RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), |
76 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), |
77 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), |
78 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), |
79 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), |
80 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), |
81 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), |
82 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), |
83 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), |
84 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), |
85 | RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), |
86 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), |
87 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), |
88 | RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), |
89 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), |
90 | RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), |
91 | RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), |
92 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), |
93 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), |
94 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |
95 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), |
96 | RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), |
97 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), |
98 | RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), |
99 | RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), |
100 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), |
101 | RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), |
102 | RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), |
103 | RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), |
104 | RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), |
105 | { /* sentinel */ }, |
106 | }; |
107 | |
108 | /* CRU parents */ |
109 | PNAME(mux_pll_p) = { "xin24m" , "xin32k" }; |
110 | |
111 | PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src" , |
112 | "clk_core_l_bpll_src" , |
113 | "clk_core_l_dpll_src" , |
114 | "clk_core_l_gpll_src" }; |
115 | PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src" , |
116 | "clk_core_b_bpll_src" , |
117 | "clk_core_b_dpll_src" , |
118 | "clk_core_b_gpll_src" }; |
119 | PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src" , |
120 | "clk_ddrc_bpll_src" , |
121 | "clk_ddrc_dpll_src" , |
122 | "clk_ddrc_gpll_src" }; |
123 | PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src" , |
124 | "gpll_aclk_cci_src" , |
125 | "npll_aclk_cci_src" , |
126 | "vpll_aclk_cci_src" }; |
127 | PNAME(mux_cci_trace_p) = { "cpll_cci_trace" , |
128 | "gpll_cci_trace" }; |
129 | PNAME(mux_cs_p) = { "cpll_cs" , "gpll_cs" , |
130 | "npll_cs" }; |
131 | PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src" , |
132 | "gpll_aclk_perihp_src" }; |
133 | |
134 | PNAME(mux_pll_src_cpll_gpll_p) = { "cpll" , "gpll" }; |
135 | PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll" , "gpll" , "npll" }; |
136 | PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll" , "gpll" , "ppll" }; |
137 | PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll" , "gpll" , "upll" }; |
138 | PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll" , "cpll" , "gpll" }; |
139 | PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll" , "gpll" , "npll" , |
140 | "ppll" }; |
141 | PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll" , "gpll" , "npll" , |
142 | "xin24m" }; |
143 | PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll" , "gpll" , "npll" , |
144 | "clk_usbphy_480m" }; |
145 | PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll" , "cpll" , "gpll" , |
146 | "npll" , "upll" }; |
147 | PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll" , "gpll" , "npll" , |
148 | "upll" , "xin24m" }; |
149 | PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll" , "gpll" , "npll" , |
150 | "ppll" , "upll" , "xin24m" }; |
151 | |
152 | PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll" , "cpll" , "gpll" }; |
153 | PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll" , "cpll" , "gpll" , |
154 | "npll" }; |
155 | PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll" , "cpll" , "gpll" , |
156 | "xin24m" }; |
157 | |
158 | PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div" , |
159 | "dclk_vop0_frac" }; |
160 | PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div" , |
161 | "dclk_vop1_frac" }; |
162 | |
163 | PNAME(mux_clk_cif_p) = { "clk_cifout_src" , "xin24m" }; |
164 | |
165 | PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m" , "clk_usbphy_480m" }; |
166 | PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m" , "clk_pciephy_ref100m" }; |
167 | PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m" , "xin32k" , |
168 | "cpll" , "gpll" }; |
169 | PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru" , |
170 | "clk_pcie_core_phy" }; |
171 | |
172 | PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src" , |
173 | "gpll_aclk_emmc_src" }; |
174 | |
175 | PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src" , |
176 | "gpll_aclk_perilp0_src" }; |
177 | |
178 | PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src" , |
179 | "gpll_fclk_cm0s_src" }; |
180 | |
181 | PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src" , |
182 | "gpll_hclk_perilp1_src" }; |
183 | |
184 | PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src" , "xin24m" }; |
185 | PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src" , "xin24m" }; |
186 | |
187 | PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src" , |
188 | "clk_usbphy1_480m_src" }; |
189 | PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src" , |
190 | "gpll_aclk_gmac_src" }; |
191 | PNAME(mux_rmii_p) = { "clk_gmac" , "clkin_gmac" }; |
192 | PNAME(mux_spdif_p) = { "clk_spdif_div" , "clk_spdif_frac" , |
193 | "clkin_i2s" , "xin12m" }; |
194 | PNAME(mux_i2s0_p) = { "clk_i2s0_div" , "clk_i2s0_frac" , |
195 | "clkin_i2s" , "xin12m" }; |
196 | PNAME(mux_i2s1_p) = { "clk_i2s1_div" , "clk_i2s1_frac" , |
197 | "clkin_i2s" , "xin12m" }; |
198 | PNAME(mux_i2s2_p) = { "clk_i2s2_div" , "clk_i2s2_frac" , |
199 | "clkin_i2s" , "xin12m" }; |
200 | PNAME(mux_i2sch_p) = { "clk_i2s0" , "clk_i2s1" , |
201 | "clk_i2s2" }; |
202 | PNAME(mux_i2sout_p) = { "clk_i2sout_src" , "xin12m" }; |
203 | |
204 | PNAME(mux_uart0_p) = { "clk_uart0_div" , "clk_uart0_frac" , "xin24m" }; |
205 | PNAME(mux_uart1_p) = { "clk_uart1_div" , "clk_uart1_frac" , "xin24m" }; |
206 | PNAME(mux_uart2_p) = { "clk_uart2_div" , "clk_uart2_frac" , "xin24m" }; |
207 | PNAME(mux_uart3_p) = { "clk_uart3_div" , "clk_uart3_frac" , "xin24m" }; |
208 | |
209 | /* PMU CRU parents */ |
210 | PNAME(mux_ppll_24m_p) = { "ppll" , "xin24m" }; |
211 | PNAME(mux_24m_ppll_p) = { "xin24m" , "ppll" }; |
212 | PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src" , "xin24m" }; |
213 | PNAME(mux_wifi_pmu_p) = { "clk_wifi_div" , "clk_wifi_frac" }; |
214 | PNAME(mux_uart4_pmu_p) = { "clk_uart4_div" , "clk_uart4_frac" , |
215 | "xin24m" }; |
216 | PNAME(mux_clk_testout2_2io_p) = { "clk_testout2" , "clk_32k_suspend_pmu" }; |
217 | |
218 | static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { |
219 | [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll" , mux_pll_p, 0, RK3399_PLL_CON(0), |
220 | RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), |
221 | [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll" , mux_pll_p, 0, RK3399_PLL_CON(8), |
222 | RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), |
223 | [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll" , mux_pll_p, 0, RK3399_PLL_CON(16), |
224 | RK3399_PLL_CON(19), 8, 31, 0, NULL), |
225 | [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll" , mux_pll_p, 0, RK3399_PLL_CON(24), |
226 | RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
227 | [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll" , mux_pll_p, 0, RK3399_PLL_CON(32), |
228 | RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
229 | [npll] = PLL(pll_rk3399, PLL_NPLL, "npll" , mux_pll_p, 0, RK3399_PLL_CON(40), |
230 | RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
231 | [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll" , mux_pll_p, 0, RK3399_PLL_CON(48), |
232 | RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
233 | }; |
234 | |
235 | static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { |
236 | [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll" , mux_pll_p, 0, RK3399_PMU_PLL_CON(0), |
237 | RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
238 | }; |
239 | |
240 | #define MFLAGS CLK_MUX_HIWORD_MASK |
241 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
242 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
243 | #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK |
244 | |
245 | static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = |
246 | MUX(0, "clk_spdif_mux" , mux_spdif_p, CLK_SET_RATE_PARENT, |
247 | RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); |
248 | |
249 | static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = |
250 | MUX(0, "clk_i2s0_mux" , mux_i2s0_p, CLK_SET_RATE_PARENT, |
251 | RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); |
252 | |
253 | static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = |
254 | MUX(0, "clk_i2s1_mux" , mux_i2s1_p, CLK_SET_RATE_PARENT, |
255 | RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); |
256 | |
257 | static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = |
258 | MUX(0, "clk_i2s2_mux" , mux_i2s2_p, CLK_SET_RATE_PARENT, |
259 | RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); |
260 | |
261 | static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = |
262 | MUX(SCLK_UART0, "clk_uart0" , mux_uart0_p, CLK_SET_RATE_PARENT, |
263 | RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); |
264 | |
265 | static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = |
266 | MUX(SCLK_UART1, "clk_uart1" , mux_uart1_p, CLK_SET_RATE_PARENT, |
267 | RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); |
268 | |
269 | static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = |
270 | MUX(SCLK_UART2, "clk_uart2" , mux_uart2_p, CLK_SET_RATE_PARENT, |
271 | RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); |
272 | |
273 | static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = |
274 | MUX(SCLK_UART3, "clk_uart3" , mux_uart3_p, CLK_SET_RATE_PARENT, |
275 | RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); |
276 | |
277 | static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = |
278 | MUX(SCLK_UART4_PMU, "clk_uart4_pmu" , mux_uart4_pmu_p, CLK_SET_RATE_PARENT, |
279 | RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); |
280 | |
281 | static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = |
282 | MUX(DCLK_VOP0, "dclk_vop0" , mux_dclk_vop0_p, CLK_SET_RATE_PARENT, |
283 | RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); |
284 | |
285 | static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = |
286 | MUX(DCLK_VOP1, "dclk_vop1" , mux_dclk_vop1_p, CLK_SET_RATE_PARENT, |
287 | RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); |
288 | |
289 | static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = |
290 | MUX(SCLK_WIFI_PMU, "clk_wifi_pmu" , mux_wifi_pmu_p, CLK_SET_RATE_PARENT, |
291 | RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); |
292 | |
293 | static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { |
294 | .core_reg[0] = RK3399_CLKSEL_CON(0), |
295 | .div_core_shift[0] = 0, |
296 | .div_core_mask[0] = 0x1f, |
297 | .num_cores = 1, |
298 | .mux_core_alt = 3, |
299 | .mux_core_main = 0, |
300 | .mux_core_shift = 6, |
301 | .mux_core_mask = 0x3, |
302 | }; |
303 | |
304 | static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { |
305 | .core_reg[0] = RK3399_CLKSEL_CON(2), |
306 | .div_core_shift[0] = 0, |
307 | .div_core_mask[0] = 0x1f, |
308 | .num_cores = 1, |
309 | .mux_core_alt = 3, |
310 | .mux_core_main = 1, |
311 | .mux_core_shift = 6, |
312 | .mux_core_mask = 0x3, |
313 | }; |
314 | |
315 | #define RK3399_DIV_ACLKM_MASK 0x1f |
316 | #define RK3399_DIV_ACLKM_SHIFT 8 |
317 | #define RK3399_DIV_ATCLK_MASK 0x1f |
318 | #define RK3399_DIV_ATCLK_SHIFT 0 |
319 | #define RK3399_DIV_PCLK_DBG_MASK 0x1f |
320 | #define RK3399_DIV_PCLK_DBG_SHIFT 8 |
321 | |
322 | #define RK3399_CLKSEL0(_offs, _aclkm) \ |
323 | { \ |
324 | .reg = RK3399_CLKSEL_CON(0 + _offs), \ |
325 | .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ |
326 | RK3399_DIV_ACLKM_SHIFT), \ |
327 | } |
328 | #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ |
329 | { \ |
330 | .reg = RK3399_CLKSEL_CON(1 + _offs), \ |
331 | .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ |
332 | RK3399_DIV_ATCLK_SHIFT) | \ |
333 | HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ |
334 | RK3399_DIV_PCLK_DBG_SHIFT), \ |
335 | } |
336 | |
337 | /* cluster_l: aclkm in clksel0, rest in clksel1 */ |
338 | #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ |
339 | { \ |
340 | .prate = _prate##U, \ |
341 | .divs = { \ |
342 | RK3399_CLKSEL0(0, _aclkm), \ |
343 | RK3399_CLKSEL1(0, _atclk, _pdbg), \ |
344 | }, \ |
345 | } |
346 | |
347 | /* cluster_b: aclkm in clksel2, rest in clksel3 */ |
348 | #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ |
349 | { \ |
350 | .prate = _prate##U, \ |
351 | .divs = { \ |
352 | RK3399_CLKSEL0(2, _aclkm), \ |
353 | RK3399_CLKSEL1(2, _atclk, _pdbg), \ |
354 | }, \ |
355 | } |
356 | |
357 | static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { |
358 | RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), |
359 | RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), |
360 | RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), |
361 | RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), |
362 | RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), |
363 | RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), |
364 | RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), |
365 | RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), |
366 | RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), |
367 | RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), |
368 | RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), |
369 | RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), |
370 | RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), |
371 | RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), |
372 | RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), |
373 | }; |
374 | |
375 | static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { |
376 | RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), |
377 | RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), |
378 | RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), |
379 | RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), |
380 | RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), |
381 | RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), |
382 | RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), |
383 | RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), |
384 | RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), |
385 | RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), |
386 | RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), |
387 | RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), |
388 | RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), |
389 | RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), |
390 | RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), |
391 | RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), |
392 | RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), |
393 | RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), |
394 | RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), |
395 | RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), |
396 | RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), |
397 | RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), |
398 | }; |
399 | |
400 | static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { |
401 | /* |
402 | * CRU Clock-Architecture |
403 | */ |
404 | |
405 | /* usbphy */ |
406 | GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref" , "xin24m" , CLK_IGNORE_UNUSED, |
407 | RK3399_CLKGATE_CON(6), 5, GFLAGS), |
408 | GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref" , "xin24m" , CLK_IGNORE_UNUSED, |
409 | RK3399_CLKGATE_CON(6), 6, GFLAGS), |
410 | |
411 | GATE(0, "clk_usbphy0_480m_src" , "clk_usbphy0_480m" , 0, |
412 | RK3399_CLKGATE_CON(13), 12, GFLAGS), |
413 | GATE(0, "clk_usbphy1_480m_src" , "clk_usbphy1_480m" , 0, |
414 | RK3399_CLKGATE_CON(13), 12, GFLAGS), |
415 | MUX(0, "clk_usbphy_480m" , mux_usbphy_480m_p, 0, |
416 | RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), |
417 | |
418 | MUX(0, "upll" , mux_pll_src_24m_usbphy480m_p, 0, |
419 | RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), |
420 | |
421 | COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy" , mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, |
422 | RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, |
423 | RK3399_CLKGATE_CON(6), 4, GFLAGS), |
424 | |
425 | COMPOSITE(ACLK_USB3, "aclk_usb3" , mux_pll_src_cpll_gpll_npll_p, 0, |
426 | RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, |
427 | RK3399_CLKGATE_CON(12), 0, GFLAGS), |
428 | GATE(ACLK_USB3_NOC, "aclk_usb3_noc" , "aclk_usb3" , CLK_IGNORE_UNUSED, |
429 | RK3399_CLKGATE_CON(30), 0, GFLAGS), |
430 | GATE(ACLK_USB3OTG0, "aclk_usb3otg0" , "aclk_usb3" , 0, |
431 | RK3399_CLKGATE_CON(30), 1, GFLAGS), |
432 | GATE(ACLK_USB3OTG1, "aclk_usb3otg1" , "aclk_usb3" , 0, |
433 | RK3399_CLKGATE_CON(30), 2, GFLAGS), |
434 | GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf" , "aclk_usb3" , 0, |
435 | RK3399_CLKGATE_CON(30), 3, GFLAGS), |
436 | GATE(ACLK_USB3_GRF, "aclk_usb3_grf" , "aclk_usb3" , 0, |
437 | RK3399_CLKGATE_CON(30), 4, GFLAGS), |
438 | |
439 | GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref" , "xin24m" , 0, |
440 | RK3399_CLKGATE_CON(12), 1, GFLAGS), |
441 | GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref" , "xin24m" , 0, |
442 | RK3399_CLKGATE_CON(12), 2, GFLAGS), |
443 | |
444 | COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend" , mux_pll_p, 0, |
445 | RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, |
446 | RK3399_CLKGATE_CON(12), 3, GFLAGS), |
447 | |
448 | COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend" , mux_pll_p, 0, |
449 | RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, |
450 | RK3399_CLKGATE_CON(12), 4, GFLAGS), |
451 | |
452 | COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref" , mux_pll_p, 0, |
453 | RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, |
454 | RK3399_CLKGATE_CON(13), 4, GFLAGS), |
455 | |
456 | COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore" , mux_pll_src_24m_32k_cpll_gpll_p, 0, |
457 | RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, |
458 | RK3399_CLKGATE_CON(13), 5, GFLAGS), |
459 | |
460 | COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref" , mux_pll_p, 0, |
461 | RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, |
462 | RK3399_CLKGATE_CON(13), 6, GFLAGS), |
463 | |
464 | COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore" , mux_pll_src_24m_32k_cpll_gpll_p, 0, |
465 | RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, |
466 | RK3399_CLKGATE_CON(13), 7, GFLAGS), |
467 | |
468 | /* little core */ |
469 | GATE(0, "clk_core_l_lpll_src" , "lpll" , CLK_IGNORE_UNUSED, |
470 | RK3399_CLKGATE_CON(0), 0, GFLAGS), |
471 | GATE(0, "clk_core_l_bpll_src" , "bpll" , CLK_IGNORE_UNUSED, |
472 | RK3399_CLKGATE_CON(0), 1, GFLAGS), |
473 | GATE(0, "clk_core_l_dpll_src" , "dpll" , CLK_IGNORE_UNUSED, |
474 | RK3399_CLKGATE_CON(0), 2, GFLAGS), |
475 | GATE(0, "clk_core_l_gpll_src" , "gpll" , CLK_IGNORE_UNUSED, |
476 | RK3399_CLKGATE_CON(0), 3, GFLAGS), |
477 | |
478 | COMPOSITE_NOMUX(0, "aclkm_core_l" , "armclkl" , CLK_IGNORE_UNUSED, |
479 | RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
480 | RK3399_CLKGATE_CON(0), 4, GFLAGS), |
481 | COMPOSITE_NOMUX(0, "atclk_core_l" , "armclkl" , CLK_IGNORE_UNUSED, |
482 | RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
483 | RK3399_CLKGATE_CON(0), 5, GFLAGS), |
484 | COMPOSITE_NOMUX(PCLK_COREDBG_L, "pclk_dbg_core_l" , "armclkl" , CLK_IGNORE_UNUSED, |
485 | RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
486 | RK3399_CLKGATE_CON(0), 6, GFLAGS), |
487 | |
488 | GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500" , "aclkm_core_l" , CLK_IGNORE_UNUSED, |
489 | RK3399_CLKGATE_CON(14), 12, GFLAGS), |
490 | GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l" , "aclkm_core_l" , CLK_IGNORE_UNUSED, |
491 | RK3399_CLKGATE_CON(14), 13, GFLAGS), |
492 | |
493 | GATE(0, "clk_dbg_pd_core_l" , "armclkl" , CLK_IGNORE_UNUSED, |
494 | RK3399_CLKGATE_CON(14), 9, GFLAGS), |
495 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l" , "armclkl" , CLK_IGNORE_UNUSED, |
496 | RK3399_CLKGATE_CON(14), 10, GFLAGS), |
497 | GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic" , "armclkl" , CLK_IGNORE_UNUSED, |
498 | RK3399_CLKGATE_CON(14), 11, GFLAGS), |
499 | GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l" , "xin24m" , 0, |
500 | RK3399_CLKGATE_CON(0), 7, GFLAGS), |
501 | |
502 | /* big core */ |
503 | GATE(0, "clk_core_b_lpll_src" , "lpll" , CLK_IGNORE_UNUSED, |
504 | RK3399_CLKGATE_CON(1), 0, GFLAGS), |
505 | GATE(0, "clk_core_b_bpll_src" , "bpll" , CLK_IGNORE_UNUSED, |
506 | RK3399_CLKGATE_CON(1), 1, GFLAGS), |
507 | GATE(0, "clk_core_b_dpll_src" , "dpll" , CLK_IGNORE_UNUSED, |
508 | RK3399_CLKGATE_CON(1), 2, GFLAGS), |
509 | GATE(0, "clk_core_b_gpll_src" , "gpll" , CLK_IGNORE_UNUSED, |
510 | RK3399_CLKGATE_CON(1), 3, GFLAGS), |
511 | |
512 | COMPOSITE_NOMUX(0, "aclkm_core_b" , "armclkb" , CLK_IGNORE_UNUSED, |
513 | RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
514 | RK3399_CLKGATE_CON(1), 4, GFLAGS), |
515 | COMPOSITE_NOMUX(0, "atclk_core_b" , "armclkb" , CLK_IGNORE_UNUSED, |
516 | RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
517 | RK3399_CLKGATE_CON(1), 5, GFLAGS), |
518 | COMPOSITE_NOMUX(0, "pclk_dbg_core_b" , "armclkb" , CLK_IGNORE_UNUSED, |
519 | RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
520 | RK3399_CLKGATE_CON(1), 6, GFLAGS), |
521 | |
522 | GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500" , "aclkm_core_b" , CLK_IGNORE_UNUSED, |
523 | RK3399_CLKGATE_CON(14), 5, GFLAGS), |
524 | GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b" , "aclkm_core_b" , CLK_IGNORE_UNUSED, |
525 | RK3399_CLKGATE_CON(14), 6, GFLAGS), |
526 | |
527 | GATE(0, "clk_dbg_pd_core_b" , "armclkb" , CLK_IGNORE_UNUSED, |
528 | RK3399_CLKGATE_CON(14), 1, GFLAGS), |
529 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b" , "armclkb" , CLK_IGNORE_UNUSED, |
530 | RK3399_CLKGATE_CON(14), 3, GFLAGS), |
531 | GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic" , "armclkb" , CLK_IGNORE_UNUSED, |
532 | RK3399_CLKGATE_CON(14), 4, GFLAGS), |
533 | |
534 | DIV(PCLK_COREDBG_B, "pclken_dbg_core_b" , "pclk_dbg_core_b" , CLK_IGNORE_UNUSED, |
535 | RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), |
536 | |
537 | GATE(0, "pclk_dbg_cxcs_pd_core_b" , "pclk_dbg_core_b" , CLK_IGNORE_UNUSED, |
538 | RK3399_CLKGATE_CON(14), 2, GFLAGS), |
539 | |
540 | GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b" , "xin24m" , 0, |
541 | RK3399_CLKGATE_CON(1), 7, GFLAGS), |
542 | |
543 | /* gmac */ |
544 | GATE(0, "cpll_aclk_gmac_src" , "cpll" , CLK_IGNORE_UNUSED, |
545 | RK3399_CLKGATE_CON(6), 9, GFLAGS), |
546 | GATE(0, "gpll_aclk_gmac_src" , "gpll" , CLK_IGNORE_UNUSED, |
547 | RK3399_CLKGATE_CON(6), 8, GFLAGS), |
548 | COMPOSITE(0, "aclk_gmac_pre" , mux_aclk_gmac_p, 0, |
549 | RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, |
550 | RK3399_CLKGATE_CON(6), 10, GFLAGS), |
551 | |
552 | GATE(ACLK_GMAC, "aclk_gmac" , "aclk_gmac_pre" , 0, |
553 | RK3399_CLKGATE_CON(32), 0, GFLAGS), |
554 | GATE(ACLK_GMAC_NOC, "aclk_gmac_noc" , "aclk_gmac_pre" , CLK_IGNORE_UNUSED, |
555 | RK3399_CLKGATE_CON(32), 1, GFLAGS), |
556 | GATE(ACLK_PERF_GMAC, "aclk_perf_gmac" , "aclk_gmac_pre" , 0, |
557 | RK3399_CLKGATE_CON(32), 4, GFLAGS), |
558 | |
559 | COMPOSITE_NOMUX(0, "pclk_gmac_pre" , "aclk_gmac_pre" , 0, |
560 | RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, |
561 | RK3399_CLKGATE_CON(6), 11, GFLAGS), |
562 | GATE(PCLK_GMAC, "pclk_gmac" , "pclk_gmac_pre" , 0, |
563 | RK3399_CLKGATE_CON(32), 2, GFLAGS), |
564 | GATE(PCLK_GMAC_NOC, "pclk_gmac_noc" , "pclk_gmac_pre" , CLK_IGNORE_UNUSED, |
565 | RK3399_CLKGATE_CON(32), 3, GFLAGS), |
566 | |
567 | COMPOSITE(SCLK_MAC, "clk_gmac" , mux_pll_src_cpll_gpll_npll_p, 0, |
568 | RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, |
569 | RK3399_CLKGATE_CON(5), 5, GFLAGS), |
570 | |
571 | MUX(SCLK_RMII_SRC, "clk_rmii_src" , mux_rmii_p, CLK_SET_RATE_PARENT, |
572 | RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), |
573 | GATE(SCLK_MACREF_OUT, "clk_mac_refout" , "clk_rmii_src" , 0, |
574 | RK3399_CLKGATE_CON(5), 6, GFLAGS), |
575 | GATE(SCLK_MACREF, "clk_mac_ref" , "clk_rmii_src" , 0, |
576 | RK3399_CLKGATE_CON(5), 7, GFLAGS), |
577 | GATE(SCLK_MAC_RX, "clk_rmii_rx" , "clk_rmii_src" , 0, |
578 | RK3399_CLKGATE_CON(5), 8, GFLAGS), |
579 | GATE(SCLK_MAC_TX, "clk_rmii_tx" , "clk_rmii_src" , 0, |
580 | RK3399_CLKGATE_CON(5), 9, GFLAGS), |
581 | |
582 | /* spdif */ |
583 | COMPOSITE(0, "clk_spdif_div" , mux_pll_src_cpll_gpll_p, 0, |
584 | RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, |
585 | RK3399_CLKGATE_CON(8), 13, GFLAGS), |
586 | COMPOSITE_FRACMUX(0, "clk_spdif_frac" , "clk_spdif_div" , 0, |
587 | RK3399_CLKSEL_CON(99), 0, |
588 | RK3399_CLKGATE_CON(8), 14, GFLAGS, |
589 | &rk3399_spdif_fracmux), |
590 | GATE(SCLK_SPDIF_8CH, "clk_spdif" , "clk_spdif_mux" , CLK_SET_RATE_PARENT, |
591 | RK3399_CLKGATE_CON(8), 15, GFLAGS), |
592 | |
593 | COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx" , mux_pll_src_cpll_gpll_p, 0, |
594 | RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, |
595 | RK3399_CLKGATE_CON(10), 6, GFLAGS), |
596 | /* i2s */ |
597 | COMPOSITE(0, "clk_i2s0_div" , mux_pll_src_cpll_gpll_p, 0, |
598 | RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, |
599 | RK3399_CLKGATE_CON(8), 3, GFLAGS), |
600 | COMPOSITE_FRACMUX(0, "clk_i2s0_frac" , "clk_i2s0_div" , 0, |
601 | RK3399_CLKSEL_CON(96), 0, |
602 | RK3399_CLKGATE_CON(8), 4, GFLAGS, |
603 | &rk3399_i2s0_fracmux), |
604 | GATE(SCLK_I2S0_8CH, "clk_i2s0" , "clk_i2s0_mux" , CLK_SET_RATE_PARENT, |
605 | RK3399_CLKGATE_CON(8), 5, GFLAGS), |
606 | |
607 | COMPOSITE(0, "clk_i2s1_div" , mux_pll_src_cpll_gpll_p, 0, |
608 | RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, |
609 | RK3399_CLKGATE_CON(8), 6, GFLAGS), |
610 | COMPOSITE_FRACMUX(0, "clk_i2s1_frac" , "clk_i2s1_div" , 0, |
611 | RK3399_CLKSEL_CON(97), 0, |
612 | RK3399_CLKGATE_CON(8), 7, GFLAGS, |
613 | &rk3399_i2s1_fracmux), |
614 | GATE(SCLK_I2S1_8CH, "clk_i2s1" , "clk_i2s1_mux" , CLK_SET_RATE_PARENT, |
615 | RK3399_CLKGATE_CON(8), 8, GFLAGS), |
616 | |
617 | COMPOSITE(0, "clk_i2s2_div" , mux_pll_src_cpll_gpll_p, 0, |
618 | RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, |
619 | RK3399_CLKGATE_CON(8), 9, GFLAGS), |
620 | COMPOSITE_FRACMUX(0, "clk_i2s2_frac" , "clk_i2s2_div" , 0, |
621 | RK3399_CLKSEL_CON(98), 0, |
622 | RK3399_CLKGATE_CON(8), 10, GFLAGS, |
623 | &rk3399_i2s2_fracmux), |
624 | GATE(SCLK_I2S2_8CH, "clk_i2s2" , "clk_i2s2_mux" , CLK_SET_RATE_PARENT, |
625 | RK3399_CLKGATE_CON(8), 11, GFLAGS), |
626 | |
627 | MUX(0, "clk_i2sout_src" , mux_i2sch_p, CLK_SET_RATE_PARENT, |
628 | RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), |
629 | COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout" , mux_i2sout_p, CLK_SET_RATE_PARENT, |
630 | RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, |
631 | RK3399_CLKGATE_CON(8), 12, GFLAGS), |
632 | |
633 | /* uart */ |
634 | MUX(0, "clk_uart0_src" , mux_pll_src_cpll_gpll_upll_p, 0, |
635 | RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), |
636 | COMPOSITE_NOMUX(0, "clk_uart0_div" , "clk_uart0_src" , 0, |
637 | RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, |
638 | RK3399_CLKGATE_CON(9), 0, GFLAGS), |
639 | COMPOSITE_FRACMUX(0, "clk_uart0_frac" , "clk_uart0_div" , 0, |
640 | RK3399_CLKSEL_CON(100), 0, |
641 | RK3399_CLKGATE_CON(9), 1, GFLAGS, |
642 | &rk3399_uart0_fracmux), |
643 | |
644 | MUX(0, "clk_uart_src" , mux_pll_src_cpll_gpll_p, 0, |
645 | RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), |
646 | COMPOSITE_NOMUX(0, "clk_uart1_div" , "clk_uart_src" , 0, |
647 | RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, |
648 | RK3399_CLKGATE_CON(9), 2, GFLAGS), |
649 | COMPOSITE_FRACMUX(0, "clk_uart1_frac" , "clk_uart1_div" , 0, |
650 | RK3399_CLKSEL_CON(101), 0, |
651 | RK3399_CLKGATE_CON(9), 3, GFLAGS, |
652 | &rk3399_uart1_fracmux), |
653 | |
654 | COMPOSITE_NOMUX(0, "clk_uart2_div" , "clk_uart_src" , 0, |
655 | RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, |
656 | RK3399_CLKGATE_CON(9), 4, GFLAGS), |
657 | COMPOSITE_FRACMUX(0, "clk_uart2_frac" , "clk_uart2_div" , 0, |
658 | RK3399_CLKSEL_CON(102), 0, |
659 | RK3399_CLKGATE_CON(9), 5, GFLAGS, |
660 | &rk3399_uart2_fracmux), |
661 | |
662 | COMPOSITE_NOMUX(0, "clk_uart3_div" , "clk_uart_src" , 0, |
663 | RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, |
664 | RK3399_CLKGATE_CON(9), 6, GFLAGS), |
665 | COMPOSITE_FRACMUX(0, "clk_uart3_frac" , "clk_uart3_div" , 0, |
666 | RK3399_CLKSEL_CON(103), 0, |
667 | RK3399_CLKGATE_CON(9), 7, GFLAGS, |
668 | &rk3399_uart3_fracmux), |
669 | |
670 | COMPOSITE(PCLK_DDR, "pclk_ddr" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
671 | RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, |
672 | RK3399_CLKGATE_CON(3), 4, GFLAGS), |
673 | |
674 | GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc" , "pclk_ddr" , CLK_IGNORE_UNUSED, |
675 | RK3399_CLKGATE_CON(18), 10, GFLAGS), |
676 | GATE(PCLK_DDR_MON, "pclk_ddr_mon" , "pclk_ddr" , 0, |
677 | RK3399_CLKGATE_CON(18), 12, GFLAGS), |
678 | GATE(PCLK_CIC, "pclk_cic" , "pclk_ddr" , CLK_IGNORE_UNUSED, |
679 | RK3399_CLKGATE_CON(18), 15, GFLAGS), |
680 | GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf" , "pclk_ddr" , CLK_IGNORE_UNUSED, |
681 | RK3399_CLKGATE_CON(19), 2, GFLAGS), |
682 | |
683 | GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr" , "xin24m" , 0, |
684 | RK3399_CLKGATE_CON(4), 11, GFLAGS), |
685 | GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer" , "xin24m" , 0, |
686 | RK3399_CLKGATE_CON(3), 5, GFLAGS), |
687 | GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer" , "xin24m" , 0, |
688 | RK3399_CLKGATE_CON(3), 6, GFLAGS), |
689 | |
690 | /* cci */ |
691 | GATE(0, "cpll_aclk_cci_src" , "cpll" , CLK_IGNORE_UNUSED, |
692 | RK3399_CLKGATE_CON(2), 0, GFLAGS), |
693 | GATE(0, "gpll_aclk_cci_src" , "gpll" , CLK_IGNORE_UNUSED, |
694 | RK3399_CLKGATE_CON(2), 1, GFLAGS), |
695 | GATE(0, "npll_aclk_cci_src" , "npll" , CLK_IGNORE_UNUSED, |
696 | RK3399_CLKGATE_CON(2), 2, GFLAGS), |
697 | GATE(0, "vpll_aclk_cci_src" , "vpll" , CLK_IGNORE_UNUSED, |
698 | RK3399_CLKGATE_CON(2), 3, GFLAGS), |
699 | |
700 | COMPOSITE(0, "aclk_cci_pre" , mux_aclk_cci_p, CLK_IGNORE_UNUSED, |
701 | RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, |
702 | RK3399_CLKGATE_CON(2), 4, GFLAGS), |
703 | |
704 | GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
705 | RK3399_CLKGATE_CON(15), 0, GFLAGS), |
706 | GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
707 | RK3399_CLKGATE_CON(15), 1, GFLAGS), |
708 | GATE(ACLK_CCI, "aclk_cci" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
709 | RK3399_CLKGATE_CON(15), 2, GFLAGS), |
710 | GATE(ACLK_CCI_NOC0, "aclk_cci_noc0" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
711 | RK3399_CLKGATE_CON(15), 3, GFLAGS), |
712 | GATE(ACLK_CCI_NOC1, "aclk_cci_noc1" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
713 | RK3399_CLKGATE_CON(15), 4, GFLAGS), |
714 | GATE(ACLK_CCI_GRF, "aclk_cci_grf" , "aclk_cci_pre" , CLK_IGNORE_UNUSED, |
715 | RK3399_CLKGATE_CON(15), 7, GFLAGS), |
716 | |
717 | GATE(0, "cpll_cci_trace" , "cpll" , CLK_IGNORE_UNUSED, |
718 | RK3399_CLKGATE_CON(2), 5, GFLAGS), |
719 | GATE(0, "gpll_cci_trace" , "gpll" , CLK_IGNORE_UNUSED, |
720 | RK3399_CLKGATE_CON(2), 6, GFLAGS), |
721 | COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace" , mux_cci_trace_p, CLK_IGNORE_UNUSED, |
722 | RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, |
723 | RK3399_CLKGATE_CON(2), 7, GFLAGS), |
724 | |
725 | GATE(0, "cpll_cs" , "cpll" , CLK_IGNORE_UNUSED, |
726 | RK3399_CLKGATE_CON(2), 8, GFLAGS), |
727 | GATE(0, "gpll_cs" , "gpll" , CLK_IGNORE_UNUSED, |
728 | RK3399_CLKGATE_CON(2), 9, GFLAGS), |
729 | GATE(0, "npll_cs" , "npll" , CLK_IGNORE_UNUSED, |
730 | RK3399_CLKGATE_CON(2), 10, GFLAGS), |
731 | COMPOSITE_NOGATE(0, "clk_cs" , mux_cs_p, CLK_IGNORE_UNUSED, |
732 | RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), |
733 | GATE(0, "clk_dbg_cxcs" , "clk_cs" , CLK_IGNORE_UNUSED, |
734 | RK3399_CLKGATE_CON(15), 5, GFLAGS), |
735 | GATE(0, "clk_dbg_noc" , "clk_cs" , CLK_IGNORE_UNUSED, |
736 | RK3399_CLKGATE_CON(15), 6, GFLAGS), |
737 | |
738 | /* vcodec */ |
739 | COMPOSITE(0, "aclk_vcodec_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
740 | RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, |
741 | RK3399_CLKGATE_CON(4), 0, GFLAGS), |
742 | COMPOSITE_NOMUX(0, "hclk_vcodec_pre" , "aclk_vcodec_pre" , 0, |
743 | RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, |
744 | RK3399_CLKGATE_CON(4), 1, GFLAGS), |
745 | GATE(HCLK_VCODEC, "hclk_vcodec" , "hclk_vcodec_pre" , 0, |
746 | RK3399_CLKGATE_CON(17), 2, GFLAGS), |
747 | GATE(0, "hclk_vcodec_noc" , "hclk_vcodec_pre" , CLK_IGNORE_UNUSED, |
748 | RK3399_CLKGATE_CON(17), 3, GFLAGS), |
749 | |
750 | GATE(ACLK_VCODEC, "aclk_vcodec" , "aclk_vcodec_pre" , 0, |
751 | RK3399_CLKGATE_CON(17), 0, GFLAGS), |
752 | GATE(0, "aclk_vcodec_noc" , "aclk_vcodec_pre" , CLK_IGNORE_UNUSED, |
753 | RK3399_CLKGATE_CON(17), 1, GFLAGS), |
754 | |
755 | /* vdu */ |
756 | COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core" , mux_pll_src_cpll_gpll_npll_p, 0, |
757 | RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, |
758 | RK3399_CLKGATE_CON(4), 4, GFLAGS), |
759 | COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca" , mux_pll_src_cpll_gpll_npll_p, 0, |
760 | RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, |
761 | RK3399_CLKGATE_CON(4), 5, GFLAGS), |
762 | |
763 | COMPOSITE(0, "aclk_vdu_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
764 | RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, |
765 | RK3399_CLKGATE_CON(4), 2, GFLAGS), |
766 | COMPOSITE_NOMUX(0, "hclk_vdu_pre" , "aclk_vdu_pre" , 0, |
767 | RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, |
768 | RK3399_CLKGATE_CON(4), 3, GFLAGS), |
769 | GATE(HCLK_VDU, "hclk_vdu" , "hclk_vdu_pre" , 0, |
770 | RK3399_CLKGATE_CON(17), 10, GFLAGS), |
771 | GATE(HCLK_VDU_NOC, "hclk_vdu_noc" , "hclk_vdu_pre" , CLK_IGNORE_UNUSED, |
772 | RK3399_CLKGATE_CON(17), 11, GFLAGS), |
773 | |
774 | GATE(ACLK_VDU, "aclk_vdu" , "aclk_vdu_pre" , 0, |
775 | RK3399_CLKGATE_CON(17), 8, GFLAGS), |
776 | GATE(ACLK_VDU_NOC, "aclk_vdu_noc" , "aclk_vdu_pre" , CLK_IGNORE_UNUSED, |
777 | RK3399_CLKGATE_CON(17), 9, GFLAGS), |
778 | |
779 | /* iep */ |
780 | COMPOSITE(0, "aclk_iep_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
781 | RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, |
782 | RK3399_CLKGATE_CON(4), 6, GFLAGS), |
783 | COMPOSITE_NOMUX(0, "hclk_iep_pre" , "aclk_iep_pre" , 0, |
784 | RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, |
785 | RK3399_CLKGATE_CON(4), 7, GFLAGS), |
786 | GATE(HCLK_IEP, "hclk_iep" , "hclk_iep_pre" , 0, |
787 | RK3399_CLKGATE_CON(16), 2, GFLAGS), |
788 | GATE(HCLK_IEP_NOC, "hclk_iep_noc" , "hclk_iep_pre" , CLK_IGNORE_UNUSED, |
789 | RK3399_CLKGATE_CON(16), 3, GFLAGS), |
790 | |
791 | GATE(ACLK_IEP, "aclk_iep" , "aclk_iep_pre" , 0, |
792 | RK3399_CLKGATE_CON(16), 0, GFLAGS), |
793 | GATE(ACLK_IEP_NOC, "aclk_iep_noc" , "aclk_iep_pre" , CLK_IGNORE_UNUSED, |
794 | RK3399_CLKGATE_CON(16), 1, GFLAGS), |
795 | |
796 | /* rga */ |
797 | COMPOSITE(SCLK_RGA_CORE, "clk_rga_core" , mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
798 | RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, |
799 | RK3399_CLKGATE_CON(4), 10, GFLAGS), |
800 | |
801 | COMPOSITE(0, "aclk_rga_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
802 | RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, |
803 | RK3399_CLKGATE_CON(4), 8, GFLAGS), |
804 | COMPOSITE_NOMUX(0, "hclk_rga_pre" , "aclk_rga_pre" , 0, |
805 | RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, |
806 | RK3399_CLKGATE_CON(4), 9, GFLAGS), |
807 | GATE(HCLK_RGA, "hclk_rga" , "hclk_rga_pre" , 0, |
808 | RK3399_CLKGATE_CON(16), 10, GFLAGS), |
809 | GATE(HCLK_RGA_NOC, "hclk_rga_noc" , "hclk_rga_pre" , CLK_IGNORE_UNUSED, |
810 | RK3399_CLKGATE_CON(16), 11, GFLAGS), |
811 | |
812 | GATE(ACLK_RGA, "aclk_rga" , "aclk_rga_pre" , 0, |
813 | RK3399_CLKGATE_CON(16), 8, GFLAGS), |
814 | GATE(ACLK_RGA_NOC, "aclk_rga_noc" , "aclk_rga_pre" , CLK_IGNORE_UNUSED, |
815 | RK3399_CLKGATE_CON(16), 9, GFLAGS), |
816 | |
817 | /* center */ |
818 | COMPOSITE(0, "aclk_center" , mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, |
819 | RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, |
820 | RK3399_CLKGATE_CON(3), 7, GFLAGS), |
821 | GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc" , "aclk_center" , CLK_IGNORE_UNUSED, |
822 | RK3399_CLKGATE_CON(19), 0, GFLAGS), |
823 | GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc" , "aclk_center" , CLK_IGNORE_UNUSED, |
824 | RK3399_CLKGATE_CON(19), 1, GFLAGS), |
825 | |
826 | /* gpu */ |
827 | COMPOSITE(0, "aclk_gpu_pre" , mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, |
828 | RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, |
829 | RK3399_CLKGATE_CON(13), 0, GFLAGS), |
830 | GATE(ACLK_GPU, "aclk_gpu" , "aclk_gpu_pre" , 0, |
831 | RK3399_CLKGATE_CON(30), 8, GFLAGS), |
832 | GATE(ACLK_PERF_GPU, "aclk_perf_gpu" , "aclk_gpu_pre" , 0, |
833 | RK3399_CLKGATE_CON(30), 10, GFLAGS), |
834 | GATE(ACLK_GPU_GRF, "aclk_gpu_grf" , "aclk_gpu_pre" , 0, |
835 | RK3399_CLKGATE_CON(30), 11, GFLAGS), |
836 | GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu" , "xin24m" , 0, |
837 | RK3399_CLKGATE_CON(13), 1, GFLAGS), |
838 | |
839 | /* perihp */ |
840 | GATE(0, "cpll_aclk_perihp_src" , "cpll" , CLK_IGNORE_UNUSED, |
841 | RK3399_CLKGATE_CON(5), 1, GFLAGS), |
842 | GATE(0, "gpll_aclk_perihp_src" , "gpll" , CLK_IGNORE_UNUSED, |
843 | RK3399_CLKGATE_CON(5), 0, GFLAGS), |
844 | COMPOSITE(ACLK_PERIHP, "aclk_perihp" , mux_aclk_perihp_p, CLK_IGNORE_UNUSED, |
845 | RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, |
846 | RK3399_CLKGATE_CON(5), 2, GFLAGS), |
847 | COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp" , "aclk_perihp" , CLK_IGNORE_UNUSED, |
848 | RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, |
849 | RK3399_CLKGATE_CON(5), 3, GFLAGS), |
850 | COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp" , "aclk_perihp" , CLK_IGNORE_UNUSED, |
851 | RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, |
852 | RK3399_CLKGATE_CON(5), 4, GFLAGS), |
853 | |
854 | GATE(ACLK_PERF_PCIE, "aclk_perf_pcie" , "aclk_perihp" , 0, |
855 | RK3399_CLKGATE_CON(20), 2, GFLAGS), |
856 | GATE(ACLK_PCIE, "aclk_pcie" , "aclk_perihp" , 0, |
857 | RK3399_CLKGATE_CON(20), 10, GFLAGS), |
858 | GATE(0, "aclk_perihp_noc" , "aclk_perihp" , CLK_IGNORE_UNUSED, |
859 | RK3399_CLKGATE_CON(20), 12, GFLAGS), |
860 | |
861 | GATE(HCLK_HOST0, "hclk_host0" , "hclk_perihp" , 0, |
862 | RK3399_CLKGATE_CON(20), 5, GFLAGS), |
863 | GATE(HCLK_HOST0_ARB, "hclk_host0_arb" , "hclk_perihp" , 0, |
864 | RK3399_CLKGATE_CON(20), 6, GFLAGS), |
865 | GATE(HCLK_HOST1, "hclk_host1" , "hclk_perihp" , 0, |
866 | RK3399_CLKGATE_CON(20), 7, GFLAGS), |
867 | GATE(HCLK_HOST1_ARB, "hclk_host1_arb" , "hclk_perihp" , 0, |
868 | RK3399_CLKGATE_CON(20), 8, GFLAGS), |
869 | GATE(HCLK_HSIC, "hclk_hsic" , "hclk_perihp" , 0, |
870 | RK3399_CLKGATE_CON(20), 9, GFLAGS), |
871 | GATE(0, "hclk_perihp_noc" , "hclk_perihp" , CLK_IGNORE_UNUSED, |
872 | RK3399_CLKGATE_CON(20), 13, GFLAGS), |
873 | GATE(0, "hclk_ahb1tom" , "hclk_perihp" , CLK_IGNORE_UNUSED, |
874 | RK3399_CLKGATE_CON(20), 15, GFLAGS), |
875 | |
876 | GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf" , "pclk_perihp" , CLK_IGNORE_UNUSED, |
877 | RK3399_CLKGATE_CON(20), 4, GFLAGS), |
878 | GATE(PCLK_PCIE, "pclk_pcie" , "pclk_perihp" , 0, |
879 | RK3399_CLKGATE_CON(20), 11, GFLAGS), |
880 | GATE(0, "pclk_perihp_noc" , "pclk_perihp" , CLK_IGNORE_UNUSED, |
881 | RK3399_CLKGATE_CON(20), 14, GFLAGS), |
882 | GATE(PCLK_HSICPHY, "pclk_hsicphy" , "pclk_perihp" , 0, |
883 | RK3399_CLKGATE_CON(31), 8, GFLAGS), |
884 | |
885 | /* sdio & sdmmc */ |
886 | COMPOSITE(HCLK_SD, "hclk_sd" , mux_pll_src_cpll_gpll_p, 0, |
887 | RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, |
888 | RK3399_CLKGATE_CON(12), 13, GFLAGS), |
889 | GATE(HCLK_SDMMC, "hclk_sdmmc" , "hclk_sd" , 0, |
890 | RK3399_CLKGATE_CON(33), 8, GFLAGS), |
891 | GATE(0, "hclk_sdmmc_noc" , "hclk_sd" , CLK_IGNORE_UNUSED, |
892 | RK3399_CLKGATE_CON(33), 9, GFLAGS), |
893 | |
894 | COMPOSITE(SCLK_SDIO, "clk_sdio" , mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, |
895 | RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, |
896 | RK3399_CLKGATE_CON(6), 0, GFLAGS), |
897 | |
898 | COMPOSITE(SCLK_SDMMC, "clk_sdmmc" , mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, |
899 | RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, |
900 | RK3399_CLKGATE_CON(6), 1, GFLAGS), |
901 | |
902 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv" , "clk_sdmmc" , RK3399_SDMMC_CON0, 1), |
903 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample" , "clk_sdmmc" , RK3399_SDMMC_CON1, 1), |
904 | |
905 | MMC(SCLK_SDIO_DRV, "sdio_drv" , "clk_sdio" , RK3399_SDIO_CON0, 1), |
906 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample" , "clk_sdio" , RK3399_SDIO_CON1, 1), |
907 | |
908 | /* pcie */ |
909 | COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm" , mux_pll_src_cpll_gpll_npll_24m_p, 0, |
910 | RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, |
911 | RK3399_CLKGATE_CON(6), 2, GFLAGS), |
912 | |
913 | COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m" , "npll" , 0, |
914 | RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, |
915 | RK3399_CLKGATE_CON(12), 6, GFLAGS), |
916 | MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref" , mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, |
917 | RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), |
918 | |
919 | COMPOSITE(0, "clk_pcie_core_cru" , mux_pll_src_cpll_gpll_npll_p, 0, |
920 | RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, |
921 | RK3399_CLKGATE_CON(6), 3, GFLAGS), |
922 | MUX(SCLK_PCIE_CORE, "clk_pcie_core" , mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, |
923 | RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), |
924 | |
925 | /* emmc */ |
926 | COMPOSITE(SCLK_EMMC, "clk_emmc" , mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, |
927 | RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, |
928 | RK3399_CLKGATE_CON(6), 14, GFLAGS), |
929 | |
930 | GATE(0, "cpll_aclk_emmc_src" , "cpll" , CLK_IGNORE_UNUSED, |
931 | RK3399_CLKGATE_CON(6), 13, GFLAGS), |
932 | GATE(0, "gpll_aclk_emmc_src" , "gpll" , CLK_IGNORE_UNUSED, |
933 | RK3399_CLKGATE_CON(6), 12, GFLAGS), |
934 | COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc" , mux_aclk_emmc_p, CLK_IGNORE_UNUSED, |
935 | RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), |
936 | GATE(ACLK_EMMC_CORE, "aclk_emmccore" , "aclk_emmc" , CLK_IGNORE_UNUSED, |
937 | RK3399_CLKGATE_CON(32), 8, GFLAGS), |
938 | GATE(ACLK_EMMC_NOC, "aclk_emmc_noc" , "aclk_emmc" , CLK_IGNORE_UNUSED, |
939 | RK3399_CLKGATE_CON(32), 9, GFLAGS), |
940 | GATE(ACLK_EMMC_GRF, "aclk_emmcgrf" , "aclk_emmc" , CLK_IGNORE_UNUSED, |
941 | RK3399_CLKGATE_CON(32), 10, GFLAGS), |
942 | |
943 | /* perilp0 */ |
944 | GATE(0, "cpll_aclk_perilp0_src" , "cpll" , CLK_IGNORE_UNUSED, |
945 | RK3399_CLKGATE_CON(7), 1, GFLAGS), |
946 | GATE(0, "gpll_aclk_perilp0_src" , "gpll" , CLK_IGNORE_UNUSED, |
947 | RK3399_CLKGATE_CON(7), 0, GFLAGS), |
948 | COMPOSITE(ACLK_PERILP0, "aclk_perilp0" , mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, |
949 | RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, |
950 | RK3399_CLKGATE_CON(7), 2, GFLAGS), |
951 | COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0" , "aclk_perilp0" , CLK_IGNORE_UNUSED, |
952 | RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, |
953 | RK3399_CLKGATE_CON(7), 3, GFLAGS), |
954 | COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0" , "aclk_perilp0" , 0, |
955 | RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, |
956 | RK3399_CLKGATE_CON(7), 4, GFLAGS), |
957 | |
958 | /* aclk_perilp0 gates */ |
959 | GATE(ACLK_INTMEM, "aclk_intmem" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), |
960 | GATE(ACLK_TZMA, "aclk_tzma" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), |
961 | GATE(SCLK_INTMEM0, "clk_intmem0" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), |
962 | GATE(SCLK_INTMEM1, "clk_intmem1" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), |
963 | GATE(SCLK_INTMEM2, "clk_intmem2" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), |
964 | GATE(SCLK_INTMEM3, "clk_intmem3" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), |
965 | GATE(SCLK_INTMEM4, "clk_intmem4" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), |
966 | GATE(SCLK_INTMEM5, "clk_intmem5" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), |
967 | GATE(ACLK_DCF, "aclk_dcf" , "aclk_perilp0" , 0, RK3399_CLKGATE_CON(23), 8, GFLAGS), |
968 | GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp" , "aclk_perilp0" , 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), |
969 | GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp" , "aclk_perilp0" , 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), |
970 | GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), |
971 | |
972 | /* hclk_perilp0 gates */ |
973 | GATE(HCLK_ROM, "hclk_rom" , "hclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), |
974 | GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0" , "hclk_perilp0" , 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), |
975 | GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0" , "hclk_perilp0" , 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), |
976 | GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1" , "hclk_perilp0" , 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), |
977 | GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1" , "hclk_perilp0" , 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), |
978 | GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc" , "hclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), |
979 | |
980 | /* pclk_perilp0 gates */ |
981 | GATE(PCLK_DCF, "pclk_dcf" , "pclk_perilp0" , 0, RK3399_CLKGATE_CON(23), 9, GFLAGS), |
982 | |
983 | /* crypto */ |
984 | COMPOSITE(SCLK_CRYPTO0, "clk_crypto0" , mux_pll_src_cpll_gpll_ppll_p, 0, |
985 | RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, |
986 | RK3399_CLKGATE_CON(7), 7, GFLAGS), |
987 | |
988 | COMPOSITE(SCLK_CRYPTO1, "clk_crypto1" , mux_pll_src_cpll_gpll_ppll_p, 0, |
989 | RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, |
990 | RK3399_CLKGATE_CON(7), 8, GFLAGS), |
991 | |
992 | /* cm0s_perilp */ |
993 | GATE(0, "cpll_fclk_cm0s_src" , "cpll" , 0, |
994 | RK3399_CLKGATE_CON(7), 6, GFLAGS), |
995 | GATE(0, "gpll_fclk_cm0s_src" , "gpll" , 0, |
996 | RK3399_CLKGATE_CON(7), 5, GFLAGS), |
997 | COMPOSITE(FCLK_CM0S, "fclk_cm0s" , mux_fclk_cm0s_p, 0, |
998 | RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, |
999 | RK3399_CLKGATE_CON(7), 9, GFLAGS), |
1000 | |
1001 | /* fclk_cm0s gates */ |
1002 | GATE(SCLK_M0_PERILP, "sclk_m0_perilp" , "fclk_cm0s" , 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), |
1003 | GATE(HCLK_M0_PERILP, "hclk_m0_perilp" , "fclk_cm0s" , 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), |
1004 | GATE(DCLK_M0_PERILP, "dclk_m0_perilp" , "fclk_cm0s" , 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), |
1005 | GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec" , "fclk_cm0s" , 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), |
1006 | GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc" , "fclk_cm0s" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), |
1007 | |
1008 | /* perilp1 */ |
1009 | GATE(0, "cpll_hclk_perilp1_src" , "cpll" , CLK_IGNORE_UNUSED, |
1010 | RK3399_CLKGATE_CON(8), 1, GFLAGS), |
1011 | GATE(0, "gpll_hclk_perilp1_src" , "gpll" , CLK_IGNORE_UNUSED, |
1012 | RK3399_CLKGATE_CON(8), 0, GFLAGS), |
1013 | COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1" , mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, |
1014 | RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), |
1015 | COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1" , "hclk_perilp1" , CLK_IGNORE_UNUSED, |
1016 | RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, |
1017 | RK3399_CLKGATE_CON(8), 2, GFLAGS), |
1018 | |
1019 | /* hclk_perilp1 gates */ |
1020 | GATE(0, "hclk_perilp1_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), |
1021 | GATE(0, "hclk_sdio_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), |
1022 | GATE(HCLK_I2S0_8CH, "hclk_i2s0" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), |
1023 | GATE(HCLK_I2S1_8CH, "hclk_i2s1" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), |
1024 | GATE(HCLK_I2S2_8CH, "hclk_i2s2" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), |
1025 | GATE(HCLK_SPDIF, "hclk_spdif" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), |
1026 | GATE(HCLK_SDIO, "hclk_sdio" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), |
1027 | GATE(PCLK_SPI5, "pclk_spi5" , "hclk_perilp1" , 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), |
1028 | GATE(0, "hclk_sdioaudio_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), |
1029 | |
1030 | /* pclk_perilp1 gates */ |
1031 | GATE(PCLK_UART0, "pclk_uart0" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), |
1032 | GATE(PCLK_UART1, "pclk_uart1" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), |
1033 | GATE(PCLK_UART2, "pclk_uart2" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), |
1034 | GATE(PCLK_UART3, "pclk_uart3" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), |
1035 | GATE(PCLK_I2C7, "pclk_rki2c7" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), |
1036 | GATE(PCLK_I2C1, "pclk_rki2c1" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), |
1037 | GATE(PCLK_I2C5, "pclk_rki2c5" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), |
1038 | GATE(PCLK_I2C6, "pclk_rki2c6" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), |
1039 | GATE(PCLK_I2C2, "pclk_rki2c2" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), |
1040 | GATE(PCLK_I2C3, "pclk_rki2c3" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), |
1041 | GATE(PCLK_MAILBOX0, "pclk_mailbox0" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), |
1042 | GATE(PCLK_SARADC, "pclk_saradc" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), |
1043 | GATE(PCLK_TSADC, "pclk_tsadc" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), |
1044 | GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), |
1045 | GATE(PCLK_EFUSE1024S, "pclk_efuse1024s" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), |
1046 | GATE(PCLK_SPI0, "pclk_spi0" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), |
1047 | GATE(PCLK_SPI1, "pclk_spi1" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), |
1048 | GATE(PCLK_SPI2, "pclk_spi2" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), |
1049 | GATE(PCLK_SPI4, "pclk_spi4" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), |
1050 | GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), |
1051 | GATE(0, "pclk_perilp1_noc" , "pclk_perilp1" , 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), |
1052 | |
1053 | /* saradc */ |
1054 | COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc" , "xin24m" , 0, |
1055 | RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, |
1056 | RK3399_CLKGATE_CON(9), 11, GFLAGS), |
1057 | |
1058 | /* tsadc */ |
1059 | COMPOSITE(SCLK_TSADC, "clk_tsadc" , mux_pll_p, 0, |
1060 | RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, |
1061 | RK3399_CLKGATE_CON(9), 10, GFLAGS), |
1062 | |
1063 | /* cif_testout */ |
1064 | MUX(0, "clk_testout1_pll_src" , mux_pll_src_cpll_gpll_npll_p, 0, |
1065 | RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), |
1066 | COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1" , mux_clk_testout1_p, 0, |
1067 | RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, |
1068 | RK3399_CLKGATE_CON(13), 14, GFLAGS), |
1069 | |
1070 | MUX(0, "clk_testout2_pll_src" , mux_pll_src_cpll_gpll_npll_p, 0, |
1071 | RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), |
1072 | COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2" , mux_clk_testout2_p, 0, |
1073 | RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, |
1074 | RK3399_CLKGATE_CON(13), 15, GFLAGS), |
1075 | |
1076 | /* vio */ |
1077 | COMPOSITE(ACLK_VIO, "aclk_vio" , mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, |
1078 | RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1079 | RK3399_CLKGATE_CON(11), 0, GFLAGS), |
1080 | COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio" , "aclk_vio" , 0, |
1081 | RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, |
1082 | RK3399_CLKGATE_CON(11), 1, GFLAGS), |
1083 | |
1084 | GATE(ACLK_VIO_NOC, "aclk_vio_noc" , "aclk_vio" , CLK_IGNORE_UNUSED, |
1085 | RK3399_CLKGATE_CON(29), 0, GFLAGS), |
1086 | |
1087 | GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0" , "pclk_vio" , 0, |
1088 | RK3399_CLKGATE_CON(29), 1, GFLAGS), |
1089 | GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1" , "pclk_vio" , 0, |
1090 | RK3399_CLKGATE_CON(29), 2, GFLAGS), |
1091 | GATE(PCLK_VIO_GRF, "pclk_vio_grf" , "pclk_vio" , CLK_IGNORE_UNUSED, |
1092 | RK3399_CLKGATE_CON(29), 12, GFLAGS), |
1093 | |
1094 | /* hdcp */ |
1095 | COMPOSITE(ACLK_HDCP, "aclk_hdcp" , mux_pll_src_cpll_gpll_ppll_p, 0, |
1096 | RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, |
1097 | RK3399_CLKGATE_CON(11), 12, GFLAGS), |
1098 | COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp" , "aclk_hdcp" , 0, |
1099 | RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, |
1100 | RK3399_CLKGATE_CON(11), 3, GFLAGS), |
1101 | COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp" , "aclk_hdcp" , 0, |
1102 | RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, |
1103 | RK3399_CLKGATE_CON(11), 10, GFLAGS), |
1104 | |
1105 | GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc" , "aclk_hdcp" , CLK_IGNORE_UNUSED, |
1106 | RK3399_CLKGATE_CON(29), 4, GFLAGS), |
1107 | GATE(ACLK_HDCP22, "aclk_hdcp22" , "aclk_hdcp" , 0, |
1108 | RK3399_CLKGATE_CON(29), 10, GFLAGS), |
1109 | |
1110 | GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc" , "hclk_hdcp" , CLK_IGNORE_UNUSED, |
1111 | RK3399_CLKGATE_CON(29), 5, GFLAGS), |
1112 | GATE(HCLK_HDCP22, "hclk_hdcp22" , "hclk_hdcp" , 0, |
1113 | RK3399_CLKGATE_CON(29), 9, GFLAGS), |
1114 | |
1115 | GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc" , "pclk_hdcp" , CLK_IGNORE_UNUSED, |
1116 | RK3399_CLKGATE_CON(29), 3, GFLAGS), |
1117 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl" , "pclk_hdcp" , 0, |
1118 | RK3399_CLKGATE_CON(29), 6, GFLAGS), |
1119 | GATE(PCLK_DP_CTRL, "pclk_dp_ctrl" , "pclk_hdcp" , 0, |
1120 | RK3399_CLKGATE_CON(29), 7, GFLAGS), |
1121 | GATE(PCLK_HDCP22, "pclk_hdcp22" , "pclk_hdcp" , 0, |
1122 | RK3399_CLKGATE_CON(29), 8, GFLAGS), |
1123 | GATE(PCLK_GASKET, "pclk_gasket" , "pclk_hdcp" , 0, |
1124 | RK3399_CLKGATE_CON(29), 11, GFLAGS), |
1125 | |
1126 | /* edp */ |
1127 | COMPOSITE(SCLK_DP_CORE, "clk_dp_core" , mux_pll_src_npll_cpll_gpll_p, 0, |
1128 | RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1129 | RK3399_CLKGATE_CON(11), 8, GFLAGS), |
1130 | |
1131 | COMPOSITE(PCLK_EDP, "pclk_edp" , mux_pll_src_cpll_gpll_p, 0, |
1132 | RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS, |
1133 | RK3399_CLKGATE_CON(11), 11, GFLAGS), |
1134 | GATE(PCLK_EDP_NOC, "pclk_edp_noc" , "pclk_edp" , CLK_IGNORE_UNUSED, |
1135 | RK3399_CLKGATE_CON(32), 12, GFLAGS), |
1136 | GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl" , "pclk_edp" , 0, |
1137 | RK3399_CLKGATE_CON(32), 13, GFLAGS), |
1138 | |
1139 | /* hdmi */ |
1140 | GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr" , "xin24m" , 0, |
1141 | RK3399_CLKGATE_CON(11), 6, GFLAGS), |
1142 | |
1143 | COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec" , mux_pll_p, 0, |
1144 | RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, |
1145 | RK3399_CLKGATE_CON(11), 7, GFLAGS), |
1146 | |
1147 | /* vop0 */ |
1148 | COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre" , mux_pll_src_vpll_cpll_gpll_npll_p, 0, |
1149 | RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1150 | RK3399_CLKGATE_CON(10), 8, GFLAGS), |
1151 | COMPOSITE_NOMUX(0, "hclk_vop0_pre" , "aclk_vop0_pre" , 0, |
1152 | RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, |
1153 | RK3399_CLKGATE_CON(10), 9, GFLAGS), |
1154 | |
1155 | GATE(ACLK_VOP0, "aclk_vop0" , "aclk_vop0_pre" , 0, |
1156 | RK3399_CLKGATE_CON(28), 3, GFLAGS), |
1157 | GATE(ACLK_VOP0_NOC, "aclk_vop0_noc" , "aclk_vop0_pre" , CLK_IGNORE_UNUSED, |
1158 | RK3399_CLKGATE_CON(28), 1, GFLAGS), |
1159 | |
1160 | GATE(HCLK_VOP0, "hclk_vop0" , "hclk_vop0_pre" , 0, |
1161 | RK3399_CLKGATE_CON(28), 2, GFLAGS), |
1162 | GATE(HCLK_VOP0_NOC, "hclk_vop0_noc" , "hclk_vop0_pre" , CLK_IGNORE_UNUSED, |
1163 | RK3399_CLKGATE_CON(28), 0, GFLAGS), |
1164 | |
1165 | COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div" , mux_pll_src_vpll_cpll_gpll_p, 0, |
1166 | RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, |
1167 | RK3399_CLKGATE_CON(10), 12, GFLAGS), |
1168 | |
1169 | COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac" , "dclk_vop0_div" , 0, |
1170 | RK3399_CLKSEL_CON(106), 0, |
1171 | &rk3399_dclk_vop0_fracmux), |
1172 | |
1173 | COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm" , mux_pll_src_vpll_cpll_gpll_24m_p, 0, |
1174 | RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1175 | RK3399_CLKGATE_CON(10), 14, GFLAGS), |
1176 | |
1177 | /* vop1 */ |
1178 | COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre" , mux_pll_src_vpll_cpll_gpll_npll_p, 0, |
1179 | RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1180 | RK3399_CLKGATE_CON(10), 10, GFLAGS), |
1181 | COMPOSITE_NOMUX(0, "hclk_vop1_pre" , "aclk_vop1_pre" , 0, |
1182 | RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, |
1183 | RK3399_CLKGATE_CON(10), 11, GFLAGS), |
1184 | |
1185 | GATE(ACLK_VOP1, "aclk_vop1" , "aclk_vop1_pre" , 0, |
1186 | RK3399_CLKGATE_CON(28), 7, GFLAGS), |
1187 | GATE(ACLK_VOP1_NOC, "aclk_vop1_noc" , "aclk_vop1_pre" , CLK_IGNORE_UNUSED, |
1188 | RK3399_CLKGATE_CON(28), 5, GFLAGS), |
1189 | |
1190 | GATE(HCLK_VOP1, "hclk_vop1" , "hclk_vop1_pre" , 0, |
1191 | RK3399_CLKGATE_CON(28), 6, GFLAGS), |
1192 | GATE(HCLK_VOP1_NOC, "hclk_vop1_noc" , "hclk_vop1_pre" , CLK_IGNORE_UNUSED, |
1193 | RK3399_CLKGATE_CON(28), 4, GFLAGS), |
1194 | |
1195 | COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div" , mux_pll_src_vpll_cpll_gpll_p, 0, |
1196 | RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, |
1197 | RK3399_CLKGATE_CON(10), 13, GFLAGS), |
1198 | |
1199 | COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac" , "dclk_vop1_div" , 0, |
1200 | RK3399_CLKSEL_CON(107), 0, |
1201 | &rk3399_dclk_vop1_fracmux), |
1202 | |
1203 | COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm" , mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, |
1204 | RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1205 | RK3399_CLKGATE_CON(10), 15, GFLAGS), |
1206 | |
1207 | /* isp */ |
1208 | COMPOSITE(ACLK_ISP0, "aclk_isp0" , mux_pll_src_cpll_gpll_ppll_p, 0, |
1209 | RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1210 | RK3399_CLKGATE_CON(12), 8, GFLAGS), |
1211 | COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0" , "aclk_isp0" , 0, |
1212 | RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, |
1213 | RK3399_CLKGATE_CON(12), 9, GFLAGS), |
1214 | |
1215 | GATE(ACLK_ISP0_NOC, "aclk_isp0_noc" , "aclk_isp0" , CLK_IGNORE_UNUSED, |
1216 | RK3399_CLKGATE_CON(27), 1, GFLAGS), |
1217 | GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper" , "aclk_isp0" , 0, |
1218 | RK3399_CLKGATE_CON(27), 5, GFLAGS), |
1219 | GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper" , "aclk_isp0" , 0, |
1220 | RK3399_CLKGATE_CON(27), 7, GFLAGS), |
1221 | |
1222 | GATE(HCLK_ISP0_NOC, "hclk_isp0_noc" , "hclk_isp0" , CLK_IGNORE_UNUSED, |
1223 | RK3399_CLKGATE_CON(27), 0, GFLAGS), |
1224 | GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper" , "hclk_isp0" , 0, |
1225 | RK3399_CLKGATE_CON(27), 4, GFLAGS), |
1226 | |
1227 | COMPOSITE(SCLK_ISP0, "clk_isp0" , mux_pll_src_cpll_gpll_npll_p, 0, |
1228 | RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1229 | RK3399_CLKGATE_CON(11), 4, GFLAGS), |
1230 | |
1231 | COMPOSITE(ACLK_ISP1, "aclk_isp1" , mux_pll_src_cpll_gpll_ppll_p, 0, |
1232 | RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, |
1233 | RK3399_CLKGATE_CON(12), 10, GFLAGS), |
1234 | COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1" , "aclk_isp1" , 0, |
1235 | RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, |
1236 | RK3399_CLKGATE_CON(12), 11, GFLAGS), |
1237 | |
1238 | GATE(ACLK_ISP1_NOC, "aclk_isp1_noc" , "aclk_isp1" , CLK_IGNORE_UNUSED, |
1239 | RK3399_CLKGATE_CON(27), 3, GFLAGS), |
1240 | |
1241 | GATE(HCLK_ISP1_NOC, "hclk_isp1_noc" , "hclk_isp1" , CLK_IGNORE_UNUSED, |
1242 | RK3399_CLKGATE_CON(27), 2, GFLAGS), |
1243 | GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper" , "hclk_isp1" , 0, |
1244 | RK3399_CLKGATE_CON(27), 8, GFLAGS), |
1245 | |
1246 | COMPOSITE(SCLK_ISP1, "clk_isp1" , mux_pll_src_cpll_gpll_npll_p, 0, |
1247 | RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, |
1248 | RK3399_CLKGATE_CON(11), 5, GFLAGS), |
1249 | |
1250 | /* |
1251 | * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, |
1252 | * so we ignore the mux and make clocks nodes as following, |
1253 | * |
1254 | * pclkin_cifinv --|-------\ |
1255 | * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper |
1256 | * pclkin_cif --|-------/ |
1257 | */ |
1258 | GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper" , "pclkin_cif" , 0, |
1259 | RK3399_CLKGATE_CON(27), 6, GFLAGS), |
1260 | |
1261 | /* cif */ |
1262 | COMPOSITE_NODIV(0, "clk_cifout_src" , mux_pll_src_cpll_gpll_npll_p, 0, |
1263 | RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, |
1264 | RK3399_CLKGATE_CON(10), 7, GFLAGS), |
1265 | |
1266 | COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout" , mux_clk_cif_p, CLK_SET_RATE_PARENT, |
1267 | RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), |
1268 | |
1269 | /* gic */ |
1270 | COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
1271 | RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, |
1272 | RK3399_CLKGATE_CON(12), 12, GFLAGS), |
1273 | |
1274 | GATE(ACLK_GIC, "aclk_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), |
1275 | GATE(ACLK_GIC_NOC, "aclk_gic_noc" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), |
1276 | GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), |
1277 | GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), |
1278 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), |
1279 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), |
1280 | |
1281 | /* alive */ |
1282 | /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ |
1283 | DIV(PCLK_ALIVE, "pclk_alive" , "gpll" , 0, |
1284 | RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), |
1285 | |
1286 | GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), |
1287 | GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), |
1288 | GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), |
1289 | GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), |
1290 | GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), |
1291 | |
1292 | GATE(PCLK_GRF, "pclk_grf" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), |
1293 | GATE(PCLK_INTR_ARB, "pclk_intr_arb" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), |
1294 | GATE(PCLK_GPIO2, "pclk_gpio2" , "pclk_alive" , 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), |
1295 | GATE(PCLK_GPIO3, "pclk_gpio3" , "pclk_alive" , 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), |
1296 | GATE(PCLK_GPIO4, "pclk_gpio4" , "pclk_alive" , 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), |
1297 | GATE(PCLK_TIMER0, "pclk_timer0" , "pclk_alive" , 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), |
1298 | GATE(PCLK_TIMER1, "pclk_timer1" , "pclk_alive" , 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), |
1299 | GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), |
1300 | GATE(PCLK_SGRF, "pclk_sgrf" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), |
1301 | |
1302 | /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ |
1303 | SGRF_GATE(PCLK_WDT, "pclk_wdt" , "pclk_alive" ), |
1304 | |
1305 | GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref" , "xin24m" , 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), |
1306 | GATE(SCLK_DPHY_PLL, "clk_dphy_pll" , "clk_mipidphy_ref" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), |
1307 | |
1308 | GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg" , "xin24m" , 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), |
1309 | GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), |
1310 | GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), |
1311 | GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), |
1312 | |
1313 | /* testout */ |
1314 | MUX(0, "clk_test_pre" , mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, |
1315 | RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), |
1316 | COMPOSITE_FRAC(0, "clk_test_frac" , "clk_test_pre" , 0, |
1317 | RK3399_CLKSEL_CON(105), 0, |
1318 | RK3399_CLKGATE_CON(13), 9, GFLAGS), |
1319 | |
1320 | DIV(0, "clk_test_24m" , "xin24m" , 0, |
1321 | RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), |
1322 | |
1323 | /* spi */ |
1324 | COMPOSITE(SCLK_SPI0, "clk_spi0" , mux_pll_src_cpll_gpll_p, 0, |
1325 | RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1326 | RK3399_CLKGATE_CON(9), 12, GFLAGS), |
1327 | |
1328 | COMPOSITE(SCLK_SPI1, "clk_spi1" , mux_pll_src_cpll_gpll_p, 0, |
1329 | RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1330 | RK3399_CLKGATE_CON(9), 13, GFLAGS), |
1331 | |
1332 | COMPOSITE(SCLK_SPI2, "clk_spi2" , mux_pll_src_cpll_gpll_p, 0, |
1333 | RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1334 | RK3399_CLKGATE_CON(9), 14, GFLAGS), |
1335 | |
1336 | COMPOSITE(SCLK_SPI4, "clk_spi4" , mux_pll_src_cpll_gpll_p, 0, |
1337 | RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1338 | RK3399_CLKGATE_CON(9), 15, GFLAGS), |
1339 | |
1340 | COMPOSITE(SCLK_SPI5, "clk_spi5" , mux_pll_src_cpll_gpll_p, 0, |
1341 | RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1342 | RK3399_CLKGATE_CON(13), 13, GFLAGS), |
1343 | |
1344 | /* i2c */ |
1345 | COMPOSITE(SCLK_I2C1, "clk_i2c1" , mux_pll_src_cpll_gpll_p, 0, |
1346 | RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1347 | RK3399_CLKGATE_CON(10), 0, GFLAGS), |
1348 | |
1349 | COMPOSITE(SCLK_I2C2, "clk_i2c2" , mux_pll_src_cpll_gpll_p, 0, |
1350 | RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1351 | RK3399_CLKGATE_CON(10), 2, GFLAGS), |
1352 | |
1353 | COMPOSITE(SCLK_I2C3, "clk_i2c3" , mux_pll_src_cpll_gpll_p, 0, |
1354 | RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1355 | RK3399_CLKGATE_CON(10), 4, GFLAGS), |
1356 | |
1357 | COMPOSITE(SCLK_I2C5, "clk_i2c5" , mux_pll_src_cpll_gpll_p, 0, |
1358 | RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1359 | RK3399_CLKGATE_CON(10), 1, GFLAGS), |
1360 | |
1361 | COMPOSITE(SCLK_I2C6, "clk_i2c6" , mux_pll_src_cpll_gpll_p, 0, |
1362 | RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1363 | RK3399_CLKGATE_CON(10), 3, GFLAGS), |
1364 | |
1365 | COMPOSITE(SCLK_I2C7, "clk_i2c7" , mux_pll_src_cpll_gpll_p, 0, |
1366 | RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, |
1367 | RK3399_CLKGATE_CON(10), 5, GFLAGS), |
1368 | |
1369 | /* timer */ |
1370 | GATE(SCLK_TIMER00, "clk_timer00" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), |
1371 | GATE(SCLK_TIMER01, "clk_timer01" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), |
1372 | GATE(SCLK_TIMER02, "clk_timer02" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), |
1373 | GATE(SCLK_TIMER03, "clk_timer03" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), |
1374 | GATE(SCLK_TIMER04, "clk_timer04" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), |
1375 | GATE(SCLK_TIMER05, "clk_timer05" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), |
1376 | GATE(SCLK_TIMER06, "clk_timer06" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), |
1377 | GATE(SCLK_TIMER07, "clk_timer07" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), |
1378 | GATE(SCLK_TIMER08, "clk_timer08" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), |
1379 | GATE(SCLK_TIMER09, "clk_timer09" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), |
1380 | GATE(SCLK_TIMER10, "clk_timer10" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), |
1381 | GATE(SCLK_TIMER11, "clk_timer11" , "xin24m" , 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), |
1382 | |
1383 | /* clk_test */ |
1384 | /* clk_test_pre is controlled by CRU_MISC_CON[3] */ |
1385 | COMPOSITE_NOMUX(0, "clk_test" , "clk_test_pre" , CLK_IGNORE_UNUSED, |
1386 | RK3399_CLKSEL_CON(58), 0, 5, DFLAGS, |
1387 | RK3399_CLKGATE_CON(13), 11, GFLAGS), |
1388 | |
1389 | /* ddrc */ |
1390 | GATE(0, "clk_ddrc_lpll_src" , "lpll" , 0, RK3399_CLKGATE_CON(3), |
1391 | 0, GFLAGS), |
1392 | GATE(0, "clk_ddrc_bpll_src" , "bpll" , 0, RK3399_CLKGATE_CON(3), |
1393 | 1, GFLAGS), |
1394 | GATE(0, "clk_ddrc_dpll_src" , "dpll" , 0, RK3399_CLKGATE_CON(3), |
1395 | 2, GFLAGS), |
1396 | GATE(0, "clk_ddrc_gpll_src" , "gpll" , 0, RK3399_CLKGATE_CON(3), |
1397 | 3, GFLAGS), |
1398 | COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc" , mux_ddrclk_p, 0, |
1399 | RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), |
1400 | }; |
1401 | |
1402 | static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { |
1403 | /* |
1404 | * PMU CRU Clock-Architecture |
1405 | */ |
1406 | |
1407 | GATE(0, "fclk_cm0s_pmu_ppll_src" , "ppll" , 0, |
1408 | RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), |
1409 | |
1410 | COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu" , mux_fclk_cm0s_pmu_ppll_p, 0, |
1411 | RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), |
1412 | |
1413 | COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu" , mux_24m_ppll_p, 0, |
1414 | RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, |
1415 | RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), |
1416 | |
1417 | COMPOSITE(0, "clk_wifi_div" , mux_ppll_24m_p, CLK_IGNORE_UNUSED, |
1418 | RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, |
1419 | RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), |
1420 | |
1421 | COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac" , "clk_wifi_div" , 0, |
1422 | RK3399_PMU_CLKSEL_CON(7), 0, |
1423 | &rk3399_pmuclk_wifi_fracmux), |
1424 | |
1425 | MUX(0, "clk_timer_src_pmu" , mux_pll_p, CLK_IGNORE_UNUSED, |
1426 | RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), |
1427 | |
1428 | COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu" , "ppll" , 0, |
1429 | RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, |
1430 | RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), |
1431 | |
1432 | COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu" , "ppll" , 0, |
1433 | RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, |
1434 | RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), |
1435 | |
1436 | COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu" , "ppll" , 0, |
1437 | RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, |
1438 | RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), |
1439 | |
1440 | DIV(0, "clk_32k_suspend_pmu" , "xin24m" , CLK_IGNORE_UNUSED, |
1441 | RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), |
1442 | MUX(0, "clk_testout_2io" , mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, |
1443 | RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), |
1444 | |
1445 | COMPOSITE(0, "clk_uart4_div" , mux_24m_ppll_p, 0, |
1446 | RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, |
1447 | RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), |
1448 | |
1449 | COMPOSITE_FRACMUX(0, "clk_uart4_frac" , "clk_uart4_div" , 0, |
1450 | RK3399_PMU_CLKSEL_CON(6), 0, |
1451 | RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, |
1452 | &rk3399_uart4_pmu_fracmux), |
1453 | |
1454 | DIV(PCLK_SRC_PMU, "pclk_pmu_src" , "ppll" , CLK_IGNORE_UNUSED, |
1455 | RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), |
1456 | |
1457 | /* pmu clock gates */ |
1458 | GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu" , "clk_timer_src_pmu" , 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), |
1459 | GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu" , "clk_timer_src_pmu" , 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), |
1460 | |
1461 | GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu" , "xin24m" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), |
1462 | |
1463 | GATE(PCLK_PMU, "pclk_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), |
1464 | GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), |
1465 | GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), |
1466 | GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), |
1467 | GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), |
1468 | GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), |
1469 | GATE(PCLK_NOC_PMU, "pclk_noc_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), |
1470 | GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), |
1471 | GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), |
1472 | GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), |
1473 | GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), |
1474 | GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), |
1475 | GATE(PCLK_TIMER_PMU, "pclk_timer_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), |
1476 | GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), |
1477 | GATE(PCLK_UART4_PMU, "pclk_uart4_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), |
1478 | GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu" , "pclk_pmu_src" , 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), |
1479 | |
1480 | GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), |
1481 | GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), |
1482 | GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), |
1483 | GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), |
1484 | GATE(HCLK_NOC_PMU, "hclk_noc_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), |
1485 | }; |
1486 | |
1487 | static const char *const rk3399_cru_critical_clocks[] __initconst = { |
1488 | "aclk_cci_pre" , |
1489 | "aclk_gic" , |
1490 | "aclk_gic_noc" , |
1491 | "aclk_hdcp_noc" , |
1492 | "hclk_hdcp_noc" , |
1493 | "pclk_hdcp_noc" , |
1494 | "pclk_perilp0" , |
1495 | "pclk_perilp0" , |
1496 | "hclk_perilp0" , |
1497 | "hclk_perilp0_noc" , |
1498 | "pclk_perilp1" , |
1499 | "pclk_perilp1_noc" , |
1500 | "pclk_perihp" , |
1501 | "pclk_perihp_noc" , |
1502 | "hclk_perihp" , |
1503 | "aclk_perihp" , |
1504 | "aclk_perihp_noc" , |
1505 | "aclk_perilp0" , |
1506 | "aclk_perilp0_noc" , |
1507 | "hclk_perilp1" , |
1508 | "hclk_perilp1_noc" , |
1509 | "aclk_dmac0_perilp" , |
1510 | "aclk_emmc_noc" , |
1511 | "gpll_hclk_perilp1_src" , |
1512 | "gpll_aclk_perilp0_src" , |
1513 | "gpll_aclk_perihp_src" , |
1514 | "aclk_vio_noc" , |
1515 | |
1516 | /* ddrc */ |
1517 | "sclk_ddrc" , |
1518 | |
1519 | "armclkl" , |
1520 | "armclkb" , |
1521 | }; |
1522 | |
1523 | static const char *const rk3399_pmucru_critical_clocks[] __initconst = { |
1524 | "ppll" , |
1525 | "pclk_pmu_src" , |
1526 | "fclk_cm0s_src_pmu" , |
1527 | "clk_timer_src_pmu" , |
1528 | "pclk_rkpwm_pmu" , |
1529 | }; |
1530 | |
1531 | static void __init rk3399_clk_init(struct device_node *np) |
1532 | { |
1533 | struct rockchip_clk_provider *ctx; |
1534 | void __iomem *reg_base; |
1535 | |
1536 | reg_base = of_iomap(node: np, index: 0); |
1537 | if (!reg_base) { |
1538 | pr_err("%s: could not map cru region\n" , __func__); |
1539 | return; |
1540 | } |
1541 | |
1542 | ctx = rockchip_clk_init(np, base: reg_base, CLK_NR_CLKS); |
1543 | if (IS_ERR(ptr: ctx)) { |
1544 | pr_err("%s: rockchip clk init failed\n" , __func__); |
1545 | iounmap(addr: reg_base); |
1546 | return; |
1547 | } |
1548 | |
1549 | rockchip_clk_register_plls(ctx, pll_list: rk3399_pll_clks, |
1550 | ARRAY_SIZE(rk3399_pll_clks), grf_lock_offset: -1); |
1551 | |
1552 | rockchip_clk_register_branches(ctx, list: rk3399_clk_branches, |
1553 | ARRAY_SIZE(rk3399_clk_branches)); |
1554 | |
1555 | rockchip_clk_register_armclk(ctx, ARMCLKL, name: "armclkl" , |
1556 | parent_names: mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), |
1557 | reg_data: &rk3399_cpuclkl_data, rates: rk3399_cpuclkl_rates, |
1558 | ARRAY_SIZE(rk3399_cpuclkl_rates)); |
1559 | |
1560 | rockchip_clk_register_armclk(ctx, ARMCLKB, name: "armclkb" , |
1561 | parent_names: mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), |
1562 | reg_data: &rk3399_cpuclkb_data, rates: rk3399_cpuclkb_rates, |
1563 | ARRAY_SIZE(rk3399_cpuclkb_rates)); |
1564 | |
1565 | rockchip_clk_protect_critical(clocks: rk3399_cru_critical_clocks, |
1566 | ARRAY_SIZE(rk3399_cru_critical_clocks)); |
1567 | |
1568 | rockchip_register_softrst(np, num_regs: 21, base: reg_base + RK3399_SOFTRST_CON(0), |
1569 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
1570 | |
1571 | rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); |
1572 | |
1573 | rockchip_clk_of_add_provider(np, ctx); |
1574 | } |
1575 | CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru" , rk3399_clk_init); |
1576 | |
1577 | static void __init rk3399_pmu_clk_init(struct device_node *np) |
1578 | { |
1579 | struct rockchip_clk_provider *ctx; |
1580 | void __iomem *reg_base; |
1581 | |
1582 | reg_base = of_iomap(node: np, index: 0); |
1583 | if (!reg_base) { |
1584 | pr_err("%s: could not map cru pmu region\n" , __func__); |
1585 | return; |
1586 | } |
1587 | |
1588 | ctx = rockchip_clk_init(np, base: reg_base, CLKPMU_NR_CLKS); |
1589 | if (IS_ERR(ptr: ctx)) { |
1590 | pr_err("%s: rockchip pmu clk init failed\n" , __func__); |
1591 | iounmap(addr: reg_base); |
1592 | return; |
1593 | } |
1594 | |
1595 | rockchip_clk_register_plls(ctx, pll_list: rk3399_pmu_pll_clks, |
1596 | ARRAY_SIZE(rk3399_pmu_pll_clks), grf_lock_offset: -1); |
1597 | |
1598 | rockchip_clk_register_branches(ctx, list: rk3399_clk_pmu_branches, |
1599 | ARRAY_SIZE(rk3399_clk_pmu_branches)); |
1600 | |
1601 | rockchip_clk_protect_critical(clocks: rk3399_pmucru_critical_clocks, |
1602 | ARRAY_SIZE(rk3399_pmucru_critical_clocks)); |
1603 | |
1604 | rockchip_register_softrst(np, num_regs: 2, base: reg_base + RK3399_PMU_SOFTRST_CON(0), |
1605 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
1606 | |
1607 | rockchip_clk_of_add_provider(np, ctx); |
1608 | } |
1609 | CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru" , rk3399_pmu_clk_init); |
1610 | |
1611 | struct clk_rk3399_inits { |
1612 | void (*inits)(struct device_node *np); |
1613 | }; |
1614 | |
1615 | static const struct clk_rk3399_inits clk_rk3399_pmucru_init = { |
1616 | .inits = rk3399_pmu_clk_init, |
1617 | }; |
1618 | |
1619 | static const struct clk_rk3399_inits clk_rk3399_cru_init = { |
1620 | .inits = rk3399_clk_init, |
1621 | }; |
1622 | |
1623 | static const struct of_device_id clk_rk3399_match_table[] = { |
1624 | { |
1625 | .compatible = "rockchip,rk3399-cru" , |
1626 | .data = &clk_rk3399_cru_init, |
1627 | }, { |
1628 | .compatible = "rockchip,rk3399-pmucru" , |
1629 | .data = &clk_rk3399_pmucru_init, |
1630 | }, |
1631 | { } |
1632 | }; |
1633 | |
1634 | static int __init clk_rk3399_probe(struct platform_device *pdev) |
1635 | { |
1636 | struct device_node *np = pdev->dev.of_node; |
1637 | const struct clk_rk3399_inits *init_data; |
1638 | |
1639 | init_data = device_get_match_data(dev: &pdev->dev); |
1640 | if (init_data->inits) |
1641 | init_data->inits(np); |
1642 | |
1643 | return 0; |
1644 | } |
1645 | |
1646 | static struct platform_driver clk_rk3399_driver = { |
1647 | .driver = { |
1648 | .name = "clk-rk3399" , |
1649 | .of_match_table = clk_rk3399_match_table, |
1650 | .suppress_bind_attrs = true, |
1651 | }, |
1652 | }; |
1653 | builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe); |
1654 | |