1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
4 | * Copyright (c) 2013 Linaro Ltd. |
5 | * Author: Thomas Abraham <thomas.ab@samsung.com> |
6 | * |
7 | * Common Clock Framework support for all Exynos4 SoCs. |
8 | */ |
9 | |
10 | #include <dt-bindings/clock/exynos4.h> |
11 | #include <linux/slab.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/clk-provider.h> |
14 | #include <linux/io.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> |
17 | |
18 | #include "clk.h" |
19 | #include "clk-cpu.h" |
20 | |
21 | /* Exynos4 clock controller register offsets */ |
22 | #define SRC_LEFTBUS 0x4200 |
23 | #define DIV_LEFTBUS 0x4500 |
24 | #define GATE_IP_LEFTBUS 0x4800 |
25 | #define E4X12_GATE_IP_IMAGE 0x4930 |
26 | #define CLKOUT_CMU_LEFTBUS 0x4a00 |
27 | #define SRC_RIGHTBUS 0x8200 |
28 | #define DIV_RIGHTBUS 0x8500 |
29 | #define GATE_IP_RIGHTBUS 0x8800 |
30 | #define E4X12_GATE_IP_PERIR 0x8960 |
31 | #define CLKOUT_CMU_RIGHTBUS 0x8a00 |
32 | #define EPLL_LOCK 0xc010 |
33 | #define VPLL_LOCK 0xc020 |
34 | #define EPLL_CON0 0xc110 |
35 | #define EPLL_CON1 0xc114 |
36 | #define EPLL_CON2 0xc118 |
37 | #define VPLL_CON0 0xc120 |
38 | #define VPLL_CON1 0xc124 |
39 | #define VPLL_CON2 0xc128 |
40 | #define SRC_TOP0 0xc210 |
41 | #define SRC_TOP1 0xc214 |
42 | #define SRC_CAM 0xc220 |
43 | #define SRC_TV 0xc224 |
44 | #define SRC_MFC 0xc228 |
45 | #define SRC_G3D 0xc22c |
46 | #define E4210_SRC_IMAGE 0xc230 |
47 | #define SRC_LCD0 0xc234 |
48 | #define E4210_SRC_LCD1 0xc238 |
49 | #define E4X12_SRC_ISP 0xc238 |
50 | #define SRC_MAUDIO 0xc23c |
51 | #define SRC_FSYS 0xc240 |
52 | #define SRC_PERIL0 0xc250 |
53 | #define SRC_PERIL1 0xc254 |
54 | #define E4X12_SRC_CAM1 0xc258 |
55 | #define SRC_MASK_TOP 0xc310 |
56 | #define SRC_MASK_CAM 0xc320 |
57 | #define SRC_MASK_TV 0xc324 |
58 | #define SRC_MASK_LCD0 0xc334 |
59 | #define E4210_SRC_MASK_LCD1 0xc338 |
60 | #define E4X12_SRC_MASK_ISP 0xc338 |
61 | #define SRC_MASK_MAUDIO 0xc33c |
62 | #define SRC_MASK_FSYS 0xc340 |
63 | #define SRC_MASK_PERIL0 0xc350 |
64 | #define SRC_MASK_PERIL1 0xc354 |
65 | #define DIV_TOP 0xc510 |
66 | #define DIV_CAM 0xc520 |
67 | #define DIV_TV 0xc524 |
68 | #define DIV_MFC 0xc528 |
69 | #define DIV_G3D 0xc52c |
70 | #define DIV_IMAGE 0xc530 |
71 | #define DIV_LCD0 0xc534 |
72 | #define E4210_DIV_LCD1 0xc538 |
73 | #define E4X12_DIV_ISP 0xc538 |
74 | #define DIV_MAUDIO 0xc53c |
75 | #define DIV_FSYS0 0xc540 |
76 | #define DIV_FSYS1 0xc544 |
77 | #define DIV_FSYS2 0xc548 |
78 | #define DIV_FSYS3 0xc54c |
79 | #define DIV_PERIL0 0xc550 |
80 | #define DIV_PERIL1 0xc554 |
81 | #define DIV_PERIL2 0xc558 |
82 | #define DIV_PERIL3 0xc55c |
83 | #define DIV_PERIL4 0xc560 |
84 | #define DIV_PERIL5 0xc564 |
85 | #define E4X12_DIV_CAM1 0xc568 |
86 | #define E4X12_GATE_BUS_FSYS1 0xc744 |
87 | #define GATE_SCLK_CAM 0xc820 |
88 | #define GATE_IP_CAM 0xc920 |
89 | #define GATE_IP_TV 0xc924 |
90 | #define GATE_IP_MFC 0xc928 |
91 | #define GATE_IP_G3D 0xc92c |
92 | #define E4210_GATE_IP_IMAGE 0xc930 |
93 | #define GATE_IP_LCD0 0xc934 |
94 | #define E4210_GATE_IP_LCD1 0xc938 |
95 | #define E4X12_GATE_IP_ISP 0xc938 |
96 | #define E4X12_GATE_IP_MAUDIO 0xc93c |
97 | #define GATE_IP_FSYS 0xc940 |
98 | #define GATE_IP_GPS 0xc94c |
99 | #define GATE_IP_PERIL 0xc950 |
100 | #define E4210_GATE_IP_PERIR 0xc960 |
101 | #define GATE_BLOCK 0xc970 |
102 | #define CLKOUT_CMU_TOP 0xca00 |
103 | #define E4X12_MPLL_LOCK 0x10008 |
104 | #define E4X12_MPLL_CON0 0x10108 |
105 | #define SRC_DMC 0x10200 |
106 | #define SRC_MASK_DMC 0x10300 |
107 | #define DIV_DMC0 0x10500 |
108 | #define DIV_DMC1 0x10504 |
109 | #define GATE_IP_DMC 0x10900 |
110 | #define CLKOUT_CMU_DMC 0x10a00 |
111 | #define APLL_LOCK 0x14000 |
112 | #define E4210_MPLL_LOCK 0x14008 |
113 | #define APLL_CON0 0x14100 |
114 | #define E4210_MPLL_CON0 0x14108 |
115 | #define SRC_CPU 0x14200 |
116 | #define DIV_CPU0 0x14500 |
117 | #define DIV_CPU1 0x14504 |
118 | #define GATE_SCLK_CPU 0x14800 |
119 | #define GATE_IP_CPU 0x14900 |
120 | #define CLKOUT_CMU_CPU 0x14a00 |
121 | #define PWR_CTRL1 0x15020 |
122 | #define E4X12_PWR_CTRL2 0x15024 |
123 | |
124 | /* Below definitions are used for PWR_CTRL settings */ |
125 | #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) |
126 | #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) |
127 | #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) |
128 | #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) |
129 | #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) |
130 | #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) |
131 | #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) |
132 | #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) |
133 | #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) |
134 | #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) |
135 | #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) |
136 | #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) |
137 | |
138 | /* NOTE: Must be equal to the last clock ID increased by one */ |
139 | #define CLKS_NR (CLK_DIV_CORE2 + 1) |
140 | |
141 | /* the exynos4 soc type */ |
142 | enum exynos4_soc { |
143 | EXYNOS4210, |
144 | EXYNOS4212, |
145 | EXYNOS4412, |
146 | }; |
147 | |
148 | /* list of PLLs to be registered */ |
149 | enum exynos4_plls { |
150 | apll, mpll, epll, vpll, |
151 | nr_plls /* number of PLLs */ |
152 | }; |
153 | |
154 | static void __iomem *reg_base; |
155 | static enum exynos4_soc exynos4_soc; |
156 | |
157 | /* |
158 | * list of controller registers to be saved and restored during a |
159 | * suspend/resume cycle. |
160 | */ |
161 | static const unsigned long exynos4210_clk_save[] __initconst = { |
162 | E4210_SRC_IMAGE, |
163 | E4210_SRC_LCD1, |
164 | E4210_SRC_MASK_LCD1, |
165 | E4210_DIV_LCD1, |
166 | E4210_GATE_IP_IMAGE, |
167 | E4210_GATE_IP_LCD1, |
168 | E4210_GATE_IP_PERIR, |
169 | E4210_MPLL_CON0, |
170 | PWR_CTRL1, |
171 | }; |
172 | |
173 | static const unsigned long exynos4x12_clk_save[] __initconst = { |
174 | E4X12_GATE_IP_IMAGE, |
175 | E4X12_GATE_IP_PERIR, |
176 | E4X12_SRC_CAM1, |
177 | E4X12_DIV_ISP, |
178 | E4X12_DIV_CAM1, |
179 | E4X12_MPLL_CON0, |
180 | PWR_CTRL1, |
181 | E4X12_PWR_CTRL2, |
182 | }; |
183 | |
184 | static const unsigned long exynos4_clk_regs[] __initconst = { |
185 | EPLL_LOCK, |
186 | VPLL_LOCK, |
187 | EPLL_CON0, |
188 | EPLL_CON1, |
189 | EPLL_CON2, |
190 | VPLL_CON0, |
191 | VPLL_CON1, |
192 | VPLL_CON2, |
193 | SRC_LEFTBUS, |
194 | DIV_LEFTBUS, |
195 | GATE_IP_LEFTBUS, |
196 | SRC_RIGHTBUS, |
197 | DIV_RIGHTBUS, |
198 | GATE_IP_RIGHTBUS, |
199 | SRC_TOP0, |
200 | SRC_TOP1, |
201 | SRC_CAM, |
202 | SRC_TV, |
203 | SRC_MFC, |
204 | SRC_G3D, |
205 | SRC_LCD0, |
206 | SRC_MAUDIO, |
207 | SRC_FSYS, |
208 | SRC_PERIL0, |
209 | SRC_PERIL1, |
210 | SRC_MASK_TOP, |
211 | SRC_MASK_CAM, |
212 | SRC_MASK_TV, |
213 | SRC_MASK_LCD0, |
214 | SRC_MASK_MAUDIO, |
215 | SRC_MASK_FSYS, |
216 | SRC_MASK_PERIL0, |
217 | SRC_MASK_PERIL1, |
218 | DIV_TOP, |
219 | DIV_CAM, |
220 | DIV_TV, |
221 | DIV_MFC, |
222 | DIV_G3D, |
223 | DIV_IMAGE, |
224 | DIV_LCD0, |
225 | DIV_MAUDIO, |
226 | DIV_FSYS0, |
227 | DIV_FSYS1, |
228 | DIV_FSYS2, |
229 | DIV_FSYS3, |
230 | DIV_PERIL0, |
231 | DIV_PERIL1, |
232 | DIV_PERIL2, |
233 | DIV_PERIL3, |
234 | DIV_PERIL4, |
235 | DIV_PERIL5, |
236 | GATE_SCLK_CAM, |
237 | GATE_IP_CAM, |
238 | GATE_IP_TV, |
239 | GATE_IP_MFC, |
240 | GATE_IP_G3D, |
241 | GATE_IP_LCD0, |
242 | GATE_IP_FSYS, |
243 | GATE_IP_GPS, |
244 | GATE_IP_PERIL, |
245 | GATE_BLOCK, |
246 | SRC_MASK_DMC, |
247 | SRC_DMC, |
248 | DIV_DMC0, |
249 | DIV_DMC1, |
250 | GATE_IP_DMC, |
251 | APLL_CON0, |
252 | SRC_CPU, |
253 | DIV_CPU0, |
254 | DIV_CPU1, |
255 | GATE_SCLK_CPU, |
256 | GATE_IP_CPU, |
257 | CLKOUT_CMU_LEFTBUS, |
258 | CLKOUT_CMU_RIGHTBUS, |
259 | CLKOUT_CMU_TOP, |
260 | CLKOUT_CMU_DMC, |
261 | CLKOUT_CMU_CPU, |
262 | }; |
263 | |
264 | static const struct samsung_clk_reg_dump src_mask_suspend[] = { |
265 | { .offset = VPLL_CON0, .value = 0x80600302, }, |
266 | { .offset = EPLL_CON0, .value = 0x806F0302, }, |
267 | { .offset = SRC_MASK_TOP, .value = 0x00000001, }, |
268 | { .offset = SRC_MASK_CAM, .value = 0x11111111, }, |
269 | { .offset = SRC_MASK_TV, .value = 0x00000111, }, |
270 | { .offset = SRC_MASK_LCD0, .value = 0x00001111, }, |
271 | { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, }, |
272 | { .offset = SRC_MASK_FSYS, .value = 0x01011111, }, |
273 | { .offset = SRC_MASK_PERIL0, .value = 0x01111111, }, |
274 | { .offset = SRC_MASK_PERIL1, .value = 0x01110111, }, |
275 | { .offset = SRC_MASK_DMC, .value = 0x00010000, }, |
276 | }; |
277 | |
278 | static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { |
279 | { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, |
280 | }; |
281 | |
282 | /* list of all parent clock list */ |
283 | PNAME(mout_apll_p) = { "fin_pll" , "fout_apll" , }; |
284 | PNAME(mout_mpll_p) = { "fin_pll" , "fout_mpll" , }; |
285 | PNAME(mout_epll_p) = { "fin_pll" , "fout_epll" , }; |
286 | PNAME(mout_vpllsrc_p) = { "fin_pll" , "sclk_hdmi24m" , }; |
287 | PNAME(mout_vpll_p) = { "fin_pll" , "fout_vpll" , }; |
288 | PNAME(sclk_evpll_p) = { "sclk_epll" , "sclk_vpll" , }; |
289 | PNAME(mout_mfc_p) = { "mout_mfc0" , "mout_mfc1" , }; |
290 | PNAME(mout_g3d_p) = { "mout_g3d0" , "mout_g3d1" , }; |
291 | PNAME(mout_g2d_p) = { "mout_g2d0" , "mout_g2d1" , }; |
292 | PNAME(mout_hdmi_p) = { "sclk_pixel" , "sclk_hdmiphy" , }; |
293 | PNAME(mout_jpeg_p) = { "mout_jpeg0" , "mout_jpeg1" , }; |
294 | PNAME(mout_spdif_p) = { "sclk_audio0" , "sclk_audio1" , "sclk_audio2" , |
295 | "spdif_extclk" , }; |
296 | PNAME(mout_onenand_p) = {"aclk133" , "aclk160" , }; |
297 | PNAME(mout_onenand1_p) = {"mout_onenand" , "sclk_vpll" , }; |
298 | |
299 | /* Exynos 4210-specific parent groups */ |
300 | PNAME(sclk_vpll_p4210) = { "mout_vpllsrc" , "fout_vpll" , }; |
301 | PNAME(mout_core_p4210) = { "mout_apll" , "sclk_mpll" , }; |
302 | PNAME(sclk_ampll_p4210) = { "sclk_mpll" , "sclk_apll" , }; |
303 | PNAME(group1_p4210) = { "xxti" , "xusbxti" , "sclk_hdmi24m" , |
304 | "sclk_usbphy0" , "none" , "sclk_hdmiphy" , |
305 | "sclk_mpll" , "sclk_epll" , "sclk_vpll" , }; |
306 | PNAME(mout_audio0_p4210) = { "cdclk0" , "none" , "sclk_hdmi24m" , |
307 | "sclk_usbphy0" , "xxti" , "xusbxti" , "sclk_mpll" , |
308 | "sclk_epll" , "sclk_vpll" }; |
309 | PNAME(mout_audio1_p4210) = { "cdclk1" , "none" , "sclk_hdmi24m" , |
310 | "sclk_usbphy0" , "xxti" , "xusbxti" , "sclk_mpll" , |
311 | "sclk_epll" , "sclk_vpll" , }; |
312 | PNAME(mout_audio2_p4210) = { "cdclk2" , "none" , "sclk_hdmi24m" , |
313 | "sclk_usbphy0" , "xxti" , "xusbxti" , "sclk_mpll" , |
314 | "sclk_epll" , "sclk_vpll" , }; |
315 | PNAME(mout_mixer_p4210) = { "sclk_dac" , "sclk_hdmi" , }; |
316 | PNAME(mout_dac_p4210) = { "sclk_vpll" , "sclk_hdmiphy" , }; |
317 | PNAME(mout_pwi_p4210) = { "xxti" , "xusbxti" , "sclk_hdmi24m" , "sclk_usbphy0" , |
318 | "sclk_usbphy1" , "sclk_hdmiphy" , "none" , |
319 | "sclk_epll" , "sclk_vpll" }; |
320 | PNAME(clkout_left_p4210) = { "sclk_mpll_div_2" , "sclk_apll_div_2" , |
321 | "div_gdl" , "div_gpl" }; |
322 | PNAME(clkout_right_p4210) = { "sclk_mpll_div_2" , "sclk_apll_div_2" , |
323 | "div_gdr" , "div_gpr" }; |
324 | PNAME(clkout_top_p4210) = { "fout_epll" , "fout_vpll" , "sclk_hdmi24m" , |
325 | "sclk_usbphy0" , "sclk_usbphy1" , "sclk_hdmiphy" , |
326 | "cdclk0" , "cdclk1" , "cdclk2" , "spdif_extclk" , |
327 | "aclk160" , "aclk133" , "aclk200" , "aclk100" , |
328 | "sclk_mfc" , "sclk_g3d" , "sclk_g2d" , |
329 | "cam_a_pclk" , "cam_b_pclk" , "s_rxbyteclkhs0_2l" , |
330 | "s_rxbyteclkhs0_4l" }; |
331 | PNAME(clkout_dmc_p4210) = { "div_dmcd" , "div_dmcp" , "div_acp_pclk" , "div_dmc" , |
332 | "div_dphy" , "none" , "div_pwi" }; |
333 | PNAME(clkout_cpu_p4210) = { "fout_apll_div_2" , "none" , "fout_mpll_div_2" , |
334 | "none" , "arm_clk_div_2" , "div_corem0" , |
335 | "div_corem1" , "div_corem0" , "div_atb" , |
336 | "div_periph" , "div_pclk_dbg" , "div_hpm" }; |
337 | |
338 | /* Exynos 4x12-specific parent groups */ |
339 | PNAME(mout_mpll_user_p4x12) = { "fin_pll" , "sclk_mpll" , }; |
340 | PNAME(mout_core_p4x12) = { "mout_apll" , "mout_mpll_user_c" , }; |
341 | PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l" , "sclk_apll" , }; |
342 | PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r" , "sclk_apll" , }; |
343 | PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t" , "sclk_apll" , }; |
344 | PNAME(group1_p4x12) = { "xxti" , "xusbxti" , "sclk_hdmi24m" , "sclk_usbphy0" , |
345 | "none" , "sclk_hdmiphy" , "mout_mpll_user_t" , |
346 | "sclk_epll" , "sclk_vpll" , }; |
347 | PNAME(mout_audio0_p4x12) = { "cdclk0" , "none" , "sclk_hdmi24m" , |
348 | "sclk_usbphy0" , "xxti" , "xusbxti" , |
349 | "mout_mpll_user_t" , "sclk_epll" , "sclk_vpll" }; |
350 | PNAME(mout_audio1_p4x12) = { "cdclk1" , "none" , "sclk_hdmi24m" , |
351 | "sclk_usbphy0" , "xxti" , "xusbxti" , |
352 | "mout_mpll_user_t" , "sclk_epll" , "sclk_vpll" , }; |
353 | PNAME(mout_audio2_p4x12) = { "cdclk2" , "none" , "sclk_hdmi24m" , |
354 | "sclk_usbphy0" , "xxti" , "xusbxti" , |
355 | "mout_mpll_user_t" , "sclk_epll" , "sclk_vpll" , }; |
356 | PNAME(aclk_p4412) = { "mout_mpll_user_t" , "sclk_apll" , }; |
357 | PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll" , "div_aclk400_mcuisp" , }; |
358 | PNAME(mout_user_aclk200_p4x12) = {"fin_pll" , "div_aclk200" , }; |
359 | PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll" , "div_aclk266_gps" , }; |
360 | PNAME(mout_pwi_p4x12) = { "xxti" , "xusbxti" , "sclk_hdmi24m" , "sclk_usbphy0" , |
361 | "none" , "sclk_hdmiphy" , "sclk_mpll" , |
362 | "sclk_epll" , "sclk_vpll" }; |
363 | PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2" , "sclk_apll_div_2" , |
364 | "div_gdl" , "div_gpl" }; |
365 | PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2" , "sclk_apll_div_2" , |
366 | "div_gdr" , "div_gpr" }; |
367 | PNAME(clkout_top_p4x12) = { "fout_epll" , "fout_vpll" , "sclk_hdmi24m" , |
368 | "sclk_usbphy0" , "none" , "sclk_hdmiphy" , |
369 | "cdclk0" , "cdclk1" , "cdclk2" , "spdif_extclk" , |
370 | "aclk160" , "aclk133" , "aclk200" , "aclk100" , |
371 | "sclk_mfc" , "sclk_g3d" , "aclk400_mcuisp" , |
372 | "cam_a_pclk" , "cam_b_pclk" , "s_rxbyteclkhs0_2l" , |
373 | "s_rxbyteclkhs0_4l" , "rx_half_byte_clk_csis0" , |
374 | "rx_half_byte_clk_csis1" , "div_jpeg" , |
375 | "sclk_pwm_isp" , "sclk_spi0_isp" , |
376 | "sclk_spi1_isp" , "sclk_uart_isp" , |
377 | "sclk_mipihsi" , "sclk_hdmi" , "sclk_fimd0" , |
378 | "sclk_pcm0" }; |
379 | PNAME(clkout_dmc_p4x12) = { "div_dmcd" , "div_dmcp" , "aclk_acp" , "div_acp_pclk" , |
380 | "div_dmc" , "div_dphy" , "fout_mpll_div_2" , |
381 | "div_pwi" , "none" , "div_c2c" , "div_c2c_aclk" }; |
382 | PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2" , "none" , "none" , "none" , |
383 | "arm_clk_div_2" , "div_corem0" , "div_corem1" , |
384 | "div_cores" , "div_atb" , "div_periph" , |
385 | "div_pclk_dbg" , "div_hpm" }; |
386 | |
387 | /* fixed rate clocks generated outside the soc */ |
388 | static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { |
389 | FRATE(CLK_XXTI, "xxti" , NULL, 0, 0), |
390 | FRATE(CLK_XUSBXTI, "xusbxti" , NULL, 0, 0), |
391 | }; |
392 | |
393 | /* fixed rate clocks generated inside the soc */ |
394 | static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = { |
395 | FRATE(0, "sclk_hdmi24m" , NULL, 0, 24000000), |
396 | FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy" , "hdmi" , 0, 27000000), |
397 | FRATE(0, "sclk_usbphy0" , NULL, 0, 48000000), |
398 | }; |
399 | |
400 | static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = { |
401 | FRATE(0, "sclk_usbphy1" , NULL, 0, 48000000), |
402 | }; |
403 | |
404 | static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = { |
405 | FFACTOR(0, "sclk_apll_div_2" , "sclk_apll" , 1, 2, 0), |
406 | FFACTOR(0, "fout_mpll_div_2" , "fout_mpll" , 1, 2, 0), |
407 | FFACTOR(0, "fout_apll_div_2" , "fout_apll" , 1, 2, 0), |
408 | FFACTOR(0, "arm_clk_div_2" , "div_core2" , 1, 2, 0), |
409 | }; |
410 | |
411 | static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = { |
412 | FFACTOR(0, "sclk_mpll_div_2" , "sclk_mpll" , 1, 2, 0), |
413 | }; |
414 | |
415 | static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = { |
416 | FFACTOR(0, "sclk_mpll_user_l_div_2" , "mout_mpll_user_l" , 1, 2, 0), |
417 | FFACTOR(0, "sclk_mpll_user_r_div_2" , "mout_mpll_user_r" , 1, 2, 0), |
418 | FFACTOR(0, "sclk_mpll_user_t_div_2" , "mout_mpll_user_t" , 1, 2, 0), |
419 | FFACTOR(0, "sclk_mpll_user_c_div_2" , "mout_mpll_user_c" , 1, 2, 0), |
420 | }; |
421 | |
422 | /* list of mux clocks supported in all exynos4 soc's */ |
423 | static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { |
424 | MUX_F(CLK_MOUT_APLL, "mout_apll" , mout_apll_p, SRC_CPU, 0, 1, |
425 | CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), |
426 | MUX(CLK_MOUT_HDMI, "mout_hdmi" , mout_hdmi_p, SRC_TV, 0, 1), |
427 | MUX(0, "mout_mfc1" , sclk_evpll_p, SRC_MFC, 4, 1), |
428 | MUX(0, "mout_mfc" , mout_mfc_p, SRC_MFC, 8, 1), |
429 | MUX_F(CLK_MOUT_G3D1, "mout_g3d1" , sclk_evpll_p, SRC_G3D, 4, 1, |
430 | CLK_SET_RATE_PARENT, 0), |
431 | MUX_F(CLK_MOUT_G3D, "mout_g3d" , mout_g3d_p, SRC_G3D, 8, 1, |
432 | CLK_SET_RATE_PARENT, 0), |
433 | MUX(0, "mout_spdif" , mout_spdif_p, SRC_PERIL1, 8, 2), |
434 | MUX(0, "mout_onenand1" , mout_onenand1_p, SRC_TOP0, 0, 1), |
435 | MUX(CLK_SCLK_EPLL, "sclk_epll" , mout_epll_p, SRC_TOP0, 4, 1), |
436 | MUX(0, "mout_onenand" , mout_onenand_p, SRC_TOP0, 28, 1), |
437 | |
438 | MUX(0, "mout_dmc_bus" , sclk_ampll_p4210, SRC_DMC, 4, 1), |
439 | MUX(0, "mout_dphy" , sclk_ampll_p4210, SRC_DMC, 8, 1), |
440 | }; |
441 | |
442 | /* list of mux clocks supported in exynos4210 soc */ |
443 | static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = { |
444 | MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc" , mout_vpllsrc_p, SRC_TOP1, 0, 1), |
445 | }; |
446 | |
447 | static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = { |
448 | MUX(0, "mout_gdl" , sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), |
449 | MUX(0, "mout_clkout_leftbus" , clkout_left_p4210, |
450 | CLKOUT_CMU_LEFTBUS, 0, 5), |
451 | |
452 | MUX(0, "mout_gdr" , sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1), |
453 | MUX(0, "mout_clkout_rightbus" , clkout_right_p4210, |
454 | CLKOUT_CMU_RIGHTBUS, 0, 5), |
455 | |
456 | MUX(0, "mout_aclk200" , sclk_ampll_p4210, SRC_TOP0, 12, 1), |
457 | MUX(0, "mout_aclk100" , sclk_ampll_p4210, SRC_TOP0, 16, 1), |
458 | MUX(0, "mout_aclk160" , sclk_ampll_p4210, SRC_TOP0, 20, 1), |
459 | MUX(0, "mout_aclk133" , sclk_ampll_p4210, SRC_TOP0, 24, 1), |
460 | MUX(CLK_MOUT_MIXER, "mout_mixer" , mout_mixer_p4210, SRC_TV, 4, 1), |
461 | MUX(0, "mout_dac" , mout_dac_p4210, SRC_TV, 8, 1), |
462 | MUX(0, "mout_g2d0" , sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), |
463 | MUX(0, "mout_g2d1" , sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), |
464 | MUX(0, "mout_g2d" , mout_g2d_p, E4210_SRC_IMAGE, 8, 1), |
465 | MUX(0, "mout_fimd1" , group1_p4210, E4210_SRC_LCD1, 0, 4), |
466 | MUX(0, "mout_mipi1" , group1_p4210, E4210_SRC_LCD1, 12, 4), |
467 | MUX(CLK_SCLK_MPLL, "sclk_mpll" , mout_mpll_p, SRC_CPU, 8, 1), |
468 | MUX(CLK_MOUT_CORE, "mout_core" , mout_core_p4210, SRC_CPU, 16, 1), |
469 | MUX(0, "mout_hpm" , mout_core_p4210, SRC_CPU, 20, 1), |
470 | MUX(CLK_SCLK_VPLL, "sclk_vpll" , sclk_vpll_p4210, SRC_TOP0, 8, 1), |
471 | MUX(CLK_MOUT_FIMC0, "mout_fimc0" , group1_p4210, SRC_CAM, 0, 4), |
472 | MUX(CLK_MOUT_FIMC1, "mout_fimc1" , group1_p4210, SRC_CAM, 4, 4), |
473 | MUX(CLK_MOUT_FIMC2, "mout_fimc2" , group1_p4210, SRC_CAM, 8, 4), |
474 | MUX(CLK_MOUT_FIMC3, "mout_fimc3" , group1_p4210, SRC_CAM, 12, 4), |
475 | MUX(CLK_MOUT_CAM0, "mout_cam0" , group1_p4210, SRC_CAM, 16, 4), |
476 | MUX(CLK_MOUT_CAM1, "mout_cam1" , group1_p4210, SRC_CAM, 20, 4), |
477 | MUX(CLK_MOUT_CSIS0, "mout_csis0" , group1_p4210, SRC_CAM, 24, 4), |
478 | MUX(CLK_MOUT_CSIS1, "mout_csis1" , group1_p4210, SRC_CAM, 28, 4), |
479 | MUX(0, "mout_mfc0" , sclk_ampll_p4210, SRC_MFC, 0, 1), |
480 | MUX_F(CLK_MOUT_G3D0, "mout_g3d0" , sclk_ampll_p4210, SRC_G3D, 0, 1, |
481 | CLK_SET_RATE_PARENT, 0), |
482 | MUX(0, "mout_fimd0" , group1_p4210, SRC_LCD0, 0, 4), |
483 | MUX(0, "mout_mipi0" , group1_p4210, SRC_LCD0, 12, 4), |
484 | MUX(0, "mout_audio0" , mout_audio0_p4210, SRC_MAUDIO, 0, 4), |
485 | MUX(0, "mout_mmc0" , group1_p4210, SRC_FSYS, 0, 4), |
486 | MUX(0, "mout_mmc1" , group1_p4210, SRC_FSYS, 4, 4), |
487 | MUX(0, "mout_mmc2" , group1_p4210, SRC_FSYS, 8, 4), |
488 | MUX(0, "mout_mmc3" , group1_p4210, SRC_FSYS, 12, 4), |
489 | MUX(0, "mout_mmc4" , group1_p4210, SRC_FSYS, 16, 4), |
490 | MUX(0, "mout_sata" , sclk_ampll_p4210, SRC_FSYS, 24, 1), |
491 | MUX(0, "mout_uart0" , group1_p4210, SRC_PERIL0, 0, 4), |
492 | MUX(0, "mout_uart1" , group1_p4210, SRC_PERIL0, 4, 4), |
493 | MUX(0, "mout_uart2" , group1_p4210, SRC_PERIL0, 8, 4), |
494 | MUX(0, "mout_uart3" , group1_p4210, SRC_PERIL0, 12, 4), |
495 | MUX(0, "mout_uart4" , group1_p4210, SRC_PERIL0, 16, 4), |
496 | MUX(0, "mout_audio1" , mout_audio1_p4210, SRC_PERIL1, 0, 4), |
497 | MUX(0, "mout_audio2" , mout_audio2_p4210, SRC_PERIL1, 4, 4), |
498 | MUX(0, "mout_spi0" , group1_p4210, SRC_PERIL1, 16, 4), |
499 | MUX(0, "mout_spi1" , group1_p4210, SRC_PERIL1, 20, 4), |
500 | MUX(0, "mout_spi2" , group1_p4210, SRC_PERIL1, 24, 4), |
501 | MUX(0, "mout_clkout_top" , clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5), |
502 | |
503 | MUX(0, "mout_pwi" , mout_pwi_p4210, SRC_DMC, 16, 4), |
504 | MUX(0, "mout_clkout_dmc" , clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5), |
505 | |
506 | MUX(0, "mout_clkout_cpu" , clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5), |
507 | }; |
508 | |
509 | /* list of mux clocks supported in exynos4x12 soc */ |
510 | static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = { |
511 | MUX(0, "mout_mpll_user_l" , mout_mpll_p, SRC_LEFTBUS, 4, 1), |
512 | MUX(0, "mout_gdl" , mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), |
513 | MUX(0, "mout_clkout_leftbus" , clkout_left_p4x12, |
514 | CLKOUT_CMU_LEFTBUS, 0, 5), |
515 | |
516 | MUX(0, "mout_mpll_user_r" , mout_mpll_p, SRC_RIGHTBUS, 4, 1), |
517 | MUX(0, "mout_gdr" , mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1), |
518 | MUX(0, "mout_clkout_rightbus" , clkout_right_p4x12, |
519 | CLKOUT_CMU_RIGHTBUS, 0, 5), |
520 | |
521 | MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c" , mout_mpll_user_p4x12, |
522 | SRC_CPU, 24, 1), |
523 | MUX(0, "mout_clkout_cpu" , clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5), |
524 | |
525 | MUX(0, "mout_aclk266_gps" , aclk_p4412, SRC_TOP1, 4, 1), |
526 | MUX(0, "mout_aclk400_mcuisp" , aclk_p4412, SRC_TOP1, 8, 1), |
527 | MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t" , mout_mpll_user_p4x12, |
528 | SRC_TOP1, 12, 1), |
529 | MUX(0, "mout_user_aclk266_gps" , mout_user_aclk266_gps_p4x12, |
530 | SRC_TOP1, 16, 1), |
531 | MUX(CLK_ACLK200, "aclk200" , mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), |
532 | MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp" , |
533 | mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), |
534 | MUX(0, "mout_aclk200" , aclk_p4412, SRC_TOP0, 12, 1), |
535 | MUX(0, "mout_aclk100" , aclk_p4412, SRC_TOP0, 16, 1), |
536 | MUX(0, "mout_aclk160" , aclk_p4412, SRC_TOP0, 20, 1), |
537 | MUX(0, "mout_aclk133" , aclk_p4412, SRC_TOP0, 24, 1), |
538 | MUX(0, "mout_mdnie0" , group1_p4x12, SRC_LCD0, 4, 4), |
539 | MUX(0, "mout_mdnie_pwm0" , group1_p4x12, SRC_LCD0, 8, 4), |
540 | MUX(0, "mout_sata" , sclk_ampll_p4x12, SRC_FSYS, 24, 1), |
541 | MUX(0, "mout_jpeg0" , sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), |
542 | MUX(0, "mout_jpeg1" , sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), |
543 | MUX(0, "mout_jpeg" , mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), |
544 | MUX(CLK_SCLK_MPLL, "sclk_mpll" , mout_mpll_p, SRC_DMC, 12, 1), |
545 | MUX(CLK_SCLK_VPLL, "sclk_vpll" , mout_vpll_p, SRC_TOP0, 8, 1), |
546 | MUX(CLK_MOUT_CORE, "mout_core" , mout_core_p4x12, SRC_CPU, 16, 1), |
547 | MUX(0, "mout_hpm" , mout_core_p4x12, SRC_CPU, 20, 1), |
548 | MUX(CLK_MOUT_FIMC0, "mout_fimc0" , group1_p4x12, SRC_CAM, 0, 4), |
549 | MUX(CLK_MOUT_FIMC1, "mout_fimc1" , group1_p4x12, SRC_CAM, 4, 4), |
550 | MUX(CLK_MOUT_FIMC2, "mout_fimc2" , group1_p4x12, SRC_CAM, 8, 4), |
551 | MUX(CLK_MOUT_FIMC3, "mout_fimc3" , group1_p4x12, SRC_CAM, 12, 4), |
552 | MUX(CLK_MOUT_CAM0, "mout_cam0" , group1_p4x12, SRC_CAM, 16, 4), |
553 | MUX(CLK_MOUT_CAM1, "mout_cam1" , group1_p4x12, SRC_CAM, 20, 4), |
554 | MUX(CLK_MOUT_CSIS0, "mout_csis0" , group1_p4x12, SRC_CAM, 24, 4), |
555 | MUX(CLK_MOUT_CSIS1, "mout_csis1" , group1_p4x12, SRC_CAM, 28, 4), |
556 | MUX(0, "mout_mfc0" , sclk_ampll_p4x12, SRC_MFC, 0, 1), |
557 | MUX_F(CLK_MOUT_G3D0, "mout_g3d0" , sclk_ampll_p4x12, SRC_G3D, 0, 1, |
558 | CLK_SET_RATE_PARENT, 0), |
559 | MUX(0, "mout_fimd0" , group1_p4x12, SRC_LCD0, 0, 4), |
560 | MUX(0, "mout_mipi0" , group1_p4x12, SRC_LCD0, 12, 4), |
561 | MUX(0, "mout_audio0" , mout_audio0_p4x12, SRC_MAUDIO, 0, 4), |
562 | MUX(0, "mout_mmc0" , group1_p4x12, SRC_FSYS, 0, 4), |
563 | MUX(0, "mout_mmc1" , group1_p4x12, SRC_FSYS, 4, 4), |
564 | MUX(0, "mout_mmc2" , group1_p4x12, SRC_FSYS, 8, 4), |
565 | MUX(0, "mout_mmc3" , group1_p4x12, SRC_FSYS, 12, 4), |
566 | MUX(0, "mout_mmc4" , group1_p4x12, SRC_FSYS, 16, 4), |
567 | MUX(0, "mout_mipihsi" , aclk_p4412, SRC_FSYS, 24, 1), |
568 | MUX(0, "mout_uart0" , group1_p4x12, SRC_PERIL0, 0, 4), |
569 | MUX(0, "mout_uart1" , group1_p4x12, SRC_PERIL0, 4, 4), |
570 | MUX(0, "mout_uart2" , group1_p4x12, SRC_PERIL0, 8, 4), |
571 | MUX(0, "mout_uart3" , group1_p4x12, SRC_PERIL0, 12, 4), |
572 | MUX(0, "mout_uart4" , group1_p4x12, SRC_PERIL0, 16, 4), |
573 | MUX(0, "mout_audio1" , mout_audio1_p4x12, SRC_PERIL1, 0, 4), |
574 | MUX(0, "mout_audio2" , mout_audio2_p4x12, SRC_PERIL1, 4, 4), |
575 | MUX(0, "mout_spi0" , group1_p4x12, SRC_PERIL1, 16, 4), |
576 | MUX(0, "mout_spi1" , group1_p4x12, SRC_PERIL1, 20, 4), |
577 | MUX(0, "mout_spi2" , group1_p4x12, SRC_PERIL1, 24, 4), |
578 | MUX(0, "mout_pwm_isp" , group1_p4x12, E4X12_SRC_ISP, 0, 4), |
579 | MUX(0, "mout_spi0_isp" , group1_p4x12, E4X12_SRC_ISP, 4, 4), |
580 | MUX(0, "mout_spi1_isp" , group1_p4x12, E4X12_SRC_ISP, 8, 4), |
581 | MUX(0, "mout_uart_isp" , group1_p4x12, E4X12_SRC_ISP, 12, 4), |
582 | MUX(0, "mout_clkout_top" , clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5), |
583 | |
584 | MUX(0, "mout_c2c" , sclk_ampll_p4210, SRC_DMC, 0, 1), |
585 | MUX(0, "mout_pwi" , mout_pwi_p4x12, SRC_DMC, 16, 4), |
586 | MUX(0, "mout_g2d0" , sclk_ampll_p4210, SRC_DMC, 20, 1), |
587 | MUX(0, "mout_g2d1" , sclk_evpll_p, SRC_DMC, 24, 1), |
588 | MUX(0, "mout_g2d" , mout_g2d_p, SRC_DMC, 28, 1), |
589 | MUX(0, "mout_clkout_dmc" , clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5), |
590 | }; |
591 | |
592 | /* list of divider clocks supported in all exynos4 soc's */ |
593 | static const struct samsung_div_clock exynos4_div_clks[] __initconst = { |
594 | DIV(CLK_DIV_GDL, "div_gdl" , "mout_gdl" , DIV_LEFTBUS, 0, 3), |
595 | DIV(0, "div_gpl" , "div_gdl" , DIV_LEFTBUS, 4, 3), |
596 | DIV(0, "div_clkout_leftbus" , "mout_clkout_leftbus" , |
597 | CLKOUT_CMU_LEFTBUS, 8, 6), |
598 | |
599 | DIV(CLK_DIV_GDR, "div_gdr" , "mout_gdr" , DIV_RIGHTBUS, 0, 3), |
600 | DIV(0, "div_gpr" , "div_gdr" , DIV_RIGHTBUS, 4, 3), |
601 | DIV(0, "div_clkout_rightbus" , "mout_clkout_rightbus" , |
602 | CLKOUT_CMU_RIGHTBUS, 8, 6), |
603 | |
604 | DIV(0, "div_core" , "mout_core" , DIV_CPU0, 0, 3), |
605 | DIV(0, "div_corem0" , "div_core2" , DIV_CPU0, 4, 3), |
606 | DIV(0, "div_corem1" , "div_core2" , DIV_CPU0, 8, 3), |
607 | DIV(0, "div_periph" , "div_core2" , DIV_CPU0, 12, 3), |
608 | DIV(0, "div_atb" , "mout_core" , DIV_CPU0, 16, 3), |
609 | DIV(0, "div_pclk_dbg" , "div_atb" , DIV_CPU0, 20, 3), |
610 | DIV(CLK_DIV_CORE2, "div_core2" , "div_core" , DIV_CPU0, 28, 3), |
611 | DIV(0, "div_copy" , "mout_hpm" , DIV_CPU1, 0, 3), |
612 | DIV(0, "div_hpm" , "div_copy" , DIV_CPU1, 4, 3), |
613 | DIV(0, "div_clkout_cpu" , "mout_clkout_cpu" , CLKOUT_CMU_CPU, 8, 6), |
614 | |
615 | DIV(0, "div_fimc0" , "mout_fimc0" , DIV_CAM, 0, 4), |
616 | DIV(0, "div_fimc1" , "mout_fimc1" , DIV_CAM, 4, 4), |
617 | DIV(0, "div_fimc2" , "mout_fimc2" , DIV_CAM, 8, 4), |
618 | DIV(0, "div_fimc3" , "mout_fimc3" , DIV_CAM, 12, 4), |
619 | DIV(0, "div_cam0" , "mout_cam0" , DIV_CAM, 16, 4), |
620 | DIV(0, "div_cam1" , "mout_cam1" , DIV_CAM, 20, 4), |
621 | DIV(0, "div_csis0" , "mout_csis0" , DIV_CAM, 24, 4), |
622 | DIV(0, "div_csis1" , "mout_csis1" , DIV_CAM, 28, 4), |
623 | DIV(CLK_SCLK_MFC, "sclk_mfc" , "mout_mfc" , DIV_MFC, 0, 4), |
624 | DIV(CLK_SCLK_G3D, "sclk_g3d" , "mout_g3d" , DIV_G3D, 0, 4), |
625 | DIV(0, "div_fimd0" , "mout_fimd0" , DIV_LCD0, 0, 4), |
626 | DIV(0, "div_mipi0" , "mout_mipi0" , DIV_LCD0, 16, 4), |
627 | DIV(0, "div_audio0" , "mout_audio0" , DIV_MAUDIO, 0, 4), |
628 | DIV(CLK_SCLK_PCM0, "sclk_pcm0" , "sclk_audio0" , DIV_MAUDIO, 4, 8), |
629 | DIV(0, "div_mmc0" , "mout_mmc0" , DIV_FSYS1, 0, 4), |
630 | DIV(0, "div_mmc1" , "mout_mmc1" , DIV_FSYS1, 16, 4), |
631 | DIV(0, "div_mmc2" , "mout_mmc2" , DIV_FSYS2, 0, 4), |
632 | DIV(0, "div_mmc3" , "mout_mmc3" , DIV_FSYS2, 16, 4), |
633 | DIV(CLK_SCLK_PIXEL, "sclk_pixel" , "sclk_vpll" , DIV_TV, 0, 4), |
634 | DIV(CLK_ACLK100, "aclk100" , "mout_aclk100" , DIV_TOP, 4, 4), |
635 | DIV(CLK_ACLK160, "aclk160" , "mout_aclk160" , DIV_TOP, 8, 3), |
636 | DIV(CLK_ACLK133, "aclk133" , "mout_aclk133" , DIV_TOP, 12, 3), |
637 | DIV(0, "div_onenand" , "mout_onenand1" , DIV_TOP, 16, 3), |
638 | DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus" , "sclk_epll" , DIV_PERIL3, 4, 4), |
639 | DIV(CLK_SCLK_PCM1, "sclk_pcm1" , "sclk_audio1" , DIV_PERIL4, 4, 8), |
640 | DIV(CLK_SCLK_PCM2, "sclk_pcm2" , "sclk_audio2" , DIV_PERIL4, 20, 8), |
641 | DIV(CLK_SCLK_I2S1, "sclk_i2s1" , "sclk_audio1" , DIV_PERIL5, 0, 6), |
642 | DIV(CLK_SCLK_I2S2, "sclk_i2s2" , "sclk_audio2" , DIV_PERIL5, 8, 6), |
643 | DIV(0, "div_mmc4" , "mout_mmc4" , DIV_FSYS3, 0, 4), |
644 | DIV_F(0, "div_mmc_pre4" , "div_mmc4" , DIV_FSYS3, 8, 8, |
645 | CLK_SET_RATE_PARENT, 0), |
646 | DIV(0, "div_uart0" , "mout_uart0" , DIV_PERIL0, 0, 4), |
647 | DIV(0, "div_uart1" , "mout_uart1" , DIV_PERIL0, 4, 4), |
648 | DIV(0, "div_uart2" , "mout_uart2" , DIV_PERIL0, 8, 4), |
649 | DIV(0, "div_uart3" , "mout_uart3" , DIV_PERIL0, 12, 4), |
650 | DIV(0, "div_uart4" , "mout_uart4" , DIV_PERIL0, 16, 4), |
651 | DIV(0, "div_spi0" , "mout_spi0" , DIV_PERIL1, 0, 4), |
652 | DIV(0, "div_spi_pre0" , "div_spi0" , DIV_PERIL1, 8, 8), |
653 | DIV(0, "div_spi1" , "mout_spi1" , DIV_PERIL1, 16, 4), |
654 | DIV(0, "div_spi_pre1" , "div_spi1" , DIV_PERIL1, 24, 8), |
655 | DIV(0, "div_spi2" , "mout_spi2" , DIV_PERIL2, 0, 4), |
656 | DIV(0, "div_spi_pre2" , "div_spi2" , DIV_PERIL2, 8, 8), |
657 | DIV(0, "div_audio1" , "mout_audio1" , DIV_PERIL4, 0, 4), |
658 | DIV(0, "div_audio2" , "mout_audio2" , DIV_PERIL4, 16, 4), |
659 | DIV(CLK_SCLK_APLL, "sclk_apll" , "mout_apll" , DIV_CPU0, 24, 3), |
660 | DIV_F(0, "div_mipi_pre0" , "div_mipi0" , DIV_LCD0, 20, 4, |
661 | CLK_SET_RATE_PARENT, 0), |
662 | DIV_F(0, "div_mmc_pre0" , "div_mmc0" , DIV_FSYS1, 8, 8, |
663 | CLK_SET_RATE_PARENT, 0), |
664 | DIV_F(0, "div_mmc_pre1" , "div_mmc1" , DIV_FSYS1, 24, 8, |
665 | CLK_SET_RATE_PARENT, 0), |
666 | DIV_F(0, "div_mmc_pre2" , "div_mmc2" , DIV_FSYS2, 8, 8, |
667 | CLK_SET_RATE_PARENT, 0), |
668 | DIV_F(0, "div_mmc_pre3" , "div_mmc3" , DIV_FSYS2, 24, 8, |
669 | CLK_SET_RATE_PARENT, 0), |
670 | DIV(0, "div_clkout_top" , "mout_clkout_top" , CLKOUT_CMU_TOP, 8, 6), |
671 | |
672 | DIV(CLK_DIV_ACP, "div_acp" , "mout_dmc_bus" , DIV_DMC0, 0, 3), |
673 | DIV(0, "div_acp_pclk" , "div_acp" , DIV_DMC0, 4, 3), |
674 | DIV(0, "div_dphy" , "mout_dphy" , DIV_DMC0, 8, 3), |
675 | DIV(CLK_DIV_DMC, "div_dmc" , "mout_dmc_bus" , DIV_DMC0, 12, 3), |
676 | DIV(0, "div_dmcd" , "div_dmc" , DIV_DMC0, 16, 3), |
677 | DIV(0, "div_dmcp" , "div_dmcd" , DIV_DMC0, 20, 3), |
678 | DIV(0, "div_pwi" , "mout_pwi" , DIV_DMC1, 8, 4), |
679 | DIV(0, "div_clkout_dmc" , "mout_clkout_dmc" , CLKOUT_CMU_DMC, 8, 6), |
680 | }; |
681 | |
682 | /* list of divider clocks supported in exynos4210 soc */ |
683 | static const struct samsung_div_clock exynos4210_div_clks[] __initconst = { |
684 | DIV(CLK_ACLK200, "aclk200" , "mout_aclk200" , DIV_TOP, 0, 3), |
685 | DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d" , "mout_g2d" , DIV_IMAGE, 0, 4), |
686 | DIV(0, "div_fimd1" , "mout_fimd1" , E4210_DIV_LCD1, 0, 4), |
687 | DIV(0, "div_mipi1" , "mout_mipi1" , E4210_DIV_LCD1, 16, 4), |
688 | DIV(0, "div_sata" , "mout_sata" , DIV_FSYS0, 20, 4), |
689 | DIV_F(0, "div_mipi_pre1" , "div_mipi1" , E4210_DIV_LCD1, 20, 4, |
690 | CLK_SET_RATE_PARENT, 0), |
691 | }; |
692 | |
693 | /* list of divider clocks supported in exynos4x12 soc */ |
694 | static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { |
695 | DIV(0, "div_mdnie0" , "mout_mdnie0" , DIV_LCD0, 4, 4), |
696 | DIV(0, "div_mdnie_pwm0" , "mout_mdnie_pwm0" , DIV_LCD0, 8, 4), |
697 | DIV(0, "div_mdnie_pwm_pre0" , "div_mdnie_pwm0" , DIV_LCD0, 12, 4), |
698 | DIV(0, "div_mipihsi" , "mout_mipihsi" , DIV_FSYS0, 20, 4), |
699 | DIV(0, "div_jpeg" , "mout_jpeg" , E4X12_DIV_CAM1, 0, 4), |
700 | DIV(CLK_DIV_ACLK200, "div_aclk200" , "mout_aclk200" , DIV_TOP, 0, 3), |
701 | DIV(0, "div_aclk266_gps" , "mout_aclk266_gps" , DIV_TOP, 20, 3), |
702 | DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp" , "mout_aclk400_mcuisp" , |
703 | DIV_TOP, 24, 3), |
704 | DIV(0, "div_pwm_isp" , "mout_pwm_isp" , E4X12_DIV_ISP, 0, 4), |
705 | DIV(0, "div_spi0_isp" , "mout_spi0_isp" , E4X12_DIV_ISP, 4, 4), |
706 | DIV(0, "div_spi0_isp_pre" , "div_spi0_isp" , E4X12_DIV_ISP, 8, 8), |
707 | DIV(0, "div_spi1_isp" , "mout_spi1_isp" , E4X12_DIV_ISP, 16, 4), |
708 | DIV(0, "div_spi1_isp_pre" , "div_spi1_isp" , E4X12_DIV_ISP, 20, 8), |
709 | DIV(0, "div_uart_isp" , "mout_uart_isp" , E4X12_DIV_ISP, 28, 4), |
710 | DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d" , "mout_g2d" , DIV_DMC1, 0, 4), |
711 | DIV(CLK_DIV_C2C, "div_c2c" , "mout_c2c" , DIV_DMC1, 4, 3), |
712 | DIV(0, "div_c2c_aclk" , "div_c2c" , DIV_DMC1, 12, 3), |
713 | }; |
714 | |
715 | /* list of gate clocks supported in all exynos4 soc's */ |
716 | static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { |
717 | GATE(CLK_PPMULEFT, "ppmuleft" , "aclk200" , GATE_IP_LEFTBUS, 1, 0, 0), |
718 | GATE(CLK_PPMURIGHT, "ppmuright" , "aclk200" , GATE_IP_RIGHTBUS, 1, 0, 0), |
719 | GATE(CLK_SCLK_HDMI, "sclk_hdmi" , "mout_hdmi" , SRC_MASK_TV, 0, 0, 0), |
720 | GATE(CLK_SCLK_SPDIF, "sclk_spdif" , "mout_spdif" , SRC_MASK_PERIL1, 8, 0, |
721 | 0), |
722 | GATE(CLK_JPEG, "jpeg" , "aclk160" , GATE_IP_CAM, 6, 0, 0), |
723 | GATE(CLK_MIE0, "mie0" , "aclk160" , GATE_IP_LCD0, 1, 0, 0), |
724 | GATE(CLK_DSIM0, "dsim0" , "aclk160" , GATE_IP_LCD0, 3, 0, 0), |
725 | GATE(CLK_FIMD1, "fimd1" , "aclk160" , E4210_GATE_IP_LCD1, 0, 0, 0), |
726 | GATE(CLK_MIE1, "mie1" , "aclk160" , E4210_GATE_IP_LCD1, 1, 0, 0), |
727 | GATE(CLK_DSIM1, "dsim1" , "aclk160" , E4210_GATE_IP_LCD1, 3, 0, 0), |
728 | GATE(CLK_SMMU_FIMD1, "smmu_fimd1" , "aclk160" , E4210_GATE_IP_LCD1, 4, 0, |
729 | 0), |
730 | GATE(CLK_TSI, "tsi" , "aclk133" , GATE_IP_FSYS, 4, 0, 0), |
731 | GATE(CLK_SROMC, "sromc" , "aclk133" , GATE_IP_FSYS, 11, 0, 0), |
732 | GATE(CLK_G3D, "g3d" , "aclk200" , GATE_IP_G3D, 0, 0, 0), |
733 | GATE(CLK_PPMUG3D, "ppmug3d" , "aclk200" , GATE_IP_G3D, 1, 0, 0), |
734 | GATE(CLK_USB_DEVICE, "usb_device" , "aclk133" , GATE_IP_FSYS, 13, 0, 0), |
735 | GATE(CLK_ONENAND, "onenand" , "aclk133" , GATE_IP_FSYS, 15, 0, 0), |
736 | GATE(CLK_NFCON, "nfcon" , "aclk133" , GATE_IP_FSYS, 16, 0, 0), |
737 | GATE(CLK_GPS, "gps" , "aclk133" , GATE_IP_GPS, 0, 0, 0), |
738 | GATE(CLK_SMMU_GPS, "smmu_gps" , "aclk133" , GATE_IP_GPS, 1, 0, 0), |
739 | GATE(CLK_PPMUGPS, "ppmugps" , "aclk200" , GATE_IP_GPS, 2, 0, 0), |
740 | GATE(CLK_SLIMBUS, "slimbus" , "aclk100" , GATE_IP_PERIL, 25, 0, 0), |
741 | GATE(CLK_SCLK_CAM0, "sclk_cam0" , "div_cam0" , GATE_SCLK_CAM, 4, |
742 | CLK_SET_RATE_PARENT, 0), |
743 | GATE(CLK_SCLK_CAM1, "sclk_cam1" , "div_cam1" , GATE_SCLK_CAM, 5, |
744 | CLK_SET_RATE_PARENT, 0), |
745 | GATE(CLK_SCLK_MIPI0, "sclk_mipi0" , "div_mipi_pre0" , |
746 | SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), |
747 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0" , "div_audio0" , SRC_MASK_MAUDIO, 0, |
748 | CLK_SET_RATE_PARENT, 0), |
749 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1" , "div_audio1" , SRC_MASK_PERIL1, 0, |
750 | CLK_SET_RATE_PARENT, 0), |
751 | GATE(CLK_VP, "vp" , "aclk160" , GATE_IP_TV, 0, 0, 0), |
752 | GATE(CLK_MIXER, "mixer" , "aclk160" , GATE_IP_TV, 1, 0, 0), |
753 | GATE(CLK_HDMI, "hdmi" , "aclk160" , GATE_IP_TV, 3, 0, 0), |
754 | GATE(CLK_PWM, "pwm" , "aclk100" , GATE_IP_PERIL, 24, 0, 0), |
755 | GATE(CLK_SDMMC4, "sdmmc4" , "aclk133" , GATE_IP_FSYS, 9, 0, 0), |
756 | GATE(CLK_USB_HOST, "usb_host" , "aclk133" , GATE_IP_FSYS, 12, 0, 0), |
757 | GATE(CLK_SCLK_FIMC0, "sclk_fimc0" , "div_fimc0" , SRC_MASK_CAM, 0, |
758 | CLK_SET_RATE_PARENT, 0), |
759 | GATE(CLK_SCLK_FIMC1, "sclk_fimc1" , "div_fimc1" , SRC_MASK_CAM, 4, |
760 | CLK_SET_RATE_PARENT, 0), |
761 | GATE(CLK_SCLK_FIMC2, "sclk_fimc2" , "div_fimc2" , SRC_MASK_CAM, 8, |
762 | CLK_SET_RATE_PARENT, 0), |
763 | GATE(CLK_SCLK_FIMC3, "sclk_fimc3" , "div_fimc3" , SRC_MASK_CAM, 12, |
764 | CLK_SET_RATE_PARENT, 0), |
765 | GATE(CLK_SCLK_CSIS0, "sclk_csis0" , "div_csis0" , SRC_MASK_CAM, 24, |
766 | CLK_SET_RATE_PARENT, 0), |
767 | GATE(CLK_SCLK_CSIS1, "sclk_csis1" , "div_csis1" , SRC_MASK_CAM, 28, |
768 | CLK_SET_RATE_PARENT, 0), |
769 | GATE(CLK_SCLK_FIMD0, "sclk_fimd0" , "div_fimd0" , SRC_MASK_LCD0, 0, |
770 | CLK_SET_RATE_PARENT, 0), |
771 | GATE(CLK_SCLK_MMC0, "sclk_mmc0" , "div_mmc_pre0" , SRC_MASK_FSYS, 0, |
772 | CLK_SET_RATE_PARENT, 0), |
773 | GATE(CLK_SCLK_MMC1, "sclk_mmc1" , "div_mmc_pre1" , SRC_MASK_FSYS, 4, |
774 | CLK_SET_RATE_PARENT, 0), |
775 | GATE(CLK_SCLK_MMC2, "sclk_mmc2" , "div_mmc_pre2" , SRC_MASK_FSYS, 8, |
776 | CLK_SET_RATE_PARENT, 0), |
777 | GATE(CLK_SCLK_MMC3, "sclk_mmc3" , "div_mmc_pre3" , SRC_MASK_FSYS, 12, |
778 | CLK_SET_RATE_PARENT, 0), |
779 | GATE(CLK_SCLK_MMC4, "sclk_mmc4" , "div_mmc_pre4" , SRC_MASK_FSYS, 16, |
780 | CLK_SET_RATE_PARENT, 0), |
781 | GATE(CLK_SCLK_UART0, "uclk0" , "div_uart0" , SRC_MASK_PERIL0, 0, |
782 | CLK_SET_RATE_PARENT, 0), |
783 | GATE(CLK_SCLK_UART1, "uclk1" , "div_uart1" , SRC_MASK_PERIL0, 4, |
784 | CLK_SET_RATE_PARENT, 0), |
785 | GATE(CLK_SCLK_UART2, "uclk2" , "div_uart2" , SRC_MASK_PERIL0, 8, |
786 | CLK_SET_RATE_PARENT, 0), |
787 | GATE(CLK_SCLK_UART3, "uclk3" , "div_uart3" , SRC_MASK_PERIL0, 12, |
788 | CLK_SET_RATE_PARENT, 0), |
789 | GATE(CLK_SCLK_UART4, "uclk4" , "div_uart4" , SRC_MASK_PERIL0, 16, |
790 | CLK_SET_RATE_PARENT, 0), |
791 | GATE(CLK_SCLK_AUDIO2, "sclk_audio2" , "div_audio2" , SRC_MASK_PERIL1, 4, |
792 | CLK_SET_RATE_PARENT, 0), |
793 | GATE(CLK_SCLK_SPI0, "sclk_spi0" , "div_spi_pre0" , SRC_MASK_PERIL1, 16, |
794 | CLK_SET_RATE_PARENT, 0), |
795 | GATE(CLK_SCLK_SPI1, "sclk_spi1" , "div_spi_pre1" , SRC_MASK_PERIL1, 20, |
796 | CLK_SET_RATE_PARENT, 0), |
797 | GATE(CLK_SCLK_SPI2, "sclk_spi2" , "div_spi_pre2" , SRC_MASK_PERIL1, 24, |
798 | CLK_SET_RATE_PARENT, 0), |
799 | GATE(CLK_FIMC0, "fimc0" , "aclk160" , GATE_IP_CAM, 0, |
800 | 0, 0), |
801 | GATE(CLK_FIMC1, "fimc1" , "aclk160" , GATE_IP_CAM, 1, |
802 | 0, 0), |
803 | GATE(CLK_FIMC2, "fimc2" , "aclk160" , GATE_IP_CAM, 2, |
804 | 0, 0), |
805 | GATE(CLK_FIMC3, "fimc3" , "aclk160" , GATE_IP_CAM, 3, |
806 | 0, 0), |
807 | GATE(CLK_CSIS0, "csis0" , "aclk160" , GATE_IP_CAM, 4, |
808 | 0, 0), |
809 | GATE(CLK_CSIS1, "csis1" , "aclk160" , GATE_IP_CAM, 5, |
810 | 0, 0), |
811 | GATE(CLK_SMMU_FIMC0, "smmu_fimc0" , "aclk160" , GATE_IP_CAM, 7, |
812 | 0, 0), |
813 | GATE(CLK_SMMU_FIMC1, "smmu_fimc1" , "aclk160" , GATE_IP_CAM, 8, |
814 | 0, 0), |
815 | GATE(CLK_SMMU_FIMC2, "smmu_fimc2" , "aclk160" , GATE_IP_CAM, 9, |
816 | 0, 0), |
817 | GATE(CLK_SMMU_FIMC3, "smmu_fimc3" , "aclk160" , GATE_IP_CAM, 10, |
818 | 0, 0), |
819 | GATE(CLK_SMMU_JPEG, "smmu_jpeg" , "aclk160" , GATE_IP_CAM, 11, |
820 | 0, 0), |
821 | GATE(CLK_PPMUCAMIF, "ppmucamif" , "aclk160" , GATE_IP_CAM, 16, 0, 0), |
822 | GATE(CLK_PIXELASYNCM0, "pxl_async0" , "aclk160" , GATE_IP_CAM, 17, 0, 0), |
823 | GATE(CLK_PIXELASYNCM1, "pxl_async1" , "aclk160" , GATE_IP_CAM, 18, 0, 0), |
824 | GATE(CLK_SMMU_TV, "smmu_tv" , "aclk160" , GATE_IP_TV, 4, |
825 | 0, 0), |
826 | GATE(CLK_PPMUTV, "ppmutv" , "aclk160" , GATE_IP_TV, 5, 0, 0), |
827 | GATE(CLK_MFC, "mfc" , "aclk100" , GATE_IP_MFC, 0, 0, 0), |
828 | GATE(CLK_SMMU_MFCL, "smmu_mfcl" , "aclk100" , GATE_IP_MFC, 1, |
829 | 0, 0), |
830 | GATE(CLK_SMMU_MFCR, "smmu_mfcr" , "aclk100" , GATE_IP_MFC, 2, |
831 | 0, 0), |
832 | GATE(CLK_PPMUMFC_L, "ppmumfc_l" , "aclk100" , GATE_IP_MFC, 3, 0, 0), |
833 | GATE(CLK_PPMUMFC_R, "ppmumfc_r" , "aclk100" , GATE_IP_MFC, 4, 0, 0), |
834 | GATE(CLK_FIMD0, "fimd0" , "aclk160" , GATE_IP_LCD0, 0, |
835 | 0, 0), |
836 | GATE(CLK_SMMU_FIMD0, "smmu_fimd0" , "aclk160" , GATE_IP_LCD0, 4, |
837 | 0, 0), |
838 | GATE(CLK_PPMULCD0, "ppmulcd0" , "aclk160" , GATE_IP_LCD0, 5, 0, 0), |
839 | GATE(CLK_PDMA0, "pdma0" , "aclk133" , GATE_IP_FSYS, 0, |
840 | 0, 0), |
841 | GATE(CLK_PDMA1, "pdma1" , "aclk133" , GATE_IP_FSYS, 1, |
842 | 0, 0), |
843 | GATE(CLK_SDMMC0, "sdmmc0" , "aclk133" , GATE_IP_FSYS, 5, |
844 | 0, 0), |
845 | GATE(CLK_SDMMC1, "sdmmc1" , "aclk133" , GATE_IP_FSYS, 6, |
846 | 0, 0), |
847 | GATE(CLK_SDMMC2, "sdmmc2" , "aclk133" , GATE_IP_FSYS, 7, |
848 | 0, 0), |
849 | GATE(CLK_SDMMC3, "sdmmc3" , "aclk133" , GATE_IP_FSYS, 8, |
850 | 0, 0), |
851 | GATE(CLK_PPMUFILE, "ppmufile" , "aclk133" , GATE_IP_FSYS, 17, 0, 0), |
852 | GATE(CLK_UART0, "uart0" , "aclk100" , GATE_IP_PERIL, 0, |
853 | 0, 0), |
854 | GATE(CLK_UART1, "uart1" , "aclk100" , GATE_IP_PERIL, 1, |
855 | 0, 0), |
856 | GATE(CLK_UART2, "uart2" , "aclk100" , GATE_IP_PERIL, 2, |
857 | 0, 0), |
858 | GATE(CLK_UART3, "uart3" , "aclk100" , GATE_IP_PERIL, 3, |
859 | 0, 0), |
860 | GATE(CLK_UART4, "uart4" , "aclk100" , GATE_IP_PERIL, 4, |
861 | 0, 0), |
862 | GATE(CLK_I2C0, "i2c0" , "aclk100" , GATE_IP_PERIL, 6, |
863 | 0, 0), |
864 | GATE(CLK_I2C1, "i2c1" , "aclk100" , GATE_IP_PERIL, 7, |
865 | 0, 0), |
866 | GATE(CLK_I2C2, "i2c2" , "aclk100" , GATE_IP_PERIL, 8, |
867 | 0, 0), |
868 | GATE(CLK_I2C3, "i2c3" , "aclk100" , GATE_IP_PERIL, 9, |
869 | 0, 0), |
870 | GATE(CLK_I2C4, "i2c4" , "aclk100" , GATE_IP_PERIL, 10, |
871 | 0, 0), |
872 | GATE(CLK_I2C5, "i2c5" , "aclk100" , GATE_IP_PERIL, 11, |
873 | 0, 0), |
874 | GATE(CLK_I2C6, "i2c6" , "aclk100" , GATE_IP_PERIL, 12, |
875 | 0, 0), |
876 | GATE(CLK_I2C7, "i2c7" , "aclk100" , GATE_IP_PERIL, 13, |
877 | 0, 0), |
878 | GATE(CLK_I2C_HDMI, "i2c-hdmi" , "aclk100" , GATE_IP_PERIL, 14, |
879 | 0, 0), |
880 | GATE(CLK_SPI0, "spi0" , "aclk100" , GATE_IP_PERIL, 16, |
881 | 0, 0), |
882 | GATE(CLK_SPI1, "spi1" , "aclk100" , GATE_IP_PERIL, 17, |
883 | 0, 0), |
884 | GATE(CLK_SPI2, "spi2" , "aclk100" , GATE_IP_PERIL, 18, |
885 | 0, 0), |
886 | GATE(CLK_I2S1, "i2s1" , "aclk100" , GATE_IP_PERIL, 20, |
887 | 0, 0), |
888 | GATE(CLK_I2S2, "i2s2" , "aclk100" , GATE_IP_PERIL, 21, |
889 | 0, 0), |
890 | GATE(CLK_PCM1, "pcm1" , "aclk100" , GATE_IP_PERIL, 22, |
891 | 0, 0), |
892 | GATE(CLK_PCM2, "pcm2" , "aclk100" , GATE_IP_PERIL, 23, |
893 | 0, 0), |
894 | GATE(CLK_SPDIF, "spdif" , "aclk100" , GATE_IP_PERIL, 26, |
895 | 0, 0), |
896 | GATE(CLK_AC97, "ac97" , "aclk100" , GATE_IP_PERIL, 27, |
897 | 0, 0), |
898 | GATE(CLK_SSS, "sss" , "aclk133" , GATE_IP_DMC, 4, 0, 0), |
899 | GATE(CLK_PPMUDMC0, "ppmudmc0" , "aclk133" , GATE_IP_DMC, 8, 0, 0), |
900 | GATE(CLK_PPMUDMC1, "ppmudmc1" , "aclk133" , GATE_IP_DMC, 9, 0, 0), |
901 | GATE(CLK_PPMUCPU, "ppmucpu" , "aclk133" , GATE_IP_DMC, 10, 0, 0), |
902 | GATE(CLK_PPMUACP, "ppmuacp" , "aclk133" , GATE_IP_DMC, 16, 0, 0), |
903 | |
904 | GATE(CLK_OUT_LEFTBUS, "clkout_leftbus" , "div_clkout_leftbus" , |
905 | CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0), |
906 | GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus" , "div_clkout_rightbus" , |
907 | CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0), |
908 | GATE(CLK_OUT_TOP, "clkout_top" , "div_clkout_top" , |
909 | CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0), |
910 | GATE(CLK_OUT_DMC, "clkout_dmc" , "div_clkout_dmc" , |
911 | CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0), |
912 | GATE(CLK_OUT_CPU, "clkout_cpu" , "div_clkout_cpu" , |
913 | CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0), |
914 | }; |
915 | |
916 | /* list of gate clocks supported in exynos4210 soc */ |
917 | static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { |
918 | GATE(CLK_TVENC, "tvenc" , "aclk160" , GATE_IP_TV, 2, 0, 0), |
919 | GATE(CLK_G2D, "g2d" , "aclk200" , E4210_GATE_IP_IMAGE, 0, 0, 0), |
920 | GATE(CLK_ROTATOR, "rotator" , "aclk200" , E4210_GATE_IP_IMAGE, 1, 0, 0), |
921 | GATE(CLK_MDMA, "mdma" , "aclk200" , E4210_GATE_IP_IMAGE, 2, 0, 0), |
922 | GATE(CLK_SMMU_G2D, "smmu_g2d" , "aclk200" , E4210_GATE_IP_IMAGE, 3, 0, 0), |
923 | GATE(CLK_SMMU_MDMA, "smmu_mdma" , "aclk200" , E4210_GATE_IP_IMAGE, 5, 0, |
924 | 0), |
925 | GATE(CLK_PPMUIMAGE, "ppmuimage" , "aclk200" , E4210_GATE_IP_IMAGE, 9, 0, |
926 | 0), |
927 | GATE(CLK_PPMULCD1, "ppmulcd1" , "aclk160" , E4210_GATE_IP_LCD1, 5, 0, 0), |
928 | GATE(CLK_PCIE_PHY, "pcie_phy" , "aclk133" , GATE_IP_FSYS, 2, 0, 0), |
929 | GATE(CLK_SATA_PHY, "sata_phy" , "aclk133" , GATE_IP_FSYS, 3, 0, 0), |
930 | GATE(CLK_SATA, "sata" , "aclk133" , GATE_IP_FSYS, 10, 0, 0), |
931 | GATE(CLK_PCIE, "pcie" , "aclk133" , GATE_IP_FSYS, 14, 0, 0), |
932 | GATE(CLK_SMMU_PCIE, "smmu_pcie" , "aclk133" , GATE_IP_FSYS, 18, 0, 0), |
933 | GATE(CLK_MODEMIF, "modemif" , "aclk100" , GATE_IP_PERIL, 28, 0, 0), |
934 | GATE(CLK_CHIPID, "chipid" , "aclk100" , E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0), |
935 | GATE(CLK_SYSREG, "sysreg" , "aclk100" , E4210_GATE_IP_PERIR, 0, |
936 | CLK_IGNORE_UNUSED, 0), |
937 | GATE(CLK_HDMI_CEC, "hdmi_cec" , "aclk100" , E4210_GATE_IP_PERIR, 11, 0, |
938 | 0), |
939 | GATE(CLK_SMMU_ROTATOR, "smmu_rotator" , "aclk200" , |
940 | E4210_GATE_IP_IMAGE, 4, 0, 0), |
941 | GATE(CLK_SCLK_MIPI1, "sclk_mipi1" , "div_mipi_pre1" , |
942 | E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), |
943 | GATE(CLK_SCLK_SATA, "sclk_sata" , "div_sata" , |
944 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), |
945 | GATE(CLK_SCLK_MIXER, "sclk_mixer" , "mout_mixer" , SRC_MASK_TV, 4, 0, 0), |
946 | GATE(CLK_SCLK_DAC, "sclk_dac" , "mout_dac" , SRC_MASK_TV, 8, 0, 0), |
947 | GATE(CLK_TSADC, "tsadc" , "aclk100" , GATE_IP_PERIL, 15, |
948 | 0, 0), |
949 | GATE(CLK_MCT, "mct" , "aclk100" , E4210_GATE_IP_PERIR, 13, |
950 | 0, 0), |
951 | GATE(CLK_WDT, "watchdog" , "aclk100" , E4210_GATE_IP_PERIR, 14, |
952 | 0, 0), |
953 | GATE(CLK_RTC, "rtc" , "aclk100" , E4210_GATE_IP_PERIR, 15, |
954 | 0, 0), |
955 | GATE(CLK_KEYIF, "keyif" , "aclk100" , E4210_GATE_IP_PERIR, 16, |
956 | 0, 0), |
957 | GATE(CLK_SCLK_FIMD1, "sclk_fimd1" , "div_fimd1" , E4210_SRC_MASK_LCD1, 0, |
958 | CLK_SET_RATE_PARENT, 0), |
959 | GATE(CLK_TMU_APBIF, "tmu_apbif" , "aclk100" , E4210_GATE_IP_PERIR, 17, 0, |
960 | 0), |
961 | }; |
962 | |
963 | /* list of gate clocks supported in exynos4x12 soc */ |
964 | static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { |
965 | GATE(CLK_ASYNC_G3D, "async_g3d" , "aclk200" , GATE_IP_LEFTBUS, 6, 0, 0), |
966 | GATE(CLK_AUDSS, "audss" , "sclk_epll" , E4X12_GATE_IP_MAUDIO, 0, 0, 0), |
967 | GATE(CLK_MDNIE0, "mdnie0" , "aclk160" , GATE_IP_LCD0, 2, 0, 0), |
968 | GATE(CLK_ROTATOR, "rotator" , "aclk200" , E4X12_GATE_IP_IMAGE, 1, 0, 0), |
969 | GATE(CLK_MDMA, "mdma" , "aclk200" , E4X12_GATE_IP_IMAGE, 2, 0, 0), |
970 | GATE(CLK_SMMU_MDMA, "smmu_mdma" , "aclk200" , E4X12_GATE_IP_IMAGE, 5, 0, |
971 | 0), |
972 | GATE(CLK_PPMUIMAGE, "ppmuimage" , "aclk200" , E4X12_GATE_IP_IMAGE, 9, 0, |
973 | 0), |
974 | GATE(CLK_TSADC, "tsadc" , "aclk133" , E4X12_GATE_BUS_FSYS1, 16, 0, 0), |
975 | GATE(CLK_MIPI_HSI, "mipi_hsi" , "aclk133" , GATE_IP_FSYS, 10, 0, 0), |
976 | GATE(CLK_CHIPID, "chipid" , "aclk100" , E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0), |
977 | GATE(CLK_SYSREG, "sysreg" , "aclk100" , E4X12_GATE_IP_PERIR, 1, |
978 | CLK_IGNORE_UNUSED, 0), |
979 | GATE(CLK_HDMI_CEC, "hdmi_cec" , "aclk100" , E4X12_GATE_IP_PERIR, 11, 0, |
980 | 0), |
981 | GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0" , "div_mdnie0" , |
982 | SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), |
983 | GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0" , "div_mdnie_pwm_pre0" , |
984 | SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), |
985 | GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi" , "div_mipihsi" , |
986 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), |
987 | GATE(CLK_SMMU_ROTATOR, "smmu_rotator" , "aclk200" , |
988 | E4X12_GATE_IP_IMAGE, 4, 0, 0), |
989 | GATE(CLK_MCT, "mct" , "aclk100" , E4X12_GATE_IP_PERIR, 13, |
990 | 0, 0), |
991 | GATE(CLK_RTC, "rtc" , "aclk100" , E4X12_GATE_IP_PERIR, 15, |
992 | 0, 0), |
993 | GATE(CLK_KEYIF, "keyif" , "aclk100" , E4X12_GATE_IP_PERIR, 16, 0, 0), |
994 | GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk" , "div_pwm_isp" , |
995 | E4X12_GATE_IP_ISP, 0, 0, 0), |
996 | GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk" , "div_spi0_isp_pre" , |
997 | E4X12_GATE_IP_ISP, 1, 0, 0), |
998 | GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk" , "div_spi1_isp_pre" , |
999 | E4X12_GATE_IP_ISP, 2, 0, 0), |
1000 | GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk" , "div_uart_isp" , |
1001 | E4X12_GATE_IP_ISP, 3, 0, 0), |
1002 | GATE(CLK_WDT, "watchdog" , "aclk100" , E4X12_GATE_IP_PERIR, 14, 0, 0), |
1003 | GATE(CLK_PCM0, "pcm0" , "aclk100" , E4X12_GATE_IP_MAUDIO, 2, |
1004 | 0, 0), |
1005 | GATE(CLK_I2S0, "i2s0" , "aclk100" , E4X12_GATE_IP_MAUDIO, 3, |
1006 | 0, 0), |
1007 | GATE(CLK_G2D, "g2d" , "aclk200" , GATE_IP_DMC, 23, 0, 0), |
1008 | GATE(CLK_SMMU_G2D, "smmu_g2d" , "aclk200" , GATE_IP_DMC, 24, 0, 0), |
1009 | GATE(CLK_TMU_APBIF, "tmu_apbif" , "aclk100" , E4X12_GATE_IP_PERIR, 17, 0, |
1010 | 0), |
1011 | }; |
1012 | |
1013 | /* |
1014 | * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit |
1015 | * resides in chipid register space, outside of the clock controller memory |
1016 | * mapped space. So to determine the parent of fin_pll clock, the chipid |
1017 | * controller is first remapped and the value of XOM[0] bit is read to |
1018 | * determine the parent clock. |
1019 | */ |
1020 | static unsigned long __init exynos4_get_xom(void) |
1021 | { |
1022 | unsigned long xom = 0; |
1023 | void __iomem *chipid_base; |
1024 | struct device_node *np; |
1025 | |
1026 | np = of_find_compatible_node(NULL, NULL, compat: "samsung,exynos4210-chipid" ); |
1027 | if (np) { |
1028 | chipid_base = of_iomap(node: np, index: 0); |
1029 | |
1030 | if (chipid_base) |
1031 | xom = readl(addr: chipid_base + 8); |
1032 | |
1033 | iounmap(addr: chipid_base); |
1034 | of_node_put(node: np); |
1035 | } |
1036 | |
1037 | return xom; |
1038 | } |
1039 | |
1040 | static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) |
1041 | { |
1042 | struct samsung_fixed_rate_clock fclk; |
1043 | struct clk *clk; |
1044 | unsigned long finpll_f = 24000000; |
1045 | char *parent_name; |
1046 | unsigned int xom = exynos4_get_xom(); |
1047 | |
1048 | parent_name = xom & 1 ? "xusbxti" : "xxti" ; |
1049 | clk = clk_get(NULL, id: parent_name); |
1050 | if (IS_ERR(ptr: clk)) { |
1051 | pr_err("%s: failed to lookup parent clock %s, assuming " |
1052 | "fin_pll clock frequency is 24MHz\n" , __func__, |
1053 | parent_name); |
1054 | } else { |
1055 | finpll_f = clk_get_rate(clk); |
1056 | } |
1057 | |
1058 | fclk.id = CLK_FIN_PLL; |
1059 | fclk.name = "fin_pll" ; |
1060 | fclk.parent_name = NULL; |
1061 | fclk.flags = 0; |
1062 | fclk.fixed_rate = finpll_f; |
1063 | samsung_clk_register_fixed_rate(ctx, clk_list: &fclk, nr_clk: 1); |
1064 | |
1065 | } |
1066 | |
1067 | static const struct of_device_id ext_clk_match[] __initconst = { |
1068 | { .compatible = "samsung,clock-xxti" , .data = (void *)0, }, |
1069 | { .compatible = "samsung,clock-xusbxti" , .data = (void *)1, }, |
1070 | {}, |
1071 | }; |
1072 | |
1073 | /* PLLs PMS values */ |
1074 | static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { |
1075 | PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28), |
1076 | PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28), |
1077 | PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28), |
1078 | PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13), |
1079 | PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13), |
1080 | PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5), |
1081 | PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28), |
1082 | PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28), |
1083 | PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28), |
1084 | { /* sentinel */ } |
1085 | }; |
1086 | |
1087 | static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { |
1088 | PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0), |
1089 | PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0), |
1090 | PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0), |
1091 | PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1), |
1092 | PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1), |
1093 | PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0), |
1094 | PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0), |
1095 | { /* sentinel */ } |
1096 | }; |
1097 | |
1098 | static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { |
1099 | PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0), |
1100 | PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1), |
1101 | PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1), |
1102 | PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0), |
1103 | PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0), |
1104 | { /* sentinel */ } |
1105 | }; |
1106 | |
1107 | static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { |
1108 | PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0), |
1109 | PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), |
1110 | PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), |
1111 | PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), |
1112 | PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), |
1113 | PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0), |
1114 | PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0), |
1115 | PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0), |
1116 | PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0), |
1117 | PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0), |
1118 | PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), |
1119 | PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1), |
1120 | PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1), |
1121 | PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1), |
1122 | PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2), |
1123 | PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2), |
1124 | { /* sentinel */ } |
1125 | }; |
1126 | |
1127 | static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { |
1128 | PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690), |
1129 | PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0), |
1130 | PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381), |
1131 | PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0), |
1132 | PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710), |
1133 | PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762), |
1134 | PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961), |
1135 | PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381), |
1136 | { /* sentinel */ } |
1137 | }; |
1138 | |
1139 | static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { |
1140 | PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384), |
1141 | PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0), |
1142 | PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0), |
1143 | PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0), |
1144 | PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0), |
1145 | PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024), |
1146 | PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024), |
1147 | { /* sentinel */ } |
1148 | }; |
1149 | |
1150 | static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { |
1151 | [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll" , "fin_pll" , |
1152 | APLL_LOCK, APLL_CON0, NULL), |
1153 | [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll" , "fin_pll" , |
1154 | E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL), |
1155 | [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll" , "fin_pll" , |
1156 | EPLL_LOCK, EPLL_CON0, NULL), |
1157 | [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll" , "mout_vpllsrc" , |
1158 | VPLL_LOCK, VPLL_CON0, NULL), |
1159 | }; |
1160 | |
1161 | static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { |
1162 | [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll" , "fin_pll" , |
1163 | APLL_LOCK, APLL_CON0, NULL), |
1164 | [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll" , "fin_pll" , |
1165 | E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), |
1166 | [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll" , "fin_pll" , |
1167 | EPLL_LOCK, EPLL_CON0, NULL), |
1168 | [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll" , "fin_pll" , |
1169 | VPLL_LOCK, VPLL_CON0, NULL), |
1170 | }; |
1171 | |
1172 | static void __init exynos4x12_core_down_clock(void) |
1173 | { |
1174 | unsigned int tmp; |
1175 | |
1176 | /* |
1177 | * Enable arm clock down (in idle) and set arm divider |
1178 | * ratios in WFI/WFE state. |
1179 | */ |
1180 | tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | |
1181 | PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | |
1182 | PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | |
1183 | PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); |
1184 | /* On Exynos4412 enable it also on core 2 and 3 */ |
1185 | if (num_possible_cpus() == 4) |
1186 | tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | |
1187 | PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; |
1188 | writel_relaxed(tmp, reg_base + PWR_CTRL1); |
1189 | |
1190 | /* |
1191 | * Disable the clock up feature in case it was enabled by bootloader. |
1192 | */ |
1193 | writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); |
1194 | } |
1195 | |
1196 | #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ |
1197 | (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ |
1198 | ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) |
1199 | #define E4210_CPU_DIV1(hpm, copy) \ |
1200 | (((hpm) << 4) | ((copy) << 0)) |
1201 | |
1202 | static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { |
1203 | { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), }, |
1204 | { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), }, |
1205 | { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, |
1206 | { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, |
1207 | { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, |
1208 | { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), }, |
1209 | { 0 }, |
1210 | }; |
1211 | |
1212 | static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { |
1213 | { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, |
1214 | { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, |
1215 | { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, |
1216 | { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, |
1217 | { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, |
1218 | { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, |
1219 | { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, |
1220 | { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, |
1221 | { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, |
1222 | { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, |
1223 | { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, |
1224 | { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, |
1225 | { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, |
1226 | { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, |
1227 | { 0 }, |
1228 | }; |
1229 | |
1230 | #define E4412_CPU_DIV1(cores, hpm, copy) \ |
1231 | (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) |
1232 | |
1233 | static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { |
1234 | { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, |
1235 | { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, |
1236 | { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, |
1237 | { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, |
1238 | { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, |
1239 | { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, |
1240 | { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, |
1241 | { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, |
1242 | { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, |
1243 | { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, |
1244 | { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, |
1245 | { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, |
1246 | { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, |
1247 | { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, |
1248 | { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, |
1249 | { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, |
1250 | { 0 }, |
1251 | }; |
1252 | |
1253 | static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { |
1254 | CPU_CLK(CLK_ARM_CLK, "armclk" , CLK_MOUT_APLL, CLK_SCLK_MPLL, |
1255 | CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d), |
1256 | }; |
1257 | |
1258 | static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = { |
1259 | CPU_CLK(CLK_ARM_CLK, "armclk" , CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, |
1260 | CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d), |
1261 | }; |
1262 | |
1263 | static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = { |
1264 | CPU_CLK(CLK_ARM_CLK, "armclk" , CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, |
1265 | CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d), |
1266 | }; |
1267 | |
1268 | /* register exynos4 clocks */ |
1269 | static void __init exynos4_clk_init(struct device_node *np, |
1270 | enum exynos4_soc soc) |
1271 | { |
1272 | struct samsung_clk_provider *ctx; |
1273 | struct clk_hw **hws; |
1274 | |
1275 | exynos4_soc = soc; |
1276 | |
1277 | reg_base = of_iomap(node: np, index: 0); |
1278 | if (!reg_base) |
1279 | panic(fmt: "%s: failed to map registers\n" , __func__); |
1280 | |
1281 | ctx = samsung_clk_init(NULL, base: reg_base, CLKS_NR); |
1282 | hws = ctx->clk_data.hws; |
1283 | |
1284 | samsung_clk_of_register_fixed_ext(ctx, fixed_rate_clk: exynos4_fixed_rate_ext_clks, |
1285 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks), |
1286 | clk_matches: ext_clk_match); |
1287 | |
1288 | exynos4_clk_register_finpll(ctx); |
1289 | |
1290 | if (exynos4_soc == EXYNOS4210) { |
1291 | samsung_clk_register_mux(ctx, clk_list: exynos4210_mux_early, |
1292 | ARRAY_SIZE(exynos4210_mux_early)); |
1293 | |
1294 | if (clk_hw_get_rate(hw: hws[CLK_FIN_PLL]) == 24000000) { |
1295 | exynos4210_plls[apll].rate_table = |
1296 | exynos4210_apll_rates; |
1297 | exynos4210_plls[epll].rate_table = |
1298 | exynos4210_epll_rates; |
1299 | } |
1300 | |
1301 | if (clk_hw_get_rate(hw: hws[CLK_MOUT_VPLLSRC]) == 24000000) |
1302 | exynos4210_plls[vpll].rate_table = |
1303 | exynos4210_vpll_rates; |
1304 | |
1305 | samsung_clk_register_pll(ctx, pll_list: exynos4210_plls, |
1306 | ARRAY_SIZE(exynos4210_plls)); |
1307 | } else { |
1308 | if (clk_hw_get_rate(hw: hws[CLK_FIN_PLL]) == 24000000) { |
1309 | exynos4x12_plls[apll].rate_table = |
1310 | exynos4x12_apll_rates; |
1311 | exynos4x12_plls[epll].rate_table = |
1312 | exynos4x12_epll_rates; |
1313 | exynos4x12_plls[vpll].rate_table = |
1314 | exynos4x12_vpll_rates; |
1315 | } |
1316 | |
1317 | samsung_clk_register_pll(ctx, pll_list: exynos4x12_plls, |
1318 | ARRAY_SIZE(exynos4x12_plls)); |
1319 | } |
1320 | |
1321 | samsung_clk_register_fixed_rate(ctx, clk_list: exynos4_fixed_rate_clks, |
1322 | ARRAY_SIZE(exynos4_fixed_rate_clks)); |
1323 | samsung_clk_register_mux(ctx, clk_list: exynos4_mux_clks, |
1324 | ARRAY_SIZE(exynos4_mux_clks)); |
1325 | samsung_clk_register_div(ctx, clk_list: exynos4_div_clks, |
1326 | ARRAY_SIZE(exynos4_div_clks)); |
1327 | samsung_clk_register_gate(ctx, clk_list: exynos4_gate_clks, |
1328 | ARRAY_SIZE(exynos4_gate_clks)); |
1329 | samsung_clk_register_fixed_factor(ctx, list: exynos4_fixed_factor_clks, |
1330 | ARRAY_SIZE(exynos4_fixed_factor_clks)); |
1331 | |
1332 | if (exynos4_soc == EXYNOS4210) { |
1333 | samsung_clk_register_fixed_rate(ctx, clk_list: exynos4210_fixed_rate_clks, |
1334 | ARRAY_SIZE(exynos4210_fixed_rate_clks)); |
1335 | samsung_clk_register_mux(ctx, clk_list: exynos4210_mux_clks, |
1336 | ARRAY_SIZE(exynos4210_mux_clks)); |
1337 | samsung_clk_register_div(ctx, clk_list: exynos4210_div_clks, |
1338 | ARRAY_SIZE(exynos4210_div_clks)); |
1339 | samsung_clk_register_gate(ctx, clk_list: exynos4210_gate_clks, |
1340 | ARRAY_SIZE(exynos4210_gate_clks)); |
1341 | samsung_clk_register_fixed_factor(ctx, |
1342 | list: exynos4210_fixed_factor_clks, |
1343 | ARRAY_SIZE(exynos4210_fixed_factor_clks)); |
1344 | samsung_clk_register_cpu(ctx, list: exynos4210_cpu_clks, |
1345 | ARRAY_SIZE(exynos4210_cpu_clks)); |
1346 | } else { |
1347 | samsung_clk_register_mux(ctx, clk_list: exynos4x12_mux_clks, |
1348 | ARRAY_SIZE(exynos4x12_mux_clks)); |
1349 | samsung_clk_register_div(ctx, clk_list: exynos4x12_div_clks, |
1350 | ARRAY_SIZE(exynos4x12_div_clks)); |
1351 | samsung_clk_register_gate(ctx, clk_list: exynos4x12_gate_clks, |
1352 | ARRAY_SIZE(exynos4x12_gate_clks)); |
1353 | samsung_clk_register_fixed_factor(ctx, |
1354 | list: exynos4x12_fixed_factor_clks, |
1355 | ARRAY_SIZE(exynos4x12_fixed_factor_clks)); |
1356 | if (soc == EXYNOS4412) |
1357 | samsung_clk_register_cpu(ctx, list: exynos4412_cpu_clks, |
1358 | ARRAY_SIZE(exynos4412_cpu_clks)); |
1359 | else |
1360 | samsung_clk_register_cpu(ctx, list: exynos4212_cpu_clks, |
1361 | ARRAY_SIZE(exynos4212_cpu_clks)); |
1362 | } |
1363 | |
1364 | if (soc == EXYNOS4212 || soc == EXYNOS4412) |
1365 | exynos4x12_core_down_clock(); |
1366 | |
1367 | samsung_clk_extended_sleep_init(reg_base, |
1368 | rdump: exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), |
1369 | rsuspend: src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); |
1370 | if (exynos4_soc == EXYNOS4210) |
1371 | samsung_clk_extended_sleep_init(reg_base, |
1372 | rdump: exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), |
1373 | rsuspend: src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); |
1374 | else |
1375 | samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, |
1376 | ARRAY_SIZE(exynos4x12_clk_save)); |
1377 | |
1378 | samsung_clk_of_add_provider(np, ctx); |
1379 | |
1380 | pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" |
1381 | "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n" , |
1382 | exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12" , |
1383 | clk_hw_get_rate(hws[CLK_SCLK_APLL]), |
1384 | clk_hw_get_rate(hws[CLK_SCLK_MPLL]), |
1385 | clk_hw_get_rate(hws[CLK_SCLK_EPLL]), |
1386 | clk_hw_get_rate(hws[CLK_SCLK_VPLL]), |
1387 | clk_hw_get_rate(hws[CLK_DIV_CORE2])); |
1388 | } |
1389 | |
1390 | |
1391 | static void __init exynos4210_clk_init(struct device_node *np) |
1392 | { |
1393 | exynos4_clk_init(np, soc: EXYNOS4210); |
1394 | } |
1395 | CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock" , exynos4210_clk_init); |
1396 | |
1397 | static void __init exynos4212_clk_init(struct device_node *np) |
1398 | { |
1399 | exynos4_clk_init(np, soc: EXYNOS4212); |
1400 | } |
1401 | CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock" , exynos4212_clk_init); |
1402 | |
1403 | static void __init exynos4412_clk_init(struct device_node *np) |
1404 | { |
1405 | exynos4_clk_init(np, soc: EXYNOS4412); |
1406 | } |
1407 | CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock" , exynos4412_clk_init); |
1408 | |