1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> |
4 | * |
5 | * based on drivers/clk/tegra/clk.h |
6 | */ |
7 | |
8 | #ifndef __SOCFPGA_CLK_H |
9 | #define __SOCFPGA_CLK_H |
10 | |
11 | #include <linux/clk-provider.h> |
12 | |
13 | /* Clock Manager offsets */ |
14 | #define CLKMGR_CTRL 0x0 |
15 | #define CLKMGR_BYPASS 0x4 |
16 | #define CLKMGR_DBCTRL 0x10 |
17 | #define CLKMGR_L4SRC 0x70 |
18 | #define CLKMGR_PERPLL_SRC 0xAC |
19 | |
20 | #define SOCFPGA_MAX_PARENTS 5 |
21 | |
22 | #define streq(a, b) (strcmp((a), (b)) == 0) |
23 | #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ |
24 | ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) |
25 | |
26 | #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ |
27 | ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) |
28 | |
29 | extern void __iomem *clk_mgr_base_addr; |
30 | extern void __iomem *clk_mgr_a10_base_addr; |
31 | |
32 | void __init socfpga_pll_init(struct device_node *node); |
33 | void __init socfpga_periph_init(struct device_node *node); |
34 | void __init socfpga_gate_init(struct device_node *node); |
35 | void socfpga_a10_pll_init(struct device_node *node); |
36 | void socfpga_a10_periph_init(struct device_node *node); |
37 | void socfpga_a10_gate_init(struct device_node *node); |
38 | |
39 | struct socfpga_pll { |
40 | struct clk_gate hw; |
41 | }; |
42 | |
43 | struct socfpga_gate_clk { |
44 | struct clk_gate hw; |
45 | char *parent_name; |
46 | u32 fixed_div; |
47 | void __iomem *div_reg; |
48 | void __iomem *bypass_reg; |
49 | struct regmap *sys_mgr_base_addr; |
50 | u32 width; /* only valid if div_reg != 0 */ |
51 | u32 shift; /* only valid if div_reg != 0 */ |
52 | u32 bypass_shift; /* only valid if bypass_reg != 0 */ |
53 | }; |
54 | |
55 | struct socfpga_periph_clk { |
56 | struct clk_gate hw; |
57 | char *parent_name; |
58 | u32 fixed_div; |
59 | void __iomem *div_reg; |
60 | void __iomem *bypass_reg; |
61 | u32 width; /* only valid if div_reg != 0 */ |
62 | u32 shift; /* only valid if div_reg != 0 */ |
63 | u32 bypass_shift; /* only valid if bypass_reg != 0 */ |
64 | }; |
65 | |
66 | #endif /* SOCFPGA_CLK_H */ |
67 | |