1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/io.h> |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/clkdev.h> |
9 | #include <linux/of.h> |
10 | #include <linux/of_address.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/export.h> |
13 | #include <linux/clk/tegra.h> |
14 | |
15 | #include "clk.h" |
16 | #include "clk-id.h" |
17 | |
18 | #define CLK_SOURCE_I2S0 0x1d8 |
19 | #define CLK_SOURCE_I2S1 0x100 |
20 | #define CLK_SOURCE_I2S2 0x104 |
21 | #define CLK_SOURCE_NDFLASH 0x160 |
22 | #define CLK_SOURCE_I2S3 0x3bc |
23 | #define CLK_SOURCE_I2S4 0x3c0 |
24 | #define CLK_SOURCE_SPDIF_OUT 0x108 |
25 | #define CLK_SOURCE_SPDIF_IN 0x10c |
26 | #define CLK_SOURCE_PWM 0x110 |
27 | #define CLK_SOURCE_ADX 0x638 |
28 | #define CLK_SOURCE_ADX1 0x670 |
29 | #define CLK_SOURCE_AMX 0x63c |
30 | #define CLK_SOURCE_AMX1 0x674 |
31 | #define CLK_SOURCE_HDA 0x428 |
32 | #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 |
33 | #define CLK_SOURCE_SBC1 0x134 |
34 | #define CLK_SOURCE_SBC2 0x118 |
35 | #define CLK_SOURCE_SBC3 0x11c |
36 | #define CLK_SOURCE_SBC4 0x1b4 |
37 | #define CLK_SOURCE_SBC5 0x3c8 |
38 | #define CLK_SOURCE_SBC6 0x3cc |
39 | #define CLK_SOURCE_SATA_OOB 0x420 |
40 | #define CLK_SOURCE_SATA 0x424 |
41 | #define CLK_SOURCE_NDSPEED 0x3f8 |
42 | #define CLK_SOURCE_VFIR 0x168 |
43 | #define CLK_SOURCE_SDMMC1 0x150 |
44 | #define CLK_SOURCE_SDMMC2 0x154 |
45 | #define CLK_SOURCE_SDMMC3 0x1bc |
46 | #define CLK_SOURCE_SDMMC4 0x164 |
47 | #define CLK_SOURCE_CVE 0x140 |
48 | #define CLK_SOURCE_TVO 0x188 |
49 | #define CLK_SOURCE_TVDAC 0x194 |
50 | #define CLK_SOURCE_VDE 0x1c8 |
51 | #define CLK_SOURCE_CSITE 0x1d4 |
52 | #define CLK_SOURCE_LA 0x1f8 |
53 | #define CLK_SOURCE_TRACE 0x634 |
54 | #define CLK_SOURCE_OWR 0x1cc |
55 | #define CLK_SOURCE_NOR 0x1d0 |
56 | #define CLK_SOURCE_MIPI 0x174 |
57 | #define CLK_SOURCE_I2C1 0x124 |
58 | #define CLK_SOURCE_I2C2 0x198 |
59 | #define CLK_SOURCE_I2C3 0x1b8 |
60 | #define CLK_SOURCE_I2C4 0x3c4 |
61 | #define CLK_SOURCE_I2C5 0x128 |
62 | #define CLK_SOURCE_I2C6 0x65c |
63 | #define CLK_SOURCE_UARTA 0x178 |
64 | #define CLK_SOURCE_UARTB 0x17c |
65 | #define CLK_SOURCE_UARTC 0x1a0 |
66 | #define CLK_SOURCE_UARTD 0x1c0 |
67 | #define CLK_SOURCE_UARTE 0x1c4 |
68 | #define CLK_SOURCE_3D 0x158 |
69 | #define CLK_SOURCE_2D 0x15c |
70 | #define CLK_SOURCE_MPE 0x170 |
71 | #define CLK_SOURCE_VI_SENSOR 0x1a8 |
72 | #define CLK_SOURCE_VI 0x148 |
73 | #define CLK_SOURCE_EPP 0x16c |
74 | #define CLK_SOURCE_MSENC 0x1f0 |
75 | #define CLK_SOURCE_TSEC 0x1f4 |
76 | #define CLK_SOURCE_HOST1X 0x180 |
77 | #define CLK_SOURCE_HDMI 0x18c |
78 | #define CLK_SOURCE_DISP1 0x138 |
79 | #define CLK_SOURCE_DISP2 0x13c |
80 | #define CLK_SOURCE_CILAB 0x614 |
81 | #define CLK_SOURCE_CILCD 0x618 |
82 | #define CLK_SOURCE_CILE 0x61c |
83 | #define CLK_SOURCE_DSIALP 0x620 |
84 | #define CLK_SOURCE_DSIBLP 0x624 |
85 | #define CLK_SOURCE_TSENSOR 0x3b8 |
86 | #define CLK_SOURCE_D_AUDIO 0x3d0 |
87 | #define CLK_SOURCE_DAM0 0x3d8 |
88 | #define CLK_SOURCE_DAM1 0x3dc |
89 | #define CLK_SOURCE_DAM2 0x3e0 |
90 | #define CLK_SOURCE_ACTMON 0x3e8 |
91 | #define CLK_SOURCE_EXTERN1 0x3ec |
92 | #define CLK_SOURCE_EXTERN2 0x3f0 |
93 | #define CLK_SOURCE_EXTERN3 0x3f4 |
94 | #define CLK_SOURCE_I2CSLOW 0x3fc |
95 | #define CLK_SOURCE_SE 0x42c |
96 | #define CLK_SOURCE_MSELECT 0x3b4 |
97 | #define CLK_SOURCE_DFLL_REF 0x62c |
98 | #define CLK_SOURCE_DFLL_SOC 0x630 |
99 | #define CLK_SOURCE_SOC_THERM 0x644 |
100 | #define CLK_SOURCE_XUSB_HOST_SRC 0x600 |
101 | #define CLK_SOURCE_XUSB_FALCON_SRC 0x604 |
102 | #define CLK_SOURCE_XUSB_FS_SRC 0x608 |
103 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 |
104 | #define CLK_SOURCE_XUSB_DEV_SRC 0x60c |
105 | #define CLK_SOURCE_ISP 0x144 |
106 | #define CLK_SOURCE_SOR0 0x414 |
107 | #define CLK_SOURCE_DPAUX 0x418 |
108 | #define CLK_SOURCE_ENTROPY 0x628 |
109 | #define CLK_SOURCE_VI_SENSOR2 0x658 |
110 | #define CLK_SOURCE_HDMI_AUDIO 0x668 |
111 | #define CLK_SOURCE_VIC03 0x678 |
112 | #define CLK_SOURCE_CLK72MHZ 0x66c |
113 | #define CLK_SOURCE_DBGAPB 0x718 |
114 | #define CLK_SOURCE_NVENC 0x6a0 |
115 | #define CLK_SOURCE_NVDEC 0x698 |
116 | #define CLK_SOURCE_NVJPG 0x69c |
117 | #define CLK_SOURCE_APE 0x6c0 |
118 | #define CLK_SOURCE_SDMMC_LEGACY 0x694 |
119 | #define CLK_SOURCE_QSPI 0x6c4 |
120 | #define CLK_SOURCE_VI_I2C 0x6c8 |
121 | #define CLK_SOURCE_MIPIBIF 0x660 |
122 | #define CLK_SOURCE_UARTAPE 0x710 |
123 | #define CLK_SOURCE_TSECB 0x6d8 |
124 | #define CLK_SOURCE_MAUD 0x6d4 |
125 | #define CLK_SOURCE_USB2_HSIC_TRK 0x6cc |
126 | #define CLK_SOURCE_DMIC1 0x64c |
127 | #define CLK_SOURCE_DMIC2 0x650 |
128 | #define CLK_SOURCE_DMIC3 0x6bc |
129 | |
130 | #define MASK(x) (BIT(x) - 1) |
131 | |
132 | #define MUX(_name, _parents, _offset, \ |
133 | _clk_num, _gate_flags, _clk_id) \ |
134 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
135 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ |
136 | _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ |
137 | NULL) |
138 | |
139 | #define MUX_FLAGS(_name, _parents, _offset,\ |
140 | _clk_num, _gate_flags, _clk_id, flags)\ |
141 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
142 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
143 | _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\ |
144 | NULL) |
145 | |
146 | #define MUX8(_name, _parents, _offset, \ |
147 | _clk_num, _gate_flags, _clk_id) \ |
148 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
149 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
150 | _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ |
151 | NULL) |
152 | |
153 | #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ |
154 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ |
155 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
156 | 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ |
157 | _parents##_idx, 0, _lock) |
158 | |
159 | #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ |
160 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ |
161 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
162 | 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ |
163 | _parents##_idx, 0, NULL) |
164 | |
165 | #define INT(_name, _parents, _offset, \ |
166 | _clk_num, _gate_flags, _clk_id) \ |
167 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
168 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ |
169 | TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ |
170 | _clk_id, _parents##_idx, 0, NULL) |
171 | |
172 | #define INT_FLAGS(_name, _parents, _offset,\ |
173 | _clk_num, _gate_flags, _clk_id, flags)\ |
174 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
175 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ |
176 | TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ |
177 | _clk_id, _parents##_idx, flags, NULL) |
178 | |
179 | #define INT8(_name, _parents, _offset,\ |
180 | _clk_num, _gate_flags, _clk_id) \ |
181 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
182 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ |
183 | TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ |
184 | _clk_id, _parents##_idx, 0, NULL) |
185 | |
186 | #define UART(_name, _parents, _offset,\ |
187 | _clk_num, _clk_id) \ |
188 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
189 | 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ |
190 | TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ |
191 | _parents##_idx, 0, NULL) |
192 | |
193 | #define UART8(_name, _parents, _offset,\ |
194 | _clk_num, _clk_id) \ |
195 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
196 | 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ |
197 | TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ |
198 | _parents##_idx, 0, NULL) |
199 | |
200 | #define I2C(_name, _parents, _offset,\ |
201 | _clk_num, _clk_id) \ |
202 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
203 | 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ |
204 | _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \ |
205 | _parents##_idx, 0, NULL) |
206 | |
207 | #define XUSB(_name, _parents, _offset, \ |
208 | _clk_num, _gate_flags, _clk_id) \ |
209 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ |
210 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ |
211 | TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ |
212 | _clk_id, _parents##_idx, 0, NULL) |
213 | |
214 | #define AUDIO(_name, _offset, _clk_num,\ |
215 | _gate_flags, _clk_id) \ |
216 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ |
217 | _offset, 16, 0xE01F, 0, 0, 8, 1, \ |
218 | TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \ |
219 | _clk_id, mux_d_audio_clk_idx, 0, NULL) |
220 | |
221 | #define NODIV(_name, _parents, _offset, \ |
222 | _mux_shift, _mux_mask, _clk_num, \ |
223 | _gate_flags, _clk_id, _lock) \ |
224 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
225 | _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ |
226 | _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\ |
227 | _clk_id, _parents##_idx, 0, _lock) |
228 | |
229 | #define GATE(_name, _parent_name, \ |
230 | _clk_num, _gate_flags, _clk_id, _flags) \ |
231 | { \ |
232 | .name = _name, \ |
233 | .clk_id = _clk_id, \ |
234 | .p.parent_name = _parent_name, \ |
235 | .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ |
236 | _clk_num, _gate_flags, NULL, NULL), \ |
237 | .flags = _flags \ |
238 | } |
239 | |
240 | #define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \ |
241 | { \ |
242 | .name = _name, \ |
243 | .clk_id = _clk_id, \ |
244 | .p.parent_name = _parent_name, \ |
245 | .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \ |
246 | TEGRA_DIVIDER_ROUND_UP, 0, 0, \ |
247 | NULL, NULL), \ |
248 | .offset = _offset, \ |
249 | .flags = _flags, \ |
250 | } |
251 | |
252 | #define PLLP_BASE 0xa0 |
253 | #define PLLP_MISC 0xac |
254 | #define PLLP_MISC1 0x680 |
255 | #define PLLP_OUTA 0xa4 |
256 | #define PLLP_OUTB 0xa8 |
257 | #define PLLP_OUTC 0x67c |
258 | |
259 | #define PLL_BASE_LOCK BIT(27) |
260 | #define PLL_MISC_LOCK_ENABLE 18 |
261 | |
262 | static DEFINE_SPINLOCK(PLLP_OUTA_lock); |
263 | static DEFINE_SPINLOCK(PLLP_OUTB_lock); |
264 | static DEFINE_SPINLOCK(PLLP_OUTC_lock); |
265 | |
266 | #define MUX_I2S_SPDIF(_id) \ |
267 | static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ |
268 | #_id, "pll_p",\ |
269 | "clk_m"}; |
270 | MUX_I2S_SPDIF(audio0) |
271 | MUX_I2S_SPDIF(audio1) |
272 | MUX_I2S_SPDIF(audio2) |
273 | MUX_I2S_SPDIF(audio3) |
274 | MUX_I2S_SPDIF(audio4) |
275 | MUX_I2S_SPDIF(audio) |
276 | |
277 | #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL |
278 | #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL |
279 | #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL |
280 | #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL |
281 | #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL |
282 | #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL |
283 | |
284 | static const char *mux_pllp_pllc_pllm_clkm[] = { |
285 | "pll_p" , "pll_c" , "pll_m" , "clk_m" |
286 | }; |
287 | #define mux_pllp_pllc_pllm_clkm_idx NULL |
288 | |
289 | static const char *mux_pllp_pllc_pllm[] = { "pll_p" , "pll_c" , "pll_m" }; |
290 | #define mux_pllp_pllc_pllm_idx NULL |
291 | |
292 | static const char *mux_pllp_pllc_clk32_clkm[] = { |
293 | "pll_p" , "pll_c" , "clk_32k" , "clk_m" |
294 | }; |
295 | #define mux_pllp_pllc_clk32_clkm_idx NULL |
296 | |
297 | static const char *mux_plla_pllc_pllp_clkm[] = { |
298 | "pll_a_out0" , "pll_c" , "pll_p" , "clk_m" |
299 | }; |
300 | #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx |
301 | |
302 | static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { |
303 | "pll_p" , "pll_c2" , "pll_c" , "pll_c3" , "pll_m" , "clk_m" |
304 | }; |
305 | static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { |
306 | [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, |
307 | }; |
308 | |
309 | static const char *mux_pllp_clkm[] = { |
310 | "pll_p" , "clk_m" |
311 | }; |
312 | static u32 mux_pllp_clkm_idx[] = { |
313 | [0] = 0, [1] = 3, |
314 | }; |
315 | |
316 | static const char *mux_pllp_clkm_2[] = { |
317 | "pll_p" , "clk_m" |
318 | }; |
319 | static u32 mux_pllp_clkm_2_idx[] = { |
320 | [0] = 2, [1] = 6, |
321 | }; |
322 | |
323 | static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = { |
324 | "pll_c2" , "pll_c" , "pll_c3" , "pll_p" , "pll_a1" , "clk_m" |
325 | }; |
326 | static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = { |
327 | [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7, |
328 | }; |
329 | |
330 | static const char * |
331 | mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = { |
332 | "pll_c4_out1" , "pll_c" , "pll_c4_out2" , "pll_p" , "clk_m" , |
333 | "pll_a_out0" , "pll_c4_out0" |
334 | }; |
335 | static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = { |
336 | [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7, |
337 | }; |
338 | |
339 | static const char *mux_pllc_pllp_plla[] = { |
340 | "pll_c" , "pll_p" , "pll_a_out0" |
341 | }; |
342 | static u32 mux_pllc_pllp_plla_idx[] = { |
343 | [0] = 1, [1] = 2, [2] = 3, |
344 | }; |
345 | |
346 | static const char *mux_clkm_pllc_pllp_plla[] = { |
347 | "clk_m" , "pll_c" , "pll_p" , "pll_a_out0" |
348 | }; |
349 | #define mux_clkm_pllc_pllp_plla_idx NULL |
350 | |
351 | static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = { |
352 | "pll_c" , "pll_p" , "pll_a1" , "pll_c2" , "pll_c3" , "clk_m" |
353 | }; |
354 | static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = { |
355 | [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, |
356 | }; |
357 | |
358 | static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = { |
359 | "pll_c2" , "pll_c" , "pll_c3" , "pll_p" , "clk_m" , "pll_a1" , "pll_c4_out0" , |
360 | }; |
361 | static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = { |
362 | [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7, |
363 | }; |
364 | |
365 | static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = { |
366 | "pll_c" , "pll_p" , "pll_a1" , "pll_c2" , "pll_c3" , "clk_m" , "pll_c4_out0" , |
367 | }; |
368 | #define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \ |
369 | mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx |
370 | |
371 | static const char * |
372 | mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = { |
373 | "pll_a_out0" , "pll_c4_out0" , "pll_c" , "pll_c4_out1" , "pll_p" , |
374 | "pll_c4_out2" , "clk_m" |
375 | }; |
376 | #define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL |
377 | |
378 | static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { |
379 | "pll_m" , "pll_c2" , "pll_c" , "pll_c3" , "pll_p" , "pll_a_out0" |
380 | }; |
381 | #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx |
382 | |
383 | static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { |
384 | "pll_p" , "pll_m" , "pll_d_out0" , "pll_a_out0" , "pll_c" , |
385 | "pll_d2_out0" , "clk_m" |
386 | }; |
387 | #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL |
388 | |
389 | static const char *mux_pllm_pllc_pllp_plla[] = { |
390 | "pll_m" , "pll_c" , "pll_p" , "pll_a_out0" |
391 | }; |
392 | #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx |
393 | |
394 | static const char *mux_pllp_pllc_clkm[] = { |
395 | "pll_p" , "pll_c" , "clk_m" |
396 | }; |
397 | static u32 mux_pllp_pllc_clkm_idx[] = { |
398 | [0] = 0, [1] = 1, [2] = 3, |
399 | }; |
400 | |
401 | static const char *mux_pllp_pllc_clkm_1[] = { |
402 | "pll_p" , "pll_c" , "clk_m" |
403 | }; |
404 | static u32 mux_pllp_pllc_clkm_1_idx[] = { |
405 | [0] = 0, [1] = 2, [2] = 5, |
406 | }; |
407 | |
408 | static const char *mux_pllp_pllc_plla_clkm[] = { |
409 | "pll_p" , "pll_c" , "pll_a_out0" , "clk_m" |
410 | }; |
411 | static u32 mux_pllp_pllc_plla_clkm_idx[] = { |
412 | [0] = 0, [1] = 2, [2] = 4, [3] = 6, |
413 | }; |
414 | |
415 | static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = { |
416 | "pll_p" , "pll_c" , "pll_c4_out0" , "pll_c4_out1" , "clk_m" , "pll_c4_out2" |
417 | }; |
418 | static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = { |
419 | [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7, |
420 | }; |
421 | |
422 | static const char * |
423 | mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = { |
424 | "pll_p" , "pll_c_out1" , "pll_c" , "pll_c4_out2" , "pll_c4_out1" , |
425 | "clk_m" , "pll_c4_out0" |
426 | }; |
427 | static u32 |
428 | mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = { |
429 | [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7, |
430 | }; |
431 | |
432 | static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = { |
433 | "pll_p" , "pll_c4_out2" , "pll_c4_out1" , "clk_m" , "pll_c4_out0" |
434 | }; |
435 | static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = { |
436 | [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7, |
437 | }; |
438 | |
439 | static const char *mux_pllp_pllc2_c_c3_clkm[] = { |
440 | "pll_p" , "pll_c2" , "pll_c" , "pll_c3" , "clk_m" |
441 | }; |
442 | static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = { |
443 | [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6, |
444 | }; |
445 | |
446 | static const char *mux_pllp_clkm_clk32_plle[] = { |
447 | "pll_p" , "clk_m" , "clk_32k" , "pll_e" |
448 | }; |
449 | static u32 mux_pllp_clkm_clk32_plle_idx[] = { |
450 | [0] = 0, [1] = 2, [2] = 4, [3] = 6, |
451 | }; |
452 | |
453 | static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = { |
454 | "pll_p" , "pll_p_out3" , "clk_m" , "clk_32k" , "pll_a_out0" |
455 | }; |
456 | #define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL |
457 | |
458 | static const char *mux_pllp_out3_clkm_pllp_pllc4[] = { |
459 | "pll_p_out3" , "clk_m" , "pll_p" , "pll_c4_out0" , "pll_c4_out1" , |
460 | "pll_c4_out2" |
461 | }; |
462 | static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = { |
463 | [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7, |
464 | }; |
465 | |
466 | static const char *mux_clkm_pllp_pllre[] = { |
467 | "clk_m" , "pll_p_out_xusb" , "pll_re_out" |
468 | }; |
469 | static u32 mux_clkm_pllp_pllre_idx[] = { |
470 | [0] = 0, [1] = 1, [2] = 5, |
471 | }; |
472 | |
473 | static const char *mux_pllp_pllc_clkm_clk32[] = { |
474 | "pll_p" , "pll_c" , "clk_m" , "clk_32k" |
475 | }; |
476 | #define mux_pllp_pllc_clkm_clk32_idx NULL |
477 | |
478 | static const char *mux_plla_clk32_pllp_clkm_plle[] = { |
479 | "pll_a_out0" , "clk_32k" , "pll_p" , "clk_m" , "pll_e_out0" |
480 | }; |
481 | #define mux_plla_clk32_pllp_clkm_plle_idx NULL |
482 | |
483 | static const char *mux_clkm_pllp_pllc_pllre[] = { |
484 | "clk_m" , "pll_p" , "pll_c" , "pll_re_out" |
485 | }; |
486 | static u32 mux_clkm_pllp_pllc_pllre_idx[] = { |
487 | [0] = 0, [1] = 1, [2] = 3, [3] = 5, |
488 | }; |
489 | |
490 | static const char *mux_clkm_48M_pllp_480M[] = { |
491 | "clk_m" , "pll_u_48M" , "pll_p" , "pll_u_480M" |
492 | }; |
493 | static u32 mux_clkm_48M_pllp_480M_idx[] = { |
494 | [0] = 0, [1] = 2, [2] = 4, [3] = 6, |
495 | }; |
496 | |
497 | static const char *mux_clkm_pllre_clk32_480M[] = { |
498 | "clk_m" , "pll_re_out" , "clk_32k" , "pll_u_480M" |
499 | }; |
500 | #define mux_clkm_pllre_clk32_480M_idx NULL |
501 | |
502 | static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { |
503 | "clk_m" , "pll_re_out" , "clk_32k" , "pll_u_480M" , "pll_c" , "pll_ref" |
504 | }; |
505 | static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { |
506 | [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, |
507 | }; |
508 | |
509 | static const char *mux_pllp_out3_pllp_pllc_clkm[] = { |
510 | "pll_p_out3" , "pll_p" , "pll_c" , "clk_m" |
511 | }; |
512 | static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = { |
513 | [0] = 0, [1] = 1, [2] = 2, [3] = 6, |
514 | }; |
515 | |
516 | static const char *mux_ss_div2_60M[] = { |
517 | "xusb_ss_div2" , "pll_u_60M" |
518 | }; |
519 | #define mux_ss_div2_60M_idx NULL |
520 | |
521 | static const char *mux_ss_div2_60M_ss[] = { |
522 | "xusb_ss_div2" , "pll_u_60M" , "xusb_ss_src" |
523 | }; |
524 | #define mux_ss_div2_60M_ss_idx NULL |
525 | |
526 | static const char *mux_ss_clkm[] = { |
527 | "xusb_ss_src" , "clk_m" |
528 | }; |
529 | #define mux_ss_clkm_idx NULL |
530 | |
531 | static const char *mux_d_audio_clk[] = { |
532 | "pll_a_out0" , "pll_p" , "clk_m" , "spdif_in_sync" , "i2s0_sync" , |
533 | "i2s1_sync" , "i2s2_sync" , "i2s3_sync" , "i2s4_sync" , "vimclk_sync" , |
534 | }; |
535 | static u32 mux_d_audio_clk_idx[] = { |
536 | [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, |
537 | [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, |
538 | }; |
539 | |
540 | static const char *mux_pllp_plld_pllc_clkm[] = { |
541 | "pll_p" , "pll_d_out0" , "pll_c" , "clk_m" |
542 | }; |
543 | #define mux_pllp_plld_pllc_clkm_idx NULL |
544 | static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = { |
545 | "pll_m" , "pll_c" , "pll_p" , "pll_a_out0" , "clk_m" , "pll_c4" , |
546 | }; |
547 | static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = { |
548 | [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7, |
549 | }; |
550 | |
551 | static const char *mux_pllp_clkm1[] = { |
552 | "pll_p" , "clk_m" , |
553 | }; |
554 | #define mux_pllp_clkm1_idx NULL |
555 | |
556 | static const char *mux_pllp3_pllc_clkm[] = { |
557 | "pll_p_out3" , "pll_c" , "pll_c2" , "clk_m" , |
558 | }; |
559 | #define mux_pllp3_pllc_clkm_idx NULL |
560 | |
561 | static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = { |
562 | "pll_m" , "pll_c" , "pll_p" , "pll_a" , "pll_c2" , "pll_c3" , "clk_m" |
563 | }; |
564 | #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL |
565 | |
566 | static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = { |
567 | "pll_m" , "pll_c2" , "pll_c" , "pll_c3" , "pll_p" , "pll_a_out0" , "pll_c4" , |
568 | }; |
569 | static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = { |
570 | [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7, |
571 | }; |
572 | |
573 | /* SOR1 mux'es */ |
574 | static const char *mux_pllp_plld_plld2_clkm[] = { |
575 | "pll_p" , "pll_d_out0" , "pll_d2_out0" , "clk_m" |
576 | }; |
577 | static u32 mux_pllp_plld_plld2_clkm_idx[] = { |
578 | [0] = 0, [1] = 2, [2] = 5, [3] = 6 |
579 | }; |
580 | |
581 | static const char *mux_pllp_pllre_clkm[] = { |
582 | "pll_p" , "pll_re_out1" , "clk_m" |
583 | }; |
584 | |
585 | static u32 mux_pllp_pllre_clkm_idx[] = { |
586 | [0] = 0, [1] = 2, [2] = 3, |
587 | }; |
588 | |
589 | static const char * const mux_dmic1[] = { |
590 | "pll_a_out0" , "dmic1_sync_clk" , "pll_p" , "clk_m" |
591 | }; |
592 | #define mux_dmic1_idx NULL |
593 | |
594 | static const char * const mux_dmic2[] = { |
595 | "pll_a_out0" , "dmic2_sync_clk" , "pll_p" , "clk_m" |
596 | }; |
597 | #define mux_dmic2_idx NULL |
598 | |
599 | static const char * const mux_dmic3[] = { |
600 | "pll_a_out0" , "dmic3_sync_clk" , "pll_p" , "clk_m" |
601 | }; |
602 | #define mux_dmic3_idx NULL |
603 | |
604 | static struct tegra_periph_init_data periph_clks[] = { |
605 | AUDIO("d_audio" , CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio), |
606 | AUDIO("dam0" , CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0), |
607 | AUDIO("dam1" , CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1), |
608 | AUDIO("dam2" , CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2), |
609 | I2C("i2c1" , mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1), |
610 | I2C("i2c2" , mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2), |
611 | I2C("i2c3" , mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3), |
612 | I2C("i2c4" , mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), |
613 | I2C("i2c5" , mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), |
614 | I2C("i2c6" , mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6), |
615 | INT("vde" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), |
616 | INT("vi" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), |
617 | INT("epp" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), |
618 | INT("host1x" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), |
619 | INT("mpe" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), |
620 | INT("2d" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), |
621 | INT("3d" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), |
622 | INT8("vde" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), |
623 | INT8("vi" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), |
624 | INT8("vi" , mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), |
625 | INT8("vi" , mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10), |
626 | INT8("epp" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), |
627 | INT8("msenc" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), |
628 | INT8("tsec" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), |
629 | INT("tsec" , mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8), |
630 | INT8("host1x" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), |
631 | INT8("host1x" , mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9), |
632 | INT8("se" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), |
633 | INT8("se" , mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se_10), |
634 | INT8("2d" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), |
635 | INT8("3d" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), |
636 | INT8("vic03" , mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03), |
637 | INT8("vic03" , mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8), |
638 | INT_FLAGS("mselect" , mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), |
639 | MUX("i2s0" , mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), |
640 | MUX("i2s1" , mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), |
641 | MUX("i2s2" , mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), |
642 | MUX("i2s3" , mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), |
643 | MUX("i2s4" , mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), |
644 | MUX("spdif_out" , mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), |
645 | MUX("spdif_in" , mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), |
646 | MUX8("spdif_in" , mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8), |
647 | MUX("pwm" , mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), |
648 | MUX("adx" , mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), |
649 | MUX("amx" , mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), |
650 | MUX("hda" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), |
651 | MUX("hda" , mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8), |
652 | MUX("hda2codec_2x" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), |
653 | MUX8("hda2codec_2x" , mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8), |
654 | MUX("vfir" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), |
655 | MUX("sdmmc1" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), |
656 | MUX("sdmmc2" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), |
657 | MUX("sdmmc3" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), |
658 | MUX("sdmmc4" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), |
659 | MUX8("sdmmc1" , mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9), |
660 | MUX8("sdmmc3" , mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9), |
661 | MUX("la" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), |
662 | MUX("trace" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), |
663 | MUX("owr" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), |
664 | MUX("owr" , mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8), |
665 | MUX("nor" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), |
666 | MUX("mipi" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), |
667 | MUX("vi_sensor" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), |
668 | MUX("vi_sensor" , mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9), |
669 | MUX("cilab" , mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), |
670 | MUX("cilcd" , mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd), |
671 | MUX("cile" , mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile), |
672 | MUX("dsialp" , mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp), |
673 | MUX("dsiblp" , mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp), |
674 | MUX("tsensor" , mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor), |
675 | MUX("actmon" , mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon), |
676 | MUX("dfll_ref" , mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref), |
677 | MUX("dfll_soc" , mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc), |
678 | MUX("i2cslow" , mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow), |
679 | MUX("sbc1" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), |
680 | MUX("sbc2" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), |
681 | MUX("sbc3" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), |
682 | MUX("sbc4" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), |
683 | MUX("sbc5" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), |
684 | MUX("sbc6" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), |
685 | MUX("cve" , mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), |
686 | MUX("tvo" , mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), |
687 | MUX("tvdac" , mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), |
688 | MUX("ndflash" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), |
689 | MUX("ndspeed" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), |
690 | MUX("sata_oob" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), |
691 | MUX("sata_oob" , mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8), |
692 | MUX("sata" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), |
693 | MUX("sata" , mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8), |
694 | MUX("adx1" , mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), |
695 | MUX("amx1" , mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), |
696 | MUX("vi_sensor2" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), |
697 | MUX("vi_sensor2" , mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8), |
698 | MUX8("sdmmc1" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8), |
699 | MUX8("sdmmc2" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8), |
700 | MUX8("sdmmc3" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8), |
701 | MUX8("sdmmc4" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8), |
702 | MUX8("sbc1" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), |
703 | MUX8("sbc2" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), |
704 | MUX8("sbc3" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), |
705 | MUX8("sbc4" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8), |
706 | MUX8("sbc5" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8), |
707 | MUX8("sbc6" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8), |
708 | MUX("sbc1" , mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9), |
709 | MUX("sbc2" , mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9), |
710 | MUX("sbc3" , mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9), |
711 | MUX("sbc4" , mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9), |
712 | MUX8("ndflash" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), |
713 | MUX8("ndspeed" , mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), |
714 | MUX8("hdmi" , mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), |
715 | MUX8("extern1" , mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, TEGRA_PERIPH_NO_RESET, tegra_clk_extern1), |
716 | MUX8("extern2" , mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, TEGRA_PERIPH_NO_RESET, tegra_clk_extern2), |
717 | MUX8("extern3" , mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, TEGRA_PERIPH_NO_RESET, tegra_clk_extern3), |
718 | MUX8("soc_therm" , mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), |
719 | MUX8("soc_therm" , mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8), |
720 | MUX8("vi_sensor" , mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), |
721 | MUX8("isp" , mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), |
722 | MUX8_NOGATE("isp" , mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9), |
723 | MUX8("entropy" , mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), |
724 | MUX8("entropy" , mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8), |
725 | MUX8("hdmi_audio" , mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), |
726 | MUX8("clk72mhz" , mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz), |
727 | MUX8("clk72mhz" , mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8), |
728 | MUX_FLAGS("csite" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), |
729 | MUX_FLAGS("csite" , mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED), |
730 | NODIV("disp1" , mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), |
731 | NODIV("disp1" , mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL), |
732 | NODIV("disp2" , mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), |
733 | NODIV("disp2" , mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL), |
734 | UART("uarta" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), |
735 | UART("uartb" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), |
736 | UART("uartc" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), |
737 | UART("uartd" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), |
738 | UART("uarte" , mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), |
739 | UART8("uarta" , mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8), |
740 | UART8("uartb" , mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8), |
741 | UART8("uartc" , mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8), |
742 | UART8("uartd" , mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8), |
743 | XUSB("xusb_host_src" , mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), |
744 | XUSB("xusb_host_src" , mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8), |
745 | XUSB("xusb_falcon_src" , mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), |
746 | XUSB("xusb_falcon_src" , mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8), |
747 | XUSB("xusb_fs_src" , mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), |
748 | XUSB("xusb_ss_src" , mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), |
749 | XUSB("xusb_ss_src" , mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8), |
750 | NODIV("xusb_hs_src" , mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL), |
751 | NODIV("xusb_hs_src" , mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL), |
752 | NODIV("xusb_ssp_src" , mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL), |
753 | XUSB("xusb_dev_src" , mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), |
754 | XUSB("xusb_dev_src" , mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8), |
755 | MUX8("dbgapb" , mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb), |
756 | MUX8("nvenc" , mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), |
757 | MUX8("nvdec" , mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), |
758 | MUX8("nvjpg" , mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), |
759 | MUX8("ape" , mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), |
760 | MUX8("sdmmc_legacy" , mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), |
761 | MUX8("qspi" , mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), |
762 | I2C("vii2c" , mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), |
763 | MUX("mipibif" , mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif), |
764 | MUX("uartape" , mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), |
765 | MUX8("tsecb" , mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), |
766 | MUX8("maud" , mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud), |
767 | MUX8("dmic1" , mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1), |
768 | MUX8("dmic2" , mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2), |
769 | MUX8("dmic3" , mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3), |
770 | }; |
771 | |
772 | static struct tegra_periph_init_data gate_clks[] = { |
773 | GATE("rtc" , "clk_32k" , 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), |
774 | GATE("timer" , "clk_m" , 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), |
775 | GATE("isp" , "clk_m" , 23, 0, tegra_clk_isp, 0), |
776 | GATE("vcp" , "clk_m" , 29, 0, tegra_clk_vcp, 0), |
777 | GATE("ahbdma" , "hclk" , 33, 0, tegra_clk_ahbdma, 0), |
778 | GATE("apbdma" , "pclk" , 34, 0, tegra_clk_apbdma, 0), |
779 | GATE("kbc" , "clk_32k" , 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), |
780 | GATE("fuse" , "clk_m" , 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), |
781 | GATE("fuse_burn" , "clk_m" , 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), |
782 | GATE("kfuse" , "clk_m" , 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), |
783 | GATE("apbif" , "clk_m" , 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), |
784 | GATE("hda2hdmi" , "clk_m" , 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0), |
785 | GATE("bsea" , "clk_m" , 62, 0, tegra_clk_bsea, 0), |
786 | GATE("bsev" , "clk_m" , 63, 0, tegra_clk_bsev, 0), |
787 | GATE("mipi-cal" , "clk72mhz" , 56, 0, tegra_clk_mipi_cal, 0), |
788 | GATE("usbd" , "clk_m" , 22, 0, tegra_clk_usbd, 0), |
789 | GATE("usb2" , "clk_m" , 58, 0, tegra_clk_usb2, 0), |
790 | GATE("usb3" , "clk_m" , 59, 0, tegra_clk_usb3, 0), |
791 | GATE("csi" , "pll_p_out3" , 52, 0, tegra_clk_csi, 0), |
792 | GATE("afi" , "mselect" , 72, 0, tegra_clk_afi, 0), |
793 | GATE("csus" , "clk_m" , 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), |
794 | GATE("dds" , "clk_m" , 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), |
795 | GATE("dp2" , "clk_m" , 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), |
796 | GATE("dtv" , "clk_m" , 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0), |
797 | GATE("xusb_host" , "xusb_host_src" , 89, 0, tegra_clk_xusb_host, 0), |
798 | GATE("xusb_ss" , "xusb_ss_src" , 156, 0, tegra_clk_xusb_ss, 0), |
799 | GATE("xusb_dev" , "xusb_dev_src" , 95, 0, tegra_clk_xusb_dev, 0), |
800 | GATE("emc" , "emc_mux" , 57, 0, tegra_clk_emc, CLK_IS_CRITICAL), |
801 | GATE("sata_cold" , "clk_m" , 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), |
802 | GATE("ispa" , "isp" , 23, 0, tegra_clk_ispa, 0), |
803 | GATE("ispb" , "isp" , 3, 0, tegra_clk_ispb, 0), |
804 | GATE("vim2_clk" , "clk_m" , 11, 0, tegra_clk_vim2_clk, 0), |
805 | GATE("pcie" , "clk_m" , 70, 0, tegra_clk_pcie, 0), |
806 | GATE("gpu" , "pll_ref" , 184, 0, tegra_clk_gpu, 0), |
807 | GATE("pllg_ref" , "pll_ref" , 189, 0, tegra_clk_pll_g_ref, 0), |
808 | GATE("hsic_trk" , "usb2_hsic_trk" , 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0), |
809 | GATE("usb2_trk" , "usb2_hsic_trk" , 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0), |
810 | GATE("xusb_gate" , "osc" , 143, 0, tegra_clk_xusb_gate, 0), |
811 | GATE("pll_p_out_cpu" , "pll_p" , 223, 0, tegra_clk_pll_p_out_cpu, 0), |
812 | GATE("pll_p_out_adsp" , "pll_p" , 187, 0, tegra_clk_pll_p_out_adsp, 0), |
813 | GATE("apb2ape" , "clk_m" , 107, 0, tegra_clk_apb2ape, 0), |
814 | GATE("cec" , "pclk" , 136, 0, tegra_clk_cec, 0), |
815 | GATE("iqc1" , "clk_m" , 221, 0, tegra_clk_iqc1, 0), |
816 | GATE("iqc2" , "clk_m" , 220, 0, tegra_clk_iqc1, 0), |
817 | GATE("pll_a_out_adsp" , "pll_a" , 188, 0, tegra_clk_pll_a_out_adsp, 0), |
818 | GATE("pll_a_out0_out_adsp" , "pll_a" , 188, 0, tegra_clk_pll_a_out0_out_adsp, 0), |
819 | GATE("adsp" , "aclk" , 199, 0, tegra_clk_adsp, 0), |
820 | GATE("adsp_neon" , "aclk" , 218, 0, tegra_clk_adsp_neon, 0), |
821 | }; |
822 | |
823 | static struct tegra_periph_init_data div_clks[] = { |
824 | DIV8("usb2_hsic_trk" , "osc" , CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0), |
825 | }; |
826 | |
827 | struct pll_out_data { |
828 | char *div_name; |
829 | char *pll_out_name; |
830 | u32 offset; |
831 | int clk_id; |
832 | u8 div_shift; |
833 | u8 div_flags; |
834 | u8 rst_shift; |
835 | spinlock_t *lock; |
836 | }; |
837 | |
838 | #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \ |
839 | {\ |
840 | .div_name = "pll_p_out" #_num "_div",\ |
841 | .pll_out_name = "pll_p_out" #_num,\ |
842 | .offset = _offset,\ |
843 | .div_shift = _div_shift,\ |
844 | .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\ |
845 | TEGRA_DIVIDER_ROUND_UP,\ |
846 | .rst_shift = _rst_shift,\ |
847 | .clk_id = tegra_clk_ ## _id,\ |
848 | .lock = &_offset ##_lock,\ |
849 | } |
850 | |
851 | static struct pll_out_data pllp_out_clks[] = { |
852 | PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1), |
853 | PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2), |
854 | PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int), |
855 | PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3), |
856 | PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4), |
857 | PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5), |
858 | }; |
859 | |
860 | static void __init periph_clk_init(void __iomem *clk_base, |
861 | struct tegra_clk *tegra_clks) |
862 | { |
863 | int i; |
864 | struct clk *clk; |
865 | struct clk **dt_clk; |
866 | |
867 | for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { |
868 | const struct tegra_clk_periph_regs *bank; |
869 | struct tegra_periph_init_data *data; |
870 | |
871 | data = periph_clks + i; |
872 | |
873 | dt_clk = tegra_lookup_dt_id(clk_id: data->clk_id, tegra_clk: tegra_clks); |
874 | if (!dt_clk) |
875 | continue; |
876 | |
877 | bank = get_reg_bank(clkid: data->periph.gate.clk_num); |
878 | if (!bank) |
879 | continue; |
880 | |
881 | data->periph.gate.regs = bank; |
882 | clk = tegra_clk_register_periph_data(clk_base, init: data); |
883 | *dt_clk = clk; |
884 | } |
885 | } |
886 | |
887 | static void __init gate_clk_init(void __iomem *clk_base, |
888 | struct tegra_clk *tegra_clks) |
889 | { |
890 | int i; |
891 | struct clk *clk; |
892 | struct clk **dt_clk; |
893 | |
894 | for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { |
895 | struct tegra_periph_init_data *data; |
896 | |
897 | data = gate_clks + i; |
898 | |
899 | dt_clk = tegra_lookup_dt_id(clk_id: data->clk_id, tegra_clk: tegra_clks); |
900 | if (!dt_clk) |
901 | continue; |
902 | |
903 | clk = tegra_clk_register_periph_gate(name: data->name, |
904 | parent_name: data->p.parent_name, gate_flags: data->periph.gate.flags, |
905 | clk_base, flags: data->flags, |
906 | clk_num: data->periph.gate.clk_num, |
907 | enable_refcnt: periph_clk_enb_refcnt); |
908 | *dt_clk = clk; |
909 | } |
910 | } |
911 | |
912 | static void __init div_clk_init(void __iomem *clk_base, |
913 | struct tegra_clk *tegra_clks) |
914 | { |
915 | int i; |
916 | struct clk *clk; |
917 | struct clk **dt_clk; |
918 | |
919 | for (i = 0; i < ARRAY_SIZE(div_clks); i++) { |
920 | struct tegra_periph_init_data *data; |
921 | |
922 | data = div_clks + i; |
923 | |
924 | dt_clk = tegra_lookup_dt_id(clk_id: data->clk_id, tegra_clk: tegra_clks); |
925 | if (!dt_clk) |
926 | continue; |
927 | |
928 | clk = tegra_clk_register_divider(name: data->name, |
929 | parent_name: data->p.parent_name, reg: clk_base + data->offset, |
930 | flags: data->flags, clk_divider_flags: data->periph.divider.flags, |
931 | shift: data->periph.divider.shift, |
932 | width: data->periph.divider.width, |
933 | frac_width: data->periph.divider.frac_width, |
934 | lock: data->periph.divider.lock); |
935 | *dt_clk = clk; |
936 | } |
937 | } |
938 | |
939 | static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, |
940 | struct tegra_clk *tegra_clks, |
941 | struct tegra_clk_pll_params *pll_params) |
942 | { |
943 | struct clk *clk; |
944 | struct clk **dt_clk; |
945 | int i; |
946 | |
947 | dt_clk = tegra_lookup_dt_id(clk_id: tegra_clk_pll_p, tegra_clk: tegra_clks); |
948 | if (dt_clk) { |
949 | /* PLLP */ |
950 | clk = tegra_clk_register_pll(name: "pll_p" , parent_name: "pll_ref" , clk_base, |
951 | pmc: pmc_base, flags: 0, pll_params, NULL); |
952 | clk_register_clkdev(clk, "pll_p" , NULL); |
953 | *dt_clk = clk; |
954 | } |
955 | |
956 | for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) { |
957 | struct pll_out_data *data; |
958 | |
959 | data = pllp_out_clks + i; |
960 | |
961 | dt_clk = tegra_lookup_dt_id(clk_id: data->clk_id, tegra_clk: tegra_clks); |
962 | if (!dt_clk) |
963 | continue; |
964 | |
965 | clk = tegra_clk_register_divider(name: data->div_name, parent_name: "pll_p" , |
966 | reg: clk_base + data->offset, flags: 0, clk_divider_flags: data->div_flags, |
967 | shift: data->div_shift, width: 8, frac_width: 1, lock: data->lock); |
968 | clk = tegra_clk_register_pll_out(name: data->pll_out_name, |
969 | parent_name: data->div_name, reg: clk_base + data->offset, |
970 | enb_bit_idx: data->rst_shift + 1, rst_bit_idx: data->rst_shift, |
971 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, pll_div_flags: 0, |
972 | lock: data->lock); |
973 | *dt_clk = clk; |
974 | } |
975 | |
976 | dt_clk = tegra_lookup_dt_id(clk_id: tegra_clk_pll_p_out_cpu, |
977 | tegra_clk: tegra_clks); |
978 | if (dt_clk) { |
979 | /* |
980 | * Tegra210 has control on enabling/disabling PLLP branches to |
981 | * CPU, register a gate clock "pll_p_out_cpu" for this gating |
982 | * function and parent "pll_p_out4" to it, so when we are |
983 | * re-parenting CPU off from "pll_p_out4" the PLLP branching to |
984 | * CPU can be disabled automatically. |
985 | */ |
986 | clk = tegra_clk_register_divider(name: "pll_p_out4_div" , |
987 | parent_name: "pll_p_out_cpu" , reg: clk_base + PLLP_OUTB, flags: 0, clk_divider_flags: 0, shift: 24, |
988 | width: 8, frac_width: 1, lock: &PLLP_OUTB_lock); |
989 | |
990 | dt_clk = tegra_lookup_dt_id(clk_id: tegra_clk_pll_p_out4_cpu, tegra_clk: tegra_clks); |
991 | if (dt_clk) { |
992 | clk = tegra_clk_register_pll_out(name: "pll_p_out4" , |
993 | parent_name: "pll_p_out4_div" , reg: clk_base + PLLP_OUTB, |
994 | enb_bit_idx: 17, rst_bit_idx: 16, CLK_IGNORE_UNUSED | |
995 | CLK_SET_RATE_PARENT, pll_div_flags: 0, |
996 | lock: &PLLP_OUTB_lock); |
997 | *dt_clk = clk; |
998 | } |
999 | } |
1000 | |
1001 | dt_clk = tegra_lookup_dt_id(clk_id: tegra_clk_pll_p_out_hsio, tegra_clk: tegra_clks); |
1002 | if (dt_clk) { |
1003 | /* PLLP_OUT_HSIO */ |
1004 | clk = clk_register_gate(NULL, name: "pll_p_out_hsio" , parent_name: "pll_p" , |
1005 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
1006 | reg: clk_base + PLLP_MISC1, bit_idx: 29, clk_gate_flags: 0, NULL); |
1007 | *dt_clk = clk; |
1008 | } |
1009 | |
1010 | dt_clk = tegra_lookup_dt_id(clk_id: tegra_clk_pll_p_out_xusb, tegra_clk: tegra_clks); |
1011 | if (dt_clk) { |
1012 | /* PLLP_OUT_XUSB */ |
1013 | clk = clk_register_gate(NULL, name: "pll_p_out_xusb" , |
1014 | parent_name: "pll_p_out_hsio" , CLK_SET_RATE_PARENT | |
1015 | CLK_IGNORE_UNUSED, reg: clk_base + PLLP_MISC1, bit_idx: 28, clk_gate_flags: 0, |
1016 | NULL); |
1017 | clk_register_clkdev(clk, "pll_p_out_xusb" , NULL); |
1018 | *dt_clk = clk; |
1019 | } |
1020 | } |
1021 | |
1022 | void __init tegra_periph_clk_init(void __iomem *clk_base, |
1023 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, |
1024 | struct tegra_clk_pll_params *pll_params) |
1025 | { |
1026 | init_pllp(clk_base, pmc_base, tegra_clks, pll_params); |
1027 | periph_clk_init(clk_base, tegra_clks); |
1028 | gate_clk_init(clk_base, tegra_clks); |
1029 | div_clk_init(clk_base, tegra_clks); |
1030 | } |
1031 | |