1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
5 *
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8 * setup events, or directly accessed using MMIO registers.
9 */
10
11#define pr_fmt(fmt) "riscv-timer: " fmt
12
13#include <linux/acpi.h>
14#include <linux/clocksource.h>
15#include <linux/clockchips.h>
16#include <linux/cpu.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/sched_clock.h>
22#include <linux/io-64-nonatomic-lo-hi.h>
23#include <linux/interrupt.h>
24#include <linux/of_irq.h>
25#include <linux/limits.h>
26#include <clocksource/timer-riscv.h>
27#include <asm/smp.h>
28#include <asm/hwcap.h>
29#include <asm/sbi.h>
30#include <asm/timex.h>
31
32static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
33static bool riscv_timer_cannot_wake_cpu;
34
35static void riscv_clock_event_stop(void)
36{
37 if (static_branch_likely(&riscv_sstc_available)) {
38 csr_write(CSR_STIMECMP, ULONG_MAX);
39 if (IS_ENABLED(CONFIG_32BIT))
40 csr_write(CSR_STIMECMPH, ULONG_MAX);
41 } else {
42 sbi_set_timer(U64_MAX);
43 }
44}
45
46static int riscv_clock_next_event(unsigned long delta,
47 struct clock_event_device *ce)
48{
49 u64 next_tval = get_cycles64() + delta;
50
51 if (static_branch_likely(&riscv_sstc_available)) {
52#if defined(CONFIG_32BIT)
53 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
54 csr_write(CSR_STIMECMPH, next_tval >> 32);
55#else
56 csr_write(CSR_STIMECMP, next_tval);
57#endif
58 } else
59 sbi_set_timer(next_tval);
60
61 return 0;
62}
63
64static unsigned int riscv_clock_event_irq;
65static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
66 .name = "riscv_timer_clockevent",
67 .features = CLOCK_EVT_FEAT_ONESHOT,
68 .rating = 100,
69 .set_next_event = riscv_clock_next_event,
70};
71
72/*
73 * It is guaranteed that all the timers across all the harts are synchronized
74 * within one tick of each other, so while this could technically go
75 * backwards when hopping between CPUs, practically it won't happen.
76 */
77static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
78{
79 return get_cycles64();
80}
81
82static u64 notrace riscv_sched_clock(void)
83{
84 return get_cycles64();
85}
86
87static struct clocksource riscv_clocksource = {
88 .name = "riscv_clocksource",
89 .rating = 400,
90 .mask = CLOCKSOURCE_MASK(64),
91 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
92 .read = riscv_clocksource_rdtime,
93#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
94 .vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
95#else
96 .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
97#endif
98};
99
100static int riscv_timer_starting_cpu(unsigned int cpu)
101{
102 struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
103
104 ce->cpumask = cpumask_of(cpu);
105 ce->irq = riscv_clock_event_irq;
106 if (riscv_timer_cannot_wake_cpu)
107 ce->features |= CLOCK_EVT_FEAT_C3STOP;
108 if (static_branch_likely(&riscv_sstc_available))
109 ce->rating = 450;
110 clockevents_config_and_register(dev: ce, freq: riscv_timebase, min_delta: 100, max_delta: 0x7fffffff);
111
112 enable_percpu_irq(irq: riscv_clock_event_irq,
113 type: irq_get_trigger_type(irq: riscv_clock_event_irq));
114 return 0;
115}
116
117static int riscv_timer_dying_cpu(unsigned int cpu)
118{
119 disable_percpu_irq(irq: riscv_clock_event_irq);
120 return 0;
121}
122
123void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
124{
125 *mult = riscv_clocksource.mult;
126 *shift = riscv_clocksource.shift;
127}
128EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
129
130/* called directly from the low-level interrupt handler */
131static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
132{
133 struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
134
135 riscv_clock_event_stop();
136 evdev->event_handler(evdev);
137
138 return IRQ_HANDLED;
139}
140
141static int __init riscv_timer_init_common(void)
142{
143 int error;
144 struct irq_domain *domain;
145 struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
146
147 domain = irq_find_matching_fwnode(fwnode: intc_fwnode, bus_token: DOMAIN_BUS_ANY);
148 if (!domain) {
149 pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
150 intc_fwnode);
151 return -ENODEV;
152 }
153
154 riscv_clock_event_irq = irq_create_mapping(host: domain, hwirq: RV_IRQ_TIMER);
155 if (!riscv_clock_event_irq) {
156 pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
157 return -ENODEV;
158 }
159
160 error = clocksource_register_hz(cs: &riscv_clocksource, hz: riscv_timebase);
161 if (error) {
162 pr_err("RISCV timer registration failed [%d]\n", error);
163 return error;
164 }
165
166 sched_clock_register(read: riscv_sched_clock, bits: 64, rate: riscv_timebase);
167
168 error = request_percpu_irq(irq: riscv_clock_event_irq,
169 handler: riscv_timer_interrupt,
170 devname: "riscv-timer", percpu_dev_id: &riscv_clock_event);
171 if (error) {
172 pr_err("registering percpu irq failed [%d]\n", error);
173 return error;
174 }
175
176 if (riscv_isa_extension_available(NULL, SSTC)) {
177 pr_info("Timer interrupt in S-mode is available via sstc extension\n");
178 static_branch_enable(&riscv_sstc_available);
179 }
180
181 error = cpuhp_setup_state(state: CPUHP_AP_RISCV_TIMER_STARTING,
182 name: "clockevents/riscv/timer:starting",
183 startup: riscv_timer_starting_cpu, teardown: riscv_timer_dying_cpu);
184 if (error)
185 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
186 error);
187
188 return error;
189}
190
191static int __init riscv_timer_init_dt(struct device_node *n)
192{
193 int cpuid, error;
194 unsigned long hartid;
195 struct device_node *child;
196
197 error = riscv_of_processor_hartid(n, &hartid);
198 if (error < 0) {
199 pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
200 n, hartid);
201 return error;
202 }
203
204 cpuid = riscv_hartid_to_cpuid(hartid);
205 if (cpuid < 0) {
206 pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
207 return cpuid;
208 }
209
210 if (cpuid != smp_processor_id())
211 return 0;
212
213 child = of_find_compatible_node(NULL, NULL, compat: "riscv,timer");
214 if (child) {
215 riscv_timer_cannot_wake_cpu = of_property_read_bool(np: child,
216 propname: "riscv,timer-cannot-wake-cpu");
217 of_node_put(node: child);
218 }
219
220 return riscv_timer_init_common();
221}
222
223TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
224
225#ifdef CONFIG_ACPI
226static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
227{
228 struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table;
229
230 riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;
231
232 return riscv_timer_init_common();
233}
234
235TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
236
237#endif
238

source code of linux/drivers/clocksource/timer-riscv.c