1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2016 Cavium, Inc. |
4 | */ |
5 | |
6 | #ifndef __CPT_COMMON_H |
7 | #define __CPT_COMMON_H |
8 | |
9 | #include <asm/byteorder.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/pci.h> |
12 | |
13 | #include "cpt_hw_types.h" |
14 | |
15 | /* Device ID */ |
16 | #define CPT_81XX_PCI_PF_DEVICE_ID 0xa040 |
17 | #define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 |
18 | |
19 | /* flags to indicate the features supported */ |
20 | #define CPT_FLAG_SRIOV_ENABLED BIT(1) |
21 | #define CPT_FLAG_VF_DRIVER BIT(2) |
22 | #define CPT_FLAG_DEVICE_READY BIT(3) |
23 | |
24 | #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED) |
25 | #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER) |
26 | #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY) |
27 | |
28 | #define CPT_MBOX_MSG_TYPE_ACK 1 |
29 | #define CPT_MBOX_MSG_TYPE_NACK 2 |
30 | #define CPT_MBOX_MSG_TIMEOUT 2000 |
31 | #define VF_STATE_DOWN 0 |
32 | #define VF_STATE_UP 1 |
33 | |
34 | /* |
35 | * CPT Registers map for 81xx |
36 | */ |
37 | |
38 | /* PF registers */ |
39 | #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36)) |
40 | #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36)) |
41 | #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36)) |
42 | #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36)) |
43 | #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36)) |
44 | #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36)) |
45 | #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36)) |
46 | #define CPTX_PF_ECC0_INT_W1S(a) (0x230ll + ((u64)(a) << 36)) |
47 | #define CPTX_PF_ECC0_ENA_W1S(a) (0x240ll + ((u64)(a) << 36)) |
48 | #define CPTX_PF_ECC0_ENA_W1C(a) (0x250ll + ((u64)(a) << 36)) |
49 | #define CPTX_PF_MBOX_INTX(a, b) \ |
50 | (0x400ll + ((u64)(a) << 36) + ((b) << 3)) |
51 | #define CPTX_PF_MBOX_INT_W1SX(a, b) \ |
52 | (0x420ll + ((u64)(a) << 36) + ((b) << 3)) |
53 | #define CPTX_PF_MBOX_ENA_W1CX(a, b) \ |
54 | (0x440ll + ((u64)(a) << 36) + ((b) << 3)) |
55 | #define CPTX_PF_MBOX_ENA_W1SX(a, b) \ |
56 | (0x460ll + ((u64)(a) << 36) + ((b) << 3)) |
57 | #define CPTX_PF_EXEC_INT(a) (0x500ll + 0x1000000000ll * ((a) & 0x1)) |
58 | #define CPTX_PF_EXEC_INT_W1S(a) (0x520ll + ((u64)(a) << 36)) |
59 | #define CPTX_PF_EXEC_ENA_W1C(a) (0x540ll + ((u64)(a) << 36)) |
60 | #define CPTX_PF_EXEC_ENA_W1S(a) (0x560ll + ((u64)(a) << 36)) |
61 | #define CPTX_PF_GX_EN(a, b) \ |
62 | (0x600ll + ((u64)(a) << 36) + ((b) << 3)) |
63 | #define CPTX_PF_EXEC_INFO(a) (0x700ll + ((u64)(a) << 36)) |
64 | #define CPTX_PF_EXEC_BUSY(a) (0x800ll + ((u64)(a) << 36)) |
65 | #define CPTX_PF_EXEC_INFO0(a) (0x900ll + ((u64)(a) << 36)) |
66 | #define CPTX_PF_EXEC_INFO1(a) (0x910ll + ((u64)(a) << 36)) |
67 | #define CPTX_PF_INST_REQ_PC(a) (0x10000ll + ((u64)(a) << 36)) |
68 | #define CPTX_PF_INST_LATENCY_PC(a) \ |
69 | (0x10020ll + ((u64)(a) << 36)) |
70 | #define CPTX_PF_RD_REQ_PC(a) (0x10040ll + ((u64)(a) << 36)) |
71 | #define CPTX_PF_RD_LATENCY_PC(a) (0x10060ll + ((u64)(a) << 36)) |
72 | #define CPTX_PF_RD_UC_PC(a) (0x10080ll + ((u64)(a) << 36)) |
73 | #define CPTX_PF_ACTIVE_CYCLES_PC(a) (0x10100ll + ((u64)(a) << 36)) |
74 | #define CPTX_PF_EXE_CTL(a) (0x4000000ll + ((u64)(a) << 36)) |
75 | #define CPTX_PF_EXE_STATUS(a) (0x4000008ll + ((u64)(a) << 36)) |
76 | #define CPTX_PF_EXE_CLK(a) (0x4000010ll + ((u64)(a) << 36)) |
77 | #define CPTX_PF_EXE_DBG_CTL(a) (0x4000018ll + ((u64)(a) << 36)) |
78 | #define CPTX_PF_EXE_DBG_DATA(a) (0x4000020ll + ((u64)(a) << 36)) |
79 | #define CPTX_PF_EXE_BIST_STATUS(a) (0x4000028ll + ((u64)(a) << 36)) |
80 | #define CPTX_PF_EXE_REQ_TIMER(a) (0x4000030ll + ((u64)(a) << 36)) |
81 | #define CPTX_PF_EXE_MEM_CTL(a) (0x4000038ll + ((u64)(a) << 36)) |
82 | #define CPTX_PF_EXE_PERF_CTL(a) (0x4001000ll + ((u64)(a) << 36)) |
83 | #define CPTX_PF_EXE_DBG_CNTX(a, b) \ |
84 | (0x4001100ll + ((u64)(a) << 36) + ((b) << 3)) |
85 | #define CPTX_PF_EXE_PERF_EVENT_CNT(a) (0x4001180ll + ((u64)(a) << 36)) |
86 | #define CPTX_PF_EXE_EPCI_INBX_CNT(a, b) \ |
87 | (0x4001200ll + ((u64)(a) << 36) + ((b) << 3)) |
88 | #define CPTX_PF_EXE_EPCI_OUTBX_CNT(a, b) \ |
89 | (0x4001240ll + ((u64)(a) << 36) + ((b) << 3)) |
90 | #define CPTX_PF_ENGX_UCODE_BASE(a, b) \ |
91 | (0x4002000ll + ((u64)(a) << 36) + ((b) << 3)) |
92 | #define CPTX_PF_QX_CTL(a, b) \ |
93 | (0x8000000ll + ((u64)(a) << 36) + ((b) << 20)) |
94 | #define CPTX_PF_QX_GMCTL(a, b) \ |
95 | (0x8000020ll + ((u64)(a) << 36) + ((b) << 20)) |
96 | #define CPTX_PF_QX_CTL2(a, b) \ |
97 | (0x8000100ll + ((u64)(a) << 36) + ((b) << 20)) |
98 | #define CPTX_PF_VFX_MBOXX(a, b, c) \ |
99 | (0x8001000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 8)) |
100 | |
101 | /* VF registers */ |
102 | #define CPTX_VQX_CTL(a, b) (0x100ll + ((u64)(a) << 36) + ((b) << 20)) |
103 | #define CPTX_VQX_SADDR(a, b) (0x200ll + ((u64)(a) << 36) + ((b) << 20)) |
104 | #define CPTX_VQX_DONE_WAIT(a, b) (0x400ll + ((u64)(a) << 36) + ((b) << 20)) |
105 | #define CPTX_VQX_INPROG(a, b) (0x410ll + ((u64)(a) << 36) + ((b) << 20)) |
106 | #define CPTX_VQX_DONE(a, b) (0x420ll + ((u64)(a) << 36) + ((b) << 20)) |
107 | #define CPTX_VQX_DONE_ACK(a, b) (0x440ll + ((u64)(a) << 36) + ((b) << 20)) |
108 | #define CPTX_VQX_DONE_INT_W1S(a, b) (0x460ll + ((u64)(a) << 36) + ((b) << 20)) |
109 | #define CPTX_VQX_DONE_INT_W1C(a, b) (0x468ll + ((u64)(a) << 36) + ((b) << 20)) |
110 | #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x470ll + ((u64)(a) << 36) + ((b) << 20)) |
111 | #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x478ll + ((u64)(a) << 36) + ((b) << 20)) |
112 | #define CPTX_VQX_MISC_INT(a, b) (0x500ll + ((u64)(a) << 36) + ((b) << 20)) |
113 | #define CPTX_VQX_MISC_INT_W1S(a, b) (0x508ll + ((u64)(a) << 36) + ((b) << 20)) |
114 | #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x510ll + ((u64)(a) << 36) + ((b) << 20)) |
115 | #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x518ll + ((u64)(a) << 36) + ((b) << 20)) |
116 | #define CPTX_VQX_DOORBELL(a, b) (0x600ll + ((u64)(a) << 36) + ((b) << 20)) |
117 | #define CPTX_VFX_PF_MBOXX(a, b, c) \ |
118 | (0x1000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 3)) |
119 | |
120 | enum vftype { |
121 | AE_TYPES = 1, |
122 | SE_TYPES = 2, |
123 | BAD_CPT_TYPES, |
124 | }; |
125 | |
126 | /* Max CPT devices supported */ |
127 | enum cpt_mbox_opcode { |
128 | CPT_MSG_VF_UP = 1, |
129 | CPT_MSG_VF_DOWN, |
130 | CPT_MSG_READY, |
131 | CPT_MSG_QLEN, |
132 | CPT_MSG_QBIND_GRP, |
133 | CPT_MSG_VQ_PRIORITY, |
134 | }; |
135 | |
136 | /* CPT mailbox structure */ |
137 | struct cpt_mbox { |
138 | u64 msg; /* Message type MBOX[0] */ |
139 | u64 data;/* Data MBOX[1] */ |
140 | }; |
141 | |
142 | /* Register read/write APIs */ |
143 | static inline void cpt_write_csr64(u8 __iomem *hw_addr, u64 offset, |
144 | u64 val) |
145 | { |
146 | writeq(val, addr: hw_addr + offset); |
147 | } |
148 | |
149 | static inline u64 cpt_read_csr64(u8 __iomem *hw_addr, u64 offset) |
150 | { |
151 | return readq(addr: hw_addr + offset); |
152 | } |
153 | #endif /* __CPT_COMMON_H */ |
154 | |