1/***********************license start************************************
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44 ***********************license end**************************************/
45
46#ifndef __ZIP_MAIN_H__
47#define __ZIP_MAIN_H__
48
49#include "zip_device.h"
50#include "zip_regs.h"
51
52/* PCI device IDs */
53#define PCI_DEVICE_ID_THUNDERX_ZIP 0xA01A
54
55/* ZIP device BARs */
56#define PCI_CFG_ZIP_PF_BAR0 0 /* Base addr for normal regs */
57
58/* Maximum available zip queues */
59#define ZIP_MAX_NUM_QUEUES 8
60
61#define ZIP_128B_ALIGN 7
62
63/* Command queue buffer size */
64#define ZIP_CMD_QBUF_SIZE (8064 + 8)
65
66struct zip_registers {
67 char *reg_name;
68 u64 reg_offset;
69};
70
71/* ZIP Compression - Decompression stats */
72struct zip_stats {
73 atomic64_t comp_req_submit;
74 atomic64_t comp_req_complete;
75 atomic64_t decomp_req_submit;
76 atomic64_t decomp_req_complete;
77 atomic64_t comp_in_bytes;
78 atomic64_t comp_out_bytes;
79 atomic64_t decomp_in_bytes;
80 atomic64_t decomp_out_bytes;
81 atomic64_t decomp_bad_reqs;
82};
83
84/* ZIP Instruction Queue */
85struct zip_iq {
86 u64 *sw_head;
87 u64 *sw_tail;
88 u64 *hw_tail;
89 u64 done_cnt;
90 u64 pend_cnt;
91 u64 free_flag;
92
93 /* ZIP IQ lock */
94 spinlock_t lock;
95};
96
97/* ZIP Device */
98struct zip_device {
99 u32 index;
100 void __iomem *reg_base;
101 struct pci_dev *pdev;
102
103 /* Different ZIP Constants */
104 u64 depth;
105 u64 onfsize;
106 u64 ctxsize;
107
108 struct zip_iq iq[ZIP_MAX_NUM_QUEUES];
109 struct zip_stats stats;
110};
111
112/* Prototypes */
113struct zip_device *zip_get_device(int node_id);
114int zip_get_node_id(void);
115void zip_reg_write(u64 val, u64 __iomem *addr);
116u64 zip_reg_read(u64 __iomem *addr);
117void zip_update_cmd_bufs(struct zip_device *zip_dev, u32 queue);
118u32 zip_load_instr(union zip_inst_s *instr, struct zip_device *zip_dev);
119
120#endif /* ZIP_MAIN_H */
121

source code of linux/drivers/crypto/cavium/zip/zip_main.h