1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright 2019 NXP */ |
3 | |
4 | #ifndef __DPAA2_QDMA_H |
5 | #define __DPAA2_QDMA_H |
6 | |
7 | #define DPAA2_QDMA_STORE_SIZE 16 |
8 | #define NUM_CH 8 |
9 | |
10 | struct dpaa2_qdma_sd_d { |
11 | u32 rsv:32; |
12 | union { |
13 | struct { |
14 | u32 ssd:12; /* souce stride distance */ |
15 | u32 sss:12; /* souce stride size */ |
16 | u32 rsv1:8; |
17 | } sdf; |
18 | struct { |
19 | u32 dsd:12; /* Destination stride distance */ |
20 | u32 dss:12; /* Destination stride size */ |
21 | u32 rsv2:8; |
22 | } ddf; |
23 | } df; |
24 | u32 rbpcmd; /* Route-by-port command */ |
25 | u32 cmd; |
26 | } __attribute__((__packed__)); |
27 | |
28 | /* Source descriptor command read transaction type for RBP=0: */ |
29 | /* coherent copy of cacheable memory */ |
30 | #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28) |
31 | /* Destination descriptor command write transaction type for RBP=0: */ |
32 | /* coherent copy of cacheable memory */ |
33 | #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28) |
34 | #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28) |
35 | |
36 | #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */ |
37 | #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */ |
38 | #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */ |
39 | #define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */ |
40 | #define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */ |
41 | |
42 | #define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */ |
43 | #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */ |
44 | |
45 | #define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */ |
46 | #define QDMA_FD_LONG_FORMAT (0) /* long format */ |
47 | #define QDMA_SER_DISABLE (8) /* no notification */ |
48 | #define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */ |
49 | #define QDMA_SER_DEST (2 << 8) /* notification by destination desc */ |
50 | #define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */ |
51 | #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */ |
52 | |
53 | #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */ |
54 | #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */ |
55 | /* Flow Context: 49bit physical address */ |
56 | #define QMAN_FD_CBMT_ENABLE BIT(15) |
57 | #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */ |
58 | #define QMAN_FD_SC_DISABLE (0) /* stashing control */ |
59 | |
60 | #define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */ |
61 | #define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */ |
62 | #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */ |
63 | #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */ |
64 | #define QDMA_FL_SL_LONG (0x0)/* long length */ |
65 | #define QDMA_FL_SL_SHORT (0x1) /* short length */ |
66 | #define QDMA_FL_F (0x1)/* last frame list bit */ |
67 | |
68 | /*Description of Frame list table structure*/ |
69 | struct dpaa2_qdma_chan { |
70 | struct dpaa2_qdma_engine *qdma; |
71 | struct virt_dma_chan vchan; |
72 | struct virt_dma_desc vdesc; |
73 | enum dma_status status; |
74 | u32 fqid; |
75 | |
76 | /* spinlock used by dpaa2 qdma driver */ |
77 | spinlock_t queue_lock; |
78 | struct dma_pool *fd_pool; |
79 | struct dma_pool *fl_pool; |
80 | struct dma_pool *sdd_pool; |
81 | |
82 | struct list_head comp_used; |
83 | struct list_head comp_free; |
84 | |
85 | }; |
86 | |
87 | struct dpaa2_qdma_comp { |
88 | dma_addr_t fd_bus_addr; |
89 | dma_addr_t fl_bus_addr; |
90 | dma_addr_t desc_bus_addr; |
91 | struct dpaa2_fd *fd_virt_addr; |
92 | struct dpaa2_fl_entry *fl_virt_addr; |
93 | struct dpaa2_qdma_sd_d *desc_virt_addr; |
94 | struct dpaa2_qdma_chan *qchan; |
95 | struct virt_dma_desc vdesc; |
96 | struct list_head list; |
97 | }; |
98 | |
99 | struct dpaa2_qdma_engine { |
100 | struct dma_device dma_dev; |
101 | u32 n_chans; |
102 | struct dpaa2_qdma_chan chans[NUM_CH]; |
103 | int qdma_wrtype_fixup; |
104 | int desc_allocated; |
105 | |
106 | struct dpaa2_qdma_priv *priv; |
107 | }; |
108 | |
109 | /* |
110 | * dpaa2_qdma_priv - driver private data |
111 | */ |
112 | struct dpaa2_qdma_priv { |
113 | int dpqdma_id; |
114 | |
115 | struct iommu_domain *iommu_domain; |
116 | struct dpdmai_attr dpdmai_attr; |
117 | struct device *dev; |
118 | struct fsl_mc_io *mc_io; |
119 | struct fsl_mc_device *dpdmai_dev; |
120 | u8 num_pairs; |
121 | |
122 | struct dpaa2_qdma_engine *dpaa2_qdma; |
123 | struct dpaa2_qdma_priv_per_prio *ppriv; |
124 | |
125 | struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; |
126 | u32 tx_fqid[DPDMAI_PRIO_NUM]; |
127 | }; |
128 | |
129 | struct dpaa2_qdma_priv_per_prio { |
130 | int req_fqid; |
131 | int rsp_fqid; |
132 | int prio; |
133 | |
134 | struct dpaa2_io_store *store; |
135 | struct dpaa2_io_notification_ctx nctx; |
136 | |
137 | struct dpaa2_qdma_priv *priv; |
138 | }; |
139 | |
140 | static struct soc_device_attribute soc_fixup_tuning[] = { |
141 | { .family = "QorIQ LX2160A" }, |
142 | { /* sentinel */ } |
143 | }; |
144 | |
145 | /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */ |
146 | #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \ |
147 | sizeof(struct dpaa2_fl_entry) * 3 + \ |
148 | sizeof(struct dpaa2_qdma_sd_d) * 2) |
149 | |
150 | static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma); |
151 | static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, |
152 | struct list_head *head); |
153 | #endif /* __DPAA2_QDMA_H */ |
154 | |