1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * DMA driver header for STMicroelectronics STi FDMA controller |
4 | * |
5 | * Copyright (C) 2014 STMicroelectronics |
6 | * |
7 | * Author: Ludovic Barre <Ludovic.barre@st.com> |
8 | */ |
9 | #ifndef __DMA_ST_FDMA_H |
10 | #define __DMA_ST_FDMA_H |
11 | |
12 | #include <linux/dmaengine.h> |
13 | #include <linux/dmapool.h> |
14 | #include <linux/io.h> |
15 | #include <linux/remoteproc/st_slim_rproc.h> |
16 | #include "virt-dma.h" |
17 | |
18 | #define ST_FDMA_NR_DREQS 32 |
19 | #define FW_NAME_SIZE 30 |
20 | #define DRIVER_NAME "st-fdma" |
21 | |
22 | /** |
23 | * struct st_fdma_generic_node - Free running/paced generic node |
24 | * |
25 | * @length: Length in bytes of a line in a 2D mem to mem |
26 | * @sstride: Stride, in bytes, between source lines in a 2D data move |
27 | * @dstride: Stride, in bytes, between destination lines in a 2D data move |
28 | */ |
29 | struct st_fdma_generic_node { |
30 | u32 length; |
31 | u32 sstride; |
32 | u32 dstride; |
33 | }; |
34 | |
35 | /** |
36 | * struct st_fdma_hw_node - Node structure used by fdma hw |
37 | * |
38 | * @next: Pointer to next node |
39 | * @control: Transfer Control Parameters |
40 | * @nbytes: Number of Bytes to read |
41 | * @saddr: Source address |
42 | * @daddr: Destination address |
43 | * |
44 | * @generic: generic node for free running/paced transfert type |
45 | * 2 others transfert type are possible, but not yet implemented |
46 | * |
47 | * The NODE structures must be aligned to a 32 byte boundary |
48 | */ |
49 | struct st_fdma_hw_node { |
50 | u32 next; |
51 | u32 control; |
52 | u32 nbytes; |
53 | u32 saddr; |
54 | u32 daddr; |
55 | union { |
56 | struct st_fdma_generic_node generic; |
57 | }; |
58 | } __aligned(32); |
59 | |
60 | /* |
61 | * node control parameters |
62 | */ |
63 | #define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0) |
64 | #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0 |
65 | #define FDMA_NODE_CTRL_REQ_MAP_DREQ(n) ((n)&FDMA_NODE_CTRL_REQ_MAP_MASK) |
66 | #define FDMA_NODE_CTRL_REQ_MAP_EXT FDMA_NODE_CTRL_REQ_MAP_MASK |
67 | #define FDMA_NODE_CTRL_SRC_MASK GENMASK(6, 5) |
68 | #define FDMA_NODE_CTRL_SRC_STATIC BIT(5) |
69 | #define FDMA_NODE_CTRL_SRC_INCR BIT(6) |
70 | #define FDMA_NODE_CTRL_DST_MASK GENMASK(8, 7) |
71 | #define FDMA_NODE_CTRL_DST_STATIC BIT(7) |
72 | #define FDMA_NODE_CTRL_DST_INCR BIT(8) |
73 | #define FDMA_NODE_CTRL_SECURE BIT(15) |
74 | #define FDMA_NODE_CTRL_PAUSE_EON BIT(30) |
75 | #define FDMA_NODE_CTRL_INT_EON BIT(31) |
76 | |
77 | /** |
78 | * struct st_fdma_sw_node - descriptor structure for link list |
79 | * |
80 | * @pdesc: Physical address of desc |
81 | * @node: link used for putting this into a channel queue |
82 | */ |
83 | struct st_fdma_sw_node { |
84 | dma_addr_t pdesc; |
85 | struct st_fdma_hw_node *desc; |
86 | }; |
87 | |
88 | #define NAME_SZ 10 |
89 | |
90 | struct st_fdma_driverdata { |
91 | u32 id; |
92 | char name[NAME_SZ]; |
93 | }; |
94 | |
95 | struct st_fdma_desc { |
96 | struct virt_dma_desc vdesc; |
97 | struct st_fdma_chan *fchan; |
98 | bool iscyclic; |
99 | unsigned int n_nodes; |
100 | struct st_fdma_sw_node node[] __counted_by(n_nodes); |
101 | }; |
102 | |
103 | enum st_fdma_type { |
104 | ST_FDMA_TYPE_FREE_RUN, |
105 | ST_FDMA_TYPE_PACED, |
106 | }; |
107 | |
108 | struct st_fdma_cfg { |
109 | struct device_node *of_node; |
110 | enum st_fdma_type type; |
111 | dma_addr_t dev_addr; |
112 | enum dma_transfer_direction dir; |
113 | int req_line; /* request line */ |
114 | long req_ctrl; /* Request control */ |
115 | }; |
116 | |
117 | struct st_fdma_chan { |
118 | struct st_fdma_dev *fdev; |
119 | struct dma_pool *node_pool; |
120 | struct dma_slave_config scfg; |
121 | struct st_fdma_cfg cfg; |
122 | |
123 | int dreq_line; |
124 | |
125 | struct virt_dma_chan vchan; |
126 | struct st_fdma_desc *fdesc; |
127 | enum dma_status status; |
128 | }; |
129 | |
130 | struct st_fdma_dev { |
131 | struct device *dev; |
132 | const struct st_fdma_driverdata *drvdata; |
133 | struct dma_device dma_device; |
134 | |
135 | struct st_slim_rproc *slim_rproc; |
136 | |
137 | int irq; |
138 | |
139 | struct st_fdma_chan *chans; |
140 | |
141 | spinlock_t dreq_lock; |
142 | unsigned long dreq_mask; |
143 | |
144 | u32 nr_channels; |
145 | char fw_name[FW_NAME_SIZE]; |
146 | }; |
147 | |
148 | /* Peripheral Registers*/ |
149 | |
150 | #define FDMA_CMD_STA_OFST 0xFC0 |
151 | #define FDMA_CMD_SET_OFST 0xFC4 |
152 | #define FDMA_CMD_CLR_OFST 0xFC8 |
153 | #define FDMA_CMD_MASK_OFST 0xFCC |
154 | #define FDMA_CMD_START(ch) (0x1 << (ch << 1)) |
155 | #define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1)) |
156 | #define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1)) |
157 | |
158 | #define FDMA_INT_STA_OFST 0xFD0 |
159 | #define FDMA_INT_STA_CH 0x1 |
160 | #define FDMA_INT_STA_ERR 0x2 |
161 | |
162 | #define FDMA_INT_SET_OFST 0xFD4 |
163 | #define FDMA_INT_CLR_OFST 0xFD8 |
164 | #define FDMA_INT_MASK_OFST 0xFDC |
165 | |
166 | #define fdma_read(fdev, name) \ |
167 | readl((fdev)->slim_rproc->peri + name) |
168 | |
169 | #define fdma_write(fdev, val, name) \ |
170 | writel((val), (fdev)->slim_rproc->peri + name) |
171 | |
172 | /* fchan interface (dmem) */ |
173 | #define FDMA_CH_CMD_OFST 0x200 |
174 | #define FDMA_CH_CMD_STA_MASK GENMASK(1, 0) |
175 | #define FDMA_CH_CMD_STA_IDLE (0x0) |
176 | #define FDMA_CH_CMD_STA_START (0x1) |
177 | #define FDMA_CH_CMD_STA_RUNNING (0x2) |
178 | #define FDMA_CH_CMD_STA_PAUSED (0x3) |
179 | #define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2) |
180 | #define FDMA_CH_CMD_ERR_INT (0x0 << 2) |
181 | #define FDMA_CH_CMD_ERR_NAND (0x1 << 2) |
182 | #define FDMA_CH_CMD_ERR_MCHI (0x2 << 2) |
183 | #define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5) |
184 | #define fchan_read(fchan, name) \ |
185 | readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ |
186 | + (fchan)->vchan.chan.chan_id * 0x4 \ |
187 | + name) |
188 | |
189 | #define fchan_write(fchan, val, name) \ |
190 | writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ |
191 | + (fchan)->vchan.chan.chan_id * 0x4 \ |
192 | + name) |
193 | |
194 | /* req interface */ |
195 | #define FDMA_REQ_CTRL_OFST 0x240 |
196 | #define dreq_write(fchan, val, name) \ |
197 | writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ |
198 | + fchan->dreq_line * 0x04 \ |
199 | + name) |
200 | /* node interface */ |
201 | #define FDMA_NODE_SZ 128 |
202 | #define FDMA_PTRN_OFST 0x800 |
203 | #define FDMA_CNTN_OFST 0x808 |
204 | #define FDMA_SADDRN_OFST 0x80c |
205 | #define FDMA_DADDRN_OFST 0x810 |
206 | #define fnode_read(fchan, name) \ |
207 | readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ |
208 | + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \ |
209 | + name) |
210 | |
211 | #define fnode_write(fchan, val, name) \ |
212 | writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \ |
213 | + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \ |
214 | + name) |
215 | |
216 | /* |
217 | * request control bits |
218 | */ |
219 | #define FDMA_REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24) |
220 | #define FDMA_REQ_CTRL_NUM_OPS(n) (FDMA_REQ_CTRL_NUM_OPS_MASK & \ |
221 | ((n) << 24)) |
222 | #define FDMA_REQ_CTRL_INITIATOR_MASK BIT(22) |
223 | #define FDMA_REQ_CTRL_INIT0 (0x0 << 22) |
224 | #define FDMA_REQ_CTRL_INIT1 (0x1 << 22) |
225 | #define FDMA_REQ_CTRL_INC_ADDR_ON BIT(21) |
226 | #define FDMA_REQ_CTRL_DATA_SWAP_ON BIT(17) |
227 | #define FDMA_REQ_CTRL_WNR BIT(14) |
228 | #define FDMA_REQ_CTRL_OPCODE_MASK GENMASK(7, 4) |
229 | #define FDMA_REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4) |
230 | #define FDMA_REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4) |
231 | #define FDMA_REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4) |
232 | #define FDMA_REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4) |
233 | #define FDMA_REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4) |
234 | #define FDMA_REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4) |
235 | #define FDMA_REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4) |
236 | #define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0) |
237 | #define FDMA_REQ_CTRL_HOLDOFF(n) ((n) & FDMA_REQ_CTRL_HOLDOFF_MASK) |
238 | |
239 | /* bits used by client to configure request control */ |
240 | #define FDMA_REQ_CTRL_CFG_MASK (FDMA_REQ_CTRL_HOLDOFF_MASK | \ |
241 | FDMA_REQ_CTRL_DATA_SWAP_ON | \ |
242 | FDMA_REQ_CTRL_INC_ADDR_ON | \ |
243 | FDMA_REQ_CTRL_INITIATOR_MASK) |
244 | |
245 | #endif /* __DMA_ST_FDMA_H */ |
246 | |