1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | |
3 | #ifndef STE_DMA40_H |
4 | #define STE_DMA40_H |
5 | |
6 | /* |
7 | * Maxium size for a single dma descriptor |
8 | * Size is limited to 16 bits. |
9 | * Size is in the units of addr-widths (1,2,4,8 bytes) |
10 | * Larger transfers will be split up to multiple linked desc |
11 | */ |
12 | #define STEDMA40_MAX_SEG_SIZE 0xFFFF |
13 | |
14 | /* dev types for memcpy */ |
15 | #define STEDMA40_DEV_DST_MEMORY (-1) |
16 | #define STEDMA40_DEV_SRC_MEMORY (-1) |
17 | |
18 | enum stedma40_mode { |
19 | STEDMA40_MODE_LOGICAL = 0, |
20 | STEDMA40_MODE_PHYSICAL, |
21 | STEDMA40_MODE_OPERATION, |
22 | }; |
23 | |
24 | enum stedma40_mode_opt { |
25 | STEDMA40_PCHAN_BASIC_MODE = 0, |
26 | STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0, |
27 | STEDMA40_PCHAN_MODULO_MODE, |
28 | STEDMA40_PCHAN_DOUBLE_DST_MODE, |
29 | STEDMA40_LCHAN_SRC_PHY_DST_LOG, |
30 | STEDMA40_LCHAN_SRC_LOG_DST_PHY, |
31 | }; |
32 | |
33 | #define STEDMA40_ESIZE_8_BIT 0x0 |
34 | #define STEDMA40_ESIZE_16_BIT 0x1 |
35 | #define STEDMA40_ESIZE_32_BIT 0x2 |
36 | #define STEDMA40_ESIZE_64_BIT 0x3 |
37 | |
38 | /* The value 4 indicates that PEN-reg shall be set to 0 */ |
39 | #define STEDMA40_PSIZE_PHY_1 0x4 |
40 | #define STEDMA40_PSIZE_PHY_2 0x0 |
41 | #define STEDMA40_PSIZE_PHY_4 0x1 |
42 | #define STEDMA40_PSIZE_PHY_8 0x2 |
43 | #define STEDMA40_PSIZE_PHY_16 0x3 |
44 | |
45 | /* |
46 | * The number of elements differ in logical and |
47 | * physical mode |
48 | */ |
49 | #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2 |
50 | #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4 |
51 | #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 |
52 | #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 |
53 | |
54 | /* Maximum number of possible physical channels */ |
55 | #define STEDMA40_MAX_PHYS 32 |
56 | |
57 | enum stedma40_flow_ctrl { |
58 | STEDMA40_NO_FLOW_CTRL, |
59 | STEDMA40_FLOW_CTRL, |
60 | }; |
61 | |
62 | /** |
63 | * struct stedma40_half_channel_info - dst/src channel configuration |
64 | * |
65 | * @big_endian: true if the src/dst should be read as big endian |
66 | * @data_width: Data width of the src/dst hardware |
67 | * @p_size: Burst size |
68 | * @flow_ctrl: Flow control on/off. |
69 | */ |
70 | struct stedma40_half_channel_info { |
71 | bool big_endian; |
72 | enum dma_slave_buswidth data_width; |
73 | int psize; |
74 | enum stedma40_flow_ctrl flow_ctrl; |
75 | }; |
76 | |
77 | /** |
78 | * struct stedma40_chan_cfg - Structure to be filled by client drivers. |
79 | * |
80 | * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH |
81 | * @high_priority: true if high-priority |
82 | * @realtime: true if realtime mode is to be enabled. Only available on DMA40 |
83 | * version 3+, i.e DB8500v2+ |
84 | * @mode: channel mode: physical, logical, or operation |
85 | * @mode_opt: options for the chosen channel mode |
86 | * @dev_type: src/dst device type (driver uses dir to figure out which) |
87 | * @src_info: Parameters for dst half channel |
88 | * @dst_info: Parameters for dst half channel |
89 | * @use_fixed_channel: if true, use physical channel specified by phy_channel |
90 | * @phy_channel: physical channel to use, only if use_fixed_channel is true |
91 | * |
92 | * This structure has to be filled by the client drivers. |
93 | * It is recommended to do all dma configurations for clients in the machine. |
94 | * |
95 | */ |
96 | struct stedma40_chan_cfg { |
97 | enum dma_transfer_direction dir; |
98 | bool high_priority; |
99 | bool realtime; |
100 | enum stedma40_mode mode; |
101 | enum stedma40_mode_opt mode_opt; |
102 | int dev_type; |
103 | struct stedma40_half_channel_info src_info; |
104 | struct stedma40_half_channel_info dst_info; |
105 | |
106 | bool use_fixed_channel; |
107 | int phy_channel; |
108 | }; |
109 | |
110 | #endif /* STE_DMA40_H */ |
111 | |