1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Intel E3-1200 |
4 | * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> |
5 | * |
6 | * Support for the E3-1200 processor family. Heavily based on previous |
7 | * Intel EDAC drivers. |
8 | * |
9 | * Since the DRAM controller is on the cpu chip, we can use its PCI device |
10 | * id to identify these processors. |
11 | * |
12 | * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) |
13 | * |
14 | * 0108: Xeon E3-1200 Processor Family DRAM Controller |
15 | * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller |
16 | * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller |
17 | * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller |
18 | * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller |
19 | * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller |
20 | * 0c08: Xeon E3-1200 v3 Processor DRAM Controller |
21 | * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers |
22 | * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers |
23 | * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers |
24 | * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers |
25 | * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers |
26 | * |
27 | * Based on Intel specification: |
28 | * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf |
29 | * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html |
30 | * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf |
31 | * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf |
32 | * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html |
33 | * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html |
34 | * |
35 | * According to the above datasheet (p.16): |
36 | * " |
37 | * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with |
38 | * requests that cross a DW boundary. |
39 | * " |
40 | * |
41 | * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into |
42 | * 2 readl() calls. This restriction may be lifted in subsequent chip releases, |
43 | * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. |
44 | */ |
45 | |
46 | #include <linux/module.h> |
47 | #include <linux/init.h> |
48 | #include <linux/pci.h> |
49 | #include <linux/pci_ids.h> |
50 | #include <linux/edac.h> |
51 | |
52 | #include <linux/io-64-nonatomic-lo-hi.h> |
53 | #include "edac_module.h" |
54 | |
55 | #define EDAC_MOD_STR "ie31200_edac" |
56 | |
57 | #define ie31200_printk(level, fmt, arg...) \ |
58 | edac_printk(level, "ie31200", fmt, ##arg) |
59 | |
60 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 |
61 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c |
62 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 |
63 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 |
64 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c |
65 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 |
66 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 |
67 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F |
68 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 |
69 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F |
70 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918 |
71 | |
72 | /* Coffee Lake-S */ |
73 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 |
74 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f |
75 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 |
76 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f |
77 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 |
78 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 |
79 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 |
80 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 |
81 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 |
82 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 |
83 | #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca |
84 | |
85 | /* Test if HB is for Skylake or later. */ |
86 | #define DEVICE_ID_SKYLAKE_OR_LATER(did) \ |
87 | (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \ |
88 | ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \ |
89 | ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \ |
90 | ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \ |
91 | (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \ |
92 | PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK)) |
93 | |
94 | #define IE31200_DIMMS 4 |
95 | #define IE31200_RANKS 8 |
96 | #define IE31200_RANKS_PER_CHANNEL 4 |
97 | #define IE31200_DIMMS_PER_CHANNEL 2 |
98 | #define IE31200_CHANNELS 2 |
99 | |
100 | /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ |
101 | #define IE31200_MCHBAR_LOW 0x48 |
102 | #define IE31200_MCHBAR_HIGH 0x4c |
103 | #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) |
104 | #define IE31200_MMR_WINDOW_SIZE BIT(15) |
105 | |
106 | /* |
107 | * Error Status Register (16b) |
108 | * |
109 | * 15 reserved |
110 | * 14 Isochronous TBWRR Run Behind FIFO Full |
111 | * (ITCV) |
112 | * 13 Isochronous TBWRR Run Behind FIFO Put |
113 | * (ITSTV) |
114 | * 12 reserved |
115 | * 11 MCH Thermal Sensor Event |
116 | * for SMI/SCI/SERR (GTSE) |
117 | * 10 reserved |
118 | * 9 LOCK to non-DRAM Memory Flag (LCKF) |
119 | * 8 reserved |
120 | * 7 DRAM Throttle Flag (DTF) |
121 | * 6:2 reserved |
122 | * 1 Multi-bit DRAM ECC Error Flag (DMERR) |
123 | * 0 Single-bit DRAM ECC Error Flag (DSERR) |
124 | */ |
125 | #define IE31200_ERRSTS 0xc8 |
126 | #define IE31200_ERRSTS_UE BIT(1) |
127 | #define IE31200_ERRSTS_CE BIT(0) |
128 | #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) |
129 | |
130 | /* |
131 | * Channel 0 ECC Error Log (64b) |
132 | * |
133 | * 63:48 Error Column Address (ERRCOL) |
134 | * 47:32 Error Row Address (ERRROW) |
135 | * 31:29 Error Bank Address (ERRBANK) |
136 | * 28:27 Error Rank Address (ERRRANK) |
137 | * 26:24 reserved |
138 | * 23:16 Error Syndrome (ERRSYND) |
139 | * 15: 2 reserved |
140 | * 1 Multiple Bit Error Status (MERRSTS) |
141 | * 0 Correctable Error Status (CERRSTS) |
142 | */ |
143 | |
144 | #define IE31200_C0ECCERRLOG 0x40c8 |
145 | #define IE31200_C1ECCERRLOG 0x44c8 |
146 | #define IE31200_C0ECCERRLOG_SKL 0x4048 |
147 | #define IE31200_C1ECCERRLOG_SKL 0x4448 |
148 | #define IE31200_ECCERRLOG_CE BIT(0) |
149 | #define IE31200_ECCERRLOG_UE BIT(1) |
150 | #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) |
151 | #define IE31200_ECCERRLOG_RANK_SHIFT 27 |
152 | #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) |
153 | #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 |
154 | |
155 | #define IE31200_ECCERRLOG_SYNDROME(log) \ |
156 | ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ |
157 | IE31200_ECCERRLOG_SYNDROME_SHIFT) |
158 | |
159 | #define IE31200_CAPID0 0xe4 |
160 | #define IE31200_CAPID0_PDCD BIT(4) |
161 | #define IE31200_CAPID0_DDPCD BIT(6) |
162 | #define IE31200_CAPID0_ECC BIT(1) |
163 | |
164 | #define IE31200_MAD_DIMM_0_OFFSET 0x5004 |
165 | #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C |
166 | #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) |
167 | #define IE31200_MAD_DIMM_A_RANK BIT(17) |
168 | #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 |
169 | #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) |
170 | #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 |
171 | #define IE31200_MAD_DIMM_A_WIDTH BIT(19) |
172 | #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 |
173 | #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) |
174 | #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 |
175 | |
176 | /* Skylake reports 1GB increments, everything else is 256MB */ |
177 | #define IE31200_PAGES(n, skl) \ |
178 | (n << (28 + (2 * skl) - PAGE_SHIFT)) |
179 | |
180 | static int nr_channels; |
181 | static struct pci_dev *mci_pdev; |
182 | static int ie31200_registered = 1; |
183 | |
184 | struct ie31200_priv { |
185 | void __iomem *window; |
186 | void __iomem *c0errlog; |
187 | void __iomem *c1errlog; |
188 | }; |
189 | |
190 | enum ie31200_chips { |
191 | IE31200 = 0, |
192 | }; |
193 | |
194 | struct ie31200_dev_info { |
195 | const char *ctl_name; |
196 | }; |
197 | |
198 | struct ie31200_error_info { |
199 | u16 errsts; |
200 | u16 errsts2; |
201 | u64 eccerrlog[IE31200_CHANNELS]; |
202 | }; |
203 | |
204 | static const struct ie31200_dev_info ie31200_devs[] = { |
205 | [IE31200] = { |
206 | .ctl_name = "IE31200" |
207 | }, |
208 | }; |
209 | |
210 | struct dimm_data { |
211 | u8 size; /* in multiples of 256MB, except Skylake is 1GB */ |
212 | u8 dual_rank : 1, |
213 | x16_width : 2; /* 0 means x8 width */ |
214 | }; |
215 | |
216 | static int how_many_channels(struct pci_dev *pdev) |
217 | { |
218 | int n_channels; |
219 | unsigned char capid0_2b; /* 2nd byte of CAPID0 */ |
220 | |
221 | pci_read_config_byte(dev: pdev, IE31200_CAPID0 + 1, val: &capid0_2b); |
222 | |
223 | /* check PDCD: Dual Channel Disable */ |
224 | if (capid0_2b & IE31200_CAPID0_PDCD) { |
225 | edac_dbg(0, "In single channel mode\n" ); |
226 | n_channels = 1; |
227 | } else { |
228 | edac_dbg(0, "In dual channel mode\n" ); |
229 | n_channels = 2; |
230 | } |
231 | |
232 | /* check DDPCD - check if both channels are filled */ |
233 | if (capid0_2b & IE31200_CAPID0_DDPCD) |
234 | edac_dbg(0, "2 DIMMS per channel disabled\n" ); |
235 | else |
236 | edac_dbg(0, "2 DIMMS per channel enabled\n" ); |
237 | |
238 | return n_channels; |
239 | } |
240 | |
241 | static bool ecc_capable(struct pci_dev *pdev) |
242 | { |
243 | unsigned char capid0_4b; /* 4th byte of CAPID0 */ |
244 | |
245 | pci_read_config_byte(dev: pdev, IE31200_CAPID0 + 3, val: &capid0_4b); |
246 | if (capid0_4b & IE31200_CAPID0_ECC) |
247 | return false; |
248 | return true; |
249 | } |
250 | |
251 | static int eccerrlog_row(u64 log) |
252 | { |
253 | return ((log & IE31200_ECCERRLOG_RANK_BITS) >> |
254 | IE31200_ECCERRLOG_RANK_SHIFT); |
255 | } |
256 | |
257 | static void ie31200_clear_error_info(struct mem_ctl_info *mci) |
258 | { |
259 | /* |
260 | * Clear any error bits. |
261 | * (Yes, we really clear bits by writing 1 to them.) |
262 | */ |
263 | pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, |
264 | IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); |
265 | } |
266 | |
267 | static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, |
268 | struct ie31200_error_info *info) |
269 | { |
270 | struct pci_dev *pdev; |
271 | struct ie31200_priv *priv = mci->pvt_info; |
272 | |
273 | pdev = to_pci_dev(mci->pdev); |
274 | |
275 | /* |
276 | * This is a mess because there is no atomic way to read all the |
277 | * registers at once and the registers can transition from CE being |
278 | * overwritten by UE. |
279 | */ |
280 | pci_read_config_word(dev: pdev, IE31200_ERRSTS, val: &info->errsts); |
281 | if (!(info->errsts & IE31200_ERRSTS_BITS)) |
282 | return; |
283 | |
284 | info->eccerrlog[0] = lo_hi_readq(addr: priv->c0errlog); |
285 | if (nr_channels == 2) |
286 | info->eccerrlog[1] = lo_hi_readq(addr: priv->c1errlog); |
287 | |
288 | pci_read_config_word(dev: pdev, IE31200_ERRSTS, val: &info->errsts2); |
289 | |
290 | /* |
291 | * If the error is the same for both reads then the first set |
292 | * of reads is valid. If there is a change then there is a CE |
293 | * with no info and the second set of reads is valid and |
294 | * should be UE info. |
295 | */ |
296 | if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { |
297 | info->eccerrlog[0] = lo_hi_readq(addr: priv->c0errlog); |
298 | if (nr_channels == 2) |
299 | info->eccerrlog[1] = |
300 | lo_hi_readq(addr: priv->c1errlog); |
301 | } |
302 | |
303 | ie31200_clear_error_info(mci); |
304 | } |
305 | |
306 | static void ie31200_process_error_info(struct mem_ctl_info *mci, |
307 | struct ie31200_error_info *info) |
308 | { |
309 | int channel; |
310 | u64 log; |
311 | |
312 | if (!(info->errsts & IE31200_ERRSTS_BITS)) |
313 | return; |
314 | |
315 | if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { |
316 | edac_mc_handle_error(type: HW_EVENT_ERR_UNCORRECTED, mci, error_count: 1, page_frame_number: 0, offset_in_page: 0, syndrome: 0, |
317 | top_layer: -1, mid_layer: -1, low_layer: -1, msg: "UE overwrote CE" , other_detail: "" ); |
318 | info->errsts = info->errsts2; |
319 | } |
320 | |
321 | for (channel = 0; channel < nr_channels; channel++) { |
322 | log = info->eccerrlog[channel]; |
323 | if (log & IE31200_ECCERRLOG_UE) { |
324 | edac_mc_handle_error(type: HW_EVENT_ERR_UNCORRECTED, mci, error_count: 1, |
325 | page_frame_number: 0, offset_in_page: 0, syndrome: 0, |
326 | top_layer: eccerrlog_row(log), |
327 | mid_layer: channel, low_layer: -1, |
328 | msg: "ie31200 UE" , other_detail: "" ); |
329 | } else if (log & IE31200_ECCERRLOG_CE) { |
330 | edac_mc_handle_error(type: HW_EVENT_ERR_CORRECTED, mci, error_count: 1, |
331 | page_frame_number: 0, offset_in_page: 0, |
332 | IE31200_ECCERRLOG_SYNDROME(log), |
333 | top_layer: eccerrlog_row(log), |
334 | mid_layer: channel, low_layer: -1, |
335 | msg: "ie31200 CE" , other_detail: "" ); |
336 | } |
337 | } |
338 | } |
339 | |
340 | static void ie31200_check(struct mem_ctl_info *mci) |
341 | { |
342 | struct ie31200_error_info info; |
343 | |
344 | ie31200_get_and_clear_error_info(mci, info: &info); |
345 | ie31200_process_error_info(mci, info: &info); |
346 | } |
347 | |
348 | static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) |
349 | { |
350 | union { |
351 | u64 mchbar; |
352 | struct { |
353 | u32 mchbar_low; |
354 | u32 mchbar_high; |
355 | }; |
356 | } u; |
357 | void __iomem *window; |
358 | |
359 | pci_read_config_dword(dev: pdev, IE31200_MCHBAR_LOW, val: &u.mchbar_low); |
360 | pci_read_config_dword(dev: pdev, IE31200_MCHBAR_HIGH, val: &u.mchbar_high); |
361 | u.mchbar &= IE31200_MCHBAR_MASK; |
362 | |
363 | if (u.mchbar != (resource_size_t)u.mchbar) { |
364 | ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n" , |
365 | (unsigned long long)u.mchbar); |
366 | return NULL; |
367 | } |
368 | |
369 | window = ioremap(offset: u.mchbar, IE31200_MMR_WINDOW_SIZE); |
370 | if (!window) |
371 | ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n" , |
372 | (unsigned long long)u.mchbar); |
373 | |
374 | return window; |
375 | } |
376 | |
377 | static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, |
378 | int chan) |
379 | { |
380 | dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; |
381 | dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; |
382 | dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> |
383 | (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); |
384 | } |
385 | |
386 | static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, |
387 | int chan) |
388 | { |
389 | dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; |
390 | dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; |
391 | dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; |
392 | } |
393 | |
394 | static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, |
395 | bool skl) |
396 | { |
397 | if (skl) |
398 | __skl_populate_dimm_info(dd, addr_decode, chan); |
399 | else |
400 | __populate_dimm_info(dd, addr_decode, chan); |
401 | } |
402 | |
403 | |
404 | static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) |
405 | { |
406 | int i, j, ret; |
407 | struct mem_ctl_info *mci = NULL; |
408 | struct edac_mc_layer layers[2]; |
409 | struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; |
410 | void __iomem *window; |
411 | struct ie31200_priv *priv; |
412 | u32 addr_decode, mad_offset; |
413 | |
414 | /* |
415 | * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit |
416 | * this logic when adding new CPU support. |
417 | */ |
418 | bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); |
419 | |
420 | edac_dbg(0, "MC:\n" ); |
421 | |
422 | if (!ecc_capable(pdev)) { |
423 | ie31200_printk(KERN_INFO, "No ECC support\n" ); |
424 | return -ENODEV; |
425 | } |
426 | |
427 | nr_channels = how_many_channels(pdev); |
428 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
429 | layers[0].size = IE31200_DIMMS; |
430 | layers[0].is_virt_csrow = true; |
431 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
432 | layers[1].size = nr_channels; |
433 | layers[1].is_virt_csrow = false; |
434 | mci = edac_mc_alloc(mc_num: 0, ARRAY_SIZE(layers), layers, |
435 | sz_pvt: sizeof(struct ie31200_priv)); |
436 | if (!mci) |
437 | return -ENOMEM; |
438 | |
439 | window = ie31200_map_mchbar(pdev); |
440 | if (!window) { |
441 | ret = -ENODEV; |
442 | goto fail_free; |
443 | } |
444 | |
445 | edac_dbg(3, "MC: init mci\n" ); |
446 | mci->pdev = &pdev->dev; |
447 | if (skl) |
448 | mci->mtype_cap = MEM_FLAG_DDR4; |
449 | else |
450 | mci->mtype_cap = MEM_FLAG_DDR3; |
451 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
452 | mci->edac_cap = EDAC_FLAG_SECDED; |
453 | mci->mod_name = EDAC_MOD_STR; |
454 | mci->ctl_name = ie31200_devs[dev_idx].ctl_name; |
455 | mci->dev_name = pci_name(pdev); |
456 | mci->edac_check = ie31200_check; |
457 | mci->ctl_page_to_phys = NULL; |
458 | priv = mci->pvt_info; |
459 | priv->window = window; |
460 | if (skl) { |
461 | priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; |
462 | priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; |
463 | mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; |
464 | } else { |
465 | priv->c0errlog = window + IE31200_C0ECCERRLOG; |
466 | priv->c1errlog = window + IE31200_C1ECCERRLOG; |
467 | mad_offset = IE31200_MAD_DIMM_0_OFFSET; |
468 | } |
469 | |
470 | /* populate DIMM info */ |
471 | for (i = 0; i < IE31200_CHANNELS; i++) { |
472 | addr_decode = readl(addr: window + mad_offset + |
473 | (i * 4)); |
474 | edac_dbg(0, "addr_decode: 0x%x\n" , addr_decode); |
475 | for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { |
476 | populate_dimm_info(dd: &dimm_info[i][j], addr_decode, chan: j, |
477 | skl); |
478 | edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n" , |
479 | dimm_info[i][j].size, |
480 | dimm_info[i][j].dual_rank, |
481 | dimm_info[i][j].x16_width); |
482 | } |
483 | } |
484 | |
485 | /* |
486 | * The dram rank boundary (DRB) reg values are boundary addresses |
487 | * for each DRAM rank with a granularity of 64MB. DRB regs are |
488 | * cumulative; the last one will contain the total memory |
489 | * contained in all ranks. |
490 | */ |
491 | for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { |
492 | for (j = 0; j < IE31200_CHANNELS; j++) { |
493 | struct dimm_info *dimm; |
494 | unsigned long nr_pages; |
495 | |
496 | nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); |
497 | if (nr_pages == 0) |
498 | continue; |
499 | |
500 | if (dimm_info[j][i].dual_rank) { |
501 | nr_pages = nr_pages / 2; |
502 | dimm = edac_get_dimm(mci, layer0: (i * 2) + 1, layer1: j, layer2: 0); |
503 | dimm->nr_pages = nr_pages; |
504 | edac_dbg(0, "set nr pages: 0x%lx\n" , nr_pages); |
505 | dimm->grain = 8; /* just a guess */ |
506 | if (skl) |
507 | dimm->mtype = MEM_DDR4; |
508 | else |
509 | dimm->mtype = MEM_DDR3; |
510 | dimm->dtype = DEV_UNKNOWN; |
511 | dimm->edac_mode = EDAC_UNKNOWN; |
512 | } |
513 | dimm = edac_get_dimm(mci, layer0: i * 2, layer1: j, layer2: 0); |
514 | dimm->nr_pages = nr_pages; |
515 | edac_dbg(0, "set nr pages: 0x%lx\n" , nr_pages); |
516 | dimm->grain = 8; /* same guess */ |
517 | if (skl) |
518 | dimm->mtype = MEM_DDR4; |
519 | else |
520 | dimm->mtype = MEM_DDR3; |
521 | dimm->dtype = DEV_UNKNOWN; |
522 | dimm->edac_mode = EDAC_UNKNOWN; |
523 | } |
524 | } |
525 | |
526 | ie31200_clear_error_info(mci); |
527 | |
528 | if (edac_mc_add_mc(mci)) { |
529 | edac_dbg(3, "MC: failed edac_mc_add_mc()\n" ); |
530 | ret = -ENODEV; |
531 | goto fail_unmap; |
532 | } |
533 | |
534 | /* get this far and it's successful */ |
535 | edac_dbg(3, "MC: success\n" ); |
536 | return 0; |
537 | |
538 | fail_unmap: |
539 | iounmap(addr: window); |
540 | |
541 | fail_free: |
542 | edac_mc_free(mci); |
543 | |
544 | return ret; |
545 | } |
546 | |
547 | static int ie31200_init_one(struct pci_dev *pdev, |
548 | const struct pci_device_id *ent) |
549 | { |
550 | int rc; |
551 | |
552 | edac_dbg(0, "MC:\n" ); |
553 | if (pci_enable_device(dev: pdev) < 0) |
554 | return -EIO; |
555 | rc = ie31200_probe1(pdev, dev_idx: ent->driver_data); |
556 | if (rc == 0 && !mci_pdev) |
557 | mci_pdev = pci_dev_get(dev: pdev); |
558 | |
559 | return rc; |
560 | } |
561 | |
562 | static void ie31200_remove_one(struct pci_dev *pdev) |
563 | { |
564 | struct mem_ctl_info *mci; |
565 | struct ie31200_priv *priv; |
566 | |
567 | edac_dbg(0, "\n" ); |
568 | pci_dev_put(dev: mci_pdev); |
569 | mci_pdev = NULL; |
570 | mci = edac_mc_del_mc(dev: &pdev->dev); |
571 | if (!mci) |
572 | return; |
573 | priv = mci->pvt_info; |
574 | iounmap(addr: priv->window); |
575 | edac_mc_free(mci); |
576 | } |
577 | |
578 | static const struct pci_device_id ie31200_pci_tbl[] = { |
579 | { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
580 | { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
581 | { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
582 | { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
583 | { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
584 | { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
585 | { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
586 | { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
587 | { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
588 | { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
589 | { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
590 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
591 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
592 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
593 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
594 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
595 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
596 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
597 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
598 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
599 | { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, |
600 | { 0, } /* 0 terminated list. */ |
601 | }; |
602 | MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); |
603 | |
604 | static struct pci_driver ie31200_driver = { |
605 | .name = EDAC_MOD_STR, |
606 | .probe = ie31200_init_one, |
607 | .remove = ie31200_remove_one, |
608 | .id_table = ie31200_pci_tbl, |
609 | }; |
610 | |
611 | static int __init ie31200_init(void) |
612 | { |
613 | int pci_rc, i; |
614 | |
615 | edac_dbg(3, "MC:\n" ); |
616 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
617 | opstate_init(); |
618 | |
619 | pci_rc = pci_register_driver(&ie31200_driver); |
620 | if (pci_rc < 0) |
621 | goto fail0; |
622 | |
623 | if (!mci_pdev) { |
624 | ie31200_registered = 0; |
625 | for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { |
626 | mci_pdev = pci_get_device(vendor: ie31200_pci_tbl[i].vendor, |
627 | device: ie31200_pci_tbl[i].device, |
628 | NULL); |
629 | if (mci_pdev) |
630 | break; |
631 | } |
632 | if (!mci_pdev) { |
633 | edac_dbg(0, "ie31200 pci_get_device fail\n" ); |
634 | pci_rc = -ENODEV; |
635 | goto fail1; |
636 | } |
637 | pci_rc = ie31200_init_one(pdev: mci_pdev, ent: &ie31200_pci_tbl[i]); |
638 | if (pci_rc < 0) { |
639 | edac_dbg(0, "ie31200 init fail\n" ); |
640 | pci_rc = -ENODEV; |
641 | goto fail1; |
642 | } |
643 | } |
644 | return 0; |
645 | |
646 | fail1: |
647 | pci_unregister_driver(dev: &ie31200_driver); |
648 | fail0: |
649 | pci_dev_put(dev: mci_pdev); |
650 | |
651 | return pci_rc; |
652 | } |
653 | |
654 | static void __exit ie31200_exit(void) |
655 | { |
656 | edac_dbg(3, "MC:\n" ); |
657 | pci_unregister_driver(dev: &ie31200_driver); |
658 | if (!ie31200_registered) |
659 | ie31200_remove_one(pdev: mci_pdev); |
660 | } |
661 | |
662 | module_init(ie31200_init); |
663 | module_exit(ie31200_exit); |
664 | |
665 | MODULE_LICENSE("GPL" ); |
666 | MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>" ); |
667 | MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers" ); |
668 | |