1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2008 Nuovation System Designs, LLC
4 * Grant Erickson <gerickson@nuovations.com>
5 */
6
7#include <linux/edac.h>
8#include <linux/interrupt.h>
9#include <linux/irq.h>
10#include <linux/kernel.h>
11#include <linux/mm.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/types.h>
17
18#include <asm/dcr.h>
19
20#include "edac_module.h"
21#include "ppc4xx_edac.h"
22
23/*
24 * This file implements a driver for monitoring and handling events
25 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
26 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
27 *
28 * As realized in the 405EX[r], this controller features:
29 *
30 * - Support for registered- and non-registered DDR1 and DDR2 memory.
31 * - 32-bit or 16-bit memory interface with optional ECC.
32 *
33 * o ECC support includes:
34 *
35 * - 4-bit SEC/DED
36 * - Aligned-nibble error detect
37 * - Bypass mode
38 *
39 * - Two (2) memory banks/ranks.
40 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
41 * bank/rank in 16-bit mode.
42 *
43 * As realized in the 440SP and 440SPe, this controller changes/adds:
44 *
45 * - 64-bit or 32-bit memory interface with optional ECC.
46 *
47 * o ECC support includes:
48 *
49 * - 8-bit SEC/DED
50 * - Aligned-nibble error detect
51 * - Bypass mode
52 *
53 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
54 * per bank/rank in 32-bit mode.
55 *
56 * As realized in the 460EX and 460GT, this controller changes/adds:
57 *
58 * - 64-bit or 32-bit memory interface with optional ECC.
59 *
60 * o ECC support includes:
61 *
62 * - 8-bit SEC/DED
63 * - Aligned-nibble error detect
64 * - Bypass mode
65 *
66 * - Four (4) memory banks/ranks.
67 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
68 * per bank/rank in 32-bit mode.
69 *
70 * At present, this driver has ONLY been tested against the controller
71 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
72 * boards (256 MiB w/o ECC memory soldered onto the board) and a
73 * proprietary board based on those designs (128 MiB ECC memory, also
74 * soldered onto the board).
75 *
76 * Dynamic feature detection and handling needs to be added for the
77 * other realizations of this controller listed above.
78 *
79 * Eventually, this driver will likely be adapted to the above variant
80 * realizations of this controller as well as broken apart to handle
81 * the other known ECC-capable controllers prevalent in other 4xx
82 * processors:
83 *
84 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
85 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
86 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
87 *
88 * For this controller, unfortunately, correctable errors report
89 * nothing more than the beat/cycle and byte/lane the correction
90 * occurred on and the check bit group that covered the error.
91 *
92 * In contrast, uncorrectable errors also report the failing address,
93 * the bus master and the transaction direction (i.e. read or write)
94 *
95 * Regardless of whether the error is a CE or a UE, we report the
96 * following pieces of information in the driver-unique message to the
97 * EDAC subsystem:
98 *
99 * - Device tree path
100 * - Bank(s)
101 * - Check bit error group
102 * - Beat(s)/lane(s)
103 */
104
105/* Preprocessor Definitions */
106
107#define EDAC_OPSTATE_INT_STR "interrupt"
108#define EDAC_OPSTATE_POLL_STR "polled"
109#define EDAC_OPSTATE_UNKNOWN_STR "unknown"
110
111#define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
112#define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
113
114#define PPC4XX_EDAC_MESSAGE_SIZE 256
115
116/*
117 * Kernel logging without an EDAC instance
118 */
119#define ppc4xx_edac_printk(level, fmt, arg...) \
120 edac_printk(level, "PPC4xx MC", fmt, ##arg)
121
122/*
123 * Kernel logging with an EDAC instance
124 */
125#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
126 edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
127
128/*
129 * Macros to convert bank configuration size enumerations into MiB and
130 * page values.
131 */
132#define SDRAM_MBCF_SZ_MiB_MIN 4
133#define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
134 << (SDRAM_MBCF_SZ_DECODE(n)))
135#define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
136 << (20 - PAGE_SHIFT + \
137 SDRAM_MBCF_SZ_DECODE(n)))
138
139/*
140 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
141 * indirectly accessed and have a base and length defined by the
142 * device tree. The base can be anything; however, we expect the
143 * length to be precisely two registers, the first for the address
144 * window and the second for the data window.
145 */
146#define SDRAM_DCR_RESOURCE_LEN 2
147#define SDRAM_DCR_ADDR_OFFSET 0
148#define SDRAM_DCR_DATA_OFFSET 1
149
150/*
151 * Device tree interrupt indices
152 */
153#define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
154#define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
155
156/* Type Definitions */
157
158/*
159 * PPC4xx SDRAM memory controller private instance data
160 */
161struct ppc4xx_edac_pdata {
162 dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
163 struct {
164 int sec; /* Single-bit correctable error IRQ assigned */
165 int ded; /* Double-bit detectable error IRQ assigned */
166 } irqs;
167};
168
169/*
170 * Various status data gathered and manipulated when checking and
171 * reporting ECC status.
172 */
173struct ppc4xx_ecc_status {
174 u32 ecces;
175 u32 besr;
176 u32 bearh;
177 u32 bearl;
178 u32 wmirq;
179};
180
181/* Global Variables */
182
183/*
184 * Device tree node type and compatible tuples this driver can match
185 * on.
186 */
187static const struct of_device_id ppc4xx_edac_match[] = {
188 {
189 .compatible = "ibm,sdram-4xx-ddr2"
190 },
191 { }
192};
193MODULE_DEVICE_TABLE(of, ppc4xx_edac_match);
194
195/*
196 * TODO: The row and channel parameters likely need to be dynamically
197 * set based on the aforementioned variant controller realizations.
198 */
199static const unsigned ppc4xx_edac_nr_csrows = 2;
200static const unsigned ppc4xx_edac_nr_chans = 1;
201
202/*
203 * Strings associated with PLB master IDs capable of being posted in
204 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
205 */
206static const char * const ppc4xx_plb_masters[9] = {
207 [SDRAM_PLB_M0ID_ICU] = "ICU",
208 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
209 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
210 [SDRAM_PLB_M0ID_DMA] = "DMA",
211 [SDRAM_PLB_M0ID_DCU] = "DCU",
212 [SDRAM_PLB_M0ID_OPB] = "OPB",
213 [SDRAM_PLB_M0ID_MAL] = "MAL",
214 [SDRAM_PLB_M0ID_SEC] = "SEC",
215 [SDRAM_PLB_M0ID_AHB] = "AHB"
216};
217
218/**
219 * mfsdram - read and return controller register data
220 * @dcr_host: A pointer to the DCR mapping.
221 * @idcr_n: The indirect DCR register to read.
222 *
223 * This routine reads and returns the data associated with the
224 * controller's specified indirect DCR register.
225 *
226 * Returns the read data.
227 */
228static inline u32
229mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
230{
231 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
232 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
233 idcr_n);
234}
235
236/**
237 * mtsdram - write controller register data
238 * @dcr_host: A pointer to the DCR mapping.
239 * @idcr_n: The indirect DCR register to write.
240 * @value: The data to write.
241 *
242 * This routine writes the provided data to the controller's specified
243 * indirect DCR register.
244 */
245static inline void
246mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
247{
248 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
249 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
250 idcr_n,
251 value);
252}
253
254/**
255 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
256 * @status: A pointer to the ECC status structure to check for an
257 * ECC bank error.
258 * @bank: The bank to check for an ECC error.
259 *
260 * This routine determines whether the specified bank has an ECC
261 * error.
262 *
263 * Returns true if the specified bank has an ECC error; otherwise,
264 * false.
265 */
266static bool
267ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
268 unsigned int bank)
269{
270 switch (bank) {
271 case 0:
272 return status->ecces & SDRAM_ECCES_BK0ER;
273 case 1:
274 return status->ecces & SDRAM_ECCES_BK1ER;
275 default:
276 return false;
277 }
278}
279
280/**
281 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
282 * @mci: A pointer to the EDAC memory controller instance associated
283 * with the bank message being generated.
284 * @status: A pointer to the ECC status structure to generate the
285 * message from.
286 * @buffer: A pointer to the buffer in which to generate the
287 * message.
288 * @size: The size, in bytes, of space available in buffer.
289 *
290 * This routine generates to the provided buffer the portion of the
291 * driver-unique report message associated with the ECCESS[BKNER]
292 * field of the specified ECC status.
293 *
294 * Returns the number of characters generated on success; otherwise, <
295 * 0 on error.
296 */
297static int
298ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
299 const struct ppc4xx_ecc_status *status,
300 char *buffer,
301 size_t size)
302{
303 int n, total = 0;
304 unsigned int row, rows;
305
306 n = snprintf(buf: buffer, size, fmt: "%s: Banks: ", mci->dev_name);
307
308 if (n < 0 || n >= size)
309 goto fail;
310
311 buffer += n;
312 size -= n;
313 total += n;
314
315 for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
316 if (ppc4xx_edac_check_bank_error(status, bank: row)) {
317 n = snprintf(buf: buffer, size, fmt: "%s%u",
318 (rows++ ? ", " : ""), row);
319
320 if (n < 0 || n >= size)
321 goto fail;
322
323 buffer += n;
324 size -= n;
325 total += n;
326 }
327 }
328
329 n = snprintf(buf: buffer, size, fmt: "%s; ", rows ? "" : "None");
330
331 if (n < 0 || n >= size)
332 goto fail;
333
334 buffer += n;
335 size -= n;
336 total += n;
337
338 fail:
339 return total;
340}
341
342/**
343 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
344 * @mci: A pointer to the EDAC memory controller instance associated
345 * with the checkbit message being generated.
346 * @status: A pointer to the ECC status structure to generate the
347 * message from.
348 * @buffer: A pointer to the buffer in which to generate the
349 * message.
350 * @size: The size, in bytes, of space available in buffer.
351 *
352 * This routine generates to the provided buffer the portion of the
353 * driver-unique report message associated with the ECCESS[CKBER]
354 * field of the specified ECC status.
355 *
356 * Returns the number of characters generated on success; otherwise, <
357 * 0 on error.
358 */
359static int
360ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
361 const struct ppc4xx_ecc_status *status,
362 char *buffer,
363 size_t size)
364{
365 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
366 const char *ckber = NULL;
367
368 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
369 case SDRAM_ECCES_CKBER_NONE:
370 ckber = "None";
371 break;
372 case SDRAM_ECCES_CKBER_32_ECC_0_3:
373 ckber = "ECC0:3";
374 break;
375 case SDRAM_ECCES_CKBER_32_ECC_4_8:
376 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
377 SDRAM_MCOPT1_WDTH_MASK) {
378 case SDRAM_MCOPT1_WDTH_16:
379 ckber = "ECC0:3";
380 break;
381 case SDRAM_MCOPT1_WDTH_32:
382 ckber = "ECC4:8";
383 break;
384 default:
385 ckber = "Unknown";
386 break;
387 }
388 break;
389 case SDRAM_ECCES_CKBER_32_ECC_0_8:
390 ckber = "ECC0:8";
391 break;
392 default:
393 ckber = "Unknown";
394 break;
395 }
396
397 return snprintf(buf: buffer, size, fmt: "Checkbit Error: %s", ckber);
398}
399
400/**
401 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
402 * @mci: A pointer to the EDAC memory controller instance associated
403 * with the byte lane message being generated.
404 * @status: A pointer to the ECC status structure to generate the
405 * message from.
406 * @buffer: A pointer to the buffer in which to generate the
407 * message.
408 * @size: The size, in bytes, of space available in buffer.
409 *
410 * This routine generates to the provided buffer the portion of the
411 * driver-unique report message associated with the ECCESS[BNCE]
412 * field of the specified ECC status.
413 *
414 * Returns the number of characters generated on success; otherwise, <
415 * 0 on error.
416 */
417static int
418ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
419 const struct ppc4xx_ecc_status *status,
420 char *buffer,
421 size_t size)
422{
423 int n, total = 0;
424 unsigned int lane, lanes;
425 const unsigned int first_lane = 0;
426 const unsigned int lane_count = 16;
427
428 n = snprintf(buf: buffer, size, fmt: "; Byte Lane Errors: ");
429
430 if (n < 0 || n >= size)
431 goto fail;
432
433 buffer += n;
434 size -= n;
435 total += n;
436
437 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
438 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
439 n = snprintf(buf: buffer, size,
440 fmt: "%s%u",
441 (lanes++ ? ", " : ""), lane);
442
443 if (n < 0 || n >= size)
444 goto fail;
445
446 buffer += n;
447 size -= n;
448 total += n;
449 }
450 }
451
452 n = snprintf(buf: buffer, size, fmt: "%s; ", lanes ? "" : "None");
453
454 if (n < 0 || n >= size)
455 goto fail;
456
457 buffer += n;
458 size -= n;
459 total += n;
460
461 fail:
462 return total;
463}
464
465/**
466 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
467 * @mci: A pointer to the EDAC memory controller instance associated
468 * with the ECCES message being generated.
469 * @status: A pointer to the ECC status structure to generate the
470 * message from.
471 * @buffer: A pointer to the buffer in which to generate the
472 * message.
473 * @size: The size, in bytes, of space available in buffer.
474 *
475 * This routine generates to the provided buffer the portion of the
476 * driver-unique report message associated with the ECCESS register of
477 * the specified ECC status.
478 *
479 * Returns the number of characters generated on success; otherwise, <
480 * 0 on error.
481 */
482static int
483ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
484 const struct ppc4xx_ecc_status *status,
485 char *buffer,
486 size_t size)
487{
488 int n, total = 0;
489
490 n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
491
492 if (n < 0 || n >= size)
493 goto fail;
494
495 buffer += n;
496 size -= n;
497 total += n;
498
499 n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
500
501 if (n < 0 || n >= size)
502 goto fail;
503
504 buffer += n;
505 size -= n;
506 total += n;
507
508 n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
509
510 if (n < 0 || n >= size)
511 goto fail;
512
513 buffer += n;
514 size -= n;
515 total += n;
516
517 fail:
518 return total;
519}
520
521/**
522 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
523 * @mci: A pointer to the EDAC memory controller instance associated
524 * with the PLB message being generated.
525 * @status: A pointer to the ECC status structure to generate the
526 * message from.
527 * @buffer: A pointer to the buffer in which to generate the
528 * message.
529 * @size: The size, in bytes, of space available in buffer.
530 *
531 * This routine generates to the provided buffer the portion of the
532 * driver-unique report message associated with the PLB-related BESR
533 * and/or WMIRQ registers of the specified ECC status.
534 *
535 * Returns the number of characters generated on success; otherwise, <
536 * 0 on error.
537 */
538static int
539ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
540 const struct ppc4xx_ecc_status *status,
541 char *buffer,
542 size_t size)
543{
544 unsigned int master;
545 bool read;
546
547 if ((status->besr & SDRAM_BESR_MASK) == 0)
548 return 0;
549
550 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
551 return 0;
552
553 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
554
555 master = SDRAM_BESR_M0ID_DECODE(status->besr);
556
557 return snprintf(buf: buffer, size,
558 fmt: "%s error w/ PLB master %u \"%s\"; ",
559 (read ? "Read" : "Write"),
560 master,
561 (((master >= SDRAM_PLB_M0ID_FIRST) &&
562 (master <= SDRAM_PLB_M0ID_LAST)) ?
563 ppc4xx_plb_masters[master] : "UNKNOWN"));
564}
565
566/**
567 * ppc4xx_edac_generate_message - generate interpretted status message
568 * @mci: A pointer to the EDAC memory controller instance associated
569 * with the driver-unique message being generated.
570 * @status: A pointer to the ECC status structure to generate the
571 * message from.
572 * @buffer: A pointer to the buffer in which to generate the
573 * message.
574 * @size: The size, in bytes, of space available in buffer.
575 *
576 * This routine generates to the provided buffer the driver-unique
577 * EDAC report message from the specified ECC status.
578 */
579static void
580ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
581 const struct ppc4xx_ecc_status *status,
582 char *buffer,
583 size_t size)
584{
585 int n;
586
587 if (buffer == NULL || size == 0)
588 return;
589
590 n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
591
592 if (n < 0 || n >= size)
593 return;
594
595 buffer += n;
596 size -= n;
597
598 ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
599}
600
601#ifdef DEBUG
602/**
603 * ppc4xx_ecc_dump_status - dump controller ECC status registers
604 * @mci: A pointer to the EDAC memory controller instance
605 * associated with the status being dumped.
606 * @status: A pointer to the ECC status structure to generate the
607 * dump from.
608 *
609 * This routine dumps to the kernel log buffer the raw and
610 * interpretted specified ECC status.
611 */
612static void
613ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
614 const struct ppc4xx_ecc_status *status)
615{
616 char message[PPC4XX_EDAC_MESSAGE_SIZE];
617
618 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
619
620 ppc4xx_edac_mc_printk(KERN_INFO, mci,
621 "\n"
622 "\tECCES: 0x%08x\n"
623 "\tWMIRQ: 0x%08x\n"
624 "\tBESR: 0x%08x\n"
625 "\tBEAR: 0x%08x%08x\n"
626 "\t%s\n",
627 status->ecces,
628 status->wmirq,
629 status->besr,
630 status->bearh,
631 status->bearl,
632 message);
633}
634#endif /* DEBUG */
635
636/**
637 * ppc4xx_ecc_get_status - get controller ECC status
638 * @mci: A pointer to the EDAC memory controller instance
639 * associated with the status being retrieved.
640 * @status: A pointer to the ECC status structure to populate the
641 * ECC status with.
642 *
643 * This routine reads and masks, as appropriate, all the relevant
644 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
645 * While we read all of them, for correctable errors, we only expect
646 * to deal with ECCES. For uncorrectable errors, we expect to deal
647 * with all of them.
648 */
649static void
650ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
651 struct ppc4xx_ecc_status *status)
652{
653 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
654 const dcr_host_t *dcr_host = &pdata->dcr_host;
655
656 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
657 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
658 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
659 status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
660 status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
661}
662
663/**
664 * ppc4xx_ecc_clear_status - clear controller ECC status
665 * @mci: A pointer to the EDAC memory controller instance
666 * associated with the status being cleared.
667 * @status: A pointer to the ECC status structure containing the
668 * values to write to clear the ECC status.
669 *
670 * This routine clears--by writing the masked (as appropriate) status
671 * values back to--the status registers that deal with
672 * ibm,sdram-4xx-ddr2 ECC errors.
673 */
674static void
675ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
676 const struct ppc4xx_ecc_status *status)
677{
678 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
679 const dcr_host_t *dcr_host = &pdata->dcr_host;
680
681 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
682 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
683 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
684 mtsdram(dcr_host, SDRAM_BEARL, 0);
685 mtsdram(dcr_host, SDRAM_BEARH, 0);
686}
687
688/**
689 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
690 * @mci: A pointer to the EDAC memory controller instance
691 * associated with the correctable error being handled and reported.
692 * @status: A pointer to the ECC status structure associated with
693 * the correctable error being handled and reported.
694 *
695 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
696 * correctable error. Per the aforementioned discussion, there's not
697 * enough status available to use the full EDAC correctable error
698 * interface, so we just pass driver-unique message to the "no info"
699 * interface.
700 */
701static void
702ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
703 const struct ppc4xx_ecc_status *status)
704{
705 int row;
706 char message[PPC4XX_EDAC_MESSAGE_SIZE];
707
708 ppc4xx_edac_generate_message(mci, status, buffer: message, size: sizeof(message));
709
710 for (row = 0; row < mci->nr_csrows; row++)
711 if (ppc4xx_edac_check_bank_error(status, bank: row))
712 edac_mc_handle_error(type: HW_EVENT_ERR_CORRECTED, mci, error_count: 1,
713 page_frame_number: 0, offset_in_page: 0, syndrome: 0,
714 top_layer: row, mid_layer: 0, low_layer: -1,
715 msg: message, other_detail: "");
716}
717
718/**
719 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
720 * @mci: A pointer to the EDAC memory controller instance
721 * associated with the uncorrectable error being handled and
722 * reported.
723 * @status: A pointer to the ECC status structure associated with
724 * the uncorrectable error being handled and reported.
725 *
726 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
727 * uncorrectable error.
728 */
729static void
730ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
731 const struct ppc4xx_ecc_status *status)
732{
733 const u64 bear = ((u64)status->bearh << 32 | status->bearl);
734 const unsigned long page = bear >> PAGE_SHIFT;
735 const unsigned long offset = bear & ~PAGE_MASK;
736 int row;
737 char message[PPC4XX_EDAC_MESSAGE_SIZE];
738
739 ppc4xx_edac_generate_message(mci, status, buffer: message, size: sizeof(message));
740
741 for (row = 0; row < mci->nr_csrows; row++)
742 if (ppc4xx_edac_check_bank_error(status, bank: row))
743 edac_mc_handle_error(type: HW_EVENT_ERR_UNCORRECTED, mci, error_count: 1,
744 page_frame_number: page, offset_in_page: offset, syndrome: 0,
745 top_layer: row, mid_layer: 0, low_layer: -1,
746 msg: message, other_detail: "");
747}
748
749/**
750 * ppc4xx_edac_check - check controller for ECC errors
751 * @mci: A pointer to the EDAC memory controller instance
752 * associated with the ibm,sdram-4xx-ddr2 controller being
753 * checked.
754 *
755 * This routine is used to check and post ECC errors and is called by
756 * both the EDAC polling thread and this driver's CE and UE interrupt
757 * handler.
758 */
759static void
760ppc4xx_edac_check(struct mem_ctl_info *mci)
761{
762#ifdef DEBUG
763 static unsigned int count;
764#endif
765 struct ppc4xx_ecc_status status;
766
767 ppc4xx_ecc_get_status(mci, status: &status);
768
769#ifdef DEBUG
770 if (count++ % 30 == 0)
771 ppc4xx_ecc_dump_status(mci, &status);
772#endif
773
774 if (status.ecces & SDRAM_ECCES_UE)
775 ppc4xx_edac_handle_ue(mci, status: &status);
776
777 if (status.ecces & SDRAM_ECCES_CE)
778 ppc4xx_edac_handle_ce(mci, status: &status);
779
780 ppc4xx_ecc_clear_status(mci, status: &status);
781}
782
783/**
784 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
785 * @irq: The virtual interrupt number being serviced.
786 * @dev_id: A pointer to the EDAC memory controller instance
787 * associated with the interrupt being handled.
788 *
789 * This routine implements the interrupt handler for both correctable
790 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
791 * controller. It simply calls through to the same routine used during
792 * polling to check, report and clear the ECC status.
793 *
794 * Unconditionally returns IRQ_HANDLED.
795 */
796static irqreturn_t
797ppc4xx_edac_isr(int irq, void *dev_id)
798{
799 struct mem_ctl_info *mci = dev_id;
800
801 ppc4xx_edac_check(mci);
802
803 return IRQ_HANDLED;
804}
805
806/**
807 * ppc4xx_edac_get_dtype - return the controller memory width
808 * @mcopt1: The 32-bit Memory Controller Option 1 register value
809 * currently set for the controller, from which the width
810 * is derived.
811 *
812 * This routine returns the EDAC device type width appropriate for the
813 * current controller configuration.
814 *
815 * TODO: This needs to be conditioned dynamically through feature
816 * flags or some such when other controller variants are supported as
817 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
818 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
819 * among them.
820 *
821 * Returns a device type width enumeration.
822 */
823static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1)
824{
825 switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
826 case SDRAM_MCOPT1_WDTH_16:
827 return DEV_X2;
828 case SDRAM_MCOPT1_WDTH_32:
829 return DEV_X4;
830 default:
831 return DEV_UNKNOWN;
832 }
833}
834
835/**
836 * ppc4xx_edac_get_mtype - return controller memory type
837 * @mcopt1: The 32-bit Memory Controller Option 1 register value
838 * currently set for the controller, from which the memory type
839 * is derived.
840 *
841 * This routine returns the EDAC memory type appropriate for the
842 * current controller configuration.
843 *
844 * Returns a memory type enumeration.
845 */
846static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1)
847{
848 bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
849
850 switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
851 case SDRAM_MCOPT1_DDR2_TYPE:
852 return rden ? MEM_RDDR2 : MEM_DDR2;
853 case SDRAM_MCOPT1_DDR1_TYPE:
854 return rden ? MEM_RDDR : MEM_DDR;
855 default:
856 return MEM_UNKNOWN;
857 }
858}
859
860/**
861 * ppc4xx_edac_init_csrows - initialize driver instance rows
862 * @mci: A pointer to the EDAC memory controller instance
863 * associated with the ibm,sdram-4xx-ddr2 controller for which
864 * the csrows (i.e. banks/ranks) are being initialized.
865 * @mcopt1: The 32-bit Memory Controller Option 1 register value
866 * currently set for the controller, from which bank width
867 * and memory typ information is derived.
868 *
869 * This routine initializes the virtual "chip select rows" associated
870 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
871 * controller bank/rank is mapped to a row.
872 *
873 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
874 * configuration cannot be determined.
875 */
876static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
877{
878 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
879 int status = 0;
880 enum mem_type mtype;
881 enum dev_type dtype;
882 enum edac_type edac_mode;
883 int row, j;
884 u32 mbxcf, size, nr_pages;
885
886 /* Establish the memory type and width */
887
888 mtype = ppc4xx_edac_get_mtype(mcopt1);
889 dtype = ppc4xx_edac_get_dtype(mcopt1);
890
891 /* Establish EDAC mode */
892
893 if (mci->edac_cap & EDAC_FLAG_SECDED)
894 edac_mode = EDAC_SECDED;
895 else if (mci->edac_cap & EDAC_FLAG_EC)
896 edac_mode = EDAC_EC;
897 else
898 edac_mode = EDAC_NONE;
899
900 /*
901 * Initialize each chip select row structure which correspond
902 * 1:1 with a controller bank/rank.
903 */
904
905 for (row = 0; row < mci->nr_csrows; row++) {
906 struct csrow_info *csi = mci->csrows[row];
907
908 /*
909 * Get the configuration settings for this
910 * row/bank/rank and skip disabled banks.
911 */
912
913 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
914
915 if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
916 continue;
917
918 /* Map the bank configuration size setting to pages. */
919
920 size = mbxcf & SDRAM_MBCF_SZ_MASK;
921
922 switch (size) {
923 case SDRAM_MBCF_SZ_4MB:
924 case SDRAM_MBCF_SZ_8MB:
925 case SDRAM_MBCF_SZ_16MB:
926 case SDRAM_MBCF_SZ_32MB:
927 case SDRAM_MBCF_SZ_64MB:
928 case SDRAM_MBCF_SZ_128MB:
929 case SDRAM_MBCF_SZ_256MB:
930 case SDRAM_MBCF_SZ_512MB:
931 case SDRAM_MBCF_SZ_1GB:
932 case SDRAM_MBCF_SZ_2GB:
933 case SDRAM_MBCF_SZ_4GB:
934 case SDRAM_MBCF_SZ_8GB:
935 nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
936 break;
937 default:
938 ppc4xx_edac_mc_printk(KERN_ERR, mci,
939 "Unrecognized memory bank %d "
940 "size 0x%08x\n",
941 row, SDRAM_MBCF_SZ_DECODE(size));
942 status = -EINVAL;
943 goto done;
944 }
945
946 /*
947 * It's unclear exactly what grain should be set to
948 * here. The SDRAM_ECCES register allows resolution of
949 * an error down to a nibble which would potentially
950 * argue for a grain of '1' byte, even though we only
951 * know the associated address for uncorrectable
952 * errors. This value is not used at present for
953 * anything other than error reporting so getting it
954 * wrong should be of little consequence. Other
955 * possible values would be the PLB width (16), the
956 * page size (PAGE_SIZE) or the memory width (2 or 4).
957 */
958 for (j = 0; j < csi->nr_channels; j++) {
959 struct dimm_info *dimm = csi->channels[j]->dimm;
960
961 dimm->nr_pages = nr_pages / csi->nr_channels;
962 dimm->grain = 1;
963
964 dimm->mtype = mtype;
965 dimm->dtype = dtype;
966
967 dimm->edac_mode = edac_mode;
968 }
969 }
970
971 done:
972 return status;
973}
974
975/**
976 * ppc4xx_edac_mc_init - initialize driver instance
977 * @mci: A pointer to the EDAC memory controller instance being
978 * initialized.
979 * @op: A pointer to the OpenFirmware device tree node associated
980 * with the controller this EDAC instance is bound to.
981 * @dcr_host: A pointer to the DCR data containing the DCR mapping
982 * for this controller instance.
983 * @mcopt1: The 32-bit Memory Controller Option 1 register value
984 * currently set for the controller, from which ECC capabilities
985 * and scrub mode are derived.
986 *
987 * This routine performs initialization of the EDAC memory controller
988 * instance and related driver-private data associated with the
989 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
990 *
991 * Returns 0 if OK; otherwise, < 0 on error.
992 */
993static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
994 struct platform_device *op,
995 const dcr_host_t *dcr_host, u32 mcopt1)
996{
997 int status = 0;
998 const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
999 struct ppc4xx_edac_pdata *pdata = NULL;
1000 const struct device_node *np = op->dev.of_node;
1001
1002 if (of_match_device(matches: ppc4xx_edac_match, dev: &op->dev) == NULL)
1003 return -EINVAL;
1004
1005 /* Initial driver pointers and private data */
1006
1007 mci->pdev = &op->dev;
1008
1009 dev_set_drvdata(dev: mci->pdev, data: mci);
1010
1011 pdata = mci->pvt_info;
1012
1013 pdata->dcr_host = *dcr_host;
1014
1015 /* Initialize controller capabilities and configuration */
1016
1017 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1018 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1019
1020 mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1021 EDAC_FLAG_EC |
1022 EDAC_FLAG_SECDED);
1023
1024 mci->scrub_cap = SCRUB_NONE;
1025 mci->scrub_mode = SCRUB_NONE;
1026
1027 /*
1028 * Update the actual capabilites based on the MCOPT1[MCHK]
1029 * settings. Scrubbing is only useful if reporting is enabled.
1030 */
1031
1032 switch (memcheck) {
1033 case SDRAM_MCOPT1_MCHK_CHK:
1034 mci->edac_cap = EDAC_FLAG_EC;
1035 break;
1036 case SDRAM_MCOPT1_MCHK_CHK_REP:
1037 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1038 mci->scrub_mode = SCRUB_SW_SRC;
1039 break;
1040 default:
1041 mci->edac_cap = EDAC_FLAG_NONE;
1042 break;
1043 }
1044
1045 /* Initialize strings */
1046
1047 mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1048 mci->ctl_name = ppc4xx_edac_match->compatible;
1049 mci->dev_name = np->full_name;
1050
1051 /* Initialize callbacks */
1052
1053 mci->edac_check = ppc4xx_edac_check;
1054 mci->ctl_page_to_phys = NULL;
1055
1056 /* Initialize chip select rows */
1057
1058 status = ppc4xx_edac_init_csrows(mci, mcopt1);
1059
1060 if (status)
1061 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1062 "Failed to initialize rows!\n");
1063
1064 return status;
1065}
1066
1067/**
1068 * ppc4xx_edac_register_irq - setup and register controller interrupts
1069 * @op: A pointer to the OpenFirmware device tree node associated
1070 * with the controller this EDAC instance is bound to.
1071 * @mci: A pointer to the EDAC memory controller instance
1072 * associated with the ibm,sdram-4xx-ddr2 controller for which
1073 * interrupts are being registered.
1074 *
1075 * This routine parses the correctable (CE) and uncorrectable error (UE)
1076 * interrupts from the device tree node and maps and assigns them to
1077 * the associated EDAC memory controller instance.
1078 *
1079 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1080 * mapped and assigned.
1081 */
1082static int ppc4xx_edac_register_irq(struct platform_device *op,
1083 struct mem_ctl_info *mci)
1084{
1085 int status = 0;
1086 int ded_irq, sec_irq;
1087 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1088 struct device_node *np = op->dev.of_node;
1089
1090 ded_irq = irq_of_parse_and_map(node: np, INTMAP_ECCDED_INDEX);
1091 sec_irq = irq_of_parse_and_map(node: np, INTMAP_ECCSEC_INDEX);
1092
1093 if (!ded_irq || !sec_irq) {
1094 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1095 "Unable to map interrupts.\n");
1096 status = -ENODEV;
1097 goto fail;
1098 }
1099
1100 status = request_irq(irq: ded_irq,
1101 handler: ppc4xx_edac_isr,
1102 flags: 0,
1103 name: "[EDAC] MC ECCDED",
1104 dev: mci);
1105
1106 if (status < 0) {
1107 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1108 "Unable to request irq %d for ECC DED",
1109 ded_irq);
1110 status = -ENODEV;
1111 goto fail1;
1112 }
1113
1114 status = request_irq(irq: sec_irq,
1115 handler: ppc4xx_edac_isr,
1116 flags: 0,
1117 name: "[EDAC] MC ECCSEC",
1118 dev: mci);
1119
1120 if (status < 0) {
1121 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1122 "Unable to request irq %d for ECC SEC",
1123 sec_irq);
1124 status = -ENODEV;
1125 goto fail2;
1126 }
1127
1128 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1129 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1130
1131 pdata->irqs.ded = ded_irq;
1132 pdata->irqs.sec = sec_irq;
1133
1134 return 0;
1135
1136 fail2:
1137 free_irq(sec_irq, mci);
1138
1139 fail1:
1140 free_irq(ded_irq, mci);
1141
1142 fail:
1143 return status;
1144}
1145
1146/**
1147 * ppc4xx_edac_map_dcrs - locate and map controller registers
1148 * @np: A pointer to the device tree node containing the DCR
1149 * resources to map.
1150 * @dcr_host: A pointer to the DCR data to populate with the
1151 * DCR mapping.
1152 *
1153 * This routine attempts to locate in the device tree and map the DCR
1154 * register resources associated with the controller's indirect DCR
1155 * address and data windows.
1156 *
1157 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1158 * error.
1159 */
1160static int ppc4xx_edac_map_dcrs(const struct device_node *np,
1161 dcr_host_t *dcr_host)
1162{
1163 unsigned int dcr_base, dcr_len;
1164
1165 if (np == NULL || dcr_host == NULL)
1166 return -EINVAL;
1167
1168 /* Get the DCR resource extent and sanity check the values. */
1169
1170 dcr_base = dcr_resource_start(np, 0);
1171 dcr_len = dcr_resource_len(np, 0);
1172
1173 if (dcr_base == 0 || dcr_len == 0) {
1174 ppc4xx_edac_printk(KERN_ERR,
1175 "Failed to obtain DCR property.\n");
1176 return -ENODEV;
1177 }
1178
1179 if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1180 ppc4xx_edac_printk(KERN_ERR,
1181 "Unexpected DCR length %d, expected %d.\n",
1182 dcr_len, SDRAM_DCR_RESOURCE_LEN);
1183 return -ENODEV;
1184 }
1185
1186 /* Attempt to map the DCR extent. */
1187
1188 *dcr_host = dcr_map(np, dcr_base, dcr_len);
1189
1190 if (!DCR_MAP_OK(*dcr_host)) {
1191 ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1192 return -ENODEV;
1193 }
1194
1195 return 0;
1196}
1197
1198/**
1199 * ppc4xx_edac_probe - check controller and bind driver
1200 * @op: A pointer to the OpenFirmware device tree node associated
1201 * with the controller being probed for driver binding.
1202 *
1203 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1204 * instance for binding with the driver.
1205 *
1206 * Returns 0 if the controller instance was successfully bound to the
1207 * driver; otherwise, < 0 on error.
1208 */
1209static int ppc4xx_edac_probe(struct platform_device *op)
1210{
1211 int status = 0;
1212 u32 mcopt1, memcheck;
1213 dcr_host_t dcr_host;
1214 const struct device_node *np = op->dev.of_node;
1215 struct mem_ctl_info *mci = NULL;
1216 struct edac_mc_layer layers[2];
1217 static int ppc4xx_edac_instance;
1218
1219 /*
1220 * At this point, we only support the controller realized on
1221 * the AMCC PPC 405EX[r]. Reject anything else.
1222 */
1223
1224 if (!of_device_is_compatible(device: np, "ibm,sdram-405ex") &&
1225 !of_device_is_compatible(device: np, "ibm,sdram-405exr")) {
1226 ppc4xx_edac_printk(KERN_NOTICE,
1227 "Only the PPC405EX[r] is supported.\n");
1228 return -ENODEV;
1229 }
1230
1231 /*
1232 * Next, get the DCR property and attempt to map it so that we
1233 * can probe the controller.
1234 */
1235
1236 status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1237
1238 if (status)
1239 return status;
1240
1241 /*
1242 * First determine whether ECC is enabled at all. If not,
1243 * there is no useful checking or monitoring that can be done
1244 * for this controller.
1245 */
1246
1247 mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1248 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1249
1250 if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1251 ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or "
1252 "ECC is disabled.\n", np);
1253 status = -ENODEV;
1254 goto done;
1255 }
1256
1257 /*
1258 * At this point, we know ECC is enabled, allocate an EDAC
1259 * controller instance and perform the appropriate
1260 * initialization.
1261 */
1262 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1263 layers[0].size = ppc4xx_edac_nr_csrows;
1264 layers[0].is_virt_csrow = true;
1265 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1266 layers[1].size = ppc4xx_edac_nr_chans;
1267 layers[1].is_virt_csrow = false;
1268 mci = edac_mc_alloc(mc_num: ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
1269 sz_pvt: sizeof(struct ppc4xx_edac_pdata));
1270 if (mci == NULL) {
1271 ppc4xx_edac_printk(KERN_ERR, "%pOF: "
1272 "Failed to allocate EDAC MC instance!\n",
1273 np);
1274 status = -ENOMEM;
1275 goto done;
1276 }
1277
1278 status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1279
1280 if (status) {
1281 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1282 "Failed to initialize instance!\n");
1283 goto fail;
1284 }
1285
1286 /*
1287 * We have a valid, initialized EDAC instance bound to the
1288 * controller. Attempt to register it with the EDAC subsystem
1289 * and, if necessary, register interrupts.
1290 */
1291
1292 if (edac_mc_add_mc(mci)) {
1293 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1294 "Failed to add instance!\n");
1295 status = -ENODEV;
1296 goto fail;
1297 }
1298
1299 if (edac_op_state == EDAC_OPSTATE_INT) {
1300 status = ppc4xx_edac_register_irq(op, mci);
1301
1302 if (status)
1303 goto fail1;
1304 }
1305
1306 ppc4xx_edac_instance++;
1307
1308 return 0;
1309
1310 fail1:
1311 edac_mc_del_mc(dev: mci->pdev);
1312
1313 fail:
1314 edac_mc_free(mci);
1315
1316 done:
1317 return status;
1318}
1319
1320/**
1321 * ppc4xx_edac_remove - unbind driver from controller
1322 * @op: A pointer to the OpenFirmware device tree node associated
1323 * with the controller this EDAC instance is to be unbound/removed
1324 * from.
1325 *
1326 * This routine unbinds the EDAC memory controller instance associated
1327 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1328 * OpenFirmware device tree node passed as a parameter.
1329 *
1330 * Unconditionally returns 0.
1331 */
1332static void ppc4xx_edac_remove(struct platform_device *op)
1333{
1334 struct mem_ctl_info *mci = dev_get_drvdata(dev: &op->dev);
1335 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1336
1337 if (edac_op_state == EDAC_OPSTATE_INT) {
1338 free_irq(pdata->irqs.sec, mci);
1339 free_irq(pdata->irqs.ded, mci);
1340 }
1341
1342 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1343
1344 edac_mc_del_mc(dev: mci->pdev);
1345 edac_mc_free(mci);
1346}
1347
1348/**
1349 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1350 *
1351 * This routine ensures that the EDAC memory controller reporting
1352 * method is mapped to a sane value as the EDAC core defines the value
1353 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1354 * opstate_init as that defaults to polling and we want interrupt as
1355 * the default.
1356 */
1357static inline void __init
1358ppc4xx_edac_opstate_init(void)
1359{
1360 switch (edac_op_state) {
1361 case EDAC_OPSTATE_POLL:
1362 case EDAC_OPSTATE_INT:
1363 break;
1364 default:
1365 edac_op_state = EDAC_OPSTATE_INT;
1366 break;
1367 }
1368
1369 ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1370 ((edac_op_state == EDAC_OPSTATE_POLL) ?
1371 EDAC_OPSTATE_POLL_STR :
1372 ((edac_op_state == EDAC_OPSTATE_INT) ?
1373 EDAC_OPSTATE_INT_STR :
1374 EDAC_OPSTATE_UNKNOWN_STR)));
1375}
1376
1377static struct platform_driver ppc4xx_edac_driver = {
1378 .probe = ppc4xx_edac_probe,
1379 .remove_new = ppc4xx_edac_remove,
1380 .driver = {
1381 .name = PPC4XX_EDAC_MODULE_NAME,
1382 .of_match_table = ppc4xx_edac_match,
1383 },
1384};
1385
1386/**
1387 * ppc4xx_edac_init - driver/module insertion entry point
1388 *
1389 * This routine is the driver/module insertion entry point. It
1390 * initializes the EDAC memory controller reporting state and
1391 * registers the driver as an OpenFirmware device tree platform
1392 * driver.
1393 */
1394static int __init
1395ppc4xx_edac_init(void)
1396{
1397 ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1398
1399 ppc4xx_edac_opstate_init();
1400
1401 return platform_driver_register(&ppc4xx_edac_driver);
1402}
1403
1404/**
1405 * ppc4xx_edac_exit - driver/module removal entry point
1406 *
1407 * This routine is the driver/module removal entry point. It
1408 * unregisters the driver as an OpenFirmware device tree platform
1409 * driver.
1410 */
1411static void __exit
1412ppc4xx_edac_exit(void)
1413{
1414 platform_driver_unregister(&ppc4xx_edac_driver);
1415}
1416
1417module_init(ppc4xx_edac_init);
1418module_exit(ppc4xx_edac_exit);
1419
1420MODULE_LICENSE("GPL v2");
1421MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1422MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1423module_param(edac_op_state, int, 0444);
1424MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1425 "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
1426

source code of linux/drivers/edac/ppc4xx_edac.c