1 | /* |
2 | * Radisys 82600 Embedded chipset Memory Controller kernel module |
3 | * (C) 2005 EADS Astrium |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. |
6 | * |
7 | * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne |
8 | * Harbaugh, Dan Hollis <goemon at anime dot net> and others. |
9 | * |
10 | * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ |
11 | * |
12 | * Written with reference to 82600 High Integration Dual PCI System |
13 | * Controller Data Book: |
14 | * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf |
15 | * references to this document given in [] |
16 | */ |
17 | |
18 | #include <linux/module.h> |
19 | #include <linux/init.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/pci_ids.h> |
22 | #include <linux/edac.h> |
23 | #include "edac_module.h" |
24 | |
25 | #define EDAC_MOD_STR "r82600_edac" |
26 | |
27 | #define r82600_printk(level, fmt, arg...) \ |
28 | edac_printk(level, "r82600", fmt, ##arg) |
29 | |
30 | #define r82600_mc_printk(mci, level, fmt, arg...) \ |
31 | edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) |
32 | |
33 | /* Radisys say "The 82600 integrates a main memory SDRAM controller that |
34 | * supports up to four banks of memory. The four banks can support a mix of |
35 | * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, |
36 | * each of which can be any size from 16MB to 512MB. Both registered (control |
37 | * signals buffered) and unbuffered DIMM types are supported. Mixing of |
38 | * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs |
39 | * is not allowed. The 82600 SDRAM interface operates at the same frequency as |
40 | * the CPU bus, 66MHz, 100MHz or 133MHz." |
41 | */ |
42 | |
43 | #define R82600_NR_CSROWS 4 |
44 | #define R82600_NR_CHANS 1 |
45 | #define R82600_NR_DIMMS 4 |
46 | |
47 | #define R82600_BRIDGE_ID 0x8200 |
48 | |
49 | /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ |
50 | #define R82600_DRAMC 0x57 /* Various SDRAM related control bits |
51 | * all bits are R/W |
52 | * |
53 | * 7 SDRAM ISA Hole Enable |
54 | * 6 Flash Page Mode Enable |
55 | * 5 ECC Enable: 1=ECC 0=noECC |
56 | * 4 DRAM DIMM Type: 1= |
57 | * 3 BIOS Alias Disable |
58 | * 2 SDRAM BIOS Flash Write Enable |
59 | * 1:0 SDRAM Refresh Rate: 00=Disabled |
60 | * 01=7.8usec (256Mbit SDRAMs) |
61 | * 10=15.6us 11=125usec |
62 | */ |
63 | |
64 | #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" |
65 | * More SDRAM related control bits |
66 | * all bits are R/W |
67 | * |
68 | * 15:8 Reserved. |
69 | * |
70 | * 7:5 Special SDRAM Mode Select |
71 | * |
72 | * 4 Force ECC |
73 | * |
74 | * 1=Drive ECC bits to 0 during |
75 | * write cycles (i.e. ECC test mode) |
76 | * |
77 | * 0=Normal ECC functioning |
78 | * |
79 | * 3 Enhanced Paging Enable |
80 | * |
81 | * 2 CAS# Latency 0=3clks 1=2clks |
82 | * |
83 | * 1 RAS# to CAS# Delay 0=3 1=2 |
84 | * |
85 | * 0 RAS# Precharge 0=3 1=2 |
86 | */ |
87 | |
88 | #define R82600_EAP 0x80 /* ECC Error Address Pointer Register |
89 | * |
90 | * 31 Disable Hardware Scrubbing (RW) |
91 | * 0=Scrub on corrected read |
92 | * 1=Don't scrub on corrected read |
93 | * |
94 | * 30:12 Error Address Pointer (RO) |
95 | * Upper 19 bits of error address |
96 | * |
97 | * 11:4 Syndrome Bits (RO) |
98 | * |
99 | * 3 BSERR# on multibit error (RW) |
100 | * 1=enable 0=disable |
101 | * |
102 | * 2 NMI on Single Bit Eror (RW) |
103 | * 1=NMI triggered by SBE n.b. other |
104 | * prerequeists |
105 | * 0=NMI not triggered |
106 | * |
107 | * 1 MBE (R/WC) |
108 | * read 1=MBE at EAP (see above) |
109 | * read 0=no MBE, or SBE occurred first |
110 | * write 1=Clear MBE status (must also |
111 | * clear SBE) |
112 | * write 0=NOP |
113 | * |
114 | * 1 SBE (R/WC) |
115 | * read 1=SBE at EAP (see above) |
116 | * read 0=no SBE, or MBE occurred first |
117 | * write 1=Clear SBE status (must also |
118 | * clear MBE) |
119 | * write 0=NOP |
120 | */ |
121 | |
122 | #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address |
123 | * Registers |
124 | * |
125 | * 7:0 Address lines 30:24 - upper limit of |
126 | * each row [p57] |
127 | */ |
128 | |
129 | struct r82600_error_info { |
130 | u32 eapr; |
131 | }; |
132 | |
133 | static bool disable_hardware_scrub; |
134 | |
135 | static struct edac_pci_ctl_info *r82600_pci; |
136 | |
137 | static void r82600_get_error_info(struct mem_ctl_info *mci, |
138 | struct r82600_error_info *info) |
139 | { |
140 | struct pci_dev *pdev; |
141 | |
142 | pdev = to_pci_dev(mci->pdev); |
143 | pci_read_config_dword(dev: pdev, R82600_EAP, val: &info->eapr); |
144 | |
145 | if (info->eapr & BIT(0)) |
146 | /* Clear error to allow next error to be reported [p.62] */ |
147 | pci_write_bits32(pdev, R82600_EAP, |
148 | value: ((u32) BIT(0) & (u32) BIT(1)), |
149 | mask: ((u32) BIT(0) & (u32) BIT(1))); |
150 | |
151 | if (info->eapr & BIT(1)) |
152 | /* Clear error to allow next error to be reported [p.62] */ |
153 | pci_write_bits32(pdev, R82600_EAP, |
154 | value: ((u32) BIT(0) & (u32) BIT(1)), |
155 | mask: ((u32) BIT(0) & (u32) BIT(1))); |
156 | } |
157 | |
158 | static int r82600_process_error_info(struct mem_ctl_info *mci, |
159 | struct r82600_error_info *info, |
160 | int handle_errors) |
161 | { |
162 | int error_found; |
163 | u32 eapaddr, page; |
164 | u32 syndrome; |
165 | |
166 | error_found = 0; |
167 | |
168 | /* bits 30:12 store the upper 19 bits of the 32 bit error address */ |
169 | eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; |
170 | /* Syndrome in bits 11:4 [p.62] */ |
171 | syndrome = (info->eapr >> 4) & 0xFF; |
172 | |
173 | /* the R82600 reports at less than page * |
174 | * granularity (upper 19 bits only) */ |
175 | page = eapaddr >> PAGE_SHIFT; |
176 | |
177 | if (info->eapr & BIT(0)) { /* CE? */ |
178 | error_found = 1; |
179 | |
180 | if (handle_errors) |
181 | edac_mc_handle_error(type: HW_EVENT_ERR_CORRECTED, mci, error_count: 1, |
182 | page_frame_number: page, offset_in_page: 0, syndrome, |
183 | top_layer: edac_mc_find_csrow_by_page(mci, page), |
184 | mid_layer: 0, low_layer: -1, |
185 | msg: mci->ctl_name, other_detail: "" ); |
186 | } |
187 | |
188 | if (info->eapr & BIT(1)) { /* UE? */ |
189 | error_found = 1; |
190 | |
191 | if (handle_errors) |
192 | /* 82600 doesn't give enough info */ |
193 | edac_mc_handle_error(type: HW_EVENT_ERR_UNCORRECTED, mci, error_count: 1, |
194 | page_frame_number: page, offset_in_page: 0, syndrome: 0, |
195 | top_layer: edac_mc_find_csrow_by_page(mci, page), |
196 | mid_layer: 0, low_layer: -1, |
197 | msg: mci->ctl_name, other_detail: "" ); |
198 | } |
199 | |
200 | return error_found; |
201 | } |
202 | |
203 | static void r82600_check(struct mem_ctl_info *mci) |
204 | { |
205 | struct r82600_error_info info; |
206 | |
207 | r82600_get_error_info(mci, info: &info); |
208 | r82600_process_error_info(mci, info: &info, handle_errors: 1); |
209 | } |
210 | |
211 | static inline int ecc_enabled(u8 dramcr) |
212 | { |
213 | return dramcr & BIT(5); |
214 | } |
215 | |
216 | static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
217 | u8 dramcr) |
218 | { |
219 | struct csrow_info *csrow; |
220 | struct dimm_info *dimm; |
221 | int index; |
222 | u8 drbar; /* SDRAM Row Boundary Address Register */ |
223 | u32 row_high_limit, row_high_limit_last; |
224 | u32 reg_sdram, ecc_on, row_base; |
225 | |
226 | ecc_on = ecc_enabled(dramcr); |
227 | reg_sdram = dramcr & BIT(4); |
228 | row_high_limit_last = 0; |
229 | |
230 | for (index = 0; index < mci->nr_csrows; index++) { |
231 | csrow = mci->csrows[index]; |
232 | dimm = csrow->channels[0]->dimm; |
233 | |
234 | /* find the DRAM Chip Select Base address and mask */ |
235 | pci_read_config_byte(dev: pdev, R82600_DRBA + index, val: &drbar); |
236 | |
237 | edac_dbg(1, "Row=%d DRBA = %#0x\n" , index, drbar); |
238 | |
239 | row_high_limit = ((u32) drbar << 24); |
240 | /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ |
241 | |
242 | edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n" , |
243 | index, row_high_limit, row_high_limit_last); |
244 | |
245 | /* Empty row [p.57] */ |
246 | if (row_high_limit == row_high_limit_last) |
247 | continue; |
248 | |
249 | row_base = row_high_limit_last; |
250 | |
251 | csrow->first_page = row_base >> PAGE_SHIFT; |
252 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; |
253 | |
254 | dimm->nr_pages = csrow->last_page - csrow->first_page + 1; |
255 | /* Error address is top 19 bits - so granularity is * |
256 | * 14 bits */ |
257 | dimm->grain = 1 << 14; |
258 | dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; |
259 | /* FIXME - check that this is unknowable with this chipset */ |
260 | dimm->dtype = DEV_UNKNOWN; |
261 | |
262 | /* Mode is global on 82600 */ |
263 | dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; |
264 | row_high_limit_last = row_high_limit; |
265 | } |
266 | } |
267 | |
268 | static int r82600_probe1(struct pci_dev *pdev, int dev_idx) |
269 | { |
270 | struct mem_ctl_info *mci; |
271 | struct edac_mc_layer layers[2]; |
272 | u8 dramcr; |
273 | u32 eapr; |
274 | u32 scrub_disabled; |
275 | u32 sdram_refresh_rate; |
276 | struct r82600_error_info discard; |
277 | |
278 | edac_dbg(0, "\n" ); |
279 | pci_read_config_byte(dev: pdev, R82600_DRAMC, val: &dramcr); |
280 | pci_read_config_dword(dev: pdev, R82600_EAP, val: &eapr); |
281 | scrub_disabled = eapr & BIT(31); |
282 | sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); |
283 | edac_dbg(2, "sdram refresh rate = %#0x\n" , sdram_refresh_rate); |
284 | edac_dbg(2, "DRAMC register = %#0x\n" , dramcr); |
285 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
286 | layers[0].size = R82600_NR_CSROWS; |
287 | layers[0].is_virt_csrow = true; |
288 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
289 | layers[1].size = R82600_NR_CHANS; |
290 | layers[1].is_virt_csrow = false; |
291 | mci = edac_mc_alloc(mc_num: 0, ARRAY_SIZE(layers), layers, sz_pvt: 0); |
292 | if (mci == NULL) |
293 | return -ENOMEM; |
294 | |
295 | edac_dbg(0, "mci = %p\n" , mci); |
296 | mci->pdev = &pdev->dev; |
297 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; |
298 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
299 | /* FIXME try to work out if the chip leads have been used for COM2 |
300 | * instead on this board? [MA6?] MAYBE: |
301 | */ |
302 | |
303 | /* On the R82600, the pins for memory bits 72:65 - i.e. the * |
304 | * EC bits are shared with the pins for COM2 (!), so if COM2 * |
305 | * is enabled, we assume COM2 is wired up, and thus no EDAC * |
306 | * is possible. */ |
307 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
308 | |
309 | if (ecc_enabled(dramcr)) { |
310 | if (scrub_disabled) |
311 | edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n" , |
312 | mci, eapr); |
313 | } else |
314 | mci->edac_cap = EDAC_FLAG_NONE; |
315 | |
316 | mci->mod_name = EDAC_MOD_STR; |
317 | mci->ctl_name = "R82600" ; |
318 | mci->dev_name = pci_name(pdev); |
319 | mci->edac_check = r82600_check; |
320 | mci->ctl_page_to_phys = NULL; |
321 | r82600_init_csrows(mci, pdev, dramcr); |
322 | r82600_get_error_info(mci, info: &discard); /* clear counters */ |
323 | |
324 | /* Here we assume that we will never see multiple instances of this |
325 | * type of memory controller. The ID is therefore hardcoded to 0. |
326 | */ |
327 | if (edac_mc_add_mc(mci)) { |
328 | edac_dbg(3, "failed edac_mc_add_mc()\n" ); |
329 | goto fail; |
330 | } |
331 | |
332 | /* get this far and it's successful */ |
333 | |
334 | if (disable_hardware_scrub) { |
335 | edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n" ); |
336 | pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); |
337 | } |
338 | |
339 | /* allocating generic PCI control info */ |
340 | r82600_pci = edac_pci_create_generic_ctl(dev: &pdev->dev, EDAC_MOD_STR); |
341 | if (!r82600_pci) { |
342 | printk(KERN_WARNING |
343 | "%s(): Unable to create PCI control\n" , |
344 | __func__); |
345 | printk(KERN_WARNING |
346 | "%s(): PCI error report via EDAC not setup\n" , |
347 | __func__); |
348 | } |
349 | |
350 | edac_dbg(3, "success\n" ); |
351 | return 0; |
352 | |
353 | fail: |
354 | edac_mc_free(mci); |
355 | return -ENODEV; |
356 | } |
357 | |
358 | /* returns count (>= 0), or negative on error */ |
359 | static int r82600_init_one(struct pci_dev *pdev, |
360 | const struct pci_device_id *ent) |
361 | { |
362 | edac_dbg(0, "\n" ); |
363 | |
364 | /* don't need to call pci_enable_device() */ |
365 | return r82600_probe1(pdev, dev_idx: ent->driver_data); |
366 | } |
367 | |
368 | static void r82600_remove_one(struct pci_dev *pdev) |
369 | { |
370 | struct mem_ctl_info *mci; |
371 | |
372 | edac_dbg(0, "\n" ); |
373 | |
374 | if (r82600_pci) |
375 | edac_pci_release_generic_ctl(pci: r82600_pci); |
376 | |
377 | if ((mci = edac_mc_del_mc(dev: &pdev->dev)) == NULL) |
378 | return; |
379 | |
380 | edac_mc_free(mci); |
381 | } |
382 | |
383 | static const struct pci_device_id r82600_pci_tbl[] = { |
384 | { |
385 | PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) |
386 | }, |
387 | { |
388 | 0, |
389 | } /* 0 terminated list. */ |
390 | }; |
391 | |
392 | MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); |
393 | |
394 | static struct pci_driver r82600_driver = { |
395 | .name = EDAC_MOD_STR, |
396 | .probe = r82600_init_one, |
397 | .remove = r82600_remove_one, |
398 | .id_table = r82600_pci_tbl, |
399 | }; |
400 | |
401 | static int __init r82600_init(void) |
402 | { |
403 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
404 | opstate_init(); |
405 | |
406 | return pci_register_driver(&r82600_driver); |
407 | } |
408 | |
409 | static void __exit r82600_exit(void) |
410 | { |
411 | pci_unregister_driver(dev: &r82600_driver); |
412 | } |
413 | |
414 | module_init(r82600_init); |
415 | module_exit(r82600_exit); |
416 | |
417 | MODULE_LICENSE("GPL" ); |
418 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. on behalf of EADS Astrium" ); |
419 | MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers" ); |
420 | |
421 | module_param(disable_hardware_scrub, bool, 0644); |
422 | MODULE_PARM_DESC(disable_hardware_scrub, |
423 | "If set, disable the chipset's automatic scrub for CEs" ); |
424 | |
425 | module_param(edac_op_state, int, 0444); |
426 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI" ); |
427 | |