1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. |
4 | * Originally split out from the skx_edac driver. |
5 | * |
6 | * Copyright (c) 2018, Intel Corporation. |
7 | */ |
8 | |
9 | #ifndef _SKX_COMM_EDAC_H |
10 | #define _SKX_COMM_EDAC_H |
11 | |
12 | #include <linux/bits.h> |
13 | #include <asm/mce.h> |
14 | |
15 | #define MSG_SIZE 1024 |
16 | |
17 | /* |
18 | * Debug macros |
19 | */ |
20 | #define skx_printk(level, fmt, arg...) \ |
21 | edac_printk(level, "skx", fmt, ##arg) |
22 | |
23 | #define skx_mc_printk(mci, level, fmt, arg...) \ |
24 | edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) |
25 | |
26 | /* |
27 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> |
28 | */ |
29 | #define GET_BITFIELD(v, lo, hi) \ |
30 | (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) |
31 | |
32 | #define SKX_NUM_IMC 2 /* Memory controllers per socket */ |
33 | #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ |
34 | #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ |
35 | |
36 | #define I10NM_NUM_DDR_IMC 12 |
37 | #define I10NM_NUM_DDR_CHANNELS 2 |
38 | #define I10NM_NUM_DDR_DIMMS 2 |
39 | |
40 | #define I10NM_NUM_HBM_IMC 16 |
41 | #define I10NM_NUM_HBM_CHANNELS 2 |
42 | #define I10NM_NUM_HBM_DIMMS 1 |
43 | |
44 | #define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC) |
45 | #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS) |
46 | #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) |
47 | |
48 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) |
49 | #define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC) |
50 | #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) |
51 | #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS) |
52 | |
53 | #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15) |
54 | #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i) |
55 | |
56 | #define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15) |
57 | #define MCI_MISC_ECC_DDRT 8 /* read from DDRT */ |
58 | |
59 | /* |
60 | * According to Intel Architecture spec vol 3B, |
61 | * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding" |
62 | * memory errors should fit one of these masks: |
63 | * 000f 0000 1mmm cccc (binary) |
64 | * 000f 0010 1mmm cccc (binary) [RAM used as cache] |
65 | * where: |
66 | * f = Correction Report Filtering Bit. If 1, subsequent errors |
67 | * won't be shown |
68 | * mmm = error type |
69 | * cccc = channel |
70 | */ |
71 | #define MCACOD_MEM_ERR_MASK 0xef80 |
72 | /* |
73 | * Errors from either the memory of the 1-level memory system or the |
74 | * 2nd level memory (the slow "far" memory) of the 2-level memory system. |
75 | */ |
76 | #define MCACOD_MEM_CTL_ERR 0x80 |
77 | /* |
78 | * Errors from the 1st level memory (the fast "near" memory as cache) |
79 | * of the 2-level memory system. |
80 | */ |
81 | #define MCACOD_EXT_MEM_ERR 0x280 |
82 | |
83 | /* |
84 | * Each cpu socket contains some pci devices that provide global |
85 | * information, and also some that are local to each of the two |
86 | * memory controllers on the die. |
87 | */ |
88 | struct skx_dev { |
89 | struct list_head list; |
90 | u8 bus[4]; |
91 | int seg; |
92 | struct pci_dev *sad_all; |
93 | struct pci_dev *util_all; |
94 | struct pci_dev *uracu; /* for i10nm CPU */ |
95 | struct pci_dev *pcu_cr3; /* for HBM memory detection */ |
96 | u32 mcroute; |
97 | struct skx_imc { |
98 | struct mem_ctl_info *mci; |
99 | struct pci_dev *mdev; /* for i10nm CPU */ |
100 | void __iomem *mbase; /* for i10nm CPU */ |
101 | int chan_mmio_sz; /* for i10nm CPU */ |
102 | int num_channels; /* channels per memory controller */ |
103 | int num_dimms; /* dimms per channel */ |
104 | bool hbm_mc; |
105 | u8 mc; /* system wide mc# */ |
106 | u8 lmc; /* socket relative mc# */ |
107 | u8 src_id, node_id; |
108 | struct skx_channel { |
109 | struct pci_dev *cdev; |
110 | struct pci_dev *edev; |
111 | u32 retry_rd_err_log_s; |
112 | u32 retry_rd_err_log_d; |
113 | u32 retry_rd_err_log_d2; |
114 | struct skx_dimm { |
115 | u8 close_pg; |
116 | u8 bank_xor_enable; |
117 | u8 fine_grain_bank; |
118 | u8 rowbits; |
119 | u8 colbits; |
120 | } dimms[NUM_DIMMS]; |
121 | } chan[NUM_CHANNELS]; |
122 | } imc[NUM_IMC]; |
123 | }; |
124 | |
125 | struct skx_pvt { |
126 | struct skx_imc *imc; |
127 | }; |
128 | |
129 | enum type { |
130 | SKX, |
131 | I10NM, |
132 | SPR, |
133 | GNR |
134 | }; |
135 | |
136 | enum { |
137 | INDEX_SOCKET, |
138 | INDEX_MEMCTRL, |
139 | INDEX_CHANNEL, |
140 | INDEX_DIMM, |
141 | INDEX_CS, |
142 | INDEX_NM_FIRST, |
143 | INDEX_NM_MEMCTRL = INDEX_NM_FIRST, |
144 | INDEX_NM_CHANNEL, |
145 | INDEX_NM_DIMM, |
146 | INDEX_NM_CS, |
147 | INDEX_MAX |
148 | }; |
149 | |
150 | #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL) |
151 | #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL) |
152 | #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM) |
153 | #define BIT_NM_CS BIT_ULL(INDEX_NM_CS) |
154 | |
155 | struct decoded_addr { |
156 | struct mce *mce; |
157 | struct skx_dev *dev; |
158 | u64 addr; |
159 | int socket; |
160 | int imc; |
161 | int channel; |
162 | u64 chan_addr; |
163 | int sktways; |
164 | int chanways; |
165 | int dimm; |
166 | int cs; |
167 | int rank; |
168 | int channel_rank; |
169 | u64 rank_address; |
170 | int row; |
171 | int column; |
172 | int bank_address; |
173 | int bank_group; |
174 | bool decoded_by_adxl; |
175 | }; |
176 | |
177 | struct pci_bdf { |
178 | u32 bus : 8; |
179 | u32 dev : 5; |
180 | u32 fun : 3; |
181 | }; |
182 | |
183 | struct res_config { |
184 | enum type type; |
185 | /* Configuration agent device ID */ |
186 | unsigned int decs_did; |
187 | /* Default bus number configuration register offset */ |
188 | int busno_cfg_offset; |
189 | /* DDR memory controllers per socket */ |
190 | int ddr_imc_num; |
191 | /* DDR channels per DDR memory controller */ |
192 | int ddr_chan_num; |
193 | /* DDR DIMMs per DDR memory channel */ |
194 | int ddr_dimm_num; |
195 | /* Per DDR channel memory-mapped I/O size */ |
196 | int ddr_chan_mmio_sz; |
197 | /* HBM memory controllers per socket */ |
198 | int hbm_imc_num; |
199 | /* HBM channels per HBM memory controller */ |
200 | int hbm_chan_num; |
201 | /* HBM DIMMs per HBM memory channel */ |
202 | int hbm_dimm_num; |
203 | /* Per HBM channel memory-mapped I/O size */ |
204 | int hbm_chan_mmio_sz; |
205 | bool support_ddr5; |
206 | /* SAD device BDF */ |
207 | struct pci_bdf sad_all_bdf; |
208 | /* PCU device BDF */ |
209 | struct pci_bdf pcu_cr3_bdf; |
210 | /* UTIL device BDF */ |
211 | struct pci_bdf util_all_bdf; |
212 | /* URACU device BDF */ |
213 | struct pci_bdf uracu_bdf; |
214 | /* DDR mdev device BDF */ |
215 | struct pci_bdf ddr_mdev_bdf; |
216 | /* HBM mdev device BDF */ |
217 | struct pci_bdf hbm_mdev_bdf; |
218 | int sad_all_offset; |
219 | /* Offsets of retry_rd_err_log registers */ |
220 | u32 *offsets_scrub; |
221 | u32 *offsets_scrub_hbm0; |
222 | u32 *offsets_scrub_hbm1; |
223 | u32 *offsets_demand; |
224 | u32 *offsets_demand2; |
225 | u32 *offsets_demand_hbm0; |
226 | u32 *offsets_demand_hbm1; |
227 | }; |
228 | |
229 | typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, |
230 | struct res_config *cfg); |
231 | typedef bool (*skx_decode_f)(struct decoded_addr *res); |
232 | typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err); |
233 | |
234 | int __init skx_adxl_get(void); |
235 | void __exit skx_adxl_put(void); |
236 | void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); |
237 | void skx_set_mem_cfg(bool mem_cfg_2lm); |
238 | |
239 | int skx_get_src_id(struct skx_dev *d, int off, u8 *id); |
240 | int skx_get_node_id(struct skx_dev *d, u8 *id); |
241 | |
242 | int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list); |
243 | |
244 | int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm); |
245 | |
246 | int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, |
247 | struct skx_imc *imc, int chan, int dimmno, |
248 | struct res_config *cfg); |
249 | |
250 | int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, |
251 | int chan, int dimmno, const char *mod_str); |
252 | |
253 | int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, |
254 | const char *ctl_name, const char *mod_str, |
255 | get_dimm_config_f get_dimm_config, |
256 | struct res_config *cfg); |
257 | |
258 | int skx_mce_check_error(struct notifier_block *nb, unsigned long val, |
259 | void *data); |
260 | |
261 | void skx_remove(void); |
262 | |
263 | #endif /* _SKX_COMM_EDAC_H */ |
264 | |