1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/gpio/driver.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24
25#define IOH_EDGE_FALLING 0
26#define IOH_EDGE_RISING BIT(0)
27#define IOH_LEVEL_L BIT(1)
28#define IOH_LEVEL_H (BIT(0) | BIT(1))
29#define IOH_EDGE_BOTH BIT(2)
30#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define IOH_IRQ_BASE 0
33
34struct ioh_reg_comn {
35 u32 ien;
36 u32 istatus;
37 u32 idisp;
38 u32 iclr;
39 u32 imask;
40 u32 imaskclr;
41 u32 po;
42 u32 pi;
43 u32 pm;
44 u32 im_0;
45 u32 im_1;
46 u32 reserved;
47};
48
49struct ioh_regs {
50 struct ioh_reg_comn regs[8];
51 u32 reserve1[16];
52 u32 ioh_sel_reg[4];
53 u32 reserve2[11];
54 u32 srst;
55};
56
57/**
58 * struct ioh_gpio_reg_data - The register store data.
59 * @ien_reg To store contents of interrupt enable register.
60 * @imask_reg: To store contents of interrupt mask regist
61 * @po_reg: To store contents of PO register.
62 * @pm_reg: To store contents of PM register.
63 * @im0_reg: To store contents of interrupt mode regist0
64 * @im1_reg: To store contents of interrupt mode regist1
65 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
66 */
67struct ioh_gpio_reg_data {
68 u32 ien_reg;
69 u32 imask_reg;
70 u32 po_reg;
71 u32 pm_reg;
72 u32 im0_reg;
73 u32 im1_reg;
74 u32 use_sel_reg;
75};
76
77/**
78 * struct ioh_gpio - GPIO private data structure.
79 * @base: PCI base address of Memory mapped I/O register.
80 * @reg: Memory mapped IOH GPIO register list.
81 * @dev: Pointer to device structure.
82 * @gpio: Data for GPIO infrastructure.
83 * @ioh_gpio_reg: Memory mapped Register data is saved here
84 * when suspend.
85 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
86 * @ch: Indicate GPIO channel
87 * @irq_base: Save base of IRQ number for interrupt
88 * @spinlock: Used for register access protection
89 */
90struct ioh_gpio {
91 void __iomem *base;
92 struct ioh_regs __iomem *reg;
93 struct device *dev;
94 struct gpio_chip gpio;
95 struct ioh_gpio_reg_data ioh_gpio_reg;
96 u32 gpio_use_sel;
97 int ch;
98 int irq_base;
99 spinlock_t spinlock;
100};
101
102static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
103
104static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
105{
106 u32 reg_val;
107 struct ioh_gpio *chip = gpiochip_get_data(gpio);
108 unsigned long flags;
109
110 spin_lock_irqsave(&chip->spinlock, flags);
111 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
112 if (val)
113 reg_val |= (1 << nr);
114 else
115 reg_val &= ~(1 << nr);
116
117 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
118 spin_unlock_irqrestore(&chip->spinlock, flags);
119}
120
121static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
122{
123 struct ioh_gpio *chip = gpiochip_get_data(gpio);
124
125 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
126}
127
128static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
129 int val)
130{
131 struct ioh_gpio *chip = gpiochip_get_data(gpio);
132 u32 pm;
133 u32 reg_val;
134 unsigned long flags;
135
136 spin_lock_irqsave(&chip->spinlock, flags);
137 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
138 ((1 << num_ports[chip->ch]) - 1);
139 pm |= (1 << nr);
140 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
141
142 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
143 if (val)
144 reg_val |= (1 << nr);
145 else
146 reg_val &= ~(1 << nr);
147 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
148
149 spin_unlock_irqrestore(&chip->spinlock, flags);
150
151 return 0;
152}
153
154static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
155{
156 struct ioh_gpio *chip = gpiochip_get_data(gpio);
157 u32 pm;
158 unsigned long flags;
159
160 spin_lock_irqsave(&chip->spinlock, flags);
161 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
162 ((1 << num_ports[chip->ch]) - 1);
163 pm &= ~(1 << nr);
164 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
165 spin_unlock_irqrestore(&chip->spinlock, flags);
166
167 return 0;
168}
169
170#ifdef CONFIG_PM
171/*
172 * Save register configuration and disable interrupts.
173 */
174static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
175{
176 int i;
177
178 for (i = 0; i < 8; i ++, chip++) {
179 chip->ioh_gpio_reg.po_reg =
180 ioread32(&chip->reg->regs[chip->ch].po);
181 chip->ioh_gpio_reg.pm_reg =
182 ioread32(&chip->reg->regs[chip->ch].pm);
183 chip->ioh_gpio_reg.ien_reg =
184 ioread32(&chip->reg->regs[chip->ch].ien);
185 chip->ioh_gpio_reg.imask_reg =
186 ioread32(&chip->reg->regs[chip->ch].imask);
187 chip->ioh_gpio_reg.im0_reg =
188 ioread32(&chip->reg->regs[chip->ch].im_0);
189 chip->ioh_gpio_reg.im1_reg =
190 ioread32(&chip->reg->regs[chip->ch].im_1);
191 if (i < 4)
192 chip->ioh_gpio_reg.use_sel_reg =
193 ioread32(&chip->reg->ioh_sel_reg[i]);
194 }
195}
196
197/*
198 * This function restores the register configuration of the GPIO device.
199 */
200static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
201{
202 int i;
203
204 for (i = 0; i < 8; i ++, chip++) {
205 iowrite32(chip->ioh_gpio_reg.po_reg,
206 &chip->reg->regs[chip->ch].po);
207 iowrite32(chip->ioh_gpio_reg.pm_reg,
208 &chip->reg->regs[chip->ch].pm);
209 iowrite32(chip->ioh_gpio_reg.ien_reg,
210 &chip->reg->regs[chip->ch].ien);
211 iowrite32(chip->ioh_gpio_reg.imask_reg,
212 &chip->reg->regs[chip->ch].imask);
213 iowrite32(chip->ioh_gpio_reg.im0_reg,
214 &chip->reg->regs[chip->ch].im_0);
215 iowrite32(chip->ioh_gpio_reg.im1_reg,
216 &chip->reg->regs[chip->ch].im_1);
217 if (i < 4)
218 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
219 &chip->reg->ioh_sel_reg[i]);
220 }
221}
222#endif
223
224static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
225{
226 struct ioh_gpio *chip = gpiochip_get_data(gpio);
227 return chip->irq_base + offset;
228}
229
230static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
231{
232 struct gpio_chip *gpio = &chip->gpio;
233
234 gpio->label = dev_name(chip->dev);
235 gpio->owner = THIS_MODULE;
236 gpio->direction_input = ioh_gpio_direction_input;
237 gpio->get = ioh_gpio_get;
238 gpio->direction_output = ioh_gpio_direction_output;
239 gpio->set = ioh_gpio_set;
240 gpio->dbg_show = NULL;
241 gpio->base = -1;
242 gpio->ngpio = num_port;
243 gpio->can_sleep = false;
244 gpio->to_irq = ioh_gpio_to_irq;
245}
246
247static int ioh_irq_type(struct irq_data *d, unsigned int type)
248{
249 u32 im;
250 void __iomem *im_reg;
251 u32 ien;
252 u32 im_pos;
253 int ch;
254 unsigned long flags;
255 u32 val;
256 int irq = d->irq;
257 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
258 struct ioh_gpio *chip = gc->private;
259
260 ch = irq - chip->irq_base;
261 if (irq <= chip->irq_base + 7) {
262 im_reg = &chip->reg->regs[chip->ch].im_0;
263 im_pos = ch;
264 } else {
265 im_reg = &chip->reg->regs[chip->ch].im_1;
266 im_pos = ch - 8;
267 }
268 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
269 __func__, irq, type, ch, im_pos, type);
270
271 spin_lock_irqsave(&chip->spinlock, flags);
272
273 switch (type) {
274 case IRQ_TYPE_EDGE_RISING:
275 val = IOH_EDGE_RISING;
276 break;
277 case IRQ_TYPE_EDGE_FALLING:
278 val = IOH_EDGE_FALLING;
279 break;
280 case IRQ_TYPE_EDGE_BOTH:
281 val = IOH_EDGE_BOTH;
282 break;
283 case IRQ_TYPE_LEVEL_HIGH:
284 val = IOH_LEVEL_H;
285 break;
286 case IRQ_TYPE_LEVEL_LOW:
287 val = IOH_LEVEL_L;
288 break;
289 case IRQ_TYPE_PROBE:
290 goto end;
291 default:
292 dev_warn(chip->dev, "%s: unknown type(%dd)",
293 __func__, type);
294 goto end;
295 }
296
297 /* Set interrupt mode */
298 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
299 iowrite32(im | (val << (im_pos * 4)), im_reg);
300
301 /* iclr */
302 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
303
304 /* IMASKCLR */
305 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
306
307 /* Enable interrupt */
308 ien = ioread32(&chip->reg->regs[chip->ch].ien);
309 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
310end:
311 spin_unlock_irqrestore(&chip->spinlock, flags);
312
313 return 0;
314}
315
316static void ioh_irq_unmask(struct irq_data *d)
317{
318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
319 struct ioh_gpio *chip = gc->private;
320
321 iowrite32(1 << (d->irq - chip->irq_base),
322 &chip->reg->regs[chip->ch].imaskclr);
323}
324
325static void ioh_irq_mask(struct irq_data *d)
326{
327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct ioh_gpio *chip = gc->private;
329
330 iowrite32(1 << (d->irq - chip->irq_base),
331 &chip->reg->regs[chip->ch].imask);
332}
333
334static void ioh_irq_disable(struct irq_data *d)
335{
336 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
337 struct ioh_gpio *chip = gc->private;
338 unsigned long flags;
339 u32 ien;
340
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
343 ien &= ~(1 << (d->irq - chip->irq_base));
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
346}
347
348static void ioh_irq_enable(struct irq_data *d)
349{
350 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
351 struct ioh_gpio *chip = gc->private;
352 unsigned long flags;
353 u32 ien;
354
355 spin_lock_irqsave(&chip->spinlock, flags);
356 ien = ioread32(&chip->reg->regs[chip->ch].ien);
357 ien |= 1 << (d->irq - chip->irq_base);
358 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
359 spin_unlock_irqrestore(&chip->spinlock, flags);
360}
361
362static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
363{
364 struct ioh_gpio *chip = dev_id;
365 u32 reg_val;
366 int i, j;
367 int ret = IRQ_NONE;
368
369 for (i = 0; i < 8; i++, chip++) {
370 reg_val = ioread32(&chip->reg->regs[i].istatus);
371 for (j = 0; j < num_ports[i]; j++) {
372 if (reg_val & BIT(j)) {
373 dev_dbg(chip->dev,
374 "%s:[%d]:irq=%d status=0x%x\n",
375 __func__, j, irq, reg_val);
376 iowrite32(BIT(j),
377 &chip->reg->regs[chip->ch].iclr);
378 generic_handle_irq(chip->irq_base + j);
379 ret = IRQ_HANDLED;
380 }
381 }
382 }
383 return ret;
384}
385
386static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
387 unsigned int irq_start,
388 unsigned int num)
389{
390 struct irq_chip_generic *gc;
391 struct irq_chip_type *ct;
392 int rv;
393
394 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
395 chip->base, handle_simple_irq);
396 if (!gc)
397 return -ENOMEM;
398
399 gc->private = chip;
400 ct = gc->chip_types;
401
402 ct->chip.irq_mask = ioh_irq_mask;
403 ct->chip.irq_unmask = ioh_irq_unmask;
404 ct->chip.irq_set_type = ioh_irq_type;
405 ct->chip.irq_disable = ioh_irq_disable;
406 ct->chip.irq_enable = ioh_irq_enable;
407
408 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
409 IRQ_GC_INIT_MASK_CACHE,
410 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
411
412 return rv;
413}
414
415static int ioh_gpio_probe(struct pci_dev *pdev,
416 const struct pci_device_id *id)
417{
418 int ret;
419 int i, j;
420 struct ioh_gpio *chip;
421 void __iomem *base;
422 void *chip_save;
423 int irq_base;
424
425 ret = pci_enable_device(pdev);
426 if (ret) {
427 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
428 goto err_pci_enable;
429 }
430
431 ret = pci_request_regions(pdev, KBUILD_MODNAME);
432 if (ret) {
433 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
434 goto err_request_regions;
435 }
436
437 base = pci_iomap(pdev, 1, 0);
438 if (!base) {
439 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
440 ret = -ENOMEM;
441 goto err_iomap;
442 }
443
444 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
445 if (chip_save == NULL) {
446 ret = -ENOMEM;
447 goto err_kzalloc;
448 }
449
450 chip = chip_save;
451 for (i = 0; i < 8; i++, chip++) {
452 chip->dev = &pdev->dev;
453 chip->base = base;
454 chip->reg = chip->base;
455 chip->ch = i;
456 spin_lock_init(&chip->spinlock);
457 ioh_gpio_setup(chip, num_ports[i]);
458 ret = gpiochip_add_data(&chip->gpio, chip);
459 if (ret) {
460 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
461 goto err_gpiochip_add;
462 }
463 }
464
465 chip = chip_save;
466 for (j = 0; j < 8; j++, chip++) {
467 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
468 num_ports[j], NUMA_NO_NODE);
469 if (irq_base < 0) {
470 dev_warn(&pdev->dev,
471 "ml_ioh_gpio: Failed to get IRQ base num\n");
472 ret = irq_base;
473 goto err_gpiochip_add;
474 }
475 chip->irq_base = irq_base;
476
477 ret = ioh_gpio_alloc_generic_chip(chip,
478 irq_base, num_ports[j]);
479 if (ret)
480 goto err_gpiochip_add;
481 }
482
483 chip = chip_save;
484 ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
485 IRQF_SHARED, KBUILD_MODNAME, chip);
486 if (ret != 0) {
487 dev_err(&pdev->dev,
488 "%s request_irq failed\n", __func__);
489 goto err_gpiochip_add;
490 }
491
492 pci_set_drvdata(pdev, chip);
493
494 return 0;
495
496err_gpiochip_add:
497 chip = chip_save;
498 while (--i >= 0) {
499 gpiochip_remove(&chip->gpio);
500 chip++;
501 }
502 kfree(chip_save);
503
504err_kzalloc:
505 pci_iounmap(pdev, base);
506
507err_iomap:
508 pci_release_regions(pdev);
509
510err_request_regions:
511 pci_disable_device(pdev);
512
513err_pci_enable:
514
515 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
516 return ret;
517}
518
519static void ioh_gpio_remove(struct pci_dev *pdev)
520{
521 int i;
522 struct ioh_gpio *chip = pci_get_drvdata(pdev);
523 void *chip_save;
524
525 chip_save = chip;
526
527 for (i = 0; i < 8; i++, chip++)
528 gpiochip_remove(&chip->gpio);
529
530 chip = chip_save;
531 pci_iounmap(pdev, chip->base);
532 pci_release_regions(pdev);
533 pci_disable_device(pdev);
534 kfree(chip);
535}
536
537#ifdef CONFIG_PM
538static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
539{
540 s32 ret;
541 struct ioh_gpio *chip = pci_get_drvdata(pdev);
542 unsigned long flags;
543
544 spin_lock_irqsave(&chip->spinlock, flags);
545 ioh_gpio_save_reg_conf(chip);
546 spin_unlock_irqrestore(&chip->spinlock, flags);
547
548 ret = pci_save_state(pdev);
549 if (ret) {
550 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
551 return ret;
552 }
553 pci_disable_device(pdev);
554 pci_set_power_state(pdev, PCI_D0);
555 ret = pci_enable_wake(pdev, PCI_D0, 1);
556 if (ret)
557 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
558
559 return 0;
560}
561
562static int ioh_gpio_resume(struct pci_dev *pdev)
563{
564 s32 ret;
565 struct ioh_gpio *chip = pci_get_drvdata(pdev);
566 unsigned long flags;
567
568 ret = pci_enable_wake(pdev, PCI_D0, 0);
569
570 pci_set_power_state(pdev, PCI_D0);
571 ret = pci_enable_device(pdev);
572 if (ret) {
573 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
574 return ret;
575 }
576 pci_restore_state(pdev);
577
578 spin_lock_irqsave(&chip->spinlock, flags);
579 iowrite32(0x01, &chip->reg->srst);
580 iowrite32(0x00, &chip->reg->srst);
581 ioh_gpio_restore_reg_conf(chip);
582 spin_unlock_irqrestore(&chip->spinlock, flags);
583
584 return 0;
585}
586#else
587#define ioh_gpio_suspend NULL
588#define ioh_gpio_resume NULL
589#endif
590
591static const struct pci_device_id ioh_gpio_pcidev_id[] = {
592 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
593 { 0, }
594};
595MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
596
597static struct pci_driver ioh_gpio_driver = {
598 .name = "ml_ioh_gpio",
599 .id_table = ioh_gpio_pcidev_id,
600 .probe = ioh_gpio_probe,
601 .remove = ioh_gpio_remove,
602 .suspend = ioh_gpio_suspend,
603 .resume = ioh_gpio_resume
604};
605
606module_pci_driver(ioh_gpio_driver);
607
608MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
609MODULE_LICENSE("GPL");
610