1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "kfd_events.h"
24#include "kfd_debug.h"
25#include "soc15_int.h"
26#include "kfd_device_queue_manager.h"
27
28/*
29 * GFX10 SQ Interrupts
30 *
31 * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit
32 * packet to the Interrupt Handler:
33 * Auto - Generated by the SQG (various cmd overflows, timestamps etc)
34 * Wave - Generated by S_SENDMSG through a shader program
35 * Error - HW generated errors (Illegal instructions, Memviols, EDC etc)
36 *
37 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
38 * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such:
39 *
40 * - context_id1[7:6]
41 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
42 *
43 * - context_id0[24]
44 * PRIV bit indicates that Wave S_SEND or error occurred within trap
45 *
46 * - context_id0[22:0]
47 * 23-bit data with the following layout per encoding type:
48 * Auto - only context_id0[8:0] is used, which reports various interrupts
49 * generated by SQG. The rest is 0.
50 * Wave - user data sent from m0 via S_SENDMSG
51 * Error - Error type (context_id0[22:19]), Error Details (rest of bits)
52 *
53 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave
54 * S_SENDMSG and Errors. These are 0 for Auto.
55 */
56
57enum SQ_INTERRUPT_WORD_ENCODING {
58 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
59 SQ_INTERRUPT_WORD_ENCODING_INST,
60 SQ_INTERRUPT_WORD_ENCODING_ERROR,
61};
62
63enum SQ_INTERRUPT_ERROR_TYPE {
64 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
65 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST,
66 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL,
67 SQ_INTERRUPT_ERROR_TYPE_EDC_FED,
68};
69
70/* SQ_INTERRUPT_WORD_AUTO_CTXID */
71#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT 0
72#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT__SHIFT 1
73#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL__SHIFT 2
74#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL__SHIFT 3
75#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR__SHIFT 7
76#define SQ_INTERRUPT_WORD_AUTO_CTXID1__SE_ID__SHIFT 4
77#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING__SHIFT 6
78
79#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK 0x00000001
80#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK 0x00000002
81#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL_MASK 0x00000004
82#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL_MASK 0x00000008
83#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK 0x00000080
84#define SQ_INTERRUPT_WORD_AUTO_CTXID1__SE_ID_MASK 0x030
85#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK 0x0c0
86
87/* SQ_INTERRUPT_WORD_WAVE_CTXID */
88#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT 0
89#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID__SHIFT 23
90#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV__SHIFT 24
91#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID__SHIFT 25
92#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SIMD_ID__SHIFT 30
93#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID__SHIFT 0
94#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SE_ID__SHIFT 4
95#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING__SHIFT 6
96
97#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK 0x000007fffff
98#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID_MASK 0x0000800000
99#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK 0x00001000000
100#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK 0x0003e000000
101#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SIMD_ID_MASK 0x000c0000000
102#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK 0x00f
103#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SE_ID_MASK 0x030
104#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK 0x0c0
105
106#define KFD_CTXID0__ERR_TYPE_MASK 0x780000
107#define KFD_CTXID0__ERR_TYPE__SHIFT 19
108
109/* GFX10 SQ interrupt ENC type bit (context_id1[7:6]) for wave s_sendmsg */
110#define KFD_CONTEXT_ID1_ENC_TYPE_WAVE_MASK 0x40
111/* GFX10 SQ interrupt PRIV bit (context_id0[24]) for s_sendmsg inside trap */
112#define KFD_CONTEXT_ID0_PRIV_MASK 0x1000000
113/*
114 * The debugger will send user data(m0) with PRIV=1 to indicate it requires
115 * notification from the KFD with the following queue id (DOORBELL_ID) and
116 * trap code (TRAP_CODE).
117 */
118#define KFD_CONTEXT_ID0_DEBUG_DOORBELL_MASK 0x0003ff
119#define KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_SHIFT 10
120#define KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_MASK 0x07fc00
121#define KFD_DEBUG_DOORBELL_ID(ctxid0) ((ctxid0) & \
122 KFD_CONTEXT_ID0_DEBUG_DOORBELL_MASK)
123#define KFD_DEBUG_TRAP_CODE(ctxid0) (((ctxid0) & \
124 KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_MASK) \
125 >> KFD_CONTEXT_ID0_DEBUG_TRAP_CODE_SHIFT)
126#define KFD_DEBUG_CP_BAD_OP_ECODE_MASK 0x3fffc00
127#define KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT 10
128#define KFD_DEBUG_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \
129 KFD_DEBUG_CP_BAD_OP_ECODE_MASK) \
130 >> KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT)
131
132static void event_interrupt_poison_consumption(struct kfd_node *dev,
133 uint16_t pasid, uint16_t client_id)
134{
135 enum amdgpu_ras_block block = 0;
136 int old_poison, ret = -EINVAL;
137 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
138
139 if (!p)
140 return;
141
142 /* all queues of a process will be unmapped in one time */
143 old_poison = atomic_cmpxchg(v: &p->poison, old: 0, new: 1);
144 kfd_unref_process(p);
145 if (old_poison)
146 return;
147
148 switch (client_id) {
149 case SOC15_IH_CLIENTID_SE0SH:
150 case SOC15_IH_CLIENTID_SE1SH:
151 case SOC15_IH_CLIENTID_SE2SH:
152 case SOC15_IH_CLIENTID_SE3SH:
153 case SOC15_IH_CLIENTID_UTCL2:
154 ret = kfd_dqm_evict_pasid(dqm: dev->dqm, pasid);
155 block = AMDGPU_RAS_BLOCK__GFX;
156 break;
157 case SOC15_IH_CLIENTID_SDMA0:
158 case SOC15_IH_CLIENTID_SDMA1:
159 case SOC15_IH_CLIENTID_SDMA2:
160 case SOC15_IH_CLIENTID_SDMA3:
161 case SOC15_IH_CLIENTID_SDMA4:
162 block = AMDGPU_RAS_BLOCK__SDMA;
163 break;
164 default:
165 break;
166 }
167
168 kfd_signal_poison_consumed_event(dev, pasid);
169
170 /* resetting queue passes, do page retirement without gpu reset
171 * resetting queue fails, fallback to gpu reset solution
172 */
173 if (!ret) {
174 dev_warn(dev->adev->dev,
175 "RAS poison consumption, unmap queue flow succeeded: client id %d\n",
176 client_id);
177 amdgpu_amdkfd_ras_poison_consumption_handler(adev: dev->adev, block, reset: false);
178 } else {
179 dev_warn(dev->adev->dev,
180 "RAS poison consumption, fall back to gpu reset flow: client id %d\n",
181 client_id);
182 amdgpu_amdkfd_ras_poison_consumption_handler(adev: dev->adev, block, reset: true);
183 }
184}
185
186static bool event_interrupt_isr_v10(struct kfd_node *dev,
187 const uint32_t *ih_ring_entry,
188 uint32_t *patched_ihre,
189 bool *patched_flag)
190{
191 uint16_t source_id, client_id, pasid, vmid;
192 const uint32_t *data = ih_ring_entry;
193
194 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
195 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
196
197 /* Only handle interrupts from KFD VMIDs */
198 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
199 if (!KFD_IRQ_IS_FENCE(client_id, source_id) &&
200 (vmid < dev->vm_info.first_vmid_kfd ||
201 vmid > dev->vm_info.last_vmid_kfd))
202 return false;
203
204 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
205
206 /* Only handle clients we care about */
207 if (client_id != SOC15_IH_CLIENTID_GRBM_CP &&
208 client_id != SOC15_IH_CLIENTID_SDMA0 &&
209 client_id != SOC15_IH_CLIENTID_SDMA1 &&
210 client_id != SOC15_IH_CLIENTID_SDMA2 &&
211 client_id != SOC15_IH_CLIENTID_SDMA3 &&
212 client_id != SOC15_IH_CLIENTID_SDMA4 &&
213 client_id != SOC15_IH_CLIENTID_SDMA5 &&
214 client_id != SOC15_IH_CLIENTID_SDMA6 &&
215 client_id != SOC15_IH_CLIENTID_SDMA7 &&
216 client_id != SOC15_IH_CLIENTID_VMC &&
217 client_id != SOC15_IH_CLIENTID_VMC1 &&
218 client_id != SOC15_IH_CLIENTID_UTCL2 &&
219 client_id != SOC15_IH_CLIENTID_SE0SH &&
220 client_id != SOC15_IH_CLIENTID_SE1SH &&
221 client_id != SOC15_IH_CLIENTID_SE2SH &&
222 client_id != SOC15_IH_CLIENTID_SE3SH)
223 return false;
224
225 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
226 client_id, source_id, vmid, pasid);
227 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",
228 data[0], data[1], data[2], data[3],
229 data[4], data[5], data[6], data[7]);
230
231 /* If there is no valid PASID, it's likely a bug */
232 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))
233 return 0;
234
235 /* Interrupt types we care about: various signals and faults.
236 * They will be forwarded to a work queue (see below).
237 */
238 return source_id == SOC15_INTSRC_CP_END_OF_PIPE ||
239 source_id == SOC15_INTSRC_SDMA_TRAP ||
240 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||
241 source_id == SOC15_INTSRC_CP_BAD_OPCODE ||
242 client_id == SOC15_IH_CLIENTID_VMC ||
243 client_id == SOC15_IH_CLIENTID_VMC1 ||
244 client_id == SOC15_IH_CLIENTID_UTCL2 ||
245 KFD_IRQ_IS_FENCE(client_id, source_id);
246}
247
248static void event_interrupt_wq_v10(struct kfd_node *dev,
249 const uint32_t *ih_ring_entry)
250{
251 uint16_t source_id, client_id, pasid, vmid;
252 uint32_t context_id0, context_id1;
253 uint32_t encoding, sq_intr_err_type;
254
255 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
256 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
257 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
258 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
259 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
260 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
261
262 if (client_id == SOC15_IH_CLIENTID_GRBM_CP ||
263 client_id == SOC15_IH_CLIENTID_SE0SH ||
264 client_id == SOC15_IH_CLIENTID_SE1SH ||
265 client_id == SOC15_IH_CLIENTID_SE2SH ||
266 client_id == SOC15_IH_CLIENTID_SE3SH) {
267 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
268 kfd_signal_event_interrupt(pasid, partial_id: context_id0, valid_id_bits: 32);
269 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
270 encoding = REG_GET_FIELD(context_id1,
271 SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);
272 switch (encoding) {
273 case SQ_INTERRUPT_WORD_ENCODING_AUTO:
274 pr_debug_ratelimited(
275 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf0_full %d, ttrac_buf1_full %d, ttrace_utc_err %d\n",
276 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_AUTO_CTXID1,
277 SE_ID),
278 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
279 THREAD_TRACE),
280 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
281 WLT),
282 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
283 THREAD_TRACE_BUF0_FULL),
284 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
285 THREAD_TRACE_BUF1_FULL),
286 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,
287 THREAD_TRACE_UTC_ERROR));
288 break;
289 case SQ_INTERRUPT_WORD_ENCODING_INST:
290 pr_debug_ratelimited("sq_intr: inst, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",
291 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
292 SE_ID),
293 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
294 DATA),
295 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
296 SA_ID),
297 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
298 PRIV),
299 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
300 WAVE_ID),
301 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
302 SIMD_ID),
303 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
304 WGP_ID));
305 if (context_id0 & SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK) {
306 if (kfd_set_dbg_ev_from_interrupt(dev, pasid,
307 KFD_DEBUG_DOORBELL_ID(context_id0),
308 KFD_DEBUG_TRAP_CODE(context_id0),
309 NULL, exception_data_size: 0))
310 return;
311 }
312 break;
313 case SQ_INTERRUPT_WORD_ENCODING_ERROR:
314 sq_intr_err_type = REG_GET_FIELD(context_id0, KFD_CTXID0,
315 ERR_TYPE);
316 pr_warn_ratelimited("sq_intr: error, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d, err_type %d\n",
317 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
318 SE_ID),
319 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
320 DATA),
321 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
322 SA_ID),
323 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
324 PRIV),
325 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
326 WAVE_ID),
327 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,
328 SIMD_ID),
329 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,
330 WGP_ID),
331 sq_intr_err_type);
332 if (sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
333 sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
334 event_interrupt_poison_consumption(dev, pasid, client_id: source_id);
335 return;
336 }
337 break;
338 default:
339 break;
340 }
341 kfd_signal_event_interrupt(pasid, partial_id: context_id0 & 0x7fffff, valid_id_bits: 23);
342 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&
343 KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {
344 kfd_set_dbg_ev_from_interrupt(dev, pasid,
345 KFD_DEBUG_DOORBELL_ID(context_id0),
346 KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),
347 NULL,
348 exception_data_size: 0);
349 }
350 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 ||
351 client_id == SOC15_IH_CLIENTID_SDMA1 ||
352 client_id == SOC15_IH_CLIENTID_SDMA2 ||
353 client_id == SOC15_IH_CLIENTID_SDMA3 ||
354 (client_id == SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid &&
355 KFD_GC_VERSION(dev) == IP_VERSION(10, 3, 0)) ||
356 client_id == SOC15_IH_CLIENTID_SDMA4 ||
357 client_id == SOC15_IH_CLIENTID_SDMA5 ||
358 client_id == SOC15_IH_CLIENTID_SDMA6 ||
359 client_id == SOC15_IH_CLIENTID_SDMA7) {
360 if (source_id == SOC15_INTSRC_SDMA_TRAP) {
361 kfd_signal_event_interrupt(pasid, partial_id: context_id0 & 0xfffffff, valid_id_bits: 28);
362 } else if (source_id == SOC15_INTSRC_SDMA_ECC) {
363 event_interrupt_poison_consumption(dev, pasid, client_id: source_id);
364 return;
365 }
366 } else if (client_id == SOC15_IH_CLIENTID_VMC ||
367 client_id == SOC15_IH_CLIENTID_VMC1 ||
368 client_id == SOC15_IH_CLIENTID_UTCL2) {
369 struct kfd_vm_fault_info info = {0};
370 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);
371 struct kfd_hsa_memory_exception_data exception_data;
372
373 if (client_id == SOC15_IH_CLIENTID_UTCL2 &&
374 amdgpu_amdkfd_ras_query_utcl2_poison_status(adev: dev->adev)) {
375 event_interrupt_poison_consumption(dev, pasid, client_id);
376 return;
377 }
378
379 info.vmid = vmid;
380 info.mc_id = client_id;
381 info.page_addr = ih_ring_entry[4] |
382 (uint64_t)(ih_ring_entry[5] & 0xf) << 32;
383 info.prot_valid = ring_id & 0x08;
384 info.prot_read = ring_id & 0x10;
385 info.prot_write = ring_id & 0x20;
386
387 memset(&exception_data, 0, sizeof(exception_data));
388 exception_data.gpu_id = dev->id;
389 exception_data.va = (info.page_addr) << PAGE_SHIFT;
390 exception_data.failure.NotPresent = info.prot_valid ? 1 : 0;
391 exception_data.failure.NoExecute = info.prot_exec ? 1 : 0;
392 exception_data.failure.ReadOnly = info.prot_write ? 1 : 0;
393 exception_data.failure.imprecise = 0;
394
395 kfd_set_dbg_ev_from_interrupt(dev,
396 pasid,
397 doorbell_id: -1,
398 KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION),
399 exception_data: &exception_data,
400 exception_data_size: sizeof(exception_data));
401 } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) {
402 kfd_process_close_interrupt_drain(pasid);
403 }
404}
405
406const struct kfd_event_interrupt_class event_interrupt_class_v10 = {
407 .interrupt_isr = event_interrupt_isr_v10,
408 .interrupt_wq = event_interrupt_wq_v10,
409};
410

source code of linux/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c