1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
2 | /* |
3 | * Copyright 2018-2022 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | */ |
24 | |
25 | #include <linux/printk.h> |
26 | #include <linux/slab.h> |
27 | #include <linux/uaccess.h> |
28 | #include "kfd_priv.h" |
29 | #include "kfd_mqd_manager.h" |
30 | #include "v10_structs.h" |
31 | #include "gc/gc_10_1_0_offset.h" |
32 | #include "gc/gc_10_1_0_sh_mask.h" |
33 | #include "amdgpu_amdkfd.h" |
34 | |
35 | static inline struct v10_compute_mqd *get_mqd(void *mqd) |
36 | { |
37 | return (struct v10_compute_mqd *)mqd; |
38 | } |
39 | |
40 | static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) |
41 | { |
42 | return (struct v10_sdma_mqd *)mqd; |
43 | } |
44 | |
45 | static void update_cu_mask(struct mqd_manager *mm, void *mqd, |
46 | struct mqd_update_info *minfo) |
47 | { |
48 | struct v10_compute_mqd *m; |
49 | uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ |
50 | |
51 | if (!minfo || !minfo->cu_mask.ptr) |
52 | return; |
53 | |
54 | mqd_symmetrically_map_cu_mask(mm, |
55 | cu_mask: minfo->cu_mask.ptr, cu_mask_count: minfo->cu_mask.count, se_mask, inst: 0); |
56 | |
57 | m = get_mqd(mqd); |
58 | m->compute_static_thread_mgmt_se0 = se_mask[0]; |
59 | m->compute_static_thread_mgmt_se1 = se_mask[1]; |
60 | m->compute_static_thread_mgmt_se2 = se_mask[2]; |
61 | m->compute_static_thread_mgmt_se3 = se_mask[3]; |
62 | |
63 | pr_debug("update cu mask to %#x %#x %#x %#x\n" , |
64 | m->compute_static_thread_mgmt_se0, |
65 | m->compute_static_thread_mgmt_se1, |
66 | m->compute_static_thread_mgmt_se2, |
67 | m->compute_static_thread_mgmt_se3); |
68 | } |
69 | |
70 | static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) |
71 | { |
72 | m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; |
73 | m->cp_hqd_queue_priority = q->priority; |
74 | } |
75 | |
76 | static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, |
77 | struct queue_properties *q) |
78 | { |
79 | struct kfd_mem_obj *mqd_mem_obj; |
80 | |
81 | if (kfd_gtt_sa_allocate(node: kfd, size: sizeof(struct v10_compute_mqd), |
82 | mem_obj: &mqd_mem_obj)) |
83 | return NULL; |
84 | |
85 | return mqd_mem_obj; |
86 | } |
87 | |
88 | static void init_mqd(struct mqd_manager *mm, void **mqd, |
89 | struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, |
90 | struct queue_properties *q) |
91 | { |
92 | uint64_t addr; |
93 | struct v10_compute_mqd *m; |
94 | |
95 | m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; |
96 | addr = mqd_mem_obj->gpu_addr; |
97 | |
98 | memset(m, 0, sizeof(struct v10_compute_mqd)); |
99 | |
100 | m->header = 0xC0310800; |
101 | m->compute_pipelinestat_enable = 1; |
102 | m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; |
103 | m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; |
104 | m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; |
105 | m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; |
106 | |
107 | m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | |
108 | 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; |
109 | |
110 | m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; |
111 | |
112 | m->cp_mqd_base_addr_lo = lower_32_bits(addr); |
113 | m->cp_mqd_base_addr_hi = upper_32_bits(addr); |
114 | |
115 | m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | |
116 | 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | |
117 | 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; |
118 | |
119 | /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the |
120 | * DISPATCH_PTR. This is required for the kfd debugger |
121 | */ |
122 | m->cp_hqd_hq_scheduler0 = 1 << 14; |
123 | |
124 | if (q->format == KFD_QUEUE_FORMAT_AQL) { |
125 | m->cp_hqd_aql_control = |
126 | 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; |
127 | } |
128 | |
129 | if (mm->dev->kfd->cwsr_enabled) { |
130 | m->cp_hqd_persistent_state |= |
131 | (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); |
132 | m->cp_hqd_ctx_save_base_addr_lo = |
133 | lower_32_bits(q->ctx_save_restore_area_address); |
134 | m->cp_hqd_ctx_save_base_addr_hi = |
135 | upper_32_bits(q->ctx_save_restore_area_address); |
136 | m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; |
137 | m->cp_hqd_cntl_stack_size = q->ctl_stack_size; |
138 | m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; |
139 | m->cp_hqd_wg_state_offset = q->ctl_stack_size; |
140 | } |
141 | |
142 | *mqd = m; |
143 | if (gart_addr) |
144 | *gart_addr = addr; |
145 | mm->update_mqd(mm, m, q, NULL); |
146 | } |
147 | |
148 | static int load_mqd(struct mqd_manager *mm, void *mqd, |
149 | uint32_t pipe_id, uint32_t queue_id, |
150 | struct queue_properties *p, struct mm_struct *mms) |
151 | { |
152 | int r = 0; |
153 | /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ |
154 | uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); |
155 | |
156 | r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, |
157 | (uint32_t __user *)p->write_ptr, |
158 | wptr_shift, 0, mms, 0); |
159 | return r; |
160 | } |
161 | |
162 | static void update_mqd(struct mqd_manager *mm, void *mqd, |
163 | struct queue_properties *q, |
164 | struct mqd_update_info *minfo) |
165 | { |
166 | struct v10_compute_mqd *m; |
167 | |
168 | m = get_mqd(mqd); |
169 | |
170 | m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; |
171 | m->cp_hqd_pq_control |= |
172 | ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; |
173 | m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; |
174 | pr_debug("cp_hqd_pq_control 0x%x\n" , m->cp_hqd_pq_control); |
175 | |
176 | m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); |
177 | m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); |
178 | |
179 | m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); |
180 | m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); |
181 | m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); |
182 | m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); |
183 | |
184 | m->cp_hqd_pq_doorbell_control = |
185 | q->doorbell_off << |
186 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; |
187 | pr_debug("cp_hqd_pq_doorbell_control 0x%x\n" , |
188 | m->cp_hqd_pq_doorbell_control); |
189 | |
190 | m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; |
191 | |
192 | /* |
193 | * HW does not clamp this field correctly. Maximum EOP queue size |
194 | * is constrained by per-SE EOP done signal count, which is 8-bit. |
195 | * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit |
196 | * more than (EOP entry count - 1) so a queue size of 0x800 dwords |
197 | * is safe, giving a maximum field value of 0xA. |
198 | */ |
199 | m->cp_hqd_eop_control = min(0xA, |
200 | ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); |
201 | m->cp_hqd_eop_base_addr_lo = |
202 | lower_32_bits(q->eop_ring_buffer_address >> 8); |
203 | m->cp_hqd_eop_base_addr_hi = |
204 | upper_32_bits(q->eop_ring_buffer_address >> 8); |
205 | |
206 | m->cp_hqd_iq_timer = 0; |
207 | |
208 | m->cp_hqd_vmid = q->vmid; |
209 | |
210 | if (q->format == KFD_QUEUE_FORMAT_AQL) { |
211 | /* GC 10 removed WPP_CLAMP from PQ Control */ |
212 | m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | |
213 | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | |
214 | 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; |
215 | m->cp_hqd_pq_doorbell_control |= |
216 | 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; |
217 | } |
218 | if (mm->dev->kfd->cwsr_enabled) |
219 | m->cp_hqd_ctx_save_control = 0; |
220 | |
221 | update_cu_mask(mm, mqd, minfo); |
222 | set_priority(m, q); |
223 | |
224 | q->is_active = QUEUE_IS_ACTIVE(*q); |
225 | } |
226 | |
227 | static uint32_t read_doorbell_id(void *mqd) |
228 | { |
229 | struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; |
230 | |
231 | return m->queue_doorbell_id0; |
232 | } |
233 | |
234 | static int get_wave_state(struct mqd_manager *mm, void *mqd, |
235 | struct queue_properties *q, |
236 | void __user *ctl_stack, |
237 | u32 *ctl_stack_used_size, |
238 | u32 *save_area_used_size) |
239 | { |
240 | struct v10_compute_mqd *m; |
241 | struct kfd_context_save_area_header ; |
242 | |
243 | m = get_mqd(mqd); |
244 | |
245 | /* Control stack is written backwards, while workgroup context data |
246 | * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. |
247 | * Current position is at m->cp_hqd_cntl_stack_offset and |
248 | * m->cp_hqd_wg_state_offset, respectively. |
249 | */ |
250 | *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - |
251 | m->cp_hqd_cntl_stack_offset; |
252 | *save_area_used_size = m->cp_hqd_wg_state_offset - |
253 | m->cp_hqd_cntl_stack_size; |
254 | |
255 | /* Control stack is not copied to user mode for GFXv10 because |
256 | * it's part of the context save area that is already |
257 | * accessible to user mode |
258 | */ |
259 | |
260 | header.wave_state.control_stack_size = *ctl_stack_used_size; |
261 | header.wave_state.wave_state_size = *save_area_used_size; |
262 | |
263 | header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; |
264 | header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; |
265 | |
266 | if (copy_to_user(to: ctl_stack, from: &header, n: sizeof(header.wave_state))) |
267 | return -EFAULT; |
268 | |
269 | return 0; |
270 | } |
271 | |
272 | static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) |
273 | { |
274 | struct v10_compute_mqd *m; |
275 | |
276 | m = get_mqd(mqd); |
277 | |
278 | memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd)); |
279 | } |
280 | |
281 | static void restore_mqd(struct mqd_manager *mm, void **mqd, |
282 | struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, |
283 | struct queue_properties *qp, |
284 | const void *mqd_src, |
285 | const void *ctl_stack_src, const u32 ctl_stack_size) |
286 | { |
287 | uint64_t addr; |
288 | struct v10_compute_mqd *m; |
289 | |
290 | m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; |
291 | addr = mqd_mem_obj->gpu_addr; |
292 | |
293 | memcpy(m, mqd_src, sizeof(*m)); |
294 | |
295 | *mqd = m; |
296 | if (gart_addr) |
297 | *gart_addr = addr; |
298 | |
299 | m->cp_hqd_pq_doorbell_control = |
300 | qp->doorbell_off << |
301 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; |
302 | pr_debug("cp_hqd_pq_doorbell_control 0x%x\n" , |
303 | m->cp_hqd_pq_doorbell_control); |
304 | |
305 | qp->is_active = 0; |
306 | } |
307 | |
308 | static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, |
309 | struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, |
310 | struct queue_properties *q) |
311 | { |
312 | struct v10_compute_mqd *m; |
313 | |
314 | init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); |
315 | |
316 | m = get_mqd(mqd: *mqd); |
317 | |
318 | m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | |
319 | 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; |
320 | } |
321 | |
322 | static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, |
323 | enum kfd_preempt_type type, unsigned int timeout, |
324 | uint32_t pipe_id, uint32_t queue_id) |
325 | { |
326 | int err; |
327 | struct v10_compute_mqd *m; |
328 | u32 doorbell_off; |
329 | |
330 | m = get_mqd(mqd); |
331 | |
332 | doorbell_off = m->cp_hqd_pq_doorbell_control >> |
333 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; |
334 | |
335 | err = amdgpu_amdkfd_unmap_hiq(adev: mm->dev->adev, doorbell_off, inst: 0); |
336 | if (err) |
337 | pr_debug("Destroy HIQ MQD failed: %d\n" , err); |
338 | |
339 | return err; |
340 | } |
341 | |
342 | static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, |
343 | struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, |
344 | struct queue_properties *q) |
345 | { |
346 | struct v10_sdma_mqd *m; |
347 | |
348 | m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; |
349 | |
350 | memset(m, 0, sizeof(struct v10_sdma_mqd)); |
351 | |
352 | *mqd = m; |
353 | if (gart_addr) |
354 | *gart_addr = mqd_mem_obj->gpu_addr; |
355 | |
356 | mm->update_mqd(mm, m, q, NULL); |
357 | } |
358 | |
359 | #define SDMA_RLC_DUMMY_DEFAULT 0xf |
360 | |
361 | static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, |
362 | struct queue_properties *q, |
363 | struct mqd_update_info *minfo) |
364 | { |
365 | struct v10_sdma_mqd *m; |
366 | |
367 | m = get_sdma_mqd(mqd); |
368 | m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) |
369 | << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | |
370 | q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | |
371 | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | |
372 | 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; |
373 | |
374 | m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); |
375 | m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); |
376 | m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); |
377 | m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); |
378 | m->sdmax_rlcx_doorbell_offset = |
379 | q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; |
380 | |
381 | m->sdma_engine_id = q->sdma_engine_id; |
382 | m->sdma_queue_id = q->sdma_queue_id; |
383 | m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; |
384 | |
385 | q->is_active = QUEUE_IS_ACTIVE(*q); |
386 | } |
387 | |
388 | static void checkpoint_mqd_sdma(struct mqd_manager *mm, |
389 | void *mqd, |
390 | void *mqd_dst, |
391 | void *ctl_stack_dst) |
392 | { |
393 | struct v10_sdma_mqd *m; |
394 | |
395 | m = get_sdma_mqd(mqd); |
396 | |
397 | memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd)); |
398 | } |
399 | |
400 | static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, |
401 | struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, |
402 | struct queue_properties *qp, |
403 | const void *mqd_src, |
404 | const void *ctl_stack_src, |
405 | const u32 ctl_stack_size) |
406 | { |
407 | uint64_t addr; |
408 | struct v10_sdma_mqd *m; |
409 | |
410 | m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; |
411 | addr = mqd_mem_obj->gpu_addr; |
412 | |
413 | memcpy(m, mqd_src, sizeof(*m)); |
414 | |
415 | m->sdmax_rlcx_doorbell_offset = |
416 | qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; |
417 | |
418 | *mqd = m; |
419 | if (gart_addr) |
420 | *gart_addr = addr; |
421 | |
422 | qp->is_active = 0; |
423 | } |
424 | |
425 | #if defined(CONFIG_DEBUG_FS) |
426 | |
427 | static int debugfs_show_mqd(struct seq_file *m, void *data) |
428 | { |
429 | seq_hex_dump(m, prefix_str: " " , prefix_type: DUMP_PREFIX_OFFSET, rowsize: 32, groupsize: 4, |
430 | buf: data, len: sizeof(struct v10_compute_mqd), ascii: false); |
431 | return 0; |
432 | } |
433 | |
434 | static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) |
435 | { |
436 | seq_hex_dump(m, prefix_str: " " , prefix_type: DUMP_PREFIX_OFFSET, rowsize: 32, groupsize: 4, |
437 | buf: data, len: sizeof(struct v10_sdma_mqd), ascii: false); |
438 | return 0; |
439 | } |
440 | |
441 | #endif |
442 | |
443 | struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, |
444 | struct kfd_node *dev) |
445 | { |
446 | struct mqd_manager *mqd; |
447 | |
448 | if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) |
449 | return NULL; |
450 | |
451 | mqd = kzalloc(size: sizeof(*mqd), GFP_KERNEL); |
452 | if (!mqd) |
453 | return NULL; |
454 | |
455 | mqd->dev = dev; |
456 | |
457 | switch (type) { |
458 | case KFD_MQD_TYPE_CP: |
459 | pr_debug("%s@%i\n" , __func__, __LINE__); |
460 | mqd->allocate_mqd = allocate_mqd; |
461 | mqd->init_mqd = init_mqd; |
462 | mqd->free_mqd = kfd_free_mqd_cp; |
463 | mqd->load_mqd = load_mqd; |
464 | mqd->update_mqd = update_mqd; |
465 | mqd->destroy_mqd = kfd_destroy_mqd_cp; |
466 | mqd->is_occupied = kfd_is_occupied_cp; |
467 | mqd->mqd_size = sizeof(struct v10_compute_mqd); |
468 | mqd->get_wave_state = get_wave_state; |
469 | mqd->checkpoint_mqd = checkpoint_mqd; |
470 | mqd->restore_mqd = restore_mqd; |
471 | mqd->mqd_stride = kfd_mqd_stride; |
472 | #if defined(CONFIG_DEBUG_FS) |
473 | mqd->debugfs_show_mqd = debugfs_show_mqd; |
474 | #endif |
475 | pr_debug("%s@%i\n" , __func__, __LINE__); |
476 | break; |
477 | case KFD_MQD_TYPE_HIQ: |
478 | pr_debug("%s@%i\n" , __func__, __LINE__); |
479 | mqd->allocate_mqd = allocate_hiq_mqd; |
480 | mqd->init_mqd = init_mqd_hiq; |
481 | mqd->free_mqd = free_mqd_hiq_sdma; |
482 | mqd->load_mqd = kfd_hiq_load_mqd_kiq; |
483 | mqd->update_mqd = update_mqd; |
484 | mqd->destroy_mqd = destroy_hiq_mqd; |
485 | mqd->is_occupied = kfd_is_occupied_cp; |
486 | mqd->mqd_size = sizeof(struct v10_compute_mqd); |
487 | mqd->mqd_stride = kfd_mqd_stride; |
488 | #if defined(CONFIG_DEBUG_FS) |
489 | mqd->debugfs_show_mqd = debugfs_show_mqd; |
490 | #endif |
491 | mqd->read_doorbell_id = read_doorbell_id; |
492 | pr_debug("%s@%i\n" , __func__, __LINE__); |
493 | break; |
494 | case KFD_MQD_TYPE_DIQ: |
495 | mqd->allocate_mqd = allocate_mqd; |
496 | mqd->init_mqd = init_mqd_hiq; |
497 | mqd->free_mqd = kfd_free_mqd_cp; |
498 | mqd->load_mqd = load_mqd; |
499 | mqd->update_mqd = update_mqd; |
500 | mqd->destroy_mqd = kfd_destroy_mqd_cp; |
501 | mqd->is_occupied = kfd_is_occupied_cp; |
502 | mqd->mqd_size = sizeof(struct v10_compute_mqd); |
503 | #if defined(CONFIG_DEBUG_FS) |
504 | mqd->debugfs_show_mqd = debugfs_show_mqd; |
505 | #endif |
506 | break; |
507 | case KFD_MQD_TYPE_SDMA: |
508 | pr_debug("%s@%i\n" , __func__, __LINE__); |
509 | mqd->allocate_mqd = allocate_sdma_mqd; |
510 | mqd->init_mqd = init_mqd_sdma; |
511 | mqd->free_mqd = free_mqd_hiq_sdma; |
512 | mqd->load_mqd = kfd_load_mqd_sdma; |
513 | mqd->update_mqd = update_mqd_sdma; |
514 | mqd->destroy_mqd = kfd_destroy_mqd_sdma; |
515 | mqd->is_occupied = kfd_is_occupied_sdma; |
516 | mqd->checkpoint_mqd = checkpoint_mqd_sdma; |
517 | mqd->restore_mqd = restore_mqd_sdma; |
518 | mqd->mqd_size = sizeof(struct v10_sdma_mqd); |
519 | mqd->mqd_stride = kfd_mqd_stride; |
520 | #if defined(CONFIG_DEBUG_FS) |
521 | mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; |
522 | #endif |
523 | pr_debug("%s@%i\n" , __func__, __LINE__); |
524 | break; |
525 | default: |
526 | kfree(objp: mqd); |
527 | return NULL; |
528 | } |
529 | |
530 | return mqd; |
531 | } |
532 | |