1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef DC_TYPES_H_
26#define DC_TYPES_H_
27
28/* AND EdidUtility only needs a portion
29 * of this file, including the rest only
30 * causes additional issues.
31 */
32#include "os_types.h"
33#include "fixed31_32.h"
34#include "irq_types.h"
35#include "dc_ddc_types.h"
36#include "dc_dp_types.h"
37#include "dc_hdmi_types.h"
38#include "dc_hw_types.h"
39#include "dal_types.h"
40#include "grph_object_defs.h"
41#include "grph_object_ctrl_defs.h"
42
43#include "dm_cp_psp.h"
44
45/* forward declarations */
46struct dc_plane_state;
47struct dc_stream_state;
48struct dc_link;
49struct dc_sink;
50struct dal;
51struct dc_dmub_srv;
52
53/********************************
54 * Environment definitions
55 ********************************/
56enum dce_environment {
57 DCE_ENV_PRODUCTION_DRV = 0,
58 /* Emulation on FPGA, in "Maximus" System.
59 * This environment enforces that *only* DC registers accessed.
60 * (access to non-DC registers will hang FPGA) */
61 DCE_ENV_FPGA_MAXIMUS,
62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
63 * requirements of Diagnostics team. */
64 DCE_ENV_DIAG,
65 /*
66 * Guest VM system, DC HW may exist but is not virtualized and
67 * should not be used. SW support for VDI only.
68 */
69 DCE_ENV_VIRTUAL_HW
70};
71
72struct dc_perf_trace {
73 unsigned long read_count;
74 unsigned long write_count;
75 unsigned long last_entry_read;
76 unsigned long last_entry_write;
77};
78
79#define MAX_SURFACE_NUM 6
80#define NUM_PIXEL_FORMATS 10
81
82enum tiling_mode {
83 TILING_MODE_INVALID,
84 TILING_MODE_LINEAR,
85 TILING_MODE_TILED,
86 TILING_MODE_COUNT
87};
88
89enum view_3d_format {
90 VIEW_3D_FORMAT_NONE = 0,
91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
92 VIEW_3D_FORMAT_SIDE_BY_SIDE,
93 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
94 VIEW_3D_FORMAT_COUNT,
95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
96};
97
98enum plane_stereo_format {
99 PLANE_STEREO_FORMAT_NONE = 0,
100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
106};
107
108/* TODO: Find way to calculate number of bits
109 * Please increase if pixel_format enum increases
110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
111 */
112
113enum dc_edid_connector_type {
114 DC_EDID_CONNECTOR_UNKNOWN = 0,
115 DC_EDID_CONNECTOR_ANALOG = 1,
116 DC_EDID_CONNECTOR_DIGITAL = 10,
117 DC_EDID_CONNECTOR_DVI = 11,
118 DC_EDID_CONNECTOR_HDMIA = 12,
119 DC_EDID_CONNECTOR_MDDI = 14,
120 DC_EDID_CONNECTOR_DISPLAYPORT = 15
121};
122
123enum dc_edid_status {
124 EDID_OK,
125 EDID_BAD_INPUT,
126 EDID_NO_RESPONSE,
127 EDID_BAD_CHECKSUM,
128 EDID_THE_SAME,
129 EDID_FALL_BACK,
130 EDID_PARTIAL_VALID,
131};
132
133enum act_return_status {
134 ACT_SUCCESS,
135 ACT_LINK_LOST,
136 ACT_FAILED
137};
138
139/* audio capability from EDID*/
140struct dc_cea_audio_mode {
141 uint8_t format_code; /* ucData[0] [6:3]*/
142 uint8_t channel_count; /* ucData[0] [2:0]*/
143 uint8_t sample_rate; /* ucData[1]*/
144 union {
145 uint8_t sample_size; /* for LPCM*/
146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t max_bit_rate;
148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
149 };
150};
151
152struct dc_edid {
153 uint32_t length;
154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
155};
156
157/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
158 * is used. In this case we assume speaker location are: front left, front
159 * right and front center. */
160#define DEFAULT_SPEAKER_LOCATION 5
161
162#define DC_MAX_AUDIO_DESC_COUNT 16
163
164#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
165
166struct dc_panel_patch {
167 unsigned int dppowerup_delay;
168 unsigned int extra_t12_ms;
169 unsigned int extra_delay_backlight_off;
170 unsigned int extra_t7_ms;
171 unsigned int skip_scdc_overwrite;
172 unsigned int delay_ignore_msa;
173 unsigned int disable_fec;
174 unsigned int extra_t3_ms;
175 unsigned int max_dsc_target_bpp_limit;
176 unsigned int embedded_tiled_slave;
177 unsigned int disable_fams;
178 unsigned int skip_avmute;
179 unsigned int mst_start_top_delay;
180 unsigned int remove_sink_ext_caps;
181};
182
183struct dc_edid_caps {
184 /* sink identification */
185 uint16_t manufacturer_id;
186 uint16_t product_id;
187 uint32_t serial_number;
188 uint8_t manufacture_week;
189 uint8_t manufacture_year;
190 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
191
192 /* audio caps */
193 uint8_t speaker_flags;
194 uint32_t audio_mode_count;
195 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
196 uint32_t audio_latency;
197 uint32_t video_latency;
198
199 uint8_t qs_bit;
200 uint8_t qy_bit;
201
202 uint32_t max_tmds_clk_mhz;
203
204 /*HDMI 2.0 caps*/
205 bool lte_340mcsc_scramble;
206
207 bool edid_hdmi;
208 bool hdr_supported;
209
210 struct dc_panel_patch panel_patch;
211};
212
213struct dc_mode_flags {
214 /* note: part of refresh rate flag*/
215 uint32_t INTERLACE :1;
216 /* native display timing*/
217 uint32_t NATIVE :1;
218 /* preferred is the recommended mode, one per display */
219 uint32_t PREFERRED :1;
220 /* true if this mode should use reduced blanking timings
221 *_not_ related to the Reduced Blanking adjustment*/
222 uint32_t REDUCED_BLANKING :1;
223 /* note: part of refreshrate flag*/
224 uint32_t VIDEO_OPTIMIZED_RATE :1;
225 /* should be reported to upper layers as mode_flags*/
226 uint32_t PACKED_PIXEL_FORMAT :1;
227 /*< preferred view*/
228 uint32_t PREFERRED_VIEW :1;
229 /* this timing should be used only in tiled mode*/
230 uint32_t TILED_MODE :1;
231 uint32_t DSE_MODE :1;
232 /* Refresh rate divider when Miracast sink is using a
233 different rate than the output display device
234 Must be zero for wired displays and non-zero for
235 Miracast displays*/
236 uint32_t MIRACAST_REFRESH_DIVIDER;
237};
238
239
240enum dc_timing_source {
241 TIMING_SOURCE_UNDEFINED,
242
243 /* explicitly specifed by user, most important*/
244 TIMING_SOURCE_USER_FORCED,
245 TIMING_SOURCE_USER_OVERRIDE,
246 TIMING_SOURCE_CUSTOM,
247 TIMING_SOURCE_EXPLICIT,
248
249 /* explicitly specified by the display device, more important*/
250 TIMING_SOURCE_EDID_CEA_SVD_3D,
251 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
252 TIMING_SOURCE_EDID_CEA_SVD_420,
253 TIMING_SOURCE_EDID_DETAILED,
254 TIMING_SOURCE_EDID_ESTABLISHED,
255 TIMING_SOURCE_EDID_STANDARD,
256 TIMING_SOURCE_EDID_CEA_SVD,
257 TIMING_SOURCE_EDID_CVT_3BYTE,
258 TIMING_SOURCE_EDID_4BYTE,
259 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
260 TIMING_SOURCE_EDID_CEA_RID,
261 TIMING_SOURCE_VBIOS,
262 TIMING_SOURCE_CV,
263 TIMING_SOURCE_TV,
264 TIMING_SOURCE_HDMI_VIC,
265
266 /* implicitly specified by display device, still safe but less important*/
267 TIMING_SOURCE_DEFAULT,
268
269 /* only used for custom base modes */
270 TIMING_SOURCE_CUSTOM_BASE,
271
272 /* these timing might not work, least important*/
273 TIMING_SOURCE_RANGELIMIT,
274 TIMING_SOURCE_OS_FORCED,
275 TIMING_SOURCE_IMPLICIT,
276
277 /* only used by default mode list*/
278 TIMING_SOURCE_BASICMODE,
279
280 TIMING_SOURCE_COUNT
281};
282
283
284struct stereo_3d_features {
285 bool supported ;
286 bool allTimings ;
287 bool cloneMode ;
288 bool scaling ;
289 bool singleFrameSWPacked;
290};
291
292enum dc_timing_support_method {
293 TIMING_SUPPORT_METHOD_UNDEFINED,
294 TIMING_SUPPORT_METHOD_EXPLICIT,
295 TIMING_SUPPORT_METHOD_IMPLICIT,
296 TIMING_SUPPORT_METHOD_NATIVE
297};
298
299struct dc_mode_info {
300 uint32_t pixel_width;
301 uint32_t pixel_height;
302 uint32_t field_rate;
303 /* Vertical refresh rate for progressive modes.
304 * Field rate for interlaced modes.*/
305
306 enum dc_timing_standard timing_standard;
307 enum dc_timing_source timing_source;
308 struct dc_mode_flags flags;
309};
310
311enum dc_power_state {
312 DC_POWER_STATE_ON = 1,
313 DC_POWER_STATE_STANDBY,
314 DC_POWER_STATE_SUSPEND,
315 DC_POWER_STATE_OFF
316};
317
318/* DC PowerStates */
319enum dc_video_power_state {
320 DC_VIDEO_POWER_UNSPECIFIED = 0,
321 DC_VIDEO_POWER_ON = 1,
322 DC_VIDEO_POWER_STANDBY,
323 DC_VIDEO_POWER_SUSPEND,
324 DC_VIDEO_POWER_OFF,
325 DC_VIDEO_POWER_HIBERNATE,
326 DC_VIDEO_POWER_SHUTDOWN,
327 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
328 DC_VIDEO_POWER_AFTER_RESET,
329 DC_VIDEO_POWER_MAXIMUM
330};
331
332enum dc_acpi_cm_power_state {
333 DC_ACPI_CM_POWER_STATE_D0 = 1,
334 DC_ACPI_CM_POWER_STATE_D1 = 2,
335 DC_ACPI_CM_POWER_STATE_D2 = 4,
336 DC_ACPI_CM_POWER_STATE_D3 = 8
337};
338
339enum dc_connection_type {
340 dc_connection_none,
341 dc_connection_single,
342 dc_connection_mst_branch,
343 dc_connection_sst_branch
344};
345
346struct dc_csc_adjustments {
347 struct fixed31_32 contrast;
348 struct fixed31_32 saturation;
349 struct fixed31_32 brightness;
350 struct fixed31_32 hue;
351};
352
353/* Scaling format */
354enum scaling_transformation {
355 SCALING_TRANSFORMATION_UNINITIALIZED,
356 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
357 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
358 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
359 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
360 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
361 SCALING_TRANSFORMATION_INVALID = 0x80000000,
362
363 /* Flag the first and last */
364 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
365 SCALING_TRANSFORMATION_END =
366 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
367};
368
369enum display_content_type {
370 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
371 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
372 DISPLAY_CONTENT_TYPE_PHOTO = 2,
373 DISPLAY_CONTENT_TYPE_CINEMA = 4,
374 DISPLAY_CONTENT_TYPE_GAME = 8
375};
376
377enum cm_gamut_adjust_type {
378 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
379 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
380 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
381};
382
383struct cm_grph_csc_adjustment {
384 struct fixed31_32 temperature_matrix[12];
385 enum cm_gamut_adjust_type gamut_adjust_type;
386 enum cm_gamut_coef_format gamut_coef_format;
387};
388
389/* writeback */
390struct dwb_stereo_params {
391 bool stereo_enabled; /* false: normal mode, true: 3D stereo */
392 enum dwb_stereo_type stereo_type; /* indicates stereo format */
393 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
394 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
395};
396
397struct dc_dwb_cnv_params {
398 unsigned int src_width; /* input active width */
399 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
400 unsigned int crop_width; /* cropped window width at cnv output */
401 bool crop_en; /* window cropping enable in cnv */
402 unsigned int crop_height; /* cropped window height at cnv output */
403 unsigned int crop_x; /* cropped window start x value at cnv output */
404 unsigned int crop_y; /* cropped window start y value at cnv output */
405 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
406 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
407 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
408 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
409 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
410};
411
412struct dc_dwb_params {
413 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
414 unsigned int hdr_mult; /* must be in FP1.6.12 */
415 struct cm_grph_csc_adjustment csc_params;
416 struct dwb_stereo_params stereo_params;
417 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
418 unsigned int dest_width; /* Destination width */
419 unsigned int dest_height; /* Destination height */
420 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
421 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
422 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
423 struct scaling_taps scaler_taps; /* Scaling taps */
424 enum dwb_subsample_position subsample_position;
425 struct dc_transfer_func *out_transfer_func;
426};
427
428/* audio*/
429
430union audio_sample_rates {
431 struct sample_rates {
432 uint8_t RATE_32:1;
433 uint8_t RATE_44_1:1;
434 uint8_t RATE_48:1;
435 uint8_t RATE_88_2:1;
436 uint8_t RATE_96:1;
437 uint8_t RATE_176_4:1;
438 uint8_t RATE_192:1;
439 } rate;
440
441 uint8_t all;
442};
443
444struct audio_speaker_flags {
445 uint32_t FL_FR:1;
446 uint32_t LFE:1;
447 uint32_t FC:1;
448 uint32_t RL_RR:1;
449 uint32_t RC:1;
450 uint32_t FLC_FRC:1;
451 uint32_t RLC_RRC:1;
452 uint32_t SUPPORT_AI:1;
453};
454
455struct audio_speaker_info {
456 uint32_t ALLSPEAKERS:7;
457 uint32_t SUPPORT_AI:1;
458};
459
460
461struct audio_info_flags {
462
463 union {
464
465 struct audio_speaker_flags speaker_flags;
466 struct audio_speaker_info info;
467
468 uint8_t all;
469 };
470};
471
472enum audio_format_code {
473 AUDIO_FORMAT_CODE_FIRST = 1,
474 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
475
476 AUDIO_FORMAT_CODE_AC3,
477 /*Layers 1 & 2 */
478 AUDIO_FORMAT_CODE_MPEG1,
479 /*MPEG1 Layer 3 */
480 AUDIO_FORMAT_CODE_MP3,
481 /*multichannel */
482 AUDIO_FORMAT_CODE_MPEG2,
483 AUDIO_FORMAT_CODE_AAC,
484 AUDIO_FORMAT_CODE_DTS,
485 AUDIO_FORMAT_CODE_ATRAC,
486 AUDIO_FORMAT_CODE_1BITAUDIO,
487 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
488 AUDIO_FORMAT_CODE_DTS_HD,
489 AUDIO_FORMAT_CODE_MAT_MLP,
490 AUDIO_FORMAT_CODE_DST,
491 AUDIO_FORMAT_CODE_WMAPRO,
492 AUDIO_FORMAT_CODE_LAST,
493 AUDIO_FORMAT_CODE_COUNT =
494 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
495};
496
497struct audio_mode {
498 /* ucData[0] [6:3] */
499 enum audio_format_code format_code;
500 /* ucData[0] [2:0] */
501 uint8_t channel_count;
502 /* ucData[1] */
503 union audio_sample_rates sample_rates;
504 union {
505 /* for LPCM */
506 uint8_t sample_size;
507 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
508 uint8_t max_bit_rate;
509 /* for Audio Formats 9-15 */
510 uint8_t vendor_specific;
511 };
512};
513
514struct audio_info {
515 struct audio_info_flags flags;
516 uint32_t video_latency;
517 uint32_t audio_latency;
518 uint32_t display_index;
519 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
520 uint32_t manufacture_id;
521 uint32_t product_id;
522 /* PortID used for ContainerID when defined */
523 uint32_t port_id[2];
524 uint32_t mode_count;
525 /* this field must be last in this struct */
526 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
527};
528struct audio_check {
529 unsigned int audio_packet_type;
530 unsigned int max_audiosample_rate;
531 unsigned int acat;
532};
533enum dc_infoframe_type {
534 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
535 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
536 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
537 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
538 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
539};
540
541struct dc_info_packet {
542 bool valid;
543 uint8_t hb0;
544 uint8_t hb1;
545 uint8_t hb2;
546 uint8_t hb3;
547 uint8_t sb[32];
548};
549
550struct dc_info_packet_128 {
551 bool valid;
552 uint8_t hb0;
553 uint8_t hb1;
554 uint8_t hb2;
555 uint8_t hb3;
556 uint8_t sb[128];
557};
558
559#define DC_PLANE_UPDATE_TIMES_MAX 10
560
561struct dc_plane_flip_time {
562 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
563 unsigned int index;
564 unsigned int prev_update_time_in_us;
565};
566
567enum dc_psr_state {
568 PSR_STATE0 = 0x0,
569 PSR_STATE1,
570 PSR_STATE1a,
571 PSR_STATE2,
572 PSR_STATE2a,
573 PSR_STATE2b,
574 PSR_STATE3,
575 PSR_STATE3Init,
576 PSR_STATE4,
577 PSR_STATE4a,
578 PSR_STATE4b,
579 PSR_STATE4c,
580 PSR_STATE4d,
581 PSR_STATE4_FULL_FRAME,
582 PSR_STATE4a_FULL_FRAME,
583 PSR_STATE4b_FULL_FRAME,
584 PSR_STATE4c_FULL_FRAME,
585 PSR_STATE4_FULL_FRAME_POWERUP,
586 PSR_STATE4_FULL_FRAME_HW_LOCK,
587 PSR_STATE5,
588 PSR_STATE5a,
589 PSR_STATE5b,
590 PSR_STATE5c,
591 PSR_STATE_HWLOCK_MGR,
592 PSR_STATE_POLLVUPDATE,
593 PSR_STATE_INVALID = 0xFF
594};
595
596struct psr_config {
597 unsigned char psr_version;
598 unsigned int psr_rfb_setup_time;
599 bool psr_exit_link_training_required;
600 bool psr_frame_capture_indication_req;
601 unsigned int psr_sdp_transmit_line_num_deadline;
602 bool allow_smu_optimizations;
603 bool allow_multi_disp_optimizations;
604 /* Panel self refresh 2 selective update granularity required */
605 bool su_granularity_required;
606 /* psr2 selective update y granularity capability */
607 uint8_t su_y_granularity;
608 unsigned int line_time_in_us;
609 uint8_t rate_control_caps;
610 uint16_t dsc_slice_height;
611};
612
613union dmcu_psr_level {
614 struct {
615 unsigned int SKIP_CRC:1;
616 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
617 unsigned int SKIP_PHY_POWER_DOWN:1;
618 unsigned int SKIP_AUX_ACK_CHECK:1;
619 unsigned int SKIP_CRTC_DISABLE:1;
620 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
621 unsigned int SKIP_SMU_NOTIFICATION:1;
622 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
623 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
624 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
625 unsigned int DISABLE_ALPM:1;
626 unsigned int ALPM_DEFAULT_PD_MODE:1;
627 unsigned int RESERVED:20;
628 } bits;
629 unsigned int u32all;
630};
631
632enum physical_phy_id {
633 PHYLD_0,
634 PHYLD_1,
635 PHYLD_2,
636 PHYLD_3,
637 PHYLD_4,
638 PHYLD_5,
639 PHYLD_6,
640 PHYLD_7,
641 PHYLD_8,
642 PHYLD_9,
643 PHYLD_COUNT,
644 PHYLD_UNKNOWN = (-1L)
645};
646
647enum phy_type {
648 PHY_TYPE_UNKNOWN = 1,
649 PHY_TYPE_PCIE_PHY = 2,
650 PHY_TYPE_UNIPHY = 3,
651};
652
653struct psr_context {
654 /* ddc line */
655 enum channel_id channel;
656 /* Transmitter id */
657 enum transmitter transmitterId;
658 /* Engine Id is used for Dig Be source select */
659 enum engine_id engineId;
660 /* Controller Id used for Dig Fe source select */
661 enum controller_id controllerId;
662 /* Pcie or Uniphy */
663 enum phy_type phyType;
664 /* Physical PHY Id used by SMU interpretation */
665 enum physical_phy_id smuPhyId;
666 /* Vertical total pixels from crtc timing.
667 * This is used for static screen detection.
668 * ie. If we want to detect half a frame,
669 * we use this to determine the hyst lines.
670 */
671 unsigned int crtcTimingVerticalTotal;
672 /* PSR supported from panel capabilities and
673 * current display configuration
674 */
675 bool psrSupportedDisplayConfig;
676 /* Whether fast link training is supported by the panel */
677 bool psrExitLinkTrainingRequired;
678 /* If RFB setup time is greater than the total VBLANK time,
679 * it is not possible for the sink to capture the video frame
680 * in the same frame the SDP is sent. In this case,
681 * the frame capture indication bit should be set and an extra
682 * static frame should be transmitted to the sink.
683 */
684 bool psrFrameCaptureIndicationReq;
685 /* Set the last possible line SDP may be transmitted without violating
686 * the RFB setup time or entering the active video frame.
687 */
688 unsigned int sdpTransmitLineNumDeadline;
689 /* The VSync rate in Hz used to calculate the
690 * step size for smooth brightness feature
691 */
692 unsigned int vsync_rate_hz;
693 unsigned int skipPsrWaitForPllLock;
694 unsigned int numberOfControllers;
695 /* Unused, for future use. To indicate that first changed frame from
696 * state3 shouldn't result in psr_inactive, but rather to perform
697 * an automatic single frame rfb_update.
698 */
699 bool rfb_update_auto_en;
700 /* Number of frame before entering static screen */
701 unsigned int timehyst_frames;
702 /* Partial frames before entering static screen */
703 unsigned int hyst_lines;
704 /* # of repeated AUX transaction attempts to make before
705 * indicating failure to the driver
706 */
707 unsigned int aux_repeats;
708 /* Controls hw blocks to power down during PSR active state */
709 union dmcu_psr_level psr_level;
710 /* Controls additional delay after remote frame capture before
711 * continuing powerd own
712 */
713 unsigned int frame_delay;
714 bool allow_smu_optimizations;
715 bool allow_multi_disp_optimizations;
716 /* Panel self refresh 2 selective update granularity required */
717 bool su_granularity_required;
718 /* psr2 selective update y granularity capability */
719 uint8_t su_y_granularity;
720 unsigned int line_time_in_us;
721 uint8_t rate_control_caps;
722 uint16_t dsc_slice_height;
723};
724
725struct colorspace_transform {
726 struct fixed31_32 matrix[12];
727 bool enable_remap;
728};
729
730enum i2c_mot_mode {
731 I2C_MOT_UNDEF,
732 I2C_MOT_TRUE,
733 I2C_MOT_FALSE
734};
735
736struct AsicStateEx {
737 unsigned int memoryClock;
738 unsigned int displayClock;
739 unsigned int engineClock;
740 unsigned int maxSupportedDppClock;
741 unsigned int dppClock;
742 unsigned int socClock;
743 unsigned int dcfClockDeepSleep;
744 unsigned int fClock;
745 unsigned int phyClock;
746};
747
748
749enum dc_clock_type {
750 DC_CLOCK_TYPE_DISPCLK = 0,
751 DC_CLOCK_TYPE_DPPCLK = 1,
752};
753
754struct dc_clock_config {
755 uint32_t max_clock_khz;
756 uint32_t min_clock_khz;
757 uint32_t bw_requirequired_clock_khz;
758 uint32_t current_clock_khz;/*current clock in use*/
759};
760
761struct hw_asic_id {
762 uint32_t chip_id;
763 uint32_t chip_family;
764 uint32_t pci_revision_id;
765 uint32_t hw_internal_rev;
766 uint32_t vram_type;
767 uint32_t vram_width;
768 uint32_t feature_flags;
769 uint32_t fake_paths_num;
770 void *atombios_base_address;
771};
772
773struct dc_context {
774 struct dc *dc;
775
776 void *driver_context; /* e.g. amdgpu_device */
777 struct dal_logger *logger;
778 struct dc_perf_trace *perf_trace;
779 void *cgs_device;
780
781 enum dce_environment dce_environment;
782 struct hw_asic_id asic_id;
783
784 /* todo: below should probably move to dc. to facilitate removal
785 * of AS we will store these here
786 */
787 enum dce_version dce_version;
788 struct dc_bios *dc_bios;
789 bool created_bios;
790 struct gpio_service *gpio_service;
791 uint32_t dc_sink_id_count;
792 uint32_t dc_stream_id_count;
793 uint32_t dc_edp_id_count;
794 uint64_t fbc_gpu_addr;
795 struct dc_dmub_srv *dmub_srv;
796 struct cp_psp cp_psp;
797 uint32_t *dcn_reg_offsets;
798 uint32_t *nbio_reg_offsets;
799 uint32_t *clk_reg_offsets;
800};
801
802/* DSC DPCD capabilities */
803union dsc_slice_caps1 {
804 struct {
805 uint8_t NUM_SLICES_1 : 1;
806 uint8_t NUM_SLICES_2 : 1;
807 uint8_t RESERVED : 1;
808 uint8_t NUM_SLICES_4 : 1;
809 uint8_t NUM_SLICES_6 : 1;
810 uint8_t NUM_SLICES_8 : 1;
811 uint8_t NUM_SLICES_10 : 1;
812 uint8_t NUM_SLICES_12 : 1;
813 } bits;
814 uint8_t raw;
815};
816
817union dsc_slice_caps2 {
818 struct {
819 uint8_t NUM_SLICES_16 : 1;
820 uint8_t NUM_SLICES_20 : 1;
821 uint8_t NUM_SLICES_24 : 1;
822 uint8_t RESERVED : 5;
823 } bits;
824 uint8_t raw;
825};
826
827union dsc_color_formats {
828 struct {
829 uint8_t RGB : 1;
830 uint8_t YCBCR_444 : 1;
831 uint8_t YCBCR_SIMPLE_422 : 1;
832 uint8_t YCBCR_NATIVE_422 : 1;
833 uint8_t YCBCR_NATIVE_420 : 1;
834 uint8_t RESERVED : 3;
835 } bits;
836 uint8_t raw;
837};
838
839union dsc_color_depth {
840 struct {
841 uint8_t RESERVED1 : 1;
842 uint8_t COLOR_DEPTH_8_BPC : 1;
843 uint8_t COLOR_DEPTH_10_BPC : 1;
844 uint8_t COLOR_DEPTH_12_BPC : 1;
845 uint8_t RESERVED2 : 3;
846 } bits;
847 uint8_t raw;
848};
849
850struct dsc_dec_dpcd_caps {
851 bool is_dsc_supported;
852 uint8_t dsc_version;
853 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
854 union dsc_slice_caps1 slice_caps1;
855 union dsc_slice_caps2 slice_caps2;
856 int32_t lb_bit_depth;
857 bool is_block_pred_supported;
858 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
859 union dsc_color_formats color_formats;
860 union dsc_color_depth color_depth;
861 int32_t throughput_mode_0_mps; /* In MPs */
862 int32_t throughput_mode_1_mps; /* In MPs */
863 int32_t max_slice_width;
864 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
865
866 /* Extended DSC caps */
867 uint32_t branch_overall_throughput_0_mps; /* In MPs */
868 uint32_t branch_overall_throughput_1_mps; /* In MPs */
869 uint32_t branch_max_line_width;
870 bool is_dp; /* Decoded format */
871};
872
873struct dc_golden_table {
874 uint16_t dc_golden_table_ver;
875 uint32_t aux_dphy_rx_control0_val;
876 uint32_t aux_dphy_tx_control_val;
877 uint32_t aux_dphy_rx_control1_val;
878 uint32_t dc_gpio_aux_ctrl_0_val;
879 uint32_t dc_gpio_aux_ctrl_1_val;
880 uint32_t dc_gpio_aux_ctrl_2_val;
881 uint32_t dc_gpio_aux_ctrl_3_val;
882 uint32_t dc_gpio_aux_ctrl_4_val;
883 uint32_t dc_gpio_aux_ctrl_5_val;
884};
885
886enum dc_gpu_mem_alloc_type {
887 DC_MEM_ALLOC_TYPE_GART,
888 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
889 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
890 DC_MEM_ALLOC_TYPE_AGP
891};
892
893enum dc_link_encoding_format {
894 DC_LINK_ENCODING_UNSPECIFIED = 0,
895 DC_LINK_ENCODING_DP_8b_10b,
896 DC_LINK_ENCODING_DP_128b_132b,
897 DC_LINK_ENCODING_HDMI_TMDS,
898 DC_LINK_ENCODING_HDMI_FRL
899};
900
901enum dc_psr_version {
902 DC_PSR_VERSION_1 = 0,
903 DC_PSR_VERSION_SU_1 = 1,
904 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
905};
906
907/* Possible values of display_endpoint_id.endpoint */
908enum display_endpoint_type {
909 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
910 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
911 DISPLAY_ENDPOINT_UNKNOWN = -1
912};
913
914/* Extends graphics_object_id with an additional member 'ep_type' for
915 * distinguishing between physical endpoints (with entries in BIOS connector table) and
916 * logical endpoints.
917 */
918struct display_endpoint_id {
919 struct graphics_object_id link_id;
920 enum display_endpoint_type ep_type;
921};
922
923#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
924struct otg_phy_mux {
925 uint8_t phy_output_num;
926 uint8_t otg_output_num;
927};
928#endif
929
930enum dc_detect_reason {
931 DETECT_REASON_BOOT,
932 DETECT_REASON_RESUMEFROMS3S4,
933 DETECT_REASON_HPD,
934 DETECT_REASON_HPDRX,
935 DETECT_REASON_FALLBACK,
936 DETECT_REASON_RETRAIN,
937 DETECT_REASON_TDR,
938};
939
940struct dc_link_status {
941 bool link_active;
942 struct dpcd_caps *dpcd_caps;
943};
944
945union hdcp_rx_caps {
946 struct {
947 uint8_t version;
948 uint8_t reserved;
949 struct {
950 uint8_t repeater : 1;
951 uint8_t hdcp_capable : 1;
952 uint8_t reserved : 6;
953 } byte0;
954 } fields;
955 uint8_t raw[3];
956};
957
958union hdcp_bcaps {
959 struct {
960 uint8_t HDCP_CAPABLE:1;
961 uint8_t REPEATER:1;
962 uint8_t RESERVED:6;
963 } bits;
964 uint8_t raw;
965};
966
967struct hdcp_caps {
968 union hdcp_rx_caps rx_caps;
969 union hdcp_bcaps bcaps;
970};
971
972/* DP MST stream allocation (payload bandwidth number) */
973struct link_mst_stream_allocation {
974 /* DIG front */
975 const struct stream_encoder *stream_enc;
976 /* HPO DP Stream Encoder */
977 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
978 /* associate DRM payload table with DC stream encoder */
979 uint8_t vcp_id;
980 /* number of slots required for the DP stream in transport packet */
981 uint8_t slot_count;
982};
983
984#define MAX_CONTROLLER_NUM 6
985
986/* DP MST stream allocation table */
987struct link_mst_stream_allocation_table {
988 /* number of DP video streams */
989 int stream_count;
990 /* array of stream allocations */
991 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
992};
993
994/* PSR feature flags */
995struct psr_settings {
996 bool psr_feature_enabled; // PSR is supported by sink
997 bool psr_allow_active; // PSR is currently active
998 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD
999 bool psr_vtotal_control_support; // Vtotal control is supported by sink
1000 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU
1001
1002 /* These parameters are calculated in Driver,
1003 * based on display timing and Sink capabilities.
1004 * If VBLANK region is too small and Sink takes a long time
1005 * to set up RFB, it may take an extra frame to enter PSR state.
1006 */
1007 bool psr_frame_capture_indication_req;
1008 unsigned int psr_sdp_transmit_line_num_deadline;
1009 uint8_t force_ffu_mode;
1010 unsigned int psr_power_opt;
1011};
1012
1013enum replay_coasting_vtotal_type {
1014 PR_COASTING_TYPE_NOM = 0,
1015 PR_COASTING_TYPE_STATIC,
1016 PR_COASTING_TYPE_FULL_SCREEN_VIDEO,
1017 PR_COASTING_TYPE_TEST_HARNESS,
1018 PR_COASTING_TYPE_NUM,
1019};
1020
1021enum replay_link_off_frame_count_level {
1022 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0,
1023 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2,
1024 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6,
1025};
1026
1027/*
1028 * This is general Interface for Replay to
1029 * set an 32 bit variable to dmub
1030 * The Message_type indicates which variable
1031 * passed to DMUB.
1032 */
1033enum replay_FW_Message_type {
1034 Replay_Msg_Not_Support = -1,
1035 Replay_Set_Timing_Sync_Supported,
1036 Replay_Set_Residency_Frameupdate_Timer,
1037 Replay_Set_Pseudo_VTotal,
1038};
1039
1040union replay_error_status {
1041 struct {
1042 unsigned char STATE_TRANSITION_ERROR :1;
1043 unsigned char LINK_CRC_ERROR :1;
1044 unsigned char DESYNC_ERROR :1;
1045 unsigned char RESERVED :5;
1046 } bits;
1047 unsigned char raw;
1048};
1049
1050struct replay_config {
1051 /* Replay feature is supported */
1052 bool replay_supported;
1053 /* Power opt flags that are supported */
1054 unsigned int replay_power_opt_supported;
1055 /* SMU optimization is supported */
1056 bool replay_smu_opt_supported;
1057 /* Replay enablement option */
1058 unsigned int replay_enable_option;
1059 /* Replay debug flags */
1060 uint32_t debug_flags;
1061 /* Replay sync is supported */
1062 bool replay_timing_sync_supported;
1063 /* Replay Disable desync error check. */
1064 bool force_disable_desync_error_check;
1065 /* Replay Received Desync Error HPD. */
1066 bool received_desync_error_hpd;
1067 /* Replay feature is supported long vblank */
1068 bool replay_support_fast_resync_in_ultra_sleep_mode;
1069 /* Replay error status */
1070 union replay_error_status replay_error_status;
1071};
1072
1073/* Replay feature flags*/
1074struct replay_settings {
1075 /* Replay configuration */
1076 struct replay_config config;
1077 /* Replay feature is ready for activating */
1078 bool replay_feature_enabled;
1079 /* Replay is currently active */
1080 bool replay_allow_active;
1081 /* Replay is currently active */
1082 bool replay_allow_long_vblank;
1083 /* Power opt flags that are activated currently */
1084 unsigned int replay_power_opt_active;
1085 /* SMU optimization is enabled */
1086 bool replay_smu_opt_enable;
1087 /* Current Coasting vtotal */
1088 uint32_t coasting_vtotal;
1089 /* Coasting vtotal table */
1090 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
1091 /* Maximum link off frame count */
1092 enum replay_link_off_frame_count_level link_off_frame_count_level;
1093 /* Replay pseudo vtotal for abm + ips on full screen video which can improve ips residency */
1094 uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal;
1095 /* Replay last pseudo vtotal set to DMUB */
1096 uint16_t last_pseudo_vtotal;
1097};
1098
1099/* To split out "global" and "per-panel" config settings.
1100 * Add a struct dc_panel_config under dc_link
1101 */
1102struct dc_panel_config {
1103 /* extra panel power sequence parameters */
1104 struct pps {
1105 unsigned int extra_t3_ms;
1106 unsigned int extra_t7_ms;
1107 unsigned int extra_delay_backlight_off;
1108 unsigned int extra_post_t7_ms;
1109 unsigned int extra_pre_t11_ms;
1110 unsigned int extra_t12_ms;
1111 unsigned int extra_post_OUI_ms;
1112 } pps;
1113 /* nit brightness */
1114 struct nits_brightness {
1115 unsigned int peak; /* nits */
1116 unsigned int max_avg; /* nits */
1117 unsigned int min; /* 1/10000 nits */
1118 unsigned int max_nonboost_brightness_millinits;
1119 unsigned int min_brightness_millinits;
1120 } nits_brightness;
1121 /* PSR */
1122 struct psr {
1123 bool disable_psr;
1124 bool disallow_psrsu;
1125 bool disallow_replay;
1126 bool rc_disable;
1127 bool rc_allow_static_screen;
1128 bool rc_allow_fullscreen_VPB;
1129 unsigned int replay_enable_option;
1130 } psr;
1131 /* ABM */
1132 struct varib {
1133 unsigned int varibright_feature_enable;
1134 unsigned int def_varibright_level;
1135 unsigned int abm_config_setting;
1136 } varib;
1137 /* edp DSC */
1138 struct dsc {
1139 bool disable_dsc_edp;
1140 unsigned int force_dsc_edp_policy;
1141 } dsc;
1142 /* eDP ILR */
1143 struct ilr {
1144 bool optimize_edp_link_rate; /* eDP ILR */
1145 } ilr;
1146};
1147
1148#define MAX_SINKS_PER_LINK 4
1149
1150/*
1151 * USB4 DPIA BW ALLOCATION STRUCTS
1152 */
1153struct dc_dpia_bw_alloc {
1154 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks
1155 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already
1156 int link_max_bw; // The Max BW that link can require/support
1157 int allocated_bw; // The Actual Allocated BW for this DPIA
1158 int estimated_bw; // The estimated available BW for this DPIA
1159 int bw_granularity; // BW Granularity
1160 int dp_overhead; // DP overhead in dp tunneling
1161 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
1162 bool response_ready; // Response ready from the CM side
1163 uint8_t nrd_max_lane_count; // Non-reduced max lane count
1164 uint8_t nrd_max_link_rate; // Non-reduced max link rate
1165};
1166
1167enum dc_hpd_enable_select {
1168 HPD_EN_FOR_ALL_EDP = 0,
1169 HPD_EN_FOR_PRIMARY_EDP_ONLY,
1170 HPD_EN_FOR_SECONDARY_EDP_ONLY,
1171};
1172
1173enum mall_stream_type {
1174 SUBVP_NONE, // subvp not in use
1175 SUBVP_MAIN, // subvp in use, this stream is main stream
1176 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
1177};
1178#endif /* DC_TYPES_H_ */
1179

source code of linux/drivers/gpu/drm/amd/display/dc/dc_types.h