| 1 | /* |
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| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | #ifndef __DCE_HWSEQ_H__ |
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| 26 | #define __DCE_HWSEQ_H__ |
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| 27 | |
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| 28 | #include "dc_types.h" |
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| 29 | |
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| 30 | #define HWSEQ_DCEF_REG_LIST_DCE8() \ |
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| 31 | .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ |
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| 32 | .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ |
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| 33 | .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ |
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| 34 | .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ |
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| 35 | .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ |
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| 36 | .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL |
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| 37 | |
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| 38 | #define HWSEQ_DCEF_REG_LIST() \ |
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| 39 | SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ |
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| 40 | SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ |
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| 41 | SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ |
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| 42 | SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ |
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| 43 | SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ |
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| 44 | SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ |
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| 45 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) |
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| 46 | |
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| 47 | #define HWSEQ_BLND_REG_LIST() \ |
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| 48 | SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ |
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| 49 | SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ |
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| 50 | SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ |
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| 51 | SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ |
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| 52 | SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ |
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| 53 | SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ |
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| 54 | SRII(BLND_CONTROL, BLND, 0), \ |
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| 55 | SRII(BLND_CONTROL, BLND, 1), \ |
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| 56 | SRII(BLND_CONTROL, BLND, 2), \ |
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| 57 | SRII(BLND_CONTROL, BLND, 3), \ |
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| 58 | SRII(BLND_CONTROL, BLND, 4), \ |
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| 59 | SRII(BLND_CONTROL, BLND, 5) |
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| 60 | |
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| 61 | #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ |
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| 62 | SRII(PIXEL_RATE_CNTL, blk, inst), \ |
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| 63 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) |
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| 64 | |
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| 65 | #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ |
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| 66 | SRII(PIXEL_RATE_CNTL, blk, 0), \ |
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| 67 | SRII(PIXEL_RATE_CNTL, blk, 1), \ |
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| 68 | SRII(PIXEL_RATE_CNTL, blk, 2), \ |
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| 69 | SRII(PIXEL_RATE_CNTL, blk, 3), \ |
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| 70 | SRII(PIXEL_RATE_CNTL, blk, 4), \ |
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| 71 | SRII(PIXEL_RATE_CNTL, blk, 5) |
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| 72 | |
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| 73 | #define HWSEQ_PIXEL_RATE_REG_LIST_201(blk) \ |
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| 74 | SRII(PIXEL_RATE_CNTL, blk, 0), \ |
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| 75 | SRII(PIXEL_RATE_CNTL, blk, 1) |
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| 76 | |
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| 77 | #define HWSEQ_PHYPLL_REG_LIST(blk) \ |
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| 78 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ |
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| 79 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ |
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| 80 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ |
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| 81 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ |
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| 82 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ |
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| 83 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) |
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| 84 | |
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| 85 | #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ |
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| 86 | SRII(PIXEL_RATE_CNTL, blk, 0), \ |
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| 87 | SRII(PIXEL_RATE_CNTL, blk, 1),\ |
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| 88 | SRII(PIXEL_RATE_CNTL, blk, 2),\ |
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| 89 | SRII(PIXEL_RATE_CNTL, blk, 3), \ |
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| 90 | SRII(PIXEL_RATE_CNTL, blk, 4), \ |
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| 91 | SRII(PIXEL_RATE_CNTL, blk, 5) |
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| 92 | |
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| 93 | #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ |
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| 94 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ |
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| 95 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ |
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| 96 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ |
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| 97 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ |
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| 98 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ |
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| 99 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) |
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| 100 | |
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| 101 | #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \ |
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| 102 | SRII(PIXEL_RATE_CNTL, blk, 0), \ |
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| 103 | SRII(PIXEL_RATE_CNTL, blk, 1),\ |
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| 104 | SRII(PIXEL_RATE_CNTL, blk, 2),\ |
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| 105 | SRII(PIXEL_RATE_CNTL, blk, 3), \ |
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| 106 | SRII(PIXEL_RATE_CNTL, blk, 4) |
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| 107 | |
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| 108 | #define HWSEQ_PHYPLL_REG_LIST_302(blk) \ |
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| 109 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ |
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| 110 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ |
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| 111 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ |
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| 112 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ |
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| 113 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4) |
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| 114 | |
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| 115 | #define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \ |
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| 116 | SRII(PIXEL_RATE_CNTL, blk, 0), \ |
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| 117 | SRII(PIXEL_RATE_CNTL, blk, 1) |
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| 118 | |
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| 119 | #define HWSEQ_PHYPLL_REG_LIST_303(blk) \ |
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| 120 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ |
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| 121 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) |
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| 122 | |
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| 123 | |
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| 124 | #define HWSEQ_PHYPLL_REG_LIST_201(blk) \ |
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| 125 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ |
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| 126 | SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1) |
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| 127 | |
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| 128 | #define HWSEQ_DCE11_REG_LIST_BASE() \ |
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| 129 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ |
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| 130 | SR(DCFEV_CLOCK_CONTROL), \ |
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| 131 | SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ |
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| 132 | SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ |
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| 133 | SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ |
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| 134 | SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ |
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| 135 | SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ |
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| 136 | SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ |
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| 137 | SRII(BLND_CONTROL, BLND, 0),\ |
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| 138 | SRII(BLND_CONTROL, BLND, 1),\ |
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| 139 | SR(BLNDV_CONTROL),\ |
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| 140 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC) |
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| 141 | |
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| 142 | #if defined(CONFIG_DRM_AMD_DC_SI) |
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| 143 | #define HWSEQ_DCE6_REG_LIST() \ |
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| 144 | HWSEQ_DCEF_REG_LIST_DCE8(), \ |
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| 145 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC) |
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| 146 | #endif |
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| 147 | |
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| 148 | #define HWSEQ_DCE8_REG_LIST() \ |
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| 149 | HWSEQ_DCEF_REG_LIST_DCE8(), \ |
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| 150 | HWSEQ_BLND_REG_LIST(), \ |
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| 151 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC) |
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| 152 | |
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| 153 | #define HWSEQ_DCE10_REG_LIST() \ |
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| 154 | HWSEQ_DCEF_REG_LIST(), \ |
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| 155 | HWSEQ_BLND_REG_LIST(), \ |
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| 156 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC) |
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| 157 | |
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| 158 | #define HWSEQ_ST_REG_LIST() \ |
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| 159 | HWSEQ_DCE11_REG_LIST_BASE(), \ |
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| 160 | .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ |
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| 161 | .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ |
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| 162 | .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ |
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| 163 | .BLND_CONTROL[2] = mmBLNDV_CONTROL |
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| 164 | |
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| 165 | #define HWSEQ_CZ_REG_LIST() \ |
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| 166 | HWSEQ_DCE11_REG_LIST_BASE(), \ |
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| 167 | SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ |
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| 168 | SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ |
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| 169 | SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ |
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| 170 | SRII(BLND_CONTROL, BLND, 2), \ |
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| 171 | .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ |
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| 172 | .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ |
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| 173 | .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ |
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| 174 | .BLND_CONTROL[3] = mmBLNDV_CONTROL |
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| 175 | |
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| 176 | #define HWSEQ_DCE120_REG_LIST() \ |
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| 177 | HWSEQ_DCE10_REG_LIST(), \ |
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| 178 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ |
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| 179 | HWSEQ_PHYPLL_REG_LIST(CRTC), \ |
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| 180 | SR(DCHUB_FB_LOCATION),\ |
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| 181 | SR(DCHUB_AGP_BASE),\ |
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| 182 | SR(DCHUB_AGP_BOT),\ |
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| 183 | SR(DCHUB_AGP_TOP) |
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| 184 | |
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| 185 | #define HWSEQ_VG20_REG_LIST() \ |
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| 186 | HWSEQ_DCE120_REG_LIST(),\ |
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| 187 | MMHUB_SR(MC_VM_XGMI_LFB_CNTL) |
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| 188 | |
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| 189 | #define HWSEQ_DCE112_REG_LIST() \ |
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| 190 | HWSEQ_DCE10_REG_LIST(), \ |
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| 191 | HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ |
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| 192 | HWSEQ_PHYPLL_REG_LIST(CRTC) |
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| 193 | |
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| 194 | #define HWSEQ_DCN_REG_LIST()\ |
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| 195 | SR(REFCLK_CNTL), \ |
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| 196 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
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| 197 | SR(DIO_MEM_PWR_CTRL), \ |
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| 198 | SR(DCCG_GATE_DISABLE_CNTL), \ |
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| 199 | SR(DCCG_GATE_DISABLE_CNTL2), \ |
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| 200 | SR(DCFCLK_CNTL),\ |
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| 201 | SR(DCFCLK_CNTL), \ |
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| 202 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) |
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| 203 | |
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| 204 | |
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| 205 | #define MMHUB_DCN_REG_LIST()\ |
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| 206 | /* todo: get these from GVM instead of reading registers ourselves */\ |
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| 207 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ |
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| 208 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ |
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| 209 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ |
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| 210 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ |
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| 211 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ |
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| 212 | MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ |
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| 213 | MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ |
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| 214 | MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ |
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| 215 | MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ |
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| 216 | MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ |
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| 217 | MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ |
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| 218 | MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) |
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| 219 | |
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| 220 | |
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| 221 | #define HWSEQ_DCN1_REG_LIST()\ |
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| 222 | HWSEQ_DCN_REG_LIST(), \ |
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| 223 | MMHUB_DCN_REG_LIST(), \ |
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| 224 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ |
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| 225 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ |
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| 226 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ |
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| 227 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ |
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| 228 | SR(DCHUBBUB_SDPIF_FB_BASE),\ |
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| 229 | SR(DCHUBBUB_SDPIF_FB_OFFSET),\ |
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| 230 | SR(DCHUBBUB_SDPIF_AGP_BASE),\ |
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| 231 | SR(DCHUBBUB_SDPIF_AGP_BOT),\ |
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| 232 | SR(DCHUBBUB_SDPIF_AGP_TOP),\ |
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| 233 | SR(DOMAIN0_PG_CONFIG), \ |
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| 234 | SR(DOMAIN1_PG_CONFIG), \ |
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| 235 | SR(DOMAIN2_PG_CONFIG), \ |
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| 236 | SR(DOMAIN3_PG_CONFIG), \ |
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| 237 | SR(DOMAIN4_PG_CONFIG), \ |
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| 238 | SR(DOMAIN5_PG_CONFIG), \ |
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| 239 | SR(DOMAIN6_PG_CONFIG), \ |
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| 240 | SR(DOMAIN7_PG_CONFIG), \ |
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| 241 | SR(DOMAIN0_PG_STATUS), \ |
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| 242 | SR(DOMAIN1_PG_STATUS), \ |
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| 243 | SR(DOMAIN2_PG_STATUS), \ |
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| 244 | SR(DOMAIN3_PG_STATUS), \ |
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| 245 | SR(DOMAIN4_PG_STATUS), \ |
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| 246 | SR(DOMAIN5_PG_STATUS), \ |
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| 247 | SR(DOMAIN6_PG_STATUS), \ |
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| 248 | SR(DOMAIN7_PG_STATUS), \ |
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| 249 | SR(D1VGA_CONTROL), \ |
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| 250 | SR(D2VGA_CONTROL), \ |
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| 251 | SR(D3VGA_CONTROL), \ |
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| 252 | SR(D4VGA_CONTROL), \ |
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| 253 | SR(VGA_TEST_CONTROL), \ |
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| 254 | SR(DC_IP_REQUEST_CNTL) |
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| 255 | |
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| 256 | #define HWSEQ_DCN2_REG_LIST()\ |
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| 257 | HWSEQ_DCN_REG_LIST(), \ |
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| 258 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ |
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| 259 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ |
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| 260 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ |
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| 261 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ |
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| 262 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ |
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| 263 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ |
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| 264 | SR(MICROSECOND_TIME_BASE_DIV), \ |
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| 265 | SR(MILLISECOND_TIME_BASE_DIV), \ |
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| 266 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
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| 267 | SR(RBBMIF_TIMEOUT_DIS), \ |
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| 268 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
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| 269 | SR(DCHUBBUB_CRC_CTRL), \ |
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| 270 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
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| 271 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
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| 272 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
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| 273 | SR(MPC_CRC_CTRL), \ |
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| 274 | SR(MPC_CRC_RESULT_GB), \ |
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| 275 | SR(MPC_CRC_RESULT_C), \ |
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| 276 | SR(MPC_CRC_RESULT_AR), \ |
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| 277 | SR(DOMAIN0_PG_CONFIG), \ |
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| 278 | SR(DOMAIN1_PG_CONFIG), \ |
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| 279 | SR(DOMAIN2_PG_CONFIG), \ |
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| 280 | SR(DOMAIN3_PG_CONFIG), \ |
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| 281 | SR(DOMAIN4_PG_CONFIG), \ |
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| 282 | SR(DOMAIN5_PG_CONFIG), \ |
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| 283 | SR(DOMAIN6_PG_CONFIG), \ |
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| 284 | SR(DOMAIN7_PG_CONFIG), \ |
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| 285 | SR(DOMAIN8_PG_CONFIG), \ |
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| 286 | SR(DOMAIN9_PG_CONFIG), \ |
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| 287 | /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ |
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| 288 | /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ |
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| 289 | SR(DOMAIN16_PG_CONFIG), \ |
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| 290 | SR(DOMAIN17_PG_CONFIG), \ |
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| 291 | SR(DOMAIN18_PG_CONFIG), \ |
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| 292 | SR(DOMAIN19_PG_CONFIG), \ |
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| 293 | SR(DOMAIN20_PG_CONFIG), \ |
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| 294 | SR(DOMAIN21_PG_CONFIG), \ |
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| 295 | SR(DOMAIN0_PG_STATUS), \ |
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| 296 | SR(DOMAIN1_PG_STATUS), \ |
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| 297 | SR(DOMAIN2_PG_STATUS), \ |
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| 298 | SR(DOMAIN3_PG_STATUS), \ |
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| 299 | SR(DOMAIN4_PG_STATUS), \ |
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| 300 | SR(DOMAIN5_PG_STATUS), \ |
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| 301 | SR(DOMAIN6_PG_STATUS), \ |
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| 302 | SR(DOMAIN7_PG_STATUS), \ |
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| 303 | SR(DOMAIN8_PG_STATUS), \ |
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| 304 | SR(DOMAIN9_PG_STATUS), \ |
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| 305 | SR(DOMAIN10_PG_STATUS), \ |
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| 306 | SR(DOMAIN11_PG_STATUS), \ |
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| 307 | SR(DOMAIN16_PG_STATUS), \ |
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| 308 | SR(DOMAIN17_PG_STATUS), \ |
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| 309 | SR(DOMAIN18_PG_STATUS), \ |
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| 310 | SR(DOMAIN19_PG_STATUS), \ |
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| 311 | SR(DOMAIN20_PG_STATUS), \ |
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| 312 | SR(DOMAIN21_PG_STATUS), \ |
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| 313 | SR(D1VGA_CONTROL), \ |
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| 314 | SR(D2VGA_CONTROL), \ |
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| 315 | SR(D3VGA_CONTROL), \ |
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| 316 | SR(D4VGA_CONTROL), \ |
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| 317 | SR(D5VGA_CONTROL), \ |
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| 318 | SR(D6VGA_CONTROL), \ |
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| 319 | SR(DC_IP_REQUEST_CNTL) |
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| 320 | |
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| 321 | #define HWSEQ_DCN21_REG_LIST()\ |
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| 322 | HWSEQ_DCN_REG_LIST(), \ |
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| 323 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ |
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| 324 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ |
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| 325 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ |
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| 326 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ |
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| 327 | MMHUB_DCN_REG_LIST(), \ |
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| 328 | SR(MICROSECOND_TIME_BASE_DIV), \ |
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| 329 | SR(MILLISECOND_TIME_BASE_DIV), \ |
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| 330 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
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| 331 | SR(RBBMIF_TIMEOUT_DIS), \ |
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| 332 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
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| 333 | SR(DCHUBBUB_CRC_CTRL), \ |
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| 334 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
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| 335 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
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| 336 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
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| 337 | SR(MPC_CRC_CTRL), \ |
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| 338 | SR(MPC_CRC_RESULT_GB), \ |
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| 339 | SR(MPC_CRC_RESULT_C), \ |
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| 340 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 341 | SR(DOMAIN0_PG_CONFIG), \ |
|---|
| 342 | SR(DOMAIN1_PG_CONFIG), \ |
|---|
| 343 | SR(DOMAIN2_PG_CONFIG), \ |
|---|
| 344 | SR(DOMAIN3_PG_CONFIG), \ |
|---|
| 345 | SR(DOMAIN4_PG_CONFIG), \ |
|---|
| 346 | SR(DOMAIN5_PG_CONFIG), \ |
|---|
| 347 | SR(DOMAIN6_PG_CONFIG), \ |
|---|
| 348 | SR(DOMAIN7_PG_CONFIG), \ |
|---|
| 349 | SR(DOMAIN16_PG_CONFIG), \ |
|---|
| 350 | SR(DOMAIN17_PG_CONFIG), \ |
|---|
| 351 | SR(DOMAIN18_PG_CONFIG), \ |
|---|
| 352 | SR(DOMAIN0_PG_STATUS), \ |
|---|
| 353 | SR(DOMAIN1_PG_STATUS), \ |
|---|
| 354 | SR(DOMAIN2_PG_STATUS), \ |
|---|
| 355 | SR(DOMAIN3_PG_STATUS), \ |
|---|
| 356 | SR(DOMAIN4_PG_STATUS), \ |
|---|
| 357 | SR(DOMAIN5_PG_STATUS), \ |
|---|
| 358 | SR(DOMAIN6_PG_STATUS), \ |
|---|
| 359 | SR(DOMAIN7_PG_STATUS), \ |
|---|
| 360 | SR(DOMAIN16_PG_STATUS), \ |
|---|
| 361 | SR(DOMAIN17_PG_STATUS), \ |
|---|
| 362 | SR(DOMAIN18_PG_STATUS), \ |
|---|
| 363 | SR(D1VGA_CONTROL), \ |
|---|
| 364 | SR(D2VGA_CONTROL), \ |
|---|
| 365 | SR(D3VGA_CONTROL), \ |
|---|
| 366 | SR(D4VGA_CONTROL), \ |
|---|
| 367 | SR(D5VGA_CONTROL), \ |
|---|
| 368 | SR(D6VGA_CONTROL), \ |
|---|
| 369 | SR(DC_IP_REQUEST_CNTL) |
|---|
| 370 | |
|---|
| 371 | #define HWSEQ_DCN201_REG_LIST()\ |
|---|
| 372 | HWSEQ_DCN_REG_LIST(), \ |
|---|
| 373 | HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \ |
|---|
| 374 | HWSEQ_PHYPLL_REG_LIST_201(OTG), \ |
|---|
| 375 | SR(MICROSECOND_TIME_BASE_DIV), \ |
|---|
| 376 | SR(MILLISECOND_TIME_BASE_DIV), \ |
|---|
| 377 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
|---|
| 378 | SR(RBBMIF_TIMEOUT_DIS), \ |
|---|
| 379 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
|---|
| 380 | SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 381 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
|---|
| 382 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
|---|
| 383 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
|---|
| 384 | SR(MPC_CRC_CTRL), \ |
|---|
| 385 | SR(MPC_CRC_RESULT_GB), \ |
|---|
| 386 | SR(MPC_CRC_RESULT_C), \ |
|---|
| 387 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 388 | SR(AZALIA_AUDIO_DTO), \ |
|---|
| 389 | SR(AZALIA_CONTROLLER_CLOCK_GATING), \ |
|---|
| 390 | MMHUB_SR(MC_VM_FB_LOCATION_BASE), \ |
|---|
| 391 | MMHUB_SR(MC_VM_FB_LOCATION_TOP), \ |
|---|
| 392 | MMHUB_SR(MC_VM_FB_OFFSET) |
|---|
| 393 | |
|---|
| 394 | #define HWSEQ_DCN30_REG_LIST()\ |
|---|
| 395 | HWSEQ_DCN2_REG_LIST(),\ |
|---|
| 396 | HWSEQ_DCN_REG_LIST(), \ |
|---|
| 397 | HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ |
|---|
| 398 | HWSEQ_PHYPLL_REG_LIST_3(OTG), \ |
|---|
| 399 | SR(MICROSECOND_TIME_BASE_DIV), \ |
|---|
| 400 | SR(MILLISECOND_TIME_BASE_DIV), \ |
|---|
| 401 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
|---|
| 402 | SR(RBBMIF_TIMEOUT_DIS), \ |
|---|
| 403 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
|---|
| 404 | SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 405 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
|---|
| 406 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
|---|
| 407 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
|---|
| 408 | SR(MPC_CRC_CTRL), \ |
|---|
| 409 | SR(MPC_CRC_RESULT_GB), \ |
|---|
| 410 | SR(MPC_CRC_RESULT_C), \ |
|---|
| 411 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 412 | SR(AZALIA_AUDIO_DTO), \ |
|---|
| 413 | SR(AZALIA_CONTROLLER_CLOCK_GATING), \ |
|---|
| 414 | SR(HPO_TOP_CLOCK_CONTROL), \ |
|---|
| 415 | SR(ODM_MEM_PWR_CTRL3), \ |
|---|
| 416 | SR(DMU_MEM_PWR_CNTL), \ |
|---|
| 417 | SR(MMHUBBUB_MEM_PWR_CNTL) |
|---|
| 418 | |
|---|
| 419 | #define HWSEQ_DCN301_REG_LIST()\ |
|---|
| 420 | SR(REFCLK_CNTL), \ |
|---|
| 421 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
|---|
| 422 | SR(DIO_MEM_PWR_CTRL), \ |
|---|
| 423 | SR(DCCG_GATE_DISABLE_CNTL), \ |
|---|
| 424 | SR(DCCG_GATE_DISABLE_CNTL2), \ |
|---|
| 425 | SR(DCFCLK_CNTL),\ |
|---|
| 426 | SR(DCFCLK_CNTL), \ |
|---|
| 427 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ |
|---|
| 428 | SRII(PIXEL_RATE_CNTL, OTG, 0), \ |
|---|
| 429 | SRII(PIXEL_RATE_CNTL, OTG, 1),\ |
|---|
| 430 | SRII(PIXEL_RATE_CNTL, OTG, 2),\ |
|---|
| 431 | SRII(PIXEL_RATE_CNTL, OTG, 3),\ |
|---|
| 432 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ |
|---|
| 433 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ |
|---|
| 434 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ |
|---|
| 435 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ |
|---|
| 436 | SR(MICROSECOND_TIME_BASE_DIV), \ |
|---|
| 437 | SR(MILLISECOND_TIME_BASE_DIV), \ |
|---|
| 438 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
|---|
| 439 | SR(RBBMIF_TIMEOUT_DIS), \ |
|---|
| 440 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
|---|
| 441 | SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 442 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
|---|
| 443 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
|---|
| 444 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
|---|
| 445 | SR(MPC_CRC_CTRL), \ |
|---|
| 446 | SR(MPC_CRC_RESULT_GB), \ |
|---|
| 447 | SR(MPC_CRC_RESULT_C), \ |
|---|
| 448 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 449 | SR(DOMAIN0_PG_CONFIG), \ |
|---|
| 450 | SR(DOMAIN1_PG_CONFIG), \ |
|---|
| 451 | SR(DOMAIN2_PG_CONFIG), \ |
|---|
| 452 | SR(DOMAIN3_PG_CONFIG), \ |
|---|
| 453 | SR(DOMAIN4_PG_CONFIG), \ |
|---|
| 454 | SR(DOMAIN5_PG_CONFIG), \ |
|---|
| 455 | SR(DOMAIN6_PG_CONFIG), \ |
|---|
| 456 | SR(DOMAIN7_PG_CONFIG), \ |
|---|
| 457 | SR(DOMAIN16_PG_CONFIG), \ |
|---|
| 458 | SR(DOMAIN17_PG_CONFIG), \ |
|---|
| 459 | SR(DOMAIN18_PG_CONFIG), \ |
|---|
| 460 | SR(DOMAIN0_PG_STATUS), \ |
|---|
| 461 | SR(DOMAIN1_PG_STATUS), \ |
|---|
| 462 | SR(DOMAIN2_PG_STATUS), \ |
|---|
| 463 | SR(DOMAIN3_PG_STATUS), \ |
|---|
| 464 | SR(DOMAIN4_PG_STATUS), \ |
|---|
| 465 | SR(DOMAIN5_PG_STATUS), \ |
|---|
| 466 | SR(DOMAIN6_PG_STATUS), \ |
|---|
| 467 | SR(DOMAIN7_PG_STATUS), \ |
|---|
| 468 | SR(DOMAIN16_PG_STATUS), \ |
|---|
| 469 | SR(DOMAIN17_PG_STATUS), \ |
|---|
| 470 | SR(DOMAIN18_PG_STATUS), \ |
|---|
| 471 | SR(D1VGA_CONTROL), \ |
|---|
| 472 | SR(D2VGA_CONTROL), \ |
|---|
| 473 | SR(D3VGA_CONTROL), \ |
|---|
| 474 | SR(D4VGA_CONTROL), \ |
|---|
| 475 | SR(D5VGA_CONTROL), \ |
|---|
| 476 | SR(D6VGA_CONTROL), \ |
|---|
| 477 | SR(DC_IP_REQUEST_CNTL), \ |
|---|
| 478 | SR(AZALIA_AUDIO_DTO), \ |
|---|
| 479 | SR(AZALIA_CONTROLLER_CLOCK_GATING) |
|---|
| 480 | |
|---|
| 481 | #define HWSEQ_DCN302_REG_LIST()\ |
|---|
| 482 | HWSEQ_DCN_REG_LIST(), \ |
|---|
| 483 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ |
|---|
| 484 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ |
|---|
| 485 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ |
|---|
| 486 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ |
|---|
| 487 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ |
|---|
| 488 | SR(MICROSECOND_TIME_BASE_DIV), \ |
|---|
| 489 | SR(MILLISECOND_TIME_BASE_DIV), \ |
|---|
| 490 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
|---|
| 491 | SR(RBBMIF_TIMEOUT_DIS), \ |
|---|
| 492 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
|---|
| 493 | SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 494 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
|---|
| 495 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
|---|
| 496 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
|---|
| 497 | SR(MPC_CRC_CTRL), \ |
|---|
| 498 | SR(MPC_CRC_RESULT_GB), \ |
|---|
| 499 | SR(MPC_CRC_RESULT_C), \ |
|---|
| 500 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 501 | SR(DOMAIN0_PG_CONFIG), \ |
|---|
| 502 | SR(DOMAIN1_PG_CONFIG), \ |
|---|
| 503 | SR(DOMAIN2_PG_CONFIG), \ |
|---|
| 504 | SR(DOMAIN3_PG_CONFIG), \ |
|---|
| 505 | SR(DOMAIN4_PG_CONFIG), \ |
|---|
| 506 | SR(DOMAIN5_PG_CONFIG), \ |
|---|
| 507 | SR(DOMAIN6_PG_CONFIG), \ |
|---|
| 508 | SR(DOMAIN7_PG_CONFIG), \ |
|---|
| 509 | SR(DOMAIN8_PG_CONFIG), \ |
|---|
| 510 | SR(DOMAIN9_PG_CONFIG), \ |
|---|
| 511 | SR(DOMAIN16_PG_CONFIG), \ |
|---|
| 512 | SR(DOMAIN17_PG_CONFIG), \ |
|---|
| 513 | SR(DOMAIN18_PG_CONFIG), \ |
|---|
| 514 | SR(DOMAIN19_PG_CONFIG), \ |
|---|
| 515 | SR(DOMAIN20_PG_CONFIG), \ |
|---|
| 516 | SR(DOMAIN0_PG_STATUS), \ |
|---|
| 517 | SR(DOMAIN1_PG_STATUS), \ |
|---|
| 518 | SR(DOMAIN2_PG_STATUS), \ |
|---|
| 519 | SR(DOMAIN3_PG_STATUS), \ |
|---|
| 520 | SR(DOMAIN4_PG_STATUS), \ |
|---|
| 521 | SR(DOMAIN5_PG_STATUS), \ |
|---|
| 522 | SR(DOMAIN6_PG_STATUS), \ |
|---|
| 523 | SR(DOMAIN7_PG_STATUS), \ |
|---|
| 524 | SR(DOMAIN8_PG_STATUS), \ |
|---|
| 525 | SR(DOMAIN9_PG_STATUS), \ |
|---|
| 526 | SR(DOMAIN16_PG_STATUS), \ |
|---|
| 527 | SR(DOMAIN17_PG_STATUS), \ |
|---|
| 528 | SR(DOMAIN18_PG_STATUS), \ |
|---|
| 529 | SR(DOMAIN19_PG_STATUS), \ |
|---|
| 530 | SR(DOMAIN20_PG_STATUS), \ |
|---|
| 531 | SR(D1VGA_CONTROL), \ |
|---|
| 532 | SR(D2VGA_CONTROL), \ |
|---|
| 533 | SR(D3VGA_CONTROL), \ |
|---|
| 534 | SR(D4VGA_CONTROL), \ |
|---|
| 535 | SR(D5VGA_CONTROL), \ |
|---|
| 536 | SR(D6VGA_CONTROL), \ |
|---|
| 537 | SR(DC_IP_REQUEST_CNTL), \ |
|---|
| 538 | HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \ |
|---|
| 539 | HWSEQ_PHYPLL_REG_LIST_302(OTG), \ |
|---|
| 540 | SR(AZALIA_AUDIO_DTO), \ |
|---|
| 541 | SR(AZALIA_CONTROLLER_CLOCK_GATING), \ |
|---|
| 542 | SR(HPO_TOP_CLOCK_CONTROL) |
|---|
| 543 | |
|---|
| 544 | #define HWSEQ_DCN303_REG_LIST() \ |
|---|
| 545 | HWSEQ_DCN_REG_LIST(), \ |
|---|
| 546 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ |
|---|
| 547 | HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ |
|---|
| 548 | SR(MICROSECOND_TIME_BASE_DIV), \ |
|---|
| 549 | SR(MILLISECOND_TIME_BASE_DIV), \ |
|---|
| 550 | SR(DISPCLK_FREQ_CHANGE_CNTL), \ |
|---|
| 551 | SR(RBBMIF_TIMEOUT_DIS), \ |
|---|
| 552 | SR(RBBMIF_TIMEOUT_DIS_2), \ |
|---|
| 553 | SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 554 | SR(DPP_TOP0_DPP_CRC_CTRL), \ |
|---|
| 555 | SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ |
|---|
| 556 | SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ |
|---|
| 557 | SR(MPC_CRC_CTRL), \ |
|---|
| 558 | SR(MPC_CRC_RESULT_GB), \ |
|---|
| 559 | SR(MPC_CRC_RESULT_C), \ |
|---|
| 560 | SR(MPC_CRC_RESULT_AR), \ |
|---|
| 561 | SR(D1VGA_CONTROL), \ |
|---|
| 562 | SR(D2VGA_CONTROL), \ |
|---|
| 563 | SR(D3VGA_CONTROL), \ |
|---|
| 564 | SR(D4VGA_CONTROL), \ |
|---|
| 565 | SR(D5VGA_CONTROL), \ |
|---|
| 566 | SR(D6VGA_CONTROL), \ |
|---|
| 567 | HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \ |
|---|
| 568 | HWSEQ_PHYPLL_REG_LIST_303(OTG), \ |
|---|
| 569 | SR(AZALIA_AUDIO_DTO), \ |
|---|
| 570 | SR(AZALIA_CONTROLLER_CLOCK_GATING), \ |
|---|
| 571 | SR(HPO_TOP_CLOCK_CONTROL) |
|---|
| 572 | |
|---|
| 573 | struct dce_hwseq_registers { |
|---|
| 574 | uint32_t DCFE_CLOCK_CONTROL[6]; |
|---|
| 575 | uint32_t DCFEV_CLOCK_CONTROL; |
|---|
| 576 | uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; |
|---|
| 577 | uint32_t BLND_V_UPDATE_LOCK[6]; |
|---|
| 578 | uint32_t BLND_CONTROL[6]; |
|---|
| 579 | uint32_t BLNDV_CONTROL; |
|---|
| 580 | uint32_t CRTC_H_BLANK_START_END[6]; |
|---|
| 581 | uint32_t PIXEL_RATE_CNTL[6]; |
|---|
| 582 | uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; |
|---|
| 583 | /*DCHUB*/ |
|---|
| 584 | uint32_t DCHUB_FB_LOCATION; |
|---|
| 585 | uint32_t DCHUB_AGP_BASE; |
|---|
| 586 | uint32_t DCHUB_AGP_BOT; |
|---|
| 587 | uint32_t DCHUB_AGP_TOP; |
|---|
| 588 | |
|---|
| 589 | uint32_t REFCLK_CNTL; |
|---|
| 590 | |
|---|
| 591 | uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; |
|---|
| 592 | uint32_t DCHUBBUB_SDPIF_FB_BASE; |
|---|
| 593 | uint32_t DCHUBBUB_SDPIF_FB_OFFSET; |
|---|
| 594 | uint32_t DCHUBBUB_SDPIF_AGP_BASE; |
|---|
| 595 | uint32_t DCHUBBUB_SDPIF_AGP_BOT; |
|---|
| 596 | uint32_t DCHUBBUB_SDPIF_AGP_TOP; |
|---|
| 597 | uint32_t DC_IP_REQUEST_CNTL; |
|---|
| 598 | uint32_t DOMAIN0_PG_CONFIG; |
|---|
| 599 | uint32_t DOMAIN1_PG_CONFIG; |
|---|
| 600 | uint32_t DOMAIN2_PG_CONFIG; |
|---|
| 601 | uint32_t DOMAIN3_PG_CONFIG; |
|---|
| 602 | uint32_t DOMAIN4_PG_CONFIG; |
|---|
| 603 | uint32_t DOMAIN5_PG_CONFIG; |
|---|
| 604 | uint32_t DOMAIN6_PG_CONFIG; |
|---|
| 605 | uint32_t DOMAIN7_PG_CONFIG; |
|---|
| 606 | uint32_t DOMAIN8_PG_CONFIG; |
|---|
| 607 | uint32_t DOMAIN9_PG_CONFIG; |
|---|
| 608 | uint32_t DOMAIN10_PG_CONFIG; |
|---|
| 609 | uint32_t DOMAIN11_PG_CONFIG; |
|---|
| 610 | uint32_t DOMAIN16_PG_CONFIG; |
|---|
| 611 | uint32_t DOMAIN17_PG_CONFIG; |
|---|
| 612 | uint32_t DOMAIN18_PG_CONFIG; |
|---|
| 613 | uint32_t DOMAIN19_PG_CONFIG; |
|---|
| 614 | uint32_t DOMAIN20_PG_CONFIG; |
|---|
| 615 | uint32_t DOMAIN21_PG_CONFIG; |
|---|
| 616 | uint32_t DOMAIN0_PG_STATUS; |
|---|
| 617 | uint32_t DOMAIN1_PG_STATUS; |
|---|
| 618 | uint32_t DOMAIN2_PG_STATUS; |
|---|
| 619 | uint32_t DOMAIN3_PG_STATUS; |
|---|
| 620 | uint32_t DOMAIN4_PG_STATUS; |
|---|
| 621 | uint32_t DOMAIN5_PG_STATUS; |
|---|
| 622 | uint32_t DOMAIN6_PG_STATUS; |
|---|
| 623 | uint32_t DOMAIN7_PG_STATUS; |
|---|
| 624 | uint32_t DOMAIN8_PG_STATUS; |
|---|
| 625 | uint32_t DOMAIN9_PG_STATUS; |
|---|
| 626 | uint32_t DOMAIN10_PG_STATUS; |
|---|
| 627 | uint32_t DOMAIN11_PG_STATUS; |
|---|
| 628 | uint32_t DOMAIN16_PG_STATUS; |
|---|
| 629 | uint32_t DOMAIN17_PG_STATUS; |
|---|
| 630 | uint32_t DOMAIN18_PG_STATUS; |
|---|
| 631 | uint32_t DOMAIN19_PG_STATUS; |
|---|
| 632 | uint32_t DOMAIN20_PG_STATUS; |
|---|
| 633 | uint32_t DOMAIN21_PG_STATUS; |
|---|
| 634 | uint32_t DIO_MEM_PWR_CTRL; |
|---|
| 635 | uint32_t DCCG_GATE_DISABLE_CNTL; |
|---|
| 636 | uint32_t DCCG_GATE_DISABLE_CNTL2; |
|---|
| 637 | uint32_t DCFCLK_CNTL; |
|---|
| 638 | uint32_t MICROSECOND_TIME_BASE_DIV; |
|---|
| 639 | uint32_t MILLISECOND_TIME_BASE_DIV; |
|---|
| 640 | uint32_t DISPCLK_FREQ_CHANGE_CNTL; |
|---|
| 641 | uint32_t RBBMIF_TIMEOUT_DIS; |
|---|
| 642 | uint32_t RBBMIF_TIMEOUT_DIS_2; |
|---|
| 643 | uint32_t DCHUBBUB_CRC_CTRL; |
|---|
| 644 | uint32_t DPP_TOP0_DPP_CRC_CTRL; |
|---|
| 645 | uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; |
|---|
| 646 | uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; |
|---|
| 647 | uint32_t MPC_CRC_CTRL; |
|---|
| 648 | uint32_t MPC_CRC_RESULT_GB; |
|---|
| 649 | uint32_t MPC_CRC_RESULT_C; |
|---|
| 650 | uint32_t MPC_CRC_RESULT_AR; |
|---|
| 651 | uint32_t D1VGA_CONTROL; |
|---|
| 652 | uint32_t D2VGA_CONTROL; |
|---|
| 653 | uint32_t D3VGA_CONTROL; |
|---|
| 654 | uint32_t D4VGA_CONTROL; |
|---|
| 655 | uint32_t D5VGA_CONTROL; |
|---|
| 656 | uint32_t D6VGA_CONTROL; |
|---|
| 657 | uint32_t VGA_TEST_CONTROL; |
|---|
| 658 | /* MMHUB registers. read only. temporary hack */ |
|---|
| 659 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; |
|---|
| 660 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; |
|---|
| 661 | uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; |
|---|
| 662 | uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; |
|---|
| 663 | uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; |
|---|
| 664 | uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; |
|---|
| 665 | uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; |
|---|
| 666 | uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; |
|---|
| 667 | uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; |
|---|
| 668 | uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; |
|---|
| 669 | uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; |
|---|
| 670 | uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; |
|---|
| 671 | uint32_t MC_VM_XGMI_LFB_CNTL; |
|---|
| 672 | uint32_t AZALIA_AUDIO_DTO; |
|---|
| 673 | uint32_t AZALIA_CONTROLLER_CLOCK_GATING; |
|---|
| 674 | /* MMHUB VM */ |
|---|
| 675 | uint32_t MC_VM_FB_LOCATION_BASE; |
|---|
| 676 | uint32_t MC_VM_FB_LOCATION_TOP; |
|---|
| 677 | uint32_t MC_VM_FB_OFFSET; |
|---|
| 678 | uint32_t MMHUBBUB_MEM_PWR_CNTL; |
|---|
| 679 | uint32_t HPO_TOP_CLOCK_CONTROL; |
|---|
| 680 | uint32_t ODM_MEM_PWR_CTRL3; |
|---|
| 681 | uint32_t DMU_MEM_PWR_CNTL; |
|---|
| 682 | uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; |
|---|
| 683 | uint32_t HPO_TOP_HW_CONTROL; |
|---|
| 684 | uint32_t DMU_CLK_CNTL; |
|---|
| 685 | uint32_t DCCG_GATE_DISABLE_CNTL4; |
|---|
| 686 | uint32_t DCCG_GATE_DISABLE_CNTL5; |
|---|
| 687 | }; |
|---|
| 688 | /* set field name */ |
|---|
| 689 | #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ |
|---|
| 690 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix |
|---|
| 691 | |
|---|
| 692 | #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ |
|---|
| 693 | .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix |
|---|
| 694 | |
|---|
| 695 | |
|---|
| 696 | #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ |
|---|
| 697 | HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ |
|---|
| 698 | SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) |
|---|
| 699 | |
|---|
| 700 | #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ |
|---|
| 701 | HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 702 | HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 703 | HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 704 | HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 705 | HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ |
|---|
| 706 | HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ |
|---|
| 707 | HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ |
|---|
| 708 | HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ |
|---|
| 709 | HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) |
|---|
| 710 | |
|---|
| 711 | #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ |
|---|
| 712 | HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ |
|---|
| 713 | HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) |
|---|
| 714 | |
|---|
| 715 | #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ |
|---|
| 716 | HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ |
|---|
| 717 | HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) |
|---|
| 718 | |
|---|
| 719 | #if defined(CONFIG_DRM_AMD_DC_SI) |
|---|
| 720 | #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\ |
|---|
| 721 | .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ |
|---|
| 722 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) |
|---|
| 723 | #endif |
|---|
| 724 | |
|---|
| 725 | #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ |
|---|
| 726 | .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ |
|---|
| 727 | HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 728 | HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 729 | HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ |
|---|
| 730 | HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ |
|---|
| 731 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) |
|---|
| 732 | |
|---|
| 733 | #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ |
|---|
| 734 | HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ |
|---|
| 735 | HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ |
|---|
| 736 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) |
|---|
| 737 | |
|---|
| 738 | #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ |
|---|
| 739 | HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ |
|---|
| 740 | SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ |
|---|
| 741 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) |
|---|
| 742 | |
|---|
| 743 | #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ |
|---|
| 744 | HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ |
|---|
| 745 | HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) |
|---|
| 746 | |
|---|
| 747 | #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ |
|---|
| 748 | SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ |
|---|
| 749 | SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ |
|---|
| 750 | SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ |
|---|
| 751 | SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ |
|---|
| 752 | SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) |
|---|
| 753 | |
|---|
| 754 | #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ |
|---|
| 755 | HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ |
|---|
| 756 | HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ |
|---|
| 757 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ |
|---|
| 758 | HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ |
|---|
| 759 | HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) |
|---|
| 760 | |
|---|
| 761 | #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ |
|---|
| 762 | HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ |
|---|
| 763 | HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ |
|---|
| 764 | HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) |
|---|
| 765 | |
|---|
| 766 | #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ |
|---|
| 767 | HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ |
|---|
| 768 | HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ |
|---|
| 769 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ |
|---|
| 770 | HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ |
|---|
| 771 | HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) |
|---|
| 772 | |
|---|
| 773 | #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ |
|---|
| 774 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 775 | HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ |
|---|
| 776 | HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ |
|---|
| 777 | HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ |
|---|
| 778 | HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ |
|---|
| 779 | HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ |
|---|
| 780 | HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ |
|---|
| 781 | /* todo: get these from GVM instead of reading registers ourselves */\ |
|---|
| 782 | HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ |
|---|
| 783 | HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ |
|---|
| 784 | HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ |
|---|
| 785 | HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ |
|---|
| 786 | HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ |
|---|
| 787 | HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ |
|---|
| 788 | HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ |
|---|
| 789 | HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ |
|---|
| 790 | HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ |
|---|
| 791 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ |
|---|
| 792 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ |
|---|
| 793 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ |
|---|
| 794 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ |
|---|
| 795 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ |
|---|
| 796 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ |
|---|
| 797 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ |
|---|
| 798 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ |
|---|
| 799 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ |
|---|
| 800 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ |
|---|
| 801 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ |
|---|
| 802 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ |
|---|
| 803 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ |
|---|
| 804 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ |
|---|
| 805 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ |
|---|
| 806 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ |
|---|
| 807 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 808 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 809 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 810 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 811 | HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 812 | HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 813 | HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 814 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 815 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ |
|---|
| 816 | HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ |
|---|
| 817 | HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ |
|---|
| 818 | HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ |
|---|
| 819 | HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ |
|---|
| 820 | HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ |
|---|
| 821 | HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) |
|---|
| 822 | |
|---|
| 823 | #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ |
|---|
| 824 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 825 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 826 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ |
|---|
| 827 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ |
|---|
| 828 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ |
|---|
| 829 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ |
|---|
| 830 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ |
|---|
| 831 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ |
|---|
| 832 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ |
|---|
| 833 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ |
|---|
| 834 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ |
|---|
| 835 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ |
|---|
| 836 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ |
|---|
| 837 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ |
|---|
| 838 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ |
|---|
| 839 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ |
|---|
| 840 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ |
|---|
| 841 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ |
|---|
| 842 | HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ |
|---|
| 843 | HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ |
|---|
| 844 | HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ |
|---|
| 845 | HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ |
|---|
| 846 | HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ |
|---|
| 847 | HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ |
|---|
| 848 | HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ |
|---|
| 849 | HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ |
|---|
| 850 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ |
|---|
| 851 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ |
|---|
| 852 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ |
|---|
| 853 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ |
|---|
| 854 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ |
|---|
| 855 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ |
|---|
| 856 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ |
|---|
| 857 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ |
|---|
| 858 | HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ |
|---|
| 859 | HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ |
|---|
| 860 | HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ |
|---|
| 861 | HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ |
|---|
| 862 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 863 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 864 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 865 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 866 | HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 867 | HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 868 | HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 869 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 870 | HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 871 | HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 872 | HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 873 | HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 874 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 875 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 876 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 877 | HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 878 | HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 879 | HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 880 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) |
|---|
| 881 | |
|---|
| 882 | #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ |
|---|
| 883 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 884 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 885 | HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ |
|---|
| 886 | HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ |
|---|
| 887 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ |
|---|
| 888 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ |
|---|
| 889 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ |
|---|
| 890 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ |
|---|
| 891 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ |
|---|
| 892 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ |
|---|
| 893 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ |
|---|
| 894 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ |
|---|
| 895 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ |
|---|
| 896 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ |
|---|
| 897 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ |
|---|
| 898 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ |
|---|
| 899 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ |
|---|
| 900 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ |
|---|
| 901 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ |
|---|
| 902 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ |
|---|
| 903 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ |
|---|
| 904 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ |
|---|
| 905 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ |
|---|
| 906 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ |
|---|
| 907 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ |
|---|
| 908 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ |
|---|
| 909 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 910 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 911 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 912 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 913 | HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 914 | HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 915 | HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 916 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 917 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 918 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 919 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 920 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) |
|---|
| 921 | |
|---|
| 922 | #define HWSEQ_DCN201_MASK_SH_LIST(mask_sh)\ |
|---|
| 923 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 924 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 925 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) |
|---|
| 926 | |
|---|
| 927 | #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ |
|---|
| 928 | HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ |
|---|
| 929 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ |
|---|
| 930 | HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh), \ |
|---|
| 931 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ |
|---|
| 932 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ |
|---|
| 933 | HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ |
|---|
| 934 | HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh) |
|---|
| 935 | |
|---|
| 936 | #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\ |
|---|
| 937 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 938 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 939 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ |
|---|
| 940 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ |
|---|
| 941 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ |
|---|
| 942 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ |
|---|
| 943 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ |
|---|
| 944 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ |
|---|
| 945 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ |
|---|
| 946 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ |
|---|
| 947 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ |
|---|
| 948 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ |
|---|
| 949 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ |
|---|
| 950 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ |
|---|
| 951 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ |
|---|
| 952 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ |
|---|
| 953 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ |
|---|
| 954 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ |
|---|
| 955 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ |
|---|
| 956 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ |
|---|
| 957 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ |
|---|
| 958 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ |
|---|
| 959 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ |
|---|
| 960 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ |
|---|
| 961 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 962 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 963 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 964 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 965 | HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 966 | HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 967 | HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 968 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 969 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 970 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 971 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 972 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ |
|---|
| 973 | HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\ |
|---|
| 974 | HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\ |
|---|
| 975 | HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\ |
|---|
| 976 | HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\ |
|---|
| 977 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) |
|---|
| 978 | |
|---|
| 979 | #define HWSEQ_DCN302_MASK_SH_LIST(mask_sh)\ |
|---|
| 980 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 981 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 982 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ |
|---|
| 983 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ |
|---|
| 984 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ |
|---|
| 985 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ |
|---|
| 986 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ |
|---|
| 987 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ |
|---|
| 988 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ |
|---|
| 989 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ |
|---|
| 990 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ |
|---|
| 991 | HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ |
|---|
| 992 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ |
|---|
| 993 | HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ |
|---|
| 994 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ |
|---|
| 995 | HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ |
|---|
| 996 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ |
|---|
| 997 | HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ |
|---|
| 998 | HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ |
|---|
| 999 | HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ |
|---|
| 1000 | HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ |
|---|
| 1001 | HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ |
|---|
| 1002 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ |
|---|
| 1003 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ |
|---|
| 1004 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ |
|---|
| 1005 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ |
|---|
| 1006 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ |
|---|
| 1007 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ |
|---|
| 1008 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ |
|---|
| 1009 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ |
|---|
| 1010 | HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ |
|---|
| 1011 | HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ |
|---|
| 1012 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1013 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1014 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1015 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1016 | HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1017 | HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1018 | HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1019 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1020 | HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1021 | HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1022 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1023 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1024 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1025 | HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1026 | HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ |
|---|
| 1027 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ |
|---|
| 1028 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ |
|---|
| 1029 | HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh) |
|---|
| 1030 | |
|---|
| 1031 | #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \ |
|---|
| 1032 | HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ |
|---|
| 1033 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ |
|---|
| 1034 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ |
|---|
| 1035 | HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh) |
|---|
| 1036 | |
|---|
| 1037 | #define HWSEQ_REG_FIELD_LIST(type) \ |
|---|
| 1038 | type DCFE_CLOCK_ENABLE; \ |
|---|
| 1039 | type DCFEV_CLOCK_ENABLE; \ |
|---|
| 1040 | type DC_MEM_GLOBAL_PWR_REQ_DIS; \ |
|---|
| 1041 | type BLND_DCP_GRPH_V_UPDATE_LOCK; \ |
|---|
| 1042 | type BLND_SCL_V_UPDATE_LOCK; \ |
|---|
| 1043 | type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ |
|---|
| 1044 | type BLND_BLND_V_UPDATE_LOCK; \ |
|---|
| 1045 | type BLND_V_UPDATE_LOCK_MODE; \ |
|---|
| 1046 | type BLND_FEEDTHROUGH_EN; \ |
|---|
| 1047 | type BLND_ALPHA_MODE; \ |
|---|
| 1048 | type BLND_MODE; \ |
|---|
| 1049 | type BLND_MULTIPLIED_MODE; \ |
|---|
| 1050 | type DP_DTO0_ENABLE; \ |
|---|
| 1051 | type PIXEL_RATE_SOURCE; \ |
|---|
| 1052 | type PHYPLL_PIXEL_RATE_SOURCE; \ |
|---|
| 1053 | type PIXEL_RATE_PLL_SOURCE; \ |
|---|
| 1054 | /* todo: get these from GVM instead of reading registers ourselves */\ |
|---|
| 1055 | type PAGE_DIRECTORY_ENTRY_HI32;\ |
|---|
| 1056 | type PAGE_DIRECTORY_ENTRY_LO32;\ |
|---|
| 1057 | type LOGICAL_PAGE_NUMBER_HI4;\ |
|---|
| 1058 | type LOGICAL_PAGE_NUMBER_LO32;\ |
|---|
| 1059 | type PHYSICAL_PAGE_ADDR_HI4;\ |
|---|
| 1060 | type PHYSICAL_PAGE_ADDR_LO32;\ |
|---|
| 1061 | type PHYSICAL_PAGE_NUMBER_MSB;\ |
|---|
| 1062 | type PHYSICAL_PAGE_NUMBER_LSB;\ |
|---|
| 1063 | type LOGICAL_ADDR; \ |
|---|
| 1064 | type PF_LFB_REGION;\ |
|---|
| 1065 | type PF_MAX_REGION;\ |
|---|
| 1066 | type ENABLE_L1_TLB;\ |
|---|
| 1067 | type SYSTEM_ACCESS_MODE; |
|---|
| 1068 | |
|---|
| 1069 | #define HWSEQ_DCN_REG_FIELD_LIST(type) \ |
|---|
| 1070 | type HUBP_VTG_SEL; \ |
|---|
| 1071 | type HUBP_CLOCK_ENABLE; \ |
|---|
| 1072 | type DPP_CLOCK_ENABLE; \ |
|---|
| 1073 | type SDPIF_FB_BASE;\ |
|---|
| 1074 | type SDPIF_FB_OFFSET;\ |
|---|
| 1075 | type SDPIF_AGP_BASE;\ |
|---|
| 1076 | type SDPIF_AGP_BOT;\ |
|---|
| 1077 | type SDPIF_AGP_TOP;\ |
|---|
| 1078 | type FB_TOP;\ |
|---|
| 1079 | type FB_BASE;\ |
|---|
| 1080 | type FB_OFFSET;\ |
|---|
| 1081 | type AGP_BASE;\ |
|---|
| 1082 | type AGP_BOT;\ |
|---|
| 1083 | type AGP_TOP;\ |
|---|
| 1084 | type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ |
|---|
| 1085 | type OPP_PIPE_CLOCK_EN;\ |
|---|
| 1086 | type IP_REQUEST_EN; \ |
|---|
| 1087 | type DOMAIN0_POWER_FORCEON; \ |
|---|
| 1088 | type DOMAIN0_POWER_GATE; \ |
|---|
| 1089 | type DOMAIN1_POWER_FORCEON; \ |
|---|
| 1090 | type DOMAIN1_POWER_GATE; \ |
|---|
| 1091 | type DOMAIN2_POWER_FORCEON; \ |
|---|
| 1092 | type DOMAIN2_POWER_GATE; \ |
|---|
| 1093 | type DOMAIN3_POWER_FORCEON; \ |
|---|
| 1094 | type DOMAIN3_POWER_GATE; \ |
|---|
| 1095 | type DOMAIN4_POWER_FORCEON; \ |
|---|
| 1096 | type DOMAIN4_POWER_GATE; \ |
|---|
| 1097 | type DOMAIN5_POWER_FORCEON; \ |
|---|
| 1098 | type DOMAIN5_POWER_GATE; \ |
|---|
| 1099 | type DOMAIN6_POWER_FORCEON; \ |
|---|
| 1100 | type DOMAIN6_POWER_GATE; \ |
|---|
| 1101 | type DOMAIN7_POWER_FORCEON; \ |
|---|
| 1102 | type DOMAIN7_POWER_GATE; \ |
|---|
| 1103 | type DOMAIN8_POWER_FORCEON; \ |
|---|
| 1104 | type DOMAIN8_POWER_GATE; \ |
|---|
| 1105 | type DOMAIN9_POWER_FORCEON; \ |
|---|
| 1106 | type DOMAIN9_POWER_GATE; \ |
|---|
| 1107 | type DOMAIN10_POWER_FORCEON; \ |
|---|
| 1108 | type DOMAIN10_POWER_GATE; \ |
|---|
| 1109 | type DOMAIN11_POWER_FORCEON; \ |
|---|
| 1110 | type DOMAIN11_POWER_GATE; \ |
|---|
| 1111 | type DOMAIN16_POWER_FORCEON; \ |
|---|
| 1112 | type DOMAIN16_POWER_GATE; \ |
|---|
| 1113 | type DOMAIN17_POWER_FORCEON; \ |
|---|
| 1114 | type DOMAIN17_POWER_GATE; \ |
|---|
| 1115 | type DOMAIN18_POWER_FORCEON; \ |
|---|
| 1116 | type DOMAIN18_POWER_GATE; \ |
|---|
| 1117 | type DOMAIN19_POWER_FORCEON; \ |
|---|
| 1118 | type DOMAIN19_POWER_GATE; \ |
|---|
| 1119 | type DOMAIN20_POWER_FORCEON; \ |
|---|
| 1120 | type DOMAIN20_POWER_GATE; \ |
|---|
| 1121 | type DOMAIN21_POWER_FORCEON; \ |
|---|
| 1122 | type DOMAIN21_POWER_GATE; \ |
|---|
| 1123 | type DOMAIN0_PGFSM_PWR_STATUS; \ |
|---|
| 1124 | type DOMAIN1_PGFSM_PWR_STATUS; \ |
|---|
| 1125 | type DOMAIN2_PGFSM_PWR_STATUS; \ |
|---|
| 1126 | type DOMAIN3_PGFSM_PWR_STATUS; \ |
|---|
| 1127 | type DOMAIN4_PGFSM_PWR_STATUS; \ |
|---|
| 1128 | type DOMAIN5_PGFSM_PWR_STATUS; \ |
|---|
| 1129 | type DOMAIN6_PGFSM_PWR_STATUS; \ |
|---|
| 1130 | type DOMAIN7_PGFSM_PWR_STATUS; \ |
|---|
| 1131 | type DOMAIN8_PGFSM_PWR_STATUS; \ |
|---|
| 1132 | type DOMAIN9_PGFSM_PWR_STATUS; \ |
|---|
| 1133 | type DOMAIN10_PGFSM_PWR_STATUS; \ |
|---|
| 1134 | type DOMAIN11_PGFSM_PWR_STATUS; \ |
|---|
| 1135 | type DOMAIN16_PGFSM_PWR_STATUS; \ |
|---|
| 1136 | type DOMAIN17_PGFSM_PWR_STATUS; \ |
|---|
| 1137 | type DOMAIN18_PGFSM_PWR_STATUS; \ |
|---|
| 1138 | type DOMAIN19_PGFSM_PWR_STATUS; \ |
|---|
| 1139 | type DOMAIN20_PGFSM_PWR_STATUS; \ |
|---|
| 1140 | type DOMAIN21_PGFSM_PWR_STATUS; \ |
|---|
| 1141 | type DCFCLK_GATE_DIS; \ |
|---|
| 1142 | type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ |
|---|
| 1143 | type VGA_TEST_ENABLE; \ |
|---|
| 1144 | type VGA_TEST_RENDER_START; \ |
|---|
| 1145 | type D1VGA_MODE_ENABLE; \ |
|---|
| 1146 | type D2VGA_MODE_ENABLE; \ |
|---|
| 1147 | type D3VGA_MODE_ENABLE; \ |
|---|
| 1148 | type D4VGA_MODE_ENABLE; \ |
|---|
| 1149 | type AZALIA_AUDIO_DTO_MODULE; \ |
|---|
| 1150 | type ODM_MEM_UNASSIGNED_PWR_MODE; \ |
|---|
| 1151 | type ODM_MEM_VBLANK_PWR_MODE; \ |
|---|
| 1152 | type DMCU_ERAM_MEM_PWR_FORCE; \ |
|---|
| 1153 | type VGA_MEM_PWR_FORCE; |
|---|
| 1154 | |
|---|
| 1155 | #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ |
|---|
| 1156 | type HPO_HDMISTREAMCLK_GATE_DIS; |
|---|
| 1157 | |
|---|
| 1158 | #define HWSEQ_DCN301_REG_FIELD_LIST(type) \ |
|---|
| 1159 | type PANEL_BLON;\ |
|---|
| 1160 | type PANEL_DIGON;\ |
|---|
| 1161 | type PANEL_DIGON_OVRD;\ |
|---|
| 1162 | type PANEL_PWRSEQ_TARGET_STATE_R; |
|---|
| 1163 | |
|---|
| 1164 | #define HWSEQ_DCN31_REG_FIELD_LIST(type) \ |
|---|
| 1165 | type DOMAIN_POWER_FORCEON;\ |
|---|
| 1166 | type DOMAIN_POWER_GATE;\ |
|---|
| 1167 | type DOMAIN_PGFSM_PWR_STATUS;\ |
|---|
| 1168 | type HPO_HDMISTREAMCLK_G_GATE_DIS;\ |
|---|
| 1169 | type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\ |
|---|
| 1170 | type I2C_LIGHT_SLEEP_FORCE;\ |
|---|
| 1171 | type HPO_IO_EN; |
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| 1172 | |
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| 1173 | #define HWSEQ_DCN35_REG_FIELD_LIST(type) \ |
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| 1174 | type DISPCLK_R_DMU_GATE_DIS;\ |
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| 1175 | type DISPCLK_G_RBBMIF_GATE_DIS;\ |
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| 1176 | type RBBMIF_FGCG_REP_DIS;\ |
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| 1177 | type IHC_FGCG_REP_DIS;\ |
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| 1178 | type DPREFCLK_ALLOW_DS_CLKSTOP;\ |
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| 1179 | type DISPCLK_ALLOW_DS_CLKSTOP;\ |
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| 1180 | type DPPCLK_ALLOW_DS_CLKSTOP;\ |
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| 1181 | type DTBCLK_ALLOW_DS_CLKSTOP;\ |
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| 1182 | type DCFCLK_ALLOW_DS_CLKSTOP;\ |
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| 1183 | type DPIACLK_ALLOW_DS_CLKSTOP;\ |
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| 1184 | type LONO_FGCG_REP_DIS;\ |
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| 1185 | type LONO_DISPCLK_GATE_DISABLE;\ |
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| 1186 | type LONO_SOCCLK_GATE_DISABLE;\ |
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| 1187 | type LONO_DMCUBCLK_GATE_DISABLE;\ |
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| 1188 | type SYMCLKA_FE_GATE_DISABLE;\ |
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| 1189 | type SYMCLKB_FE_GATE_DISABLE;\ |
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| 1190 | type SYMCLKC_FE_GATE_DISABLE;\ |
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| 1191 | type SYMCLKD_FE_GATE_DISABLE;\ |
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| 1192 | type SYMCLKE_FE_GATE_DISABLE;\ |
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| 1193 | type HDMICHARCLK0_GATE_DISABLE;\ |
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| 1194 | type SYMCLKA_GATE_DISABLE;\ |
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| 1195 | type SYMCLKB_GATE_DISABLE;\ |
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| 1196 | type SYMCLKC_GATE_DISABLE;\ |
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| 1197 | type SYMCLKD_GATE_DISABLE;\ |
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| 1198 | type SYMCLKE_GATE_DISABLE;\ |
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| 1199 | type PHYASYMCLK_ROOT_GATE_DISABLE;\ |
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| 1200 | type PHYBSYMCLK_ROOT_GATE_DISABLE;\ |
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| 1201 | type PHYCSYMCLK_ROOT_GATE_DISABLE;\ |
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| 1202 | type PHYDSYMCLK_ROOT_GATE_DISABLE;\ |
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| 1203 | type PHYESYMCLK_ROOT_GATE_DISABLE;\ |
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| 1204 | type DTBCLK_P0_GATE_DISABLE;\ |
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| 1205 | type DTBCLK_P1_GATE_DISABLE;\ |
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| 1206 | type DTBCLK_P2_GATE_DISABLE;\ |
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| 1207 | type DTBCLK_P3_GATE_DISABLE;\ |
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| 1208 | type DPSTREAMCLK0_GATE_DISABLE;\ |
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| 1209 | type DPSTREAMCLK1_GATE_DISABLE;\ |
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| 1210 | type DPSTREAMCLK2_GATE_DISABLE;\ |
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| 1211 | type DPSTREAMCLK3_GATE_DISABLE;\ |
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| 1212 | type DPIASYMCLK0_GATE_DISABLE;\ |
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| 1213 | type DPIASYMCLK1_GATE_DISABLE;\ |
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| 1214 | type DPIASYMCLK2_GATE_DISABLE;\ |
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| 1215 | type DPIASYMCLK3_GATE_DISABLE; |
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| 1216 | |
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| 1217 | struct dce_hwseq_shift { |
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| 1218 | HWSEQ_REG_FIELD_LIST(uint8_t) |
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| 1219 | HWSEQ_DCN_REG_FIELD_LIST(uint8_t) |
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| 1220 | HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) |
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| 1221 | HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) |
|---|
| 1222 | HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) |
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| 1223 | HWSEQ_DCN35_REG_FIELD_LIST(uint8_t) |
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| 1224 | }; |
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| 1225 | |
|---|
| 1226 | struct dce_hwseq_mask { |
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| 1227 | HWSEQ_REG_FIELD_LIST(uint32_t) |
|---|
| 1228 | HWSEQ_DCN_REG_FIELD_LIST(uint32_t) |
|---|
| 1229 | HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) |
|---|
| 1230 | HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) |
|---|
| 1231 | HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) |
|---|
| 1232 | HWSEQ_DCN35_REG_FIELD_LIST(uint32_t) |
|---|
| 1233 | }; |
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| 1234 | |
|---|
| 1235 | |
|---|
| 1236 | enum blnd_mode { |
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| 1237 | BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ |
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| 1238 | BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ |
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| 1239 | BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ |
|---|
| 1240 | }; |
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| 1241 | |
|---|
| 1242 | struct dce_hwseq; |
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| 1243 | struct pipe_ctx; |
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| 1244 | struct clock_source; |
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| 1245 | |
|---|
| 1246 | void dce_enable_fe_clock(struct dce_hwseq *hwss, |
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| 1247 | unsigned int inst, bool enable); |
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| 1248 | |
|---|
| 1249 | void dce_pipe_control_lock(struct dc *dc, |
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| 1250 | struct pipe_ctx *pipe, |
|---|
| 1251 | bool lock); |
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| 1252 | |
|---|
| 1253 | void dce_set_blender_mode(struct dce_hwseq *hws, |
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| 1254 | unsigned int blnd_inst, enum blnd_mode mode); |
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| 1255 | |
|---|
| 1256 | #if defined(CONFIG_DRM_AMD_DC_SI) |
|---|
| 1257 | void dce60_pipe_control_lock(struct dc *dc, |
|---|
| 1258 | struct pipe_ctx *pipe, |
|---|
| 1259 | bool lock); |
|---|
| 1260 | #endif |
|---|
| 1261 | |
|---|
| 1262 | void dce_clock_gating_power_up(struct dce_hwseq *hws, |
|---|
| 1263 | bool enable); |
|---|
| 1264 | |
|---|
| 1265 | void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, |
|---|
| 1266 | struct clock_source *clk_src, |
|---|
| 1267 | unsigned int tg_inst); |
|---|
| 1268 | |
|---|
| 1269 | bool dce_use_lut(enum surface_pixel_format format); |
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| 1270 | #endif /*__DCE_HWSEQ_H__*/ |
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| 1271 | |
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