1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27
28#include "include/logger_interface.h"
29
30#include "../dce110/irq_service_dce110.h"
31
32#include "dcn/dcn_2_1_0_offset.h"
33#include "dcn/dcn_2_1_0_sh_mask.h"
34#include "renoir_ip_offset.h"
35
36
37#include "irq_service_dcn21.h"
38
39#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
40
41static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_service,
42 uint32_t src_id,
43 uint32_t ext_id)
44{
45 switch (src_id) {
46 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
47 return DC_IRQ_SOURCE_VBLANK1;
48 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK2;
50 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK3;
52 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
53 return DC_IRQ_SOURCE_VBLANK4;
54 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK5;
56 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK6;
58 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
59 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
60 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
61 return DC_IRQ_SOURCE_DC1_VLINE0;
62 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
63 return DC_IRQ_SOURCE_DC2_VLINE0;
64 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
65 return DC_IRQ_SOURCE_DC3_VLINE0;
66 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
67 return DC_IRQ_SOURCE_DC4_VLINE0;
68 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
69 return DC_IRQ_SOURCE_DC5_VLINE0;
70 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
71 return DC_IRQ_SOURCE_DC6_VLINE0;
72 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
73 return DC_IRQ_SOURCE_PFLIP1;
74 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
75 return DC_IRQ_SOURCE_PFLIP2;
76 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
77 return DC_IRQ_SOURCE_PFLIP3;
78 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
79 return DC_IRQ_SOURCE_PFLIP4;
80 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
81 return DC_IRQ_SOURCE_PFLIP5;
82 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
83 return DC_IRQ_SOURCE_PFLIP6;
84 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
85 return DC_IRQ_SOURCE_VUPDATE1;
86 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
87 return DC_IRQ_SOURCE_VUPDATE2;
88 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
89 return DC_IRQ_SOURCE_VUPDATE3;
90 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
91 return DC_IRQ_SOURCE_VUPDATE4;
92 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
93 return DC_IRQ_SOURCE_VUPDATE5;
94 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
95 return DC_IRQ_SOURCE_VUPDATE6;
96
97 case DCN_1_0__SRCID__DC_HPD1_INT:
98 /* generic src_id for all HPD and HPDRX interrupts */
99 switch (ext_id) {
100 case DCN_1_0__CTXID__DC_HPD1_INT:
101 return DC_IRQ_SOURCE_HPD1;
102 case DCN_1_0__CTXID__DC_HPD2_INT:
103 return DC_IRQ_SOURCE_HPD2;
104 case DCN_1_0__CTXID__DC_HPD3_INT:
105 return DC_IRQ_SOURCE_HPD3;
106 case DCN_1_0__CTXID__DC_HPD4_INT:
107 return DC_IRQ_SOURCE_HPD4;
108 case DCN_1_0__CTXID__DC_HPD5_INT:
109 return DC_IRQ_SOURCE_HPD5;
110 case DCN_1_0__CTXID__DC_HPD6_INT:
111 return DC_IRQ_SOURCE_HPD6;
112 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
113 return DC_IRQ_SOURCE_HPD1RX;
114 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
115 return DC_IRQ_SOURCE_HPD2RX;
116 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
117 return DC_IRQ_SOURCE_HPD3RX;
118 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
119 return DC_IRQ_SOURCE_HPD4RX;
120 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
121 return DC_IRQ_SOURCE_HPD5RX;
122 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
123 return DC_IRQ_SOURCE_HPD6RX;
124 default:
125 return DC_IRQ_SOURCE_INVALID;
126 }
127 break;
128
129 default:
130 break;
131 }
132 return DC_IRQ_SOURCE_INVALID;
133}
134
135static bool hpd_ack(
136 struct irq_service *irq_service,
137 const struct irq_source_info *info)
138{
139 uint32_t addr = info->status_reg;
140 uint32_t value = dm_read_reg(irq_service->ctx, addr);
141 uint32_t current_status =
142 get_reg_field_value(
143 value,
144 HPD0_DC_HPD_INT_STATUS,
145 DC_HPD_SENSE_DELAYED);
146
147 dal_irq_service_ack_generic(irq_service, info);
148
149 value = dm_read_reg(irq_service->ctx, info->enable_reg);
150
151 set_reg_field_value(
152 value,
153 current_status ? 0 : 1,
154 HPD0_DC_HPD_INT_CONTROL,
155 DC_HPD_INT_POLARITY);
156
157 dm_write_reg(irq_service->ctx, info->enable_reg, value);
158
159 return true;
160}
161
162static struct irq_source_info_funcs hpd_irq_info_funcs = {
163 .set = NULL,
164 .ack = hpd_ack
165};
166
167static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
168 .set = NULL,
169 .ack = NULL
170};
171
172static struct irq_source_info_funcs pflip_irq_info_funcs = {
173 .set = NULL,
174 .ack = NULL
175};
176
177static struct irq_source_info_funcs vblank_irq_info_funcs = {
178 .set = NULL,
179 .ack = NULL
180};
181
182static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
183 .set = NULL,
184 .ack = NULL
185};
186
187static struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
188 .set = NULL,
189 .ack = NULL
190};
191
192static struct irq_source_info_funcs vline0_irq_info_funcs = {
193 .set = NULL,
194 .ack = NULL
195};
196
197#undef BASE_INNER
198#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
199
200/* compile time expand base address. */
201#define BASE(seg) \
202 BASE_INNER(seg)
203
204
205#define SRI(reg_name, block, id)\
206 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
207 mm ## block ## id ## _ ## reg_name
208
209#define SRI_DMUB(reg_name)\
210 BASE(mm ## reg_name ## _BASE_IDX) + \
211 mm ## reg_name
212
213#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
214 .enable_reg = SRI(reg1, block, reg_num),\
215 .enable_mask = \
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
217 .enable_value = {\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
220 },\
221 .ack_reg = SRI(reg2, block, reg_num),\
222 .ack_mask = \
223 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
224 .ack_value = \
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
226
227#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
228 .enable_reg = SRI_DMUB(reg1),\
229 .enable_mask = \
230 reg1 ## __ ## mask1 ## _MASK,\
231 .enable_value = {\
232 reg1 ## __ ## mask1 ## _MASK,\
233 ~reg1 ## __ ## mask1 ## _MASK \
234 },\
235 .ack_reg = SRI_DMUB(reg2),\
236 .ack_mask = \
237 reg2 ## __ ## mask2 ## _MASK,\
238 .ack_value = \
239 reg2 ## __ ## mask2 ## _MASK \
240
241#define hpd_int_entry(reg_num)\
242 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
243 IRQ_REG_ENTRY(HPD, reg_num,\
244 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
245 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
246 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
247 .funcs = &hpd_irq_info_funcs\
248 }
249
250#define hpd_rx_int_entry(reg_num)\
251 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
252 IRQ_REG_ENTRY(HPD, reg_num,\
253 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
254 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
255 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
256 .funcs = &hpd_rx_irq_info_funcs\
257 }
258#define pflip_int_entry(reg_num)\
259 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
260 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
261 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
262 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
263 .funcs = &pflip_irq_info_funcs\
264 }
265
266/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
267 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
268 */
269#define vupdate_no_lock_int_entry(reg_num)\
270 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
271 IRQ_REG_ENTRY(OTG, reg_num,\
272 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
273 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
274 .funcs = &vupdate_no_lock_irq_info_funcs\
275 }
276
277#define vblank_int_entry(reg_num)\
278 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
279 IRQ_REG_ENTRY(OTG, reg_num,\
280 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
281 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
282 .funcs = &vblank_irq_info_funcs\
283 }
284
285#define vline0_int_entry(reg_num)\
286 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
287 IRQ_REG_ENTRY(OTG, reg_num,\
288 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
289 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
290 .funcs = &vline0_irq_info_funcs\
291 }
292
293#define dmub_outbox_int_entry()\
294 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
295 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
296 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
297 .funcs = &dmub_outbox_irq_info_funcs\
298 }
299
300#define dummy_irq_entry() \
301 {\
302 .funcs = &dummy_irq_info_funcs\
303 }
304
305#define i2c_int_entry(reg_num) \
306 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
307
308#define dp_sink_int_entry(reg_num) \
309 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
310
311#define gpio_pad_int_entry(reg_num) \
312 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
313
314#define dc_underflow_int_entry(reg_num) \
315 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
316
317static struct irq_source_info_funcs dummy_irq_info_funcs = {
318 .set = dal_irq_service_dummy_set,
319 .ack = dal_irq_service_dummy_ack
320};
321
322static const struct irq_source_info
323irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
324 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
325 hpd_int_entry(0),
326 hpd_int_entry(1),
327 hpd_int_entry(2),
328 hpd_int_entry(3),
329 hpd_int_entry(4),
330 hpd_rx_int_entry(0),
331 hpd_rx_int_entry(1),
332 hpd_rx_int_entry(2),
333 hpd_rx_int_entry(3),
334 hpd_rx_int_entry(4),
335 i2c_int_entry(1),
336 i2c_int_entry(2),
337 i2c_int_entry(3),
338 i2c_int_entry(4),
339 i2c_int_entry(5),
340 i2c_int_entry(6),
341 dp_sink_int_entry(1),
342 dp_sink_int_entry(2),
343 dp_sink_int_entry(3),
344 dp_sink_int_entry(4),
345 dp_sink_int_entry(5),
346 dp_sink_int_entry(6),
347 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
348 pflip_int_entry(0),
349 pflip_int_entry(1),
350 pflip_int_entry(2),
351 pflip_int_entry(3),
352 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
353 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
354 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
355 gpio_pad_int_entry(0),
356 gpio_pad_int_entry(1),
357 gpio_pad_int_entry(2),
358 gpio_pad_int_entry(3),
359 gpio_pad_int_entry(4),
360 gpio_pad_int_entry(5),
361 gpio_pad_int_entry(6),
362 gpio_pad_int_entry(7),
363 gpio_pad_int_entry(8),
364 gpio_pad_int_entry(9),
365 gpio_pad_int_entry(10),
366 gpio_pad_int_entry(11),
367 gpio_pad_int_entry(12),
368 gpio_pad_int_entry(13),
369 gpio_pad_int_entry(14),
370 gpio_pad_int_entry(15),
371 gpio_pad_int_entry(16),
372 gpio_pad_int_entry(17),
373 gpio_pad_int_entry(18),
374 gpio_pad_int_entry(19),
375 gpio_pad_int_entry(20),
376 gpio_pad_int_entry(21),
377 gpio_pad_int_entry(22),
378 gpio_pad_int_entry(23),
379 gpio_pad_int_entry(24),
380 gpio_pad_int_entry(25),
381 gpio_pad_int_entry(26),
382 gpio_pad_int_entry(27),
383 gpio_pad_int_entry(28),
384 gpio_pad_int_entry(29),
385 gpio_pad_int_entry(30),
386 dc_underflow_int_entry(1),
387 dc_underflow_int_entry(2),
388 dc_underflow_int_entry(3),
389 dc_underflow_int_entry(4),
390 dc_underflow_int_entry(5),
391 dc_underflow_int_entry(6),
392 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
393 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
394 vupdate_no_lock_int_entry(0),
395 vupdate_no_lock_int_entry(1),
396 vupdate_no_lock_int_entry(2),
397 vupdate_no_lock_int_entry(3),
398 vupdate_no_lock_int_entry(4),
399 vupdate_no_lock_int_entry(5),
400 vblank_int_entry(0),
401 vblank_int_entry(1),
402 vblank_int_entry(2),
403 vblank_int_entry(3),
404 vblank_int_entry(4),
405 vblank_int_entry(5),
406 vline0_int_entry(0),
407 vline0_int_entry(1),
408 vline0_int_entry(2),
409 vline0_int_entry(3),
410 vline0_int_entry(4),
411 vline0_int_entry(5),
412 dmub_outbox_int_entry(),
413};
414
415static const struct irq_service_funcs irq_service_funcs_dcn21 = {
416 .to_dal_irq_source = to_dal_irq_source_dcn21
417};
418
419static void dcn21_irq_construct(
420 struct irq_service *irq_service,
421 struct irq_service_init_data *init_data)
422{
423 dal_irq_service_construct(irq_service, init_data);
424
425 irq_service->info = irq_source_info_dcn21;
426 irq_service->funcs = &irq_service_funcs_dcn21;
427}
428
429struct irq_service *dal_irq_service_dcn21_create(
430 struct irq_service_init_data *init_data)
431{
432 struct irq_service *irq_service = kzalloc(size: sizeof(*irq_service),
433 GFP_KERNEL);
434
435 if (!irq_service)
436 return NULL;
437
438 dcn21_irq_construct(irq_service, init_data);
439 return irq_service;
440}
441

source code of linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c