1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright (C) 2021 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | #include "dm_services.h" |
28 | #include "irq_service_dcn303.h" |
29 | #include "../dce110/irq_service_dce110.h" |
30 | |
31 | #include "sienna_cichlid_ip_offset.h" |
32 | #include "dcn/dcn_3_0_3_offset.h" |
33 | #include "dcn/dcn_3_0_3_sh_mask.h" |
34 | |
35 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
36 | |
37 | static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service, |
38 | uint32_t src_id, |
39 | uint32_t ext_id) |
40 | { |
41 | switch (src_id) { |
42 | case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: |
43 | return DC_IRQ_SOURCE_VBLANK1; |
44 | case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: |
45 | return DC_IRQ_SOURCE_VBLANK2; |
46 | case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: |
47 | return DC_IRQ_SOURCE_DC1_VLINE0; |
48 | case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: |
49 | return DC_IRQ_SOURCE_DC2_VLINE0; |
50 | case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: |
51 | return DC_IRQ_SOURCE_PFLIP1; |
52 | case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: |
53 | return DC_IRQ_SOURCE_PFLIP2; |
54 | case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
55 | return DC_IRQ_SOURCE_VUPDATE1; |
56 | case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
57 | return DC_IRQ_SOURCE_VUPDATE2; |
58 | |
59 | case DCN_1_0__SRCID__DC_HPD1_INT: |
60 | /* generic src_id for all HPD and HPDRX interrupts */ |
61 | switch (ext_id) { |
62 | case DCN_1_0__CTXID__DC_HPD1_INT: |
63 | return DC_IRQ_SOURCE_HPD1; |
64 | case DCN_1_0__CTXID__DC_HPD2_INT: |
65 | return DC_IRQ_SOURCE_HPD2; |
66 | case DCN_1_0__CTXID__DC_HPD1_RX_INT: |
67 | return DC_IRQ_SOURCE_HPD1RX; |
68 | case DCN_1_0__CTXID__DC_HPD2_RX_INT: |
69 | return DC_IRQ_SOURCE_HPD2RX; |
70 | default: |
71 | return DC_IRQ_SOURCE_INVALID; |
72 | } |
73 | break; |
74 | |
75 | default: |
76 | return DC_IRQ_SOURCE_INVALID; |
77 | } |
78 | } |
79 | |
80 | static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info) |
81 | { |
82 | uint32_t addr = info->status_reg; |
83 | uint32_t value = dm_read_reg(irq_service->ctx, addr); |
84 | uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED); |
85 | |
86 | dal_irq_service_ack_generic(irq_service, info); |
87 | |
88 | value = dm_read_reg(irq_service->ctx, info->enable_reg); |
89 | |
90 | set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); |
91 | |
92 | dm_write_reg(irq_service->ctx, info->enable_reg, value); |
93 | |
94 | return true; |
95 | } |
96 | |
97 | static struct irq_source_info_funcs hpd_irq_info_funcs = { |
98 | .set = NULL, |
99 | .ack = hpd_ack |
100 | }; |
101 | |
102 | static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { |
103 | .set = NULL, |
104 | .ack = NULL |
105 | }; |
106 | |
107 | static struct irq_source_info_funcs pflip_irq_info_funcs = { |
108 | .set = NULL, |
109 | .ack = NULL |
110 | }; |
111 | |
112 | static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { |
113 | .set = NULL, |
114 | .ack = NULL |
115 | }; |
116 | |
117 | static struct irq_source_info_funcs vblank_irq_info_funcs = { |
118 | .set = NULL, |
119 | .ack = NULL |
120 | }; |
121 | |
122 | static struct irq_source_info_funcs vline0_irq_info_funcs = { |
123 | .set = NULL, |
124 | .ack = NULL |
125 | }; |
126 | |
127 | #undef BASE_INNER |
128 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg |
129 | |
130 | /* compile time expand base address. */ |
131 | #define BASE(seg) BASE_INNER(seg) |
132 | |
133 | #define SRI(reg_name, block, id)\ |
134 | BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ |
135 | mm ## block ## id ## _ ## reg_name |
136 | |
137 | |
138 | #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ |
139 | .enable_reg = SRI(reg1, block, reg_num),\ |
140 | .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ |
141 | .enable_value = {\ |
142 | block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ |
143 | ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ |
144 | },\ |
145 | .ack_reg = SRI(reg2, block, reg_num),\ |
146 | .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ |
147 | .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ |
148 | |
149 | |
150 | |
151 | #define hpd_int_entry(reg_num)\ |
152 | [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ |
153 | IRQ_REG_ENTRY(HPD, reg_num,\ |
154 | DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ |
155 | DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ |
156 | .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ |
157 | .funcs = &hpd_irq_info_funcs\ |
158 | } |
159 | |
160 | #define hpd_rx_int_entry(reg_num)\ |
161 | [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ |
162 | IRQ_REG_ENTRY(HPD, reg_num,\ |
163 | DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ |
164 | DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ |
165 | .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ |
166 | .funcs = &hpd_rx_irq_info_funcs\ |
167 | } |
168 | #define pflip_int_entry(reg_num)\ |
169 | [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ |
170 | IRQ_REG_ENTRY(HUBPREQ, reg_num,\ |
171 | DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ |
172 | DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ |
173 | .funcs = &pflip_irq_info_funcs\ |
174 | } |
175 | |
176 | /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic |
177 | * of DCE's DC_IRQ_SOURCE_VUPDATEx. |
178 | */ |
179 | #define vupdate_no_lock_int_entry(reg_num)\ |
180 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ |
181 | IRQ_REG_ENTRY(OTG, reg_num,\ |
182 | OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ |
183 | OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ |
184 | .funcs = &vupdate_no_lock_irq_info_funcs\ |
185 | } |
186 | |
187 | #define vblank_int_entry(reg_num)\ |
188 | [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ |
189 | IRQ_REG_ENTRY(OTG, reg_num,\ |
190 | OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ |
191 | OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ |
192 | .funcs = &vblank_irq_info_funcs\ |
193 | } |
194 | |
195 | #define vline0_int_entry(reg_num)\ |
196 | [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ |
197 | IRQ_REG_ENTRY(OTG, reg_num,\ |
198 | OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ |
199 | OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ |
200 | .funcs = &vline0_irq_info_funcs\ |
201 | } |
202 | |
203 | #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs } |
204 | |
205 | #define i2c_int_entry(reg_num) \ |
206 | [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() |
207 | |
208 | #define dp_sink_int_entry(reg_num) \ |
209 | [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() |
210 | |
211 | #define gpio_pad_int_entry(reg_num) \ |
212 | [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() |
213 | |
214 | #define dc_underflow_int_entry(reg_num) \ |
215 | [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() |
216 | |
217 | static struct irq_source_info_funcs dummy_irq_info_funcs = { |
218 | .set = dal_irq_service_dummy_set, |
219 | .ack = dal_irq_service_dummy_ack |
220 | }; |
221 | |
222 | static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = { |
223 | [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), |
224 | hpd_int_entry(0), |
225 | hpd_int_entry(1), |
226 | hpd_rx_int_entry(0), |
227 | hpd_rx_int_entry(1), |
228 | i2c_int_entry(1), |
229 | i2c_int_entry(2), |
230 | dp_sink_int_entry(1), |
231 | dp_sink_int_entry(2), |
232 | [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), |
233 | pflip_int_entry(0), |
234 | pflip_int_entry(1), |
235 | [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), |
236 | gpio_pad_int_entry(0), |
237 | gpio_pad_int_entry(1), |
238 | gpio_pad_int_entry(2), |
239 | gpio_pad_int_entry(3), |
240 | gpio_pad_int_entry(4), |
241 | gpio_pad_int_entry(5), |
242 | gpio_pad_int_entry(6), |
243 | gpio_pad_int_entry(7), |
244 | gpio_pad_int_entry(8), |
245 | gpio_pad_int_entry(9), |
246 | gpio_pad_int_entry(10), |
247 | gpio_pad_int_entry(11), |
248 | gpio_pad_int_entry(12), |
249 | gpio_pad_int_entry(13), |
250 | gpio_pad_int_entry(14), |
251 | gpio_pad_int_entry(15), |
252 | gpio_pad_int_entry(16), |
253 | gpio_pad_int_entry(17), |
254 | gpio_pad_int_entry(18), |
255 | gpio_pad_int_entry(19), |
256 | gpio_pad_int_entry(20), |
257 | gpio_pad_int_entry(21), |
258 | gpio_pad_int_entry(22), |
259 | gpio_pad_int_entry(23), |
260 | gpio_pad_int_entry(24), |
261 | gpio_pad_int_entry(25), |
262 | gpio_pad_int_entry(26), |
263 | gpio_pad_int_entry(27), |
264 | gpio_pad_int_entry(28), |
265 | gpio_pad_int_entry(29), |
266 | gpio_pad_int_entry(30), |
267 | dc_underflow_int_entry(1), |
268 | dc_underflow_int_entry(2), |
269 | [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), |
270 | [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), |
271 | vupdate_no_lock_int_entry(0), |
272 | vupdate_no_lock_int_entry(1), |
273 | vblank_int_entry(0), |
274 | vblank_int_entry(1), |
275 | vline0_int_entry(0), |
276 | vline0_int_entry(1), |
277 | }; |
278 | |
279 | static const struct irq_service_funcs irq_service_funcs_dcn303 = { |
280 | .to_dal_irq_source = to_dal_irq_source_dcn303 |
281 | }; |
282 | |
283 | static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data) |
284 | { |
285 | dal_irq_service_construct(irq_service, init_data); |
286 | |
287 | irq_service->info = irq_source_info_dcn303; |
288 | irq_service->funcs = &irq_service_funcs_dcn303; |
289 | } |
290 | |
291 | struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data) |
292 | { |
293 | struct irq_service *irq_service = kzalloc(size: sizeof(*irq_service), GFP_KERNEL); |
294 | |
295 | if (!irq_service) |
296 | return NULL; |
297 | |
298 | dcn303_irq_construct(irq_service, init_data); |
299 | return irq_service; |
300 | } |
301 | |