1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dm_services.h" |
27 | #include "include/logger_interface.h" |
28 | #include "../dce110/irq_service_dce110.h" |
29 | |
30 | |
31 | #include "dcn/dcn_3_1_5_offset.h" |
32 | #include "dcn/dcn_3_1_5_sh_mask.h" |
33 | |
34 | #include "irq_service_dcn315.h" |
35 | |
36 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
37 | |
38 | #define DCN_BASE__INST0_SEG0 0x00000012 |
39 | #define DCN_BASE__INST0_SEG1 0x000000C0 |
40 | #define DCN_BASE__INST0_SEG2 0x000034C0 |
41 | #define DCN_BASE__INST0_SEG3 0x00009000 |
42 | #define DCN_BASE__INST0_SEG4 0x02403C00 |
43 | #define DCN_BASE__INST0_SEG5 0 |
44 | |
45 | static enum dc_irq_source to_dal_irq_source_dcn315( |
46 | struct irq_service *irq_service, |
47 | uint32_t src_id, |
48 | uint32_t ext_id) |
49 | { |
50 | switch (src_id) { |
51 | case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: |
52 | return DC_IRQ_SOURCE_VBLANK1; |
53 | case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: |
54 | return DC_IRQ_SOURCE_VBLANK2; |
55 | case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: |
56 | return DC_IRQ_SOURCE_VBLANK3; |
57 | case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: |
58 | return DC_IRQ_SOURCE_VBLANK4; |
59 | case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: |
60 | return DC_IRQ_SOURCE_VBLANK5; |
61 | case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: |
62 | return DC_IRQ_SOURCE_VBLANK6; |
63 | case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: |
64 | return DC_IRQ_SOURCE_DC1_VLINE0; |
65 | case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: |
66 | return DC_IRQ_SOURCE_DC2_VLINE0; |
67 | case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: |
68 | return DC_IRQ_SOURCE_DC3_VLINE0; |
69 | case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: |
70 | return DC_IRQ_SOURCE_DC4_VLINE0; |
71 | case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: |
72 | return DC_IRQ_SOURCE_DC5_VLINE0; |
73 | case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: |
74 | return DC_IRQ_SOURCE_DC6_VLINE0; |
75 | case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: |
76 | return DC_IRQ_SOURCE_PFLIP1; |
77 | case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: |
78 | return DC_IRQ_SOURCE_PFLIP2; |
79 | case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: |
80 | return DC_IRQ_SOURCE_PFLIP3; |
81 | case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: |
82 | return DC_IRQ_SOURCE_PFLIP4; |
83 | case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: |
84 | return DC_IRQ_SOURCE_PFLIP5; |
85 | case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: |
86 | return DC_IRQ_SOURCE_PFLIP6; |
87 | case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
88 | return DC_IRQ_SOURCE_VUPDATE1; |
89 | case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
90 | return DC_IRQ_SOURCE_VUPDATE2; |
91 | case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
92 | return DC_IRQ_SOURCE_VUPDATE3; |
93 | case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
94 | return DC_IRQ_SOURCE_VUPDATE4; |
95 | case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
96 | return DC_IRQ_SOURCE_VUPDATE5; |
97 | case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: |
98 | return DC_IRQ_SOURCE_VUPDATE6; |
99 | case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: |
100 | return DC_IRQ_SOURCE_DMCUB_OUTBOX; |
101 | case DCN_1_0__SRCID__DC_HPD1_INT: |
102 | /* generic src_id for all HPD and HPDRX interrupts */ |
103 | switch (ext_id) { |
104 | case DCN_1_0__CTXID__DC_HPD1_INT: |
105 | return DC_IRQ_SOURCE_HPD1; |
106 | case DCN_1_0__CTXID__DC_HPD2_INT: |
107 | return DC_IRQ_SOURCE_HPD2; |
108 | case DCN_1_0__CTXID__DC_HPD3_INT: |
109 | return DC_IRQ_SOURCE_HPD3; |
110 | case DCN_1_0__CTXID__DC_HPD4_INT: |
111 | return DC_IRQ_SOURCE_HPD4; |
112 | case DCN_1_0__CTXID__DC_HPD5_INT: |
113 | return DC_IRQ_SOURCE_HPD5; |
114 | case DCN_1_0__CTXID__DC_HPD6_INT: |
115 | return DC_IRQ_SOURCE_HPD6; |
116 | case DCN_1_0__CTXID__DC_HPD1_RX_INT: |
117 | return DC_IRQ_SOURCE_HPD1RX; |
118 | case DCN_1_0__CTXID__DC_HPD2_RX_INT: |
119 | return DC_IRQ_SOURCE_HPD2RX; |
120 | case DCN_1_0__CTXID__DC_HPD3_RX_INT: |
121 | return DC_IRQ_SOURCE_HPD3RX; |
122 | case DCN_1_0__CTXID__DC_HPD4_RX_INT: |
123 | return DC_IRQ_SOURCE_HPD4RX; |
124 | case DCN_1_0__CTXID__DC_HPD5_RX_INT: |
125 | return DC_IRQ_SOURCE_HPD5RX; |
126 | case DCN_1_0__CTXID__DC_HPD6_RX_INT: |
127 | return DC_IRQ_SOURCE_HPD6RX; |
128 | default: |
129 | return DC_IRQ_SOURCE_INVALID; |
130 | } |
131 | break; |
132 | |
133 | default: |
134 | return DC_IRQ_SOURCE_INVALID; |
135 | } |
136 | } |
137 | |
138 | static bool hpd_ack( |
139 | struct irq_service *irq_service, |
140 | const struct irq_source_info *info) |
141 | { |
142 | uint32_t addr = info->status_reg; |
143 | uint32_t value = dm_read_reg(irq_service->ctx, addr); |
144 | uint32_t current_status = |
145 | get_reg_field_value( |
146 | value, |
147 | HPD0_DC_HPD_INT_STATUS, |
148 | DC_HPD_SENSE_DELAYED); |
149 | |
150 | dal_irq_service_ack_generic(irq_service, info); |
151 | |
152 | value = dm_read_reg(irq_service->ctx, info->enable_reg); |
153 | |
154 | set_reg_field_value( |
155 | value, |
156 | current_status ? 0 : 1, |
157 | HPD0_DC_HPD_INT_CONTROL, |
158 | DC_HPD_INT_POLARITY); |
159 | |
160 | dm_write_reg(irq_service->ctx, info->enable_reg, value); |
161 | |
162 | return true; |
163 | } |
164 | |
165 | static struct irq_source_info_funcs hpd_irq_info_funcs = { |
166 | .set = NULL, |
167 | .ack = hpd_ack |
168 | }; |
169 | |
170 | static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { |
171 | .set = NULL, |
172 | .ack = NULL |
173 | }; |
174 | |
175 | static struct irq_source_info_funcs pflip_irq_info_funcs = { |
176 | .set = NULL, |
177 | .ack = NULL |
178 | }; |
179 | |
180 | static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { |
181 | .set = NULL, |
182 | .ack = NULL |
183 | }; |
184 | |
185 | static struct irq_source_info_funcs vblank_irq_info_funcs = { |
186 | .set = NULL, |
187 | .ack = NULL |
188 | }; |
189 | |
190 | static struct irq_source_info_funcs outbox_irq_info_funcs = { |
191 | .set = NULL, |
192 | .ack = NULL |
193 | }; |
194 | |
195 | static struct irq_source_info_funcs vline0_irq_info_funcs = { |
196 | .set = NULL, |
197 | .ack = NULL |
198 | }; |
199 | |
200 | #undef BASE_INNER |
201 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg |
202 | |
203 | /* compile time expand base address. */ |
204 | #define BASE(seg) \ |
205 | BASE_INNER(seg) |
206 | |
207 | #define SRI(reg_name, block, id)\ |
208 | BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ |
209 | reg ## block ## id ## _ ## reg_name |
210 | |
211 | #define SRI_DMUB(reg_name)\ |
212 | BASE(reg ## reg_name ## _BASE_IDX) + \ |
213 | reg ## reg_name |
214 | |
215 | #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ |
216 | .enable_reg = SRI(reg1, block, reg_num),\ |
217 | .enable_mask = \ |
218 | block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ |
219 | .enable_value = {\ |
220 | block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ |
221 | ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ |
222 | },\ |
223 | .ack_reg = SRI(reg2, block, reg_num),\ |
224 | .ack_mask = \ |
225 | block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ |
226 | .ack_value = \ |
227 | block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ |
228 | |
229 | #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ |
230 | .enable_reg = SRI_DMUB(reg1),\ |
231 | .enable_mask = \ |
232 | reg1 ## __ ## mask1 ## _MASK,\ |
233 | .enable_value = {\ |
234 | reg1 ## __ ## mask1 ## _MASK,\ |
235 | ~reg1 ## __ ## mask1 ## _MASK \ |
236 | },\ |
237 | .ack_reg = SRI_DMUB(reg2),\ |
238 | .ack_mask = \ |
239 | reg2 ## __ ## mask2 ## _MASK,\ |
240 | .ack_value = \ |
241 | reg2 ## __ ## mask2 ## _MASK \ |
242 | |
243 | #define hpd_int_entry(reg_num)\ |
244 | [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ |
245 | IRQ_REG_ENTRY(HPD, reg_num,\ |
246 | DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ |
247 | DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ |
248 | .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ |
249 | .funcs = &hpd_irq_info_funcs\ |
250 | } |
251 | |
252 | #define hpd_rx_int_entry(reg_num)\ |
253 | [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ |
254 | IRQ_REG_ENTRY(HPD, reg_num,\ |
255 | DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ |
256 | DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ |
257 | .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ |
258 | .funcs = &hpd_rx_irq_info_funcs\ |
259 | } |
260 | #define pflip_int_entry(reg_num)\ |
261 | [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ |
262 | IRQ_REG_ENTRY(HUBPREQ, reg_num,\ |
263 | DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ |
264 | DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ |
265 | .funcs = &pflip_irq_info_funcs\ |
266 | } |
267 | |
268 | /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic |
269 | * of DCE's DC_IRQ_SOURCE_VUPDATEx. |
270 | */ |
271 | #define vupdate_no_lock_int_entry(reg_num)\ |
272 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ |
273 | IRQ_REG_ENTRY(OTG, reg_num,\ |
274 | OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ |
275 | OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ |
276 | .funcs = &vupdate_no_lock_irq_info_funcs\ |
277 | } |
278 | |
279 | #define vblank_int_entry(reg_num)\ |
280 | [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ |
281 | IRQ_REG_ENTRY(OTG, reg_num,\ |
282 | OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ |
283 | OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ |
284 | .funcs = &vblank_irq_info_funcs\ |
285 | } |
286 | |
287 | #define vline0_int_entry(reg_num)\ |
288 | [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ |
289 | IRQ_REG_ENTRY(OTG, reg_num,\ |
290 | OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ |
291 | OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ |
292 | .funcs = &vline0_irq_info_funcs\ |
293 | } |
294 | #define dmub_outbox_int_entry()\ |
295 | [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ |
296 | IRQ_REG_ENTRY_DMUB(\ |
297 | DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ |
298 | DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ |
299 | .funcs = &outbox_irq_info_funcs\ |
300 | } |
301 | |
302 | #define dummy_irq_entry() \ |
303 | {\ |
304 | .funcs = &dummy_irq_info_funcs\ |
305 | } |
306 | |
307 | #define i2c_int_entry(reg_num) \ |
308 | [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() |
309 | |
310 | #define dp_sink_int_entry(reg_num) \ |
311 | [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() |
312 | |
313 | #define gpio_pad_int_entry(reg_num) \ |
314 | [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() |
315 | |
316 | #define dc_underflow_int_entry(reg_num) \ |
317 | [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() |
318 | |
319 | static struct irq_source_info_funcs dummy_irq_info_funcs = { |
320 | .set = dal_irq_service_dummy_set, |
321 | .ack = dal_irq_service_dummy_ack |
322 | }; |
323 | |
324 | static const struct irq_source_info |
325 | irq_source_info_dcn315[DAL_IRQ_SOURCES_NUMBER] = { |
326 | [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), |
327 | hpd_int_entry(0), |
328 | hpd_int_entry(1), |
329 | hpd_int_entry(2), |
330 | hpd_int_entry(3), |
331 | hpd_int_entry(4), |
332 | hpd_rx_int_entry(0), |
333 | hpd_rx_int_entry(1), |
334 | hpd_rx_int_entry(2), |
335 | hpd_rx_int_entry(3), |
336 | hpd_rx_int_entry(4), |
337 | i2c_int_entry(1), |
338 | i2c_int_entry(2), |
339 | i2c_int_entry(3), |
340 | i2c_int_entry(4), |
341 | i2c_int_entry(5), |
342 | i2c_int_entry(6), |
343 | dp_sink_int_entry(1), |
344 | dp_sink_int_entry(2), |
345 | dp_sink_int_entry(3), |
346 | dp_sink_int_entry(4), |
347 | dp_sink_int_entry(5), |
348 | dp_sink_int_entry(6), |
349 | [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), |
350 | pflip_int_entry(0), |
351 | pflip_int_entry(1), |
352 | pflip_int_entry(2), |
353 | pflip_int_entry(3), |
354 | [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), |
355 | [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), |
356 | [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), |
357 | gpio_pad_int_entry(0), |
358 | gpio_pad_int_entry(1), |
359 | gpio_pad_int_entry(2), |
360 | gpio_pad_int_entry(3), |
361 | gpio_pad_int_entry(4), |
362 | gpio_pad_int_entry(5), |
363 | gpio_pad_int_entry(6), |
364 | gpio_pad_int_entry(7), |
365 | gpio_pad_int_entry(8), |
366 | gpio_pad_int_entry(9), |
367 | gpio_pad_int_entry(10), |
368 | gpio_pad_int_entry(11), |
369 | gpio_pad_int_entry(12), |
370 | gpio_pad_int_entry(13), |
371 | gpio_pad_int_entry(14), |
372 | gpio_pad_int_entry(15), |
373 | gpio_pad_int_entry(16), |
374 | gpio_pad_int_entry(17), |
375 | gpio_pad_int_entry(18), |
376 | gpio_pad_int_entry(19), |
377 | gpio_pad_int_entry(20), |
378 | gpio_pad_int_entry(21), |
379 | gpio_pad_int_entry(22), |
380 | gpio_pad_int_entry(23), |
381 | gpio_pad_int_entry(24), |
382 | gpio_pad_int_entry(25), |
383 | gpio_pad_int_entry(26), |
384 | gpio_pad_int_entry(27), |
385 | gpio_pad_int_entry(28), |
386 | gpio_pad_int_entry(29), |
387 | gpio_pad_int_entry(30), |
388 | dc_underflow_int_entry(1), |
389 | dc_underflow_int_entry(2), |
390 | dc_underflow_int_entry(3), |
391 | dc_underflow_int_entry(4), |
392 | dc_underflow_int_entry(5), |
393 | dc_underflow_int_entry(6), |
394 | [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), |
395 | [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), |
396 | vupdate_no_lock_int_entry(0), |
397 | vupdate_no_lock_int_entry(1), |
398 | vupdate_no_lock_int_entry(2), |
399 | vupdate_no_lock_int_entry(3), |
400 | vblank_int_entry(0), |
401 | vblank_int_entry(1), |
402 | vblank_int_entry(2), |
403 | vblank_int_entry(3), |
404 | vline0_int_entry(0), |
405 | vline0_int_entry(1), |
406 | vline0_int_entry(2), |
407 | vline0_int_entry(3), |
408 | [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), |
409 | [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), |
410 | dmub_outbox_int_entry(), |
411 | }; |
412 | |
413 | static const struct irq_service_funcs irq_service_funcs_dcn315 = { |
414 | .to_dal_irq_source = to_dal_irq_source_dcn315 |
415 | }; |
416 | |
417 | static void dcn315_irq_construct( |
418 | struct irq_service *irq_service, |
419 | struct irq_service_init_data *init_data) |
420 | { |
421 | dal_irq_service_construct(irq_service, init_data); |
422 | |
423 | irq_service->info = irq_source_info_dcn315; |
424 | irq_service->funcs = &irq_service_funcs_dcn315; |
425 | } |
426 | |
427 | struct irq_service *dal_irq_service_dcn315_create( |
428 | struct irq_service_init_data *init_data) |
429 | { |
430 | struct irq_service *irq_service = kzalloc(size: sizeof(*irq_service), |
431 | GFP_KERNEL); |
432 | |
433 | if (!irq_service) |
434 | return NULL; |
435 | |
436 | dcn315_irq_construct(irq_service, init_data); |
437 | return irq_service; |
438 | } |
439 | |