| 1 | /* |
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| 2 | * DCE_10_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef DCE_10_0_SH_MASK_H |
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| 25 | #define DCE_10_0_SH_MASK_H |
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| 26 | |
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| 27 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 |
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| 28 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 |
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| 29 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 |
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| 30 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 |
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| 31 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff |
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| 32 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 |
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| 33 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 34 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 35 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 36 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 37 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 38 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 39 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 40 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 41 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 |
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| 42 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 |
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| 43 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 |
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| 44 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 |
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| 45 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff |
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| 46 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 |
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| 47 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 48 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 49 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 50 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 51 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 52 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 53 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 54 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 55 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 |
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| 56 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 |
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| 57 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 |
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| 58 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 |
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| 59 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff |
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| 60 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 |
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| 61 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 62 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 63 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 64 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 65 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 66 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 67 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 68 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 69 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 |
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| 70 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 |
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| 71 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 |
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| 72 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 |
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| 73 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff |
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| 74 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 |
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| 75 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 76 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 77 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 78 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 79 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 80 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 81 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 82 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 83 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 |
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| 84 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 |
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| 85 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 |
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| 86 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 |
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| 87 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff |
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| 88 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 |
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| 89 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 90 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 91 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 92 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 93 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 94 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 95 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 96 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 97 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 |
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| 98 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 |
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| 99 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 |
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| 100 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 |
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| 101 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff |
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| 102 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 |
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| 103 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 104 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 105 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 106 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 107 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 108 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 109 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 110 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 111 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 |
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| 112 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 |
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| 113 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff |
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| 114 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 |
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| 115 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff |
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| 116 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 |
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| 117 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 |
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| 118 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 |
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| 119 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 |
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| 120 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 |
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| 121 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 |
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| 122 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 |
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| 123 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 |
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| 124 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 |
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| 125 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff |
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| 126 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 127 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
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| 128 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
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| 129 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 130 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 |
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| 131 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff |
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| 132 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 |
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| 133 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff |
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| 134 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 |
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| 135 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff |
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| 136 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 |
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| 137 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff |
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| 138 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 |
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| 139 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff |
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| 140 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 |
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| 141 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff |
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| 142 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 |
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| 143 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 |
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| 144 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 |
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| 145 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 |
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| 146 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 |
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| 147 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 |
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| 148 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 |
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| 149 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 |
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| 150 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 |
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| 151 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 |
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| 152 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 |
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| 153 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 154 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 155 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 156 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 157 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 158 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 159 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 160 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 161 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 162 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 163 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 |
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| 164 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 |
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| 165 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 |
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| 166 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 |
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| 167 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 |
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| 168 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 |
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| 169 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 |
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| 170 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 |
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| 171 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
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| 172 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
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| 173 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
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| 174 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
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| 175 | #define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 |
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| 176 | #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 |
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| 177 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 |
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| 178 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 |
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| 179 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 |
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| 180 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f |
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| 181 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf |
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| 182 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 |
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| 183 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 |
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| 184 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 |
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| 185 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 |
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| 186 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 |
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| 187 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 188 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 189 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff |
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| 190 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 |
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| 191 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 |
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| 192 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 |
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| 193 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 194 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 195 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff |
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| 196 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 |
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| 197 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 |
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| 198 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 |
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| 199 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 200 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 201 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff |
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| 202 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 |
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| 203 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 |
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| 204 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 |
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| 205 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 206 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 207 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff |
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| 208 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 |
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| 209 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 |
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| 210 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 |
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| 211 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 212 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 213 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff |
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| 214 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 |
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| 215 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 |
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| 216 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 |
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| 217 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 218 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 219 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff |
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| 220 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 |
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| 221 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 |
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| 222 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 |
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| 223 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 224 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 225 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff |
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| 226 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 |
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| 227 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 |
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| 228 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 |
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| 229 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 |
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| 230 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c |
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| 231 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 |
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| 232 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d |
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| 233 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 |
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| 234 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e |
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| 235 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 236 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 237 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 |
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| 238 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 |
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| 239 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 |
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| 240 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 |
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| 241 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 |
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| 242 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 |
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| 243 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 |
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| 244 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 |
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| 245 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 |
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| 246 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 |
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| 247 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 |
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| 248 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 |
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| 249 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 |
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| 250 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 |
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| 251 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 |
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| 252 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 |
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| 253 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 |
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| 254 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 |
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| 255 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 |
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| 256 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 |
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| 257 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 |
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| 258 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa |
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| 259 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 |
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| 260 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 |
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| 261 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 |
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| 262 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 |
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| 263 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 |
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| 264 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f |
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| 265 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 |
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| 266 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 |
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| 267 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 |
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| 268 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 |
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| 269 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 |
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| 270 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc |
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| 271 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 |
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| 272 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 |
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| 273 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 |
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| 274 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 |
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| 275 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 |
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| 276 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 |
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| 277 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 |
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| 278 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 |
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| 279 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 |
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| 280 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c |
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| 281 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 |
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| 282 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d |
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| 283 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 |
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| 284 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e |
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| 285 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 286 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 287 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff |
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| 288 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 |
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| 289 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff |
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| 290 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 |
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| 291 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 |
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| 292 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 |
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| 293 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff |
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| 294 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 |
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| 295 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 |
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| 296 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 |
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| 297 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff |
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| 298 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 |
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| 299 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff |
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| 300 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 |
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| 301 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff |
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| 302 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 |
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| 303 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 |
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| 304 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 |
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| 305 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 306 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 307 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff |
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| 308 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 |
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| 309 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff |
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| 310 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 |
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| 311 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 312 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 313 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 314 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 315 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 316 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 317 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 318 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 319 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 320 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 321 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 322 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 323 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 324 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 325 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 326 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 327 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 328 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 329 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 330 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 331 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff |
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| 332 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 |
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| 333 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff |
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| 334 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 |
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| 335 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff |
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| 336 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 |
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| 337 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff |
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| 338 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 |
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| 339 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff |
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| 340 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 |
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| 341 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff |
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| 342 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 |
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| 343 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff |
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| 344 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 |
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| 345 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff |
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| 346 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 |
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| 347 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff |
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| 348 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 |
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| 349 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff |
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| 350 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 |
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| 351 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff |
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| 352 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 |
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| 353 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff |
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| 354 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 |
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| 355 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff |
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| 356 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 |
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| 357 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff |
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| 358 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 |
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| 359 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff |
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| 360 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 |
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| 361 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff |
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| 362 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 |
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| 363 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff |
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| 364 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 |
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| 365 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff |
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| 366 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 |
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| 367 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff |
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| 368 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 |
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| 369 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff |
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| 370 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 |
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| 371 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff |
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| 372 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 |
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| 373 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff |
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| 374 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 |
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| 375 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff |
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| 376 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 |
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| 377 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff |
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| 378 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 |
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| 379 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff |
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| 380 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 |
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| 381 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff |
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| 382 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 |
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| 383 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff |
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| 384 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 |
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| 385 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff |
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| 386 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 |
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| 387 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff |
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| 388 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 |
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| 389 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff |
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| 390 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 |
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| 391 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 |
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| 392 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa |
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| 393 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 |
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| 394 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 |
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| 395 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 |
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| 396 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f |
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| 397 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff |
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| 398 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 399 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 |
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| 400 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
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| 401 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 402 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 |
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| 403 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 |
|---|
| 404 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 |
|---|
| 405 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 |
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| 406 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 |
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| 407 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 |
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| 408 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc |
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| 409 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 |
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| 410 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 |
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| 411 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 |
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| 412 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f |
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| 413 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff |
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| 414 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 |
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| 415 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 |
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| 416 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 |
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| 417 | #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf |
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| 418 | #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 |
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| 419 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 |
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| 420 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 |
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| 421 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 |
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| 422 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 |
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| 423 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 |
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| 424 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 |
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| 425 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 |
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| 426 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 |
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| 427 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 |
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| 428 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 |
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| 429 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 |
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| 430 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 |
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| 431 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 |
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| 432 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 |
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| 433 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 |
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| 434 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb |
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| 435 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 |
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| 436 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc |
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| 437 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 |
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| 438 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe |
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| 439 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 |
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| 440 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf |
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| 441 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 |
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| 442 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 |
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| 443 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 |
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| 444 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 |
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| 445 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 |
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| 446 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 |
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| 447 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 |
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| 448 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 |
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| 449 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 |
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| 450 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 |
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| 451 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 |
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| 452 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 |
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| 453 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 |
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| 454 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a |
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| 455 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 |
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| 456 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b |
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| 457 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 |
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| 458 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d |
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| 459 | #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 |
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| 460 | #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 |
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| 461 | #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc |
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| 462 | #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 |
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| 463 | #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 |
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| 464 | #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 |
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| 465 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 |
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| 466 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 |
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| 467 | #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 |
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| 468 | #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 |
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| 469 | #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 |
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| 470 | #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa |
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| 471 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 |
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| 472 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc |
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| 473 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 |
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| 474 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe |
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| 475 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 |
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| 476 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 |
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| 477 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 |
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| 478 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 |
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| 479 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK 0x80000 |
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| 480 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT 0x13 |
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| 481 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK 0x100000 |
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| 482 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT 0x14 |
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| 483 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 |
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| 484 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 |
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| 485 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 |
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| 486 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 |
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| 487 | #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 |
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| 488 | #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 |
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| 489 | #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc |
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| 490 | #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 |
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| 491 | #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 |
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| 492 | #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 |
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| 493 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 |
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| 494 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 |
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| 495 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 |
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| 496 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 |
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| 497 | #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 |
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| 498 | #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa |
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| 499 | #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 |
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| 500 | #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc |
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| 501 | #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 |
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| 502 | #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe |
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| 503 | #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 |
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| 504 | #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 |
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| 505 | #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 |
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| 506 | #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 |
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| 507 | #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 |
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| 508 | #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 |
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| 509 | #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 |
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| 510 | #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 |
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| 511 | #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK 0x1000000 |
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| 512 | #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT 0x18 |
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| 513 | #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff |
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| 514 | #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 |
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| 515 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff |
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| 516 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 |
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| 517 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 |
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| 518 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 |
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| 519 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff |
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| 520 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 |
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| 521 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 |
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| 522 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 |
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| 523 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 |
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| 524 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 |
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| 525 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 |
|---|
| 526 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 |
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| 527 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 |
|---|
| 528 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 |
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| 529 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff |
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| 530 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 |
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| 531 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 |
|---|
| 532 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 |
|---|
| 533 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 |
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| 534 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 |
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| 535 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 |
|---|
| 536 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 |
|---|
| 537 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 |
|---|
| 538 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 |
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| 539 | #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff |
|---|
| 540 | #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 |
|---|
| 541 | #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 |
|---|
| 542 | #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 |
|---|
| 543 | #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff |
|---|
| 544 | #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 |
|---|
| 545 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff |
|---|
| 546 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 |
|---|
| 547 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff |
|---|
| 548 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 |
|---|
| 549 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 |
|---|
| 550 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 |
|---|
| 551 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 |
|---|
| 552 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 |
|---|
| 553 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 |
|---|
| 554 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 |
|---|
| 555 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 |
|---|
| 556 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 |
|---|
| 557 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 |
|---|
| 558 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc |
|---|
| 559 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 |
|---|
| 560 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf |
|---|
| 561 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 |
|---|
| 562 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
|---|
| 563 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 |
|---|
| 564 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
|---|
| 565 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 |
|---|
| 566 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
|---|
| 567 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 |
|---|
| 568 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
|---|
| 569 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 |
|---|
| 570 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
|---|
| 571 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 |
|---|
| 572 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 |
|---|
| 573 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 |
|---|
| 574 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
|---|
| 575 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff |
|---|
| 576 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 |
|---|
| 577 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 |
|---|
| 578 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 |
|---|
| 579 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff |
|---|
| 580 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 |
|---|
| 581 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 |
|---|
| 582 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 |
|---|
| 583 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 |
|---|
| 584 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 |
|---|
| 585 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff |
|---|
| 586 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 |
|---|
| 587 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 |
|---|
| 588 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 |
|---|
| 589 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 |
|---|
| 590 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 |
|---|
| 591 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 |
|---|
| 592 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 |
|---|
| 593 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e |
|---|
| 594 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 |
|---|
| 595 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff |
|---|
| 596 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 |
|---|
| 597 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 598 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 |
|---|
| 599 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f |
|---|
| 600 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 601 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 |
|---|
| 602 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 |
|---|
| 603 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 |
|---|
| 604 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 |
|---|
| 605 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 |
|---|
| 606 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 |
|---|
| 607 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 |
|---|
| 608 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa |
|---|
| 609 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 |
|---|
| 610 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb |
|---|
| 611 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
|---|
| 612 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
|---|
| 613 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
|---|
| 614 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
|---|
| 615 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 |
|---|
| 616 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
|---|
| 617 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 |
|---|
| 618 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 |
|---|
| 619 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 |
|---|
| 620 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f |
|---|
| 621 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 |
|---|
| 622 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
|---|
| 623 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f |
|---|
| 624 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 625 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 |
|---|
| 626 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 |
|---|
| 627 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 |
|---|
| 628 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 |
|---|
| 629 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 |
|---|
| 630 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 |
|---|
| 631 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 |
|---|
| 632 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa |
|---|
| 633 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 |
|---|
| 634 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb |
|---|
| 635 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
|---|
| 636 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
|---|
| 637 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
|---|
| 638 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
|---|
| 639 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 |
|---|
| 640 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
|---|
| 641 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 |
|---|
| 642 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 |
|---|
| 643 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 |
|---|
| 644 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f |
|---|
| 645 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 |
|---|
| 646 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
|---|
| 647 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 |
|---|
| 648 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
|---|
| 649 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 |
|---|
| 650 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
|---|
| 651 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 |
|---|
| 652 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
|---|
| 653 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 |
|---|
| 654 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
|---|
| 655 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 |
|---|
| 656 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
|---|
| 657 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f |
|---|
| 658 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 659 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 |
|---|
| 660 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
|---|
| 661 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 |
|---|
| 662 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
|---|
| 663 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 |
|---|
| 664 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
|---|
| 665 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 |
|---|
| 666 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
|---|
| 667 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 |
|---|
| 668 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
|---|
| 669 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 |
|---|
| 670 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
|---|
| 671 | #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff |
|---|
| 672 | #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 |
|---|
| 673 | #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 |
|---|
| 674 | #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 |
|---|
| 675 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 |
|---|
| 676 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 |
|---|
| 677 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 |
|---|
| 678 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 |
|---|
| 679 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 |
|---|
| 680 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc |
|---|
| 681 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 |
|---|
| 682 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd |
|---|
| 683 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 |
|---|
| 684 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe |
|---|
| 685 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 |
|---|
| 686 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
|---|
| 687 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 |
|---|
| 688 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 |
|---|
| 689 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 |
|---|
| 690 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 |
|---|
| 691 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 |
|---|
| 692 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d |
|---|
| 693 | #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 |
|---|
| 694 | #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e |
|---|
| 695 | #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 |
|---|
| 696 | #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f |
|---|
| 697 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 |
|---|
| 698 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 |
|---|
| 699 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 |
|---|
| 700 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 |
|---|
| 701 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 |
|---|
| 702 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 |
|---|
| 703 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 |
|---|
| 704 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 |
|---|
| 705 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 |
|---|
| 706 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
|---|
| 707 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 |
|---|
| 708 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
|---|
| 709 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 |
|---|
| 710 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
|---|
| 711 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 |
|---|
| 712 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
|---|
| 713 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 |
|---|
| 714 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 |
|---|
| 715 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff |
|---|
| 716 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
|---|
| 717 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 |
|---|
| 718 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
|---|
| 719 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff |
|---|
| 720 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 |
|---|
| 721 | #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 |
|---|
| 722 | #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 |
|---|
| 723 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 |
|---|
| 724 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 |
|---|
| 725 | #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 |
|---|
| 726 | #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 |
|---|
| 727 | #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 |
|---|
| 728 | #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 |
|---|
| 729 | #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 |
|---|
| 730 | #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 |
|---|
| 731 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 |
|---|
| 732 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
|---|
| 733 | #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 |
|---|
| 734 | #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 |
|---|
| 735 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 |
|---|
| 736 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 |
|---|
| 737 | #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 |
|---|
| 738 | #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 |
|---|
| 739 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff |
|---|
| 740 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 |
|---|
| 741 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 742 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 |
|---|
| 743 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff |
|---|
| 744 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 |
|---|
| 745 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff |
|---|
| 746 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 |
|---|
| 747 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff |
|---|
| 748 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 |
|---|
| 749 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff |
|---|
| 750 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 |
|---|
| 751 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 |
|---|
| 752 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
|---|
| 753 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e |
|---|
| 754 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 |
|---|
| 755 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 |
|---|
| 756 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 |
|---|
| 757 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 |
|---|
| 758 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
|---|
| 759 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 |
|---|
| 760 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
|---|
| 761 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 |
|---|
| 762 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
|---|
| 763 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 |
|---|
| 764 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
|---|
| 765 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 |
|---|
| 766 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 |
|---|
| 767 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 |
|---|
| 768 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
|---|
| 769 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 |
|---|
| 770 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 |
|---|
| 771 | #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 |
|---|
| 772 | #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 |
|---|
| 773 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 |
|---|
| 774 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
|---|
| 775 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff |
|---|
| 776 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
|---|
| 777 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 |
|---|
| 778 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
|---|
| 779 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 |
|---|
| 780 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 |
|---|
| 781 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 |
|---|
| 782 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
|---|
| 783 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 |
|---|
| 784 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
|---|
| 785 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 |
|---|
| 786 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 |
|---|
| 787 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 |
|---|
| 788 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
|---|
| 789 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 |
|---|
| 790 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 |
|---|
| 791 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 |
|---|
| 792 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 |
|---|
| 793 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 |
|---|
| 794 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 |
|---|
| 795 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 |
|---|
| 796 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
|---|
| 797 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 |
|---|
| 798 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
|---|
| 799 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff |
|---|
| 800 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
|---|
| 801 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 802 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
|---|
| 803 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff |
|---|
| 804 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
|---|
| 805 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 |
|---|
| 806 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 |
|---|
| 807 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 |
|---|
| 808 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 |
|---|
| 809 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 |
|---|
| 810 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc |
|---|
| 811 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 |
|---|
| 812 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 |
|---|
| 813 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 |
|---|
| 814 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c |
|---|
| 815 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 |
|---|
| 816 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 |
|---|
| 817 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 |
|---|
| 818 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
|---|
| 819 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 |
|---|
| 820 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 |
|---|
| 821 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 |
|---|
| 822 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 |
|---|
| 823 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 |
|---|
| 824 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
|---|
| 825 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 |
|---|
| 826 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
|---|
| 827 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 |
|---|
| 828 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
|---|
| 829 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 |
|---|
| 830 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
|---|
| 831 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 |
|---|
| 832 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 |
|---|
| 833 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 |
|---|
| 834 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 |
|---|
| 835 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 |
|---|
| 836 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a |
|---|
| 837 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 |
|---|
| 838 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b |
|---|
| 839 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 |
|---|
| 840 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
|---|
| 841 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 |
|---|
| 842 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
|---|
| 843 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 |
|---|
| 844 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
|---|
| 845 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 |
|---|
| 846 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
|---|
| 847 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 |
|---|
| 848 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 849 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 |
|---|
| 850 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 851 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 |
|---|
| 852 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 |
|---|
| 853 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 |
|---|
| 854 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
|---|
| 855 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 |
|---|
| 856 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 |
|---|
| 857 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 |
|---|
| 858 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 |
|---|
| 859 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 |
|---|
| 860 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 |
|---|
| 861 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 |
|---|
| 862 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
|---|
| 863 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 |
|---|
| 864 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
|---|
| 865 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf |
|---|
| 866 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 |
|---|
| 867 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 |
|---|
| 868 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 |
|---|
| 869 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 |
|---|
| 870 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 |
|---|
| 871 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 |
|---|
| 872 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc |
|---|
| 873 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 |
|---|
| 874 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
|---|
| 875 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff |
|---|
| 876 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 |
|---|
| 877 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 |
|---|
| 878 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 |
|---|
| 879 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 |
|---|
| 880 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 881 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 |
|---|
| 882 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 |
|---|
| 883 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 |
|---|
| 884 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 |
|---|
| 885 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 |
|---|
| 886 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 |
|---|
| 887 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 |
|---|
| 888 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 |
|---|
| 889 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 |
|---|
| 890 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 |
|---|
| 891 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff |
|---|
| 892 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 |
|---|
| 893 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 |
|---|
| 894 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 |
|---|
| 895 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 |
|---|
| 896 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 |
|---|
| 897 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 |
|---|
| 898 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 |
|---|
| 899 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 |
|---|
| 900 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 |
|---|
| 901 | #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 |
|---|
| 902 | #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 |
|---|
| 903 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff |
|---|
| 904 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 |
|---|
| 905 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 |
|---|
| 906 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 |
|---|
| 907 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 |
|---|
| 908 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 |
|---|
| 909 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 |
|---|
| 910 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 |
|---|
| 911 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff |
|---|
| 912 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 |
|---|
| 913 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 |
|---|
| 914 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa |
|---|
| 915 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 |
|---|
| 916 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 |
|---|
| 917 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 |
|---|
| 918 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 |
|---|
| 919 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 |
|---|
| 920 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 |
|---|
| 921 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 |
|---|
| 922 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 |
|---|
| 923 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff |
|---|
| 924 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
|---|
| 925 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 |
|---|
| 926 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
|---|
| 927 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 |
|---|
| 928 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
|---|
| 929 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 |
|---|
| 930 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
|---|
| 931 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 |
|---|
| 932 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
|---|
| 933 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 |
|---|
| 934 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
|---|
| 935 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff |
|---|
| 936 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 |
|---|
| 937 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 |
|---|
| 938 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa |
|---|
| 939 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 |
|---|
| 940 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 |
|---|
| 941 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 |
|---|
| 942 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
|---|
| 943 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 |
|---|
| 944 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
|---|
| 945 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 |
|---|
| 946 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
|---|
| 947 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff |
|---|
| 948 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
|---|
| 949 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 |
|---|
| 950 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
|---|
| 951 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 |
|---|
| 952 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
|---|
| 953 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 |
|---|
| 954 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
|---|
| 955 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 |
|---|
| 956 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
|---|
| 957 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 |
|---|
| 958 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
|---|
| 959 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 |
|---|
| 960 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
|---|
| 961 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 |
|---|
| 962 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
|---|
| 963 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff |
|---|
| 964 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
|---|
| 965 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 |
|---|
| 966 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
|---|
| 967 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 |
|---|
| 968 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
|---|
| 969 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 |
|---|
| 970 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
|---|
| 971 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 |
|---|
| 972 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
|---|
| 973 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 |
|---|
| 974 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
|---|
| 975 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff |
|---|
| 976 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
|---|
| 977 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 |
|---|
| 978 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
|---|
| 979 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 |
|---|
| 980 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
|---|
| 981 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 |
|---|
| 982 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
|---|
| 983 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 |
|---|
| 984 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
|---|
| 985 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 |
|---|
| 986 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
|---|
| 987 | #define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 |
|---|
| 988 | #define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 |
|---|
| 989 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 |
|---|
| 990 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 |
|---|
| 991 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 |
|---|
| 992 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 |
|---|
| 993 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 |
|---|
| 994 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc |
|---|
| 995 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 |
|---|
| 996 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 |
|---|
| 997 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 |
|---|
| 998 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 |
|---|
| 999 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 |
|---|
| 1000 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 |
|---|
| 1001 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff |
|---|
| 1002 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 |
|---|
| 1003 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 |
|---|
| 1004 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 |
|---|
| 1005 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff |
|---|
| 1006 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
|---|
| 1007 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 |
|---|
| 1008 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
|---|
| 1009 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff |
|---|
| 1010 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 |
|---|
| 1011 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 |
|---|
| 1012 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 |
|---|
| 1013 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff |
|---|
| 1014 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
|---|
| 1015 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 |
|---|
| 1016 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
|---|
| 1017 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff |
|---|
| 1018 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
|---|
| 1019 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 |
|---|
| 1020 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
|---|
| 1021 | #define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff |
|---|
| 1022 | #define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
|---|
| 1023 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff |
|---|
| 1024 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 |
|---|
| 1025 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 |
|---|
| 1026 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 |
|---|
| 1027 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff |
|---|
| 1028 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
|---|
| 1029 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 |
|---|
| 1030 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
|---|
| 1031 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff |
|---|
| 1032 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 |
|---|
| 1033 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 |
|---|
| 1034 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 |
|---|
| 1035 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff |
|---|
| 1036 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
|---|
| 1037 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 |
|---|
| 1038 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
|---|
| 1039 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff |
|---|
| 1040 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
|---|
| 1041 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 |
|---|
| 1042 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
|---|
| 1043 | #define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff |
|---|
| 1044 | #define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
|---|
| 1045 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 |
|---|
| 1046 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 |
|---|
| 1047 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 |
|---|
| 1048 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 |
|---|
| 1049 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 |
|---|
| 1050 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 |
|---|
| 1051 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 |
|---|
| 1052 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 |
|---|
| 1053 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 |
|---|
| 1054 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 |
|---|
| 1055 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 |
|---|
| 1056 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 |
|---|
| 1057 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 |
|---|
| 1058 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc |
|---|
| 1059 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 |
|---|
| 1060 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd |
|---|
| 1061 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 |
|---|
| 1062 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe |
|---|
| 1063 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 |
|---|
| 1064 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 |
|---|
| 1065 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 |
|---|
| 1066 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c |
|---|
| 1067 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff |
|---|
| 1068 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 |
|---|
| 1069 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000 |
|---|
| 1070 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 |
|---|
| 1071 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff |
|---|
| 1072 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 |
|---|
| 1073 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000 |
|---|
| 1074 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 |
|---|
| 1075 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 |
|---|
| 1076 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 |
|---|
| 1077 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 |
|---|
| 1078 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 |
|---|
| 1079 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 |
|---|
| 1080 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 |
|---|
| 1081 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 |
|---|
| 1082 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 |
|---|
| 1083 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 |
|---|
| 1084 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 |
|---|
| 1085 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 |
|---|
| 1086 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d |
|---|
| 1087 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 |
|---|
| 1088 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 |
|---|
| 1089 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 |
|---|
| 1090 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 |
|---|
| 1091 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 |
|---|
| 1092 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 |
|---|
| 1093 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 |
|---|
| 1094 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 |
|---|
| 1095 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 |
|---|
| 1096 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 |
|---|
| 1097 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 |
|---|
| 1098 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 |
|---|
| 1099 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 |
|---|
| 1100 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 |
|---|
| 1101 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 |
|---|
| 1102 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 |
|---|
| 1103 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 |
|---|
| 1104 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 |
|---|
| 1105 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 |
|---|
| 1106 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 |
|---|
| 1107 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff |
|---|
| 1108 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
|---|
| 1109 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 |
|---|
| 1110 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
|---|
| 1111 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 |
|---|
| 1112 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 |
|---|
| 1113 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 |
|---|
| 1114 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 |
|---|
| 1115 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 |
|---|
| 1116 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a |
|---|
| 1117 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 |
|---|
| 1118 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b |
|---|
| 1119 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 |
|---|
| 1120 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c |
|---|
| 1121 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 |
|---|
| 1122 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 |
|---|
| 1123 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 |
|---|
| 1124 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 |
|---|
| 1125 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 |
|---|
| 1126 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
|---|
| 1127 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 |
|---|
| 1128 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
|---|
| 1129 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 |
|---|
| 1130 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
|---|
| 1131 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 |
|---|
| 1132 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
|---|
| 1133 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 |
|---|
| 1134 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
|---|
| 1135 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff |
|---|
| 1136 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
|---|
| 1137 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 |
|---|
| 1138 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
|---|
| 1139 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 |
|---|
| 1140 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
|---|
| 1141 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 |
|---|
| 1142 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
|---|
| 1143 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 |
|---|
| 1144 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
|---|
| 1145 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 |
|---|
| 1146 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
|---|
| 1147 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 |
|---|
| 1148 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
|---|
| 1149 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 |
|---|
| 1150 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 |
|---|
| 1151 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff |
|---|
| 1152 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 |
|---|
| 1153 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 |
|---|
| 1154 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 |
|---|
| 1155 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff |
|---|
| 1156 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 |
|---|
| 1157 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 |
|---|
| 1158 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 |
|---|
| 1159 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 |
|---|
| 1160 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
|---|
| 1161 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1162 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1163 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1164 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1165 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1166 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1167 | #define DAC_ENABLE__DAC_ENABLE_MASK 0x1 |
|---|
| 1168 | #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 |
|---|
| 1169 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 |
|---|
| 1170 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 |
|---|
| 1171 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc |
|---|
| 1172 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 |
|---|
| 1173 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 |
|---|
| 1174 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 |
|---|
| 1175 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 |
|---|
| 1176 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 |
|---|
| 1177 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 |
|---|
| 1178 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 |
|---|
| 1179 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 |
|---|
| 1180 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 1181 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 |
|---|
| 1182 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 |
|---|
| 1183 | #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 |
|---|
| 1184 | #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 |
|---|
| 1185 | #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 |
|---|
| 1186 | #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 |
|---|
| 1187 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 |
|---|
| 1188 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 |
|---|
| 1189 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 |
|---|
| 1190 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 |
|---|
| 1191 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff |
|---|
| 1192 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
|---|
| 1193 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 |
|---|
| 1194 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa |
|---|
| 1195 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 |
|---|
| 1196 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 |
|---|
| 1197 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f |
|---|
| 1198 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 |
|---|
| 1199 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff |
|---|
| 1200 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 |
|---|
| 1201 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 |
|---|
| 1202 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa |
|---|
| 1203 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 |
|---|
| 1204 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 |
|---|
| 1205 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f |
|---|
| 1206 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 |
|---|
| 1207 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 |
|---|
| 1208 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 |
|---|
| 1209 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 |
|---|
| 1210 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 |
|---|
| 1211 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 |
|---|
| 1212 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 |
|---|
| 1213 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 |
|---|
| 1214 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 |
|---|
| 1215 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 |
|---|
| 1216 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 |
|---|
| 1217 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 |
|---|
| 1218 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 |
|---|
| 1219 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 |
|---|
| 1220 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 |
|---|
| 1221 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff |
|---|
| 1222 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 |
|---|
| 1223 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 |
|---|
| 1224 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 |
|---|
| 1225 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff |
|---|
| 1226 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 |
|---|
| 1227 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 |
|---|
| 1228 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 |
|---|
| 1229 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 |
|---|
| 1230 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 |
|---|
| 1231 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 |
|---|
| 1232 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 |
|---|
| 1233 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 |
|---|
| 1234 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 |
|---|
| 1235 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 |
|---|
| 1236 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 |
|---|
| 1237 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 |
|---|
| 1238 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 |
|---|
| 1239 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 |
|---|
| 1240 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 |
|---|
| 1241 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 |
|---|
| 1242 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 |
|---|
| 1243 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 |
|---|
| 1244 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 |
|---|
| 1245 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 |
|---|
| 1246 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 |
|---|
| 1247 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 |
|---|
| 1248 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 |
|---|
| 1249 | #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff |
|---|
| 1250 | #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 |
|---|
| 1251 | #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 |
|---|
| 1252 | #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 |
|---|
| 1253 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 |
|---|
| 1254 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 |
|---|
| 1255 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 |
|---|
| 1256 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 |
|---|
| 1257 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 |
|---|
| 1258 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 |
|---|
| 1259 | #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 |
|---|
| 1260 | #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 |
|---|
| 1261 | #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 |
|---|
| 1262 | #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 |
|---|
| 1263 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 |
|---|
| 1264 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 |
|---|
| 1265 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 |
|---|
| 1266 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 |
|---|
| 1267 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 |
|---|
| 1268 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 |
|---|
| 1269 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 |
|---|
| 1270 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 |
|---|
| 1271 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 |
|---|
| 1272 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 |
|---|
| 1273 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 |
|---|
| 1274 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 |
|---|
| 1275 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 |
|---|
| 1276 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 |
|---|
| 1277 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 |
|---|
| 1278 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 |
|---|
| 1279 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 |
|---|
| 1280 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 |
|---|
| 1281 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 |
|---|
| 1282 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 |
|---|
| 1283 | #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 |
|---|
| 1284 | #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 |
|---|
| 1285 | #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 |
|---|
| 1286 | #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 |
|---|
| 1287 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff |
|---|
| 1288 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 |
|---|
| 1289 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
|---|
| 1290 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
|---|
| 1291 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
|---|
| 1292 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
|---|
| 1293 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
|---|
| 1294 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
|---|
| 1295 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 |
|---|
| 1296 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
|---|
| 1297 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
|---|
| 1298 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
|---|
| 1299 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 |
|---|
| 1300 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d |
|---|
| 1301 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
|---|
| 1302 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
|---|
| 1303 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
|---|
| 1304 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
|---|
| 1305 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1306 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1307 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1308 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1309 | #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1310 | #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1311 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff |
|---|
| 1312 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
|---|
| 1313 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 |
|---|
| 1314 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
|---|
| 1315 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 |
|---|
| 1316 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
|---|
| 1317 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 |
|---|
| 1318 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe |
|---|
| 1319 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 |
|---|
| 1320 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf |
|---|
| 1321 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 |
|---|
| 1322 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 |
|---|
| 1323 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 |
|---|
| 1324 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 |
|---|
| 1325 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 |
|---|
| 1326 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 |
|---|
| 1327 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 |
|---|
| 1328 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 |
|---|
| 1329 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 |
|---|
| 1330 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 |
|---|
| 1331 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 |
|---|
| 1332 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 |
|---|
| 1333 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 |
|---|
| 1334 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a |
|---|
| 1335 | #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 |
|---|
| 1336 | #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b |
|---|
| 1337 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 |
|---|
| 1338 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
|---|
| 1339 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 |
|---|
| 1340 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
|---|
| 1341 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 |
|---|
| 1342 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
|---|
| 1343 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 |
|---|
| 1344 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
|---|
| 1345 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 |
|---|
| 1346 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
|---|
| 1347 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 |
|---|
| 1348 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
|---|
| 1349 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 |
|---|
| 1350 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
|---|
| 1351 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 |
|---|
| 1352 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
|---|
| 1353 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 |
|---|
| 1354 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
|---|
| 1355 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 |
|---|
| 1356 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
|---|
| 1357 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 |
|---|
| 1358 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
|---|
| 1359 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 |
|---|
| 1360 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
|---|
| 1361 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 |
|---|
| 1362 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
|---|
| 1363 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 |
|---|
| 1364 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
|---|
| 1365 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 |
|---|
| 1366 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
|---|
| 1367 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 |
|---|
| 1368 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
|---|
| 1369 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 |
|---|
| 1370 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
|---|
| 1371 | #define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 |
|---|
| 1372 | #define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
|---|
| 1373 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc |
|---|
| 1374 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 |
|---|
| 1375 | #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 |
|---|
| 1376 | #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
|---|
| 1377 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 |
|---|
| 1378 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
|---|
| 1379 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 |
|---|
| 1380 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
|---|
| 1381 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 |
|---|
| 1382 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
|---|
| 1383 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 |
|---|
| 1384 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
|---|
| 1385 | #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 |
|---|
| 1386 | #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
|---|
| 1387 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 |
|---|
| 1388 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
|---|
| 1389 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 |
|---|
| 1390 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
|---|
| 1391 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 |
|---|
| 1392 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
|---|
| 1393 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 |
|---|
| 1394 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
|---|
| 1395 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 |
|---|
| 1396 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
|---|
| 1397 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 |
|---|
| 1398 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
|---|
| 1399 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 |
|---|
| 1400 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
|---|
| 1401 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 |
|---|
| 1402 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
|---|
| 1403 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 |
|---|
| 1404 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
|---|
| 1405 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 |
|---|
| 1406 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
|---|
| 1407 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 |
|---|
| 1408 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
|---|
| 1409 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 |
|---|
| 1410 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
|---|
| 1411 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 |
|---|
| 1412 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
|---|
| 1413 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 |
|---|
| 1414 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
|---|
| 1415 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 |
|---|
| 1416 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
|---|
| 1417 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 |
|---|
| 1418 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
|---|
| 1419 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 |
|---|
| 1420 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
|---|
| 1421 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff |
|---|
| 1422 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
|---|
| 1423 | #define PERFMON_HI__PERFMON_HI_MASK 0xffff |
|---|
| 1424 | #define PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
|---|
| 1425 | #define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 |
|---|
| 1426 | #define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
|---|
| 1427 | #define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff |
|---|
| 1428 | #define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
|---|
| 1429 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1430 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1431 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1432 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1433 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1434 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1435 | #define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 |
|---|
| 1436 | #define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 |
|---|
| 1437 | #define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 |
|---|
| 1438 | #define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 |
|---|
| 1439 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf |
|---|
| 1440 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 |
|---|
| 1441 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 |
|---|
| 1442 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 |
|---|
| 1443 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 |
|---|
| 1444 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 |
|---|
| 1445 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff |
|---|
| 1446 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 |
|---|
| 1447 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 |
|---|
| 1448 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 |
|---|
| 1449 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff |
|---|
| 1450 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 |
|---|
| 1451 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 |
|---|
| 1452 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 |
|---|
| 1453 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff |
|---|
| 1454 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 |
|---|
| 1455 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff |
|---|
| 1456 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 |
|---|
| 1457 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff |
|---|
| 1458 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 |
|---|
| 1459 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff |
|---|
| 1460 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 |
|---|
| 1461 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff |
|---|
| 1462 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 |
|---|
| 1463 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 |
|---|
| 1464 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 |
|---|
| 1465 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 |
|---|
| 1466 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 |
|---|
| 1467 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 |
|---|
| 1468 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 |
|---|
| 1469 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 |
|---|
| 1470 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 |
|---|
| 1471 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 |
|---|
| 1472 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 |
|---|
| 1473 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 |
|---|
| 1474 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 |
|---|
| 1475 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff |
|---|
| 1476 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 |
|---|
| 1477 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 |
|---|
| 1478 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 |
|---|
| 1479 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 |
|---|
| 1480 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 |
|---|
| 1481 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 |
|---|
| 1482 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 |
|---|
| 1483 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 |
|---|
| 1484 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 |
|---|
| 1485 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 |
|---|
| 1486 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 |
|---|
| 1487 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 |
|---|
| 1488 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 |
|---|
| 1489 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 |
|---|
| 1490 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 |
|---|
| 1491 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 |
|---|
| 1492 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 |
|---|
| 1493 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 |
|---|
| 1494 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 |
|---|
| 1495 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 |
|---|
| 1496 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 |
|---|
| 1497 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 |
|---|
| 1498 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 |
|---|
| 1499 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 |
|---|
| 1500 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 |
|---|
| 1501 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 |
|---|
| 1502 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 |
|---|
| 1503 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 |
|---|
| 1504 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 |
|---|
| 1505 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 |
|---|
| 1506 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 |
|---|
| 1507 | #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 |
|---|
| 1508 | #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 |
|---|
| 1509 | #define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 |
|---|
| 1510 | #define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 |
|---|
| 1511 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 |
|---|
| 1512 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 |
|---|
| 1513 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 |
|---|
| 1514 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 |
|---|
| 1515 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 |
|---|
| 1516 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 |
|---|
| 1517 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 |
|---|
| 1518 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 |
|---|
| 1519 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 |
|---|
| 1520 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 |
|---|
| 1521 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 |
|---|
| 1522 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 |
|---|
| 1523 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 |
|---|
| 1524 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 |
|---|
| 1525 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 |
|---|
| 1526 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 |
|---|
| 1527 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 |
|---|
| 1528 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 |
|---|
| 1529 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 |
|---|
| 1530 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 |
|---|
| 1531 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 |
|---|
| 1532 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 |
|---|
| 1533 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 |
|---|
| 1534 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 |
|---|
| 1535 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 |
|---|
| 1536 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 |
|---|
| 1537 | #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 |
|---|
| 1538 | #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 |
|---|
| 1539 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 |
|---|
| 1540 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 |
|---|
| 1541 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 |
|---|
| 1542 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 |
|---|
| 1543 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 |
|---|
| 1544 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 |
|---|
| 1545 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 |
|---|
| 1546 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 |
|---|
| 1547 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 |
|---|
| 1548 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 |
|---|
| 1549 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 |
|---|
| 1550 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 |
|---|
| 1551 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 |
|---|
| 1552 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 |
|---|
| 1553 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 |
|---|
| 1554 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 |
|---|
| 1555 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 |
|---|
| 1556 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 |
|---|
| 1557 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 |
|---|
| 1558 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a |
|---|
| 1559 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 |
|---|
| 1560 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b |
|---|
| 1561 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 |
|---|
| 1562 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c |
|---|
| 1563 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 |
|---|
| 1564 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d |
|---|
| 1565 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 |
|---|
| 1566 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e |
|---|
| 1567 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1568 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1569 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1570 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1571 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 |
|---|
| 1572 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc |
|---|
| 1573 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1574 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1575 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1576 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1577 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 |
|---|
| 1578 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc |
|---|
| 1579 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1580 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1581 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1582 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1583 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1584 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1585 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1586 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1587 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff |
|---|
| 1588 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 |
|---|
| 1589 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1590 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1591 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 |
|---|
| 1592 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 |
|---|
| 1593 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1594 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1595 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 |
|---|
| 1596 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 |
|---|
| 1597 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1598 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1599 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 |
|---|
| 1600 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 |
|---|
| 1601 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f |
|---|
| 1602 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 |
|---|
| 1603 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 |
|---|
| 1604 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 |
|---|
| 1605 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 |
|---|
| 1606 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 |
|---|
| 1607 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 |
|---|
| 1608 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 |
|---|
| 1609 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
|---|
| 1610 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
|---|
| 1611 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 |
|---|
| 1612 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 |
|---|
| 1613 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff |
|---|
| 1614 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 |
|---|
| 1615 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
|---|
| 1616 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
|---|
| 1617 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff |
|---|
| 1618 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 |
|---|
| 1619 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 |
|---|
| 1620 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 |
|---|
| 1621 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 |
|---|
| 1622 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 |
|---|
| 1623 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 |
|---|
| 1624 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 |
|---|
| 1625 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 |
|---|
| 1626 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c |
|---|
| 1627 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 |
|---|
| 1628 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d |
|---|
| 1629 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 |
|---|
| 1630 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e |
|---|
| 1631 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 |
|---|
| 1632 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f |
|---|
| 1633 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 |
|---|
| 1634 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 |
|---|
| 1635 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 |
|---|
| 1636 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 |
|---|
| 1637 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 |
|---|
| 1638 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 |
|---|
| 1639 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 |
|---|
| 1640 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 |
|---|
| 1641 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 |
|---|
| 1642 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 |
|---|
| 1643 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 |
|---|
| 1644 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 |
|---|
| 1645 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 |
|---|
| 1646 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 |
|---|
| 1647 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 |
|---|
| 1648 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 |
|---|
| 1649 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 |
|---|
| 1650 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 |
|---|
| 1651 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 |
|---|
| 1652 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 |
|---|
| 1653 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 |
|---|
| 1654 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb |
|---|
| 1655 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 |
|---|
| 1656 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 |
|---|
| 1657 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 |
|---|
| 1658 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 |
|---|
| 1659 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1660 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1661 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 |
|---|
| 1662 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 |
|---|
| 1663 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 |
|---|
| 1664 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 |
|---|
| 1665 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 |
|---|
| 1666 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1667 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 |
|---|
| 1668 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1669 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1670 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1671 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1672 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1673 | #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff |
|---|
| 1674 | #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 |
|---|
| 1675 | #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff |
|---|
| 1676 | #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 |
|---|
| 1677 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1678 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1679 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 |
|---|
| 1680 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 |
|---|
| 1681 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 |
|---|
| 1682 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 |
|---|
| 1683 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 |
|---|
| 1684 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1685 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 |
|---|
| 1686 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1687 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1688 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1689 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1690 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1691 | #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff |
|---|
| 1692 | #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 |
|---|
| 1693 | #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff |
|---|
| 1694 | #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 |
|---|
| 1695 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1696 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1697 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 |
|---|
| 1698 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 |
|---|
| 1699 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 |
|---|
| 1700 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 |
|---|
| 1701 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 |
|---|
| 1702 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1703 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 |
|---|
| 1704 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1705 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1706 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1707 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1708 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1709 | #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff |
|---|
| 1710 | #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 |
|---|
| 1711 | #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff |
|---|
| 1712 | #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 |
|---|
| 1713 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1714 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1715 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 |
|---|
| 1716 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 |
|---|
| 1717 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 |
|---|
| 1718 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 |
|---|
| 1719 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 |
|---|
| 1720 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1721 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 |
|---|
| 1722 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1723 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1724 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1725 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1726 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1727 | #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff |
|---|
| 1728 | #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 |
|---|
| 1729 | #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff |
|---|
| 1730 | #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 |
|---|
| 1731 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1732 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1733 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 |
|---|
| 1734 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 |
|---|
| 1735 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 |
|---|
| 1736 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 |
|---|
| 1737 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 |
|---|
| 1738 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1739 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 |
|---|
| 1740 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1741 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1742 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1743 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1744 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1745 | #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff |
|---|
| 1746 | #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 |
|---|
| 1747 | #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff |
|---|
| 1748 | #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 |
|---|
| 1749 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1750 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1751 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 |
|---|
| 1752 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 |
|---|
| 1753 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 |
|---|
| 1754 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 |
|---|
| 1755 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 |
|---|
| 1756 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1757 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 |
|---|
| 1758 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1759 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1760 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1761 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1762 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1763 | #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff |
|---|
| 1764 | #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 |
|---|
| 1765 | #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff |
|---|
| 1766 | #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 |
|---|
| 1767 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 |
|---|
| 1768 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 |
|---|
| 1769 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 |
|---|
| 1770 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 |
|---|
| 1771 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 |
|---|
| 1772 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 |
|---|
| 1773 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 |
|---|
| 1774 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 |
|---|
| 1775 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 |
|---|
| 1776 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 |
|---|
| 1777 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 |
|---|
| 1778 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 |
|---|
| 1779 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 |
|---|
| 1780 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc |
|---|
| 1781 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 |
|---|
| 1782 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd |
|---|
| 1783 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 |
|---|
| 1784 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe |
|---|
| 1785 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 |
|---|
| 1786 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf |
|---|
| 1787 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 |
|---|
| 1788 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 |
|---|
| 1789 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 |
|---|
| 1790 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 |
|---|
| 1791 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 |
|---|
| 1792 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 |
|---|
| 1793 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 |
|---|
| 1794 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 |
|---|
| 1795 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 |
|---|
| 1796 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 |
|---|
| 1797 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 |
|---|
| 1798 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 |
|---|
| 1799 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1800 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1801 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 |
|---|
| 1802 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1803 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1804 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1805 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1806 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1807 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 |
|---|
| 1808 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1809 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1810 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1811 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1812 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1813 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 |
|---|
| 1814 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1815 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1816 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1817 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1818 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1819 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 |
|---|
| 1820 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1821 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1822 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1823 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1824 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1825 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 |
|---|
| 1826 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1827 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1828 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1829 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1830 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1831 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 |
|---|
| 1832 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1833 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1834 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1835 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 |
|---|
| 1836 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 |
|---|
| 1837 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 |
|---|
| 1838 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 |
|---|
| 1839 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 |
|---|
| 1840 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 |
|---|
| 1841 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 |
|---|
| 1842 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 |
|---|
| 1843 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 |
|---|
| 1844 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 |
|---|
| 1845 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1846 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1847 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 |
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| 1848 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 |
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| 1849 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 |
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| 1850 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 |
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| 1851 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 |
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| 1852 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 |
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| 1853 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 |
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| 1854 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 |
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| 1855 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1856 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1857 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 |
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| 1858 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 |
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| 1859 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 |
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| 1860 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 |
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| 1861 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 |
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| 1862 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 |
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| 1863 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 |
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| 1864 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c |
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| 1865 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 |
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| 1866 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 |
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| 1867 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 |
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| 1868 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 |
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| 1869 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 |
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| 1870 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 |
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| 1871 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1872 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1873 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 |
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| 1874 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 |
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| 1875 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 |
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| 1876 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 |
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| 1877 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 |
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| 1878 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 |
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| 1879 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 |
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| 1880 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc |
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| 1881 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 |
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| 1882 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 |
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| 1883 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 |
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| 1884 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 |
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| 1885 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 |
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| 1886 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 |
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| 1887 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 |
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| 1888 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c |
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| 1889 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff |
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| 1890 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 |
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| 1891 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff |
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| 1892 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 |
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| 1893 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff |
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| 1894 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 |
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| 1895 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff |
|---|
| 1896 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 |
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| 1897 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff |
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| 1898 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 1899 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1900 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1901 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 1902 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1903 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff |
|---|
| 1904 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 |
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| 1905 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 |
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| 1906 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc |
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| 1907 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 |
|---|
| 1908 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 |
|---|
| 1909 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 |
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| 1910 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c |
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| 1911 | #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1912 | #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1913 | #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1914 | #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1915 | #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1916 | #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1917 | #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1918 | #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1919 | #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1920 | #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1921 | #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1922 | #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1923 | #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1924 | #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1925 | #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1926 | #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1927 | #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1928 | #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1929 | #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1930 | #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1931 | #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1932 | #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1933 | #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1934 | #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1935 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1936 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1937 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1938 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1939 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1940 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1941 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1942 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1943 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1944 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1945 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1946 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1947 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1948 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1949 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1950 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1951 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1952 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1953 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1954 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1955 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1956 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1957 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1958 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1959 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1960 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1961 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1962 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1963 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1964 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1965 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1966 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1967 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1968 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1969 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1970 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1971 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1972 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1973 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1974 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1975 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1976 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1977 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1978 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1979 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1980 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1981 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1982 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1983 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1984 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1985 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1986 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1987 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1988 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1989 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1990 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1991 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1992 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1993 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1994 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1995 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1996 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1997 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1998 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1999 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2000 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2001 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2002 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2003 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2004 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2005 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2006 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2007 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2008 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2009 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2010 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2011 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2012 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2013 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2014 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2015 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2016 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2017 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2018 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2019 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f |
|---|
| 2020 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 |
|---|
| 2021 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 |
|---|
| 2022 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 |
|---|
| 2023 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 |
|---|
| 2024 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf |
|---|
| 2025 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 |
|---|
| 2026 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 |
|---|
| 2027 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 |
|---|
| 2028 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 |
|---|
| 2029 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 |
|---|
| 2030 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 |
|---|
| 2031 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 |
|---|
| 2032 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 |
|---|
| 2033 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 |
|---|
| 2034 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 |
|---|
| 2035 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 |
|---|
| 2036 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 |
|---|
| 2037 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 |
|---|
| 2038 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 |
|---|
| 2039 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff |
|---|
| 2040 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 |
|---|
| 2041 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff |
|---|
| 2042 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 |
|---|
| 2043 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff |
|---|
| 2044 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 |
|---|
| 2045 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff |
|---|
| 2046 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 |
|---|
| 2047 | #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff |
|---|
| 2048 | #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 |
|---|
| 2049 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f |
|---|
| 2050 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 |
|---|
| 2051 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 |
|---|
| 2052 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 |
|---|
| 2053 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 |
|---|
| 2054 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc |
|---|
| 2055 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 |
|---|
| 2056 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf |
|---|
| 2057 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 |
|---|
| 2058 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 |
|---|
| 2059 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 |
|---|
| 2060 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c |
|---|
| 2061 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f |
|---|
| 2062 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 |
|---|
| 2063 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 |
|---|
| 2064 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 |
|---|
| 2065 | #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 |
|---|
| 2066 | #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 |
|---|
| 2067 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff |
|---|
| 2068 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 |
|---|
| 2069 | #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 |
|---|
| 2070 | #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
|---|
| 2071 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 |
|---|
| 2072 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
|---|
| 2073 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 |
|---|
| 2074 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
|---|
| 2075 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 |
|---|
| 2076 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc |
|---|
| 2077 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 |
|---|
| 2078 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
|---|
| 2079 | #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 |
|---|
| 2080 | #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
|---|
| 2081 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 |
|---|
| 2082 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
|---|
| 2083 | #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 |
|---|
| 2084 | #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 |
|---|
| 2085 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 |
|---|
| 2086 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 |
|---|
| 2087 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 |
|---|
| 2088 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 |
|---|
| 2089 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 |
|---|
| 2090 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 |
|---|
| 2091 | #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 |
|---|
| 2092 | #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb |
|---|
| 2093 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 |
|---|
| 2094 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc |
|---|
| 2095 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 |
|---|
| 2096 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 |
|---|
| 2097 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 |
|---|
| 2098 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 |
|---|
| 2099 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 |
|---|
| 2100 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d |
|---|
| 2101 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff |
|---|
| 2102 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 |
|---|
| 2103 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00 |
|---|
| 2104 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 |
|---|
| 2105 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 |
|---|
| 2106 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 |
|---|
| 2107 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 |
|---|
| 2108 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 |
|---|
| 2109 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 |
|---|
| 2110 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 |
|---|
| 2111 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 |
|---|
| 2112 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 |
|---|
| 2113 | #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 |
|---|
| 2114 | #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c |
|---|
| 2115 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff |
|---|
| 2116 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 |
|---|
| 2117 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff |
|---|
| 2118 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 |
|---|
| 2119 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 |
|---|
| 2120 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 |
|---|
| 2121 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2122 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2123 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2124 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2125 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2126 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2127 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2128 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2129 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2130 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2131 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2132 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2133 | #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2134 | #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2135 | #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2136 | #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2137 | #define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf |
|---|
| 2138 | #define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 |
|---|
| 2139 | #define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 |
|---|
| 2140 | #define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 |
|---|
| 2141 | #define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 |
|---|
| 2142 | #define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 |
|---|
| 2143 | #define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 |
|---|
| 2144 | #define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc |
|---|
| 2145 | #define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 |
|---|
| 2146 | #define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 |
|---|
| 2147 | #define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 |
|---|
| 2148 | #define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 |
|---|
| 2149 | #define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 |
|---|
| 2150 | #define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 |
|---|
| 2151 | #define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 |
|---|
| 2152 | #define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c |
|---|
| 2153 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 |
|---|
| 2154 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 2155 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 |
|---|
| 2156 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 |
|---|
| 2157 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2158 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2159 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2160 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2161 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2162 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2163 | #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff |
|---|
| 2164 | #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 |
|---|
| 2165 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 |
|---|
| 2166 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 |
|---|
| 2167 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 |
|---|
| 2168 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 |
|---|
| 2169 | #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff |
|---|
| 2170 | #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 |
|---|
| 2171 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 |
|---|
| 2172 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 |
|---|
| 2173 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 |
|---|
| 2174 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 |
|---|
| 2175 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 |
|---|
| 2176 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
|---|
| 2177 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 |
|---|
| 2178 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c |
|---|
| 2179 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 |
|---|
| 2180 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 |
|---|
| 2181 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 |
|---|
| 2182 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 |
|---|
| 2183 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 |
|---|
| 2184 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 |
|---|
| 2185 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 |
|---|
| 2186 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 |
|---|
| 2187 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 |
|---|
| 2188 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 |
|---|
| 2189 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 |
|---|
| 2190 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 |
|---|
| 2191 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 |
|---|
| 2192 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 |
|---|
| 2193 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 |
|---|
| 2194 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 |
|---|
| 2195 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2196 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2197 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2198 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2199 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2200 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2201 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2202 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2203 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2204 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2205 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2206 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2207 | #define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2208 | #define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2209 | #define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2210 | #define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2211 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 |
|---|
| 2212 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 |
|---|
| 2213 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 |
|---|
| 2214 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 |
|---|
| 2215 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 |
|---|
| 2216 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 |
|---|
| 2217 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 |
|---|
| 2218 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 |
|---|
| 2219 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 |
|---|
| 2220 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb |
|---|
| 2221 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 |
|---|
| 2222 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc |
|---|
| 2223 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 |
|---|
| 2224 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 |
|---|
| 2225 | #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 |
|---|
| 2226 | #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 |
|---|
| 2227 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 |
|---|
| 2228 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 |
|---|
| 2229 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 |
|---|
| 2230 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 |
|---|
| 2231 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 |
|---|
| 2232 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc |
|---|
| 2233 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 |
|---|
| 2234 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 |
|---|
| 2235 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 |
|---|
| 2236 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 |
|---|
| 2237 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 |
|---|
| 2238 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e |
|---|
| 2239 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 |
|---|
| 2240 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f |
|---|
| 2241 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff |
|---|
| 2242 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 |
|---|
| 2243 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 |
|---|
| 2244 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 |
|---|
| 2245 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2246 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2247 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2248 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2249 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2250 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2251 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff |
|---|
| 2252 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 |
|---|
| 2253 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff |
|---|
| 2254 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 |
|---|
| 2255 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff |
|---|
| 2256 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 |
|---|
| 2257 | #define MCIF_VMID__MCIF_WR_VMID_MASK 0xf |
|---|
| 2258 | #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 |
|---|
| 2259 | #define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 |
|---|
| 2260 | #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 |
|---|
| 2261 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 |
|---|
| 2262 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 |
|---|
| 2263 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 |
|---|
| 2264 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 |
|---|
| 2265 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 |
|---|
| 2266 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 |
|---|
| 2267 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 |
|---|
| 2268 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 |
|---|
| 2269 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 |
|---|
| 2270 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 |
|---|
| 2271 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e |
|---|
| 2272 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 |
|---|
| 2273 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK 0x100 |
|---|
| 2274 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT 0x8 |
|---|
| 2275 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK 0x1e00 |
|---|
| 2276 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT 0x9 |
|---|
| 2277 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 |
|---|
| 2278 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 |
|---|
| 2279 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 |
|---|
| 2280 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 |
|---|
| 2281 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 |
|---|
| 2282 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 |
|---|
| 2283 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 |
|---|
| 2284 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc |
|---|
| 2285 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 |
|---|
| 2286 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 |
|---|
| 2287 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 |
|---|
| 2288 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 |
|---|
| 2289 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 |
|---|
| 2290 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 |
|---|
| 2291 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 |
|---|
| 2292 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c |
|---|
| 2293 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff |
|---|
| 2294 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 |
|---|
| 2295 | #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK 0xfff00000 |
|---|
| 2296 | #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT 0x14 |
|---|
| 2297 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff |
|---|
| 2298 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 |
|---|
| 2299 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 |
|---|
| 2300 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c |
|---|
| 2301 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 |
|---|
| 2302 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d |
|---|
| 2303 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 |
|---|
| 2304 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e |
|---|
| 2305 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 |
|---|
| 2306 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f |
|---|
| 2307 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 |
|---|
| 2308 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 |
|---|
| 2309 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 |
|---|
| 2310 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 |
|---|
| 2311 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 |
|---|
| 2312 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 |
|---|
| 2313 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 |
|---|
| 2314 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 |
|---|
| 2315 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 |
|---|
| 2316 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 2317 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 |
|---|
| 2318 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 |
|---|
| 2319 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 |
|---|
| 2320 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 |
|---|
| 2321 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 |
|---|
| 2322 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 |
|---|
| 2323 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 |
|---|
| 2324 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 |
|---|
| 2325 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 |
|---|
| 2326 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 |
|---|
| 2327 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 |
|---|
| 2328 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa |
|---|
| 2329 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 |
|---|
| 2330 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb |
|---|
| 2331 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 |
|---|
| 2332 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc |
|---|
| 2333 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 |
|---|
| 2334 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd |
|---|
| 2335 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 |
|---|
| 2336 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe |
|---|
| 2337 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x7 |
|---|
| 2338 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 |
|---|
| 2339 | #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK 0x8 |
|---|
| 2340 | #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT 0x3 |
|---|
| 2341 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 |
|---|
| 2342 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 |
|---|
| 2343 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 |
|---|
| 2344 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 |
|---|
| 2345 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 |
|---|
| 2346 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 |
|---|
| 2347 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 |
|---|
| 2348 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 |
|---|
| 2349 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc |
|---|
| 2350 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 |
|---|
| 2351 | #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 |
|---|
| 2352 | #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 2353 | #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 |
|---|
| 2354 | #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 |
|---|
| 2355 | #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 |
|---|
| 2356 | #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 |
|---|
| 2357 | #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 |
|---|
| 2358 | #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 |
|---|
| 2359 | #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 |
|---|
| 2360 | #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb |
|---|
| 2361 | #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 2362 | #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 2363 | #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 |
|---|
| 2364 | #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe |
|---|
| 2365 | #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000 |
|---|
| 2366 | #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10 |
|---|
| 2367 | #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000 |
|---|
| 2368 | #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12 |
|---|
| 2369 | #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000 |
|---|
| 2370 | #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14 |
|---|
| 2371 | #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 |
|---|
| 2372 | #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 |
|---|
| 2373 | #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 |
|---|
| 2374 | #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 |
|---|
| 2375 | #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 |
|---|
| 2376 | #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a |
|---|
| 2377 | #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 |
|---|
| 2378 | #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c |
|---|
| 2379 | #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 |
|---|
| 2380 | #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 |
|---|
| 2381 | #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc |
|---|
| 2382 | #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 |
|---|
| 2383 | #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 |
|---|
| 2384 | #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 2385 | #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 |
|---|
| 2386 | #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 |
|---|
| 2387 | #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 |
|---|
| 2388 | #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 |
|---|
| 2389 | #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 |
|---|
| 2390 | #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 |
|---|
| 2391 | #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 |
|---|
| 2392 | #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa |
|---|
| 2393 | #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 2394 | #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 2395 | #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 |
|---|
| 2396 | #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe |
|---|
| 2397 | #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 |
|---|
| 2398 | #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf |
|---|
| 2399 | #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 |
|---|
| 2400 | #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 |
|---|
| 2401 | #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 |
|---|
| 2402 | #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 |
|---|
| 2403 | #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 |
|---|
| 2404 | #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 |
|---|
| 2405 | #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 |
|---|
| 2406 | #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 |
|---|
| 2407 | #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 |
|---|
| 2408 | #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 |
|---|
| 2409 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f |
|---|
| 2410 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 |
|---|
| 2411 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 |
|---|
| 2412 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 |
|---|
| 2413 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 |
|---|
| 2414 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 |
|---|
| 2415 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 |
|---|
| 2416 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 |
|---|
| 2417 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 |
|---|
| 2418 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 |
|---|
| 2419 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 |
|---|
| 2420 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 |
|---|
| 2421 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 |
|---|
| 2422 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb |
|---|
| 2423 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 |
|---|
| 2424 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd |
|---|
| 2425 | #define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 |
|---|
| 2426 | #define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe |
|---|
| 2427 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 |
|---|
| 2428 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf |
|---|
| 2429 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 |
|---|
| 2430 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 |
|---|
| 2431 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 |
|---|
| 2432 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 |
|---|
| 2433 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 |
|---|
| 2434 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 |
|---|
| 2435 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 |
|---|
| 2436 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 |
|---|
| 2437 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 |
|---|
| 2438 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 |
|---|
| 2439 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 |
|---|
| 2440 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 |
|---|
| 2441 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 |
|---|
| 2442 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 |
|---|
| 2443 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 |
|---|
| 2444 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 |
|---|
| 2445 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 |
|---|
| 2446 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 |
|---|
| 2447 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000 |
|---|
| 2448 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19 |
|---|
| 2449 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000 |
|---|
| 2450 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a |
|---|
| 2451 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 |
|---|
| 2452 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b |
|---|
| 2453 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2454 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2455 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2456 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2457 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 |
|---|
| 2458 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2459 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 |
|---|
| 2460 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 |
|---|
| 2461 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 |
|---|
| 2462 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 |
|---|
| 2463 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 |
|---|
| 2464 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 |
|---|
| 2465 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 |
|---|
| 2466 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 |
|---|
| 2467 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 |
|---|
| 2468 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 |
|---|
| 2469 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 |
|---|
| 2470 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 |
|---|
| 2471 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 |
|---|
| 2472 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb |
|---|
| 2473 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 |
|---|
| 2474 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc |
|---|
| 2475 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2476 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2477 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 |
|---|
| 2478 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2479 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 |
|---|
| 2480 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 |
|---|
| 2481 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 |
|---|
| 2482 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 |
|---|
| 2483 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 |
|---|
| 2484 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 |
|---|
| 2485 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 |
|---|
| 2486 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 |
|---|
| 2487 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 |
|---|
| 2488 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 |
|---|
| 2489 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 |
|---|
| 2490 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 |
|---|
| 2491 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 |
|---|
| 2492 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 |
|---|
| 2493 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 |
|---|
| 2494 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a |
|---|
| 2495 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 |
|---|
| 2496 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c |
|---|
| 2497 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 |
|---|
| 2498 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d |
|---|
| 2499 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 |
|---|
| 2500 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e |
|---|
| 2501 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2502 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2503 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2504 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2505 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 |
|---|
| 2506 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2507 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 |
|---|
| 2508 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 |
|---|
| 2509 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 |
|---|
| 2510 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 |
|---|
| 2511 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 |
|---|
| 2512 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 |
|---|
| 2513 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 |
|---|
| 2514 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 |
|---|
| 2515 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 |
|---|
| 2516 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa |
|---|
| 2517 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 |
|---|
| 2518 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb |
|---|
| 2519 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2520 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2521 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 |
|---|
| 2522 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2523 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 |
|---|
| 2524 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf |
|---|
| 2525 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 |
|---|
| 2526 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 |
|---|
| 2527 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 |
|---|
| 2528 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 |
|---|
| 2529 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 |
|---|
| 2530 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 |
|---|
| 2531 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 |
|---|
| 2532 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 |
|---|
| 2533 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 |
|---|
| 2534 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 |
|---|
| 2535 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 |
|---|
| 2536 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 |
|---|
| 2537 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 |
|---|
| 2538 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 |
|---|
| 2539 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 |
|---|
| 2540 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a |
|---|
| 2541 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 |
|---|
| 2542 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b |
|---|
| 2543 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 |
|---|
| 2544 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d |
|---|
| 2545 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 |
|---|
| 2546 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e |
|---|
| 2547 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 |
|---|
| 2548 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f |
|---|
| 2549 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2550 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2551 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2552 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2553 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 |
|---|
| 2554 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2555 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 |
|---|
| 2556 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 |
|---|
| 2557 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 |
|---|
| 2558 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 |
|---|
| 2559 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 |
|---|
| 2560 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 |
|---|
| 2561 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 |
|---|
| 2562 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 |
|---|
| 2563 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 |
|---|
| 2564 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa |
|---|
| 2565 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 |
|---|
| 2566 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb |
|---|
| 2567 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2568 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2569 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 |
|---|
| 2570 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2571 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 |
|---|
| 2572 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf |
|---|
| 2573 | #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 |
|---|
| 2574 | #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 |
|---|
| 2575 | #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 |
|---|
| 2576 | #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 |
|---|
| 2577 | #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 |
|---|
| 2578 | #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 |
|---|
| 2579 | #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 |
|---|
| 2580 | #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 |
|---|
| 2581 | #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 |
|---|
| 2582 | #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 |
|---|
| 2583 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 |
|---|
| 2584 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 |
|---|
| 2585 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 |
|---|
| 2586 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b |
|---|
| 2587 | #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 |
|---|
| 2588 | #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d |
|---|
| 2589 | #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 |
|---|
| 2590 | #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 |
|---|
| 2591 | #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 |
|---|
| 2592 | #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 |
|---|
| 2593 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 |
|---|
| 2594 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 |
|---|
| 2595 | #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 |
|---|
| 2596 | #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 |
|---|
| 2597 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 |
|---|
| 2598 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 |
|---|
| 2599 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 |
|---|
| 2600 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 |
|---|
| 2601 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 |
|---|
| 2602 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 |
|---|
| 2603 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 |
|---|
| 2604 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 |
|---|
| 2605 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 |
|---|
| 2606 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 |
|---|
| 2607 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 |
|---|
| 2608 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 |
|---|
| 2609 | #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 |
|---|
| 2610 | #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa |
|---|
| 2611 | #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 |
|---|
| 2612 | #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb |
|---|
| 2613 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 |
|---|
| 2614 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc |
|---|
| 2615 | #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 |
|---|
| 2616 | #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 |
|---|
| 2617 | #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 |
|---|
| 2618 | #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 |
|---|
| 2619 | #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 |
|---|
| 2620 | #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 |
|---|
| 2621 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2622 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2623 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2624 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2625 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2626 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2627 | #define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 |
|---|
| 2628 | #define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 |
|---|
| 2629 | #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 |
|---|
| 2630 | #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 |
|---|
| 2631 | #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 |
|---|
| 2632 | #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 |
|---|
| 2633 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2634 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2635 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2636 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2637 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2638 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2639 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2640 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2641 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2642 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2643 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2644 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2645 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2646 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2647 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2648 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2649 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2650 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2651 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2652 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2653 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2654 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2655 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2656 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2657 | #define DC_GENERICA__GENERICA_EN_MASK 0x1 |
|---|
| 2658 | #define DC_GENERICA__GENERICA_EN__SHIFT 0x0 |
|---|
| 2659 | #define DC_GENERICA__GENERICA_SEL_MASK 0xf80 |
|---|
| 2660 | #define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 |
|---|
| 2661 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
|---|
| 2662 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
|---|
| 2663 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
|---|
| 2664 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
|---|
| 2665 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
|---|
| 2666 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
|---|
| 2667 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
|---|
| 2668 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
|---|
| 2669 | #define DC_GENERICB__GENERICB_EN_MASK 0x1 |
|---|
| 2670 | #define DC_GENERICB__GENERICB_EN__SHIFT 0x0 |
|---|
| 2671 | #define DC_GENERICB__GENERICB_SEL_MASK 0xf00 |
|---|
| 2672 | #define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 |
|---|
| 2673 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
|---|
| 2674 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
|---|
| 2675 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
|---|
| 2676 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
|---|
| 2677 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
|---|
| 2678 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
|---|
| 2679 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
|---|
| 2680 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
|---|
| 2681 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf |
|---|
| 2682 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 |
|---|
| 2683 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 |
|---|
| 2684 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 |
|---|
| 2685 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 |
|---|
| 2686 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 |
|---|
| 2687 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 |
|---|
| 2688 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 |
|---|
| 2689 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 |
|---|
| 2690 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 |
|---|
| 2691 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 |
|---|
| 2692 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 |
|---|
| 2693 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 |
|---|
| 2694 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 |
|---|
| 2695 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 |
|---|
| 2696 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 |
|---|
| 2697 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 |
|---|
| 2698 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f |
|---|
| 2699 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2700 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2701 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2702 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2703 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2704 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2705 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2706 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2707 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2708 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2709 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2710 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2711 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2712 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2713 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2714 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2715 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2716 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2717 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2718 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2719 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2720 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2721 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2722 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2723 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2724 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2725 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2726 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2727 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2728 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2729 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2730 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2731 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2732 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2733 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2734 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2735 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2736 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2737 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2738 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2739 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2740 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2741 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2742 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2743 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2744 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2745 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2746 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2747 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2748 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2749 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2750 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2751 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2752 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2753 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2754 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2755 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2756 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2757 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2758 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2759 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2760 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2761 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2762 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2763 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2764 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2765 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2766 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2767 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2768 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2769 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2770 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2771 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2772 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2773 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2774 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2775 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2776 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2777 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2778 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2779 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2780 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2781 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2782 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2783 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2784 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2785 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2786 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2787 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2788 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2789 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2790 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2791 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2792 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2793 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2794 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2795 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2796 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2797 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2798 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2799 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2800 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2801 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2802 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2803 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2804 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2805 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2806 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2807 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2808 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2809 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2810 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2811 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2812 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2813 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2814 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2815 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2816 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2817 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2818 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2819 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2820 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2821 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2822 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2823 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2824 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2825 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2826 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2827 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2828 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2829 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2830 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2831 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2832 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2833 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2834 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2835 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2836 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2837 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2838 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2839 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2840 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2841 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2842 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2843 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2844 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2845 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2846 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2847 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2848 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2849 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2850 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2851 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2852 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2853 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2854 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2855 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2856 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2857 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2858 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2859 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2860 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2861 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2862 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2863 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2864 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2865 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2866 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2867 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2868 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2869 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2870 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2871 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2872 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2873 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2874 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2875 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2876 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2877 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2878 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2879 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2880 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2881 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2882 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2883 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2884 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2885 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2886 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2887 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2888 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2889 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2890 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2891 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2892 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2893 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2894 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2895 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 |
|---|
| 2896 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 |
|---|
| 2897 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 |
|---|
| 2898 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 |
|---|
| 2899 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 |
|---|
| 2900 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 |
|---|
| 2901 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 |
|---|
| 2902 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa |
|---|
| 2903 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 |
|---|
| 2904 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 |
|---|
| 2905 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 |
|---|
| 2906 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 |
|---|
| 2907 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 |
|---|
| 2908 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 |
|---|
| 2909 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 |
|---|
| 2910 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c |
|---|
| 2911 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 |
|---|
| 2912 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e |
|---|
| 2913 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 |
|---|
| 2914 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 |
|---|
| 2915 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 |
|---|
| 2916 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 |
|---|
| 2917 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 |
|---|
| 2918 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 |
|---|
| 2919 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 |
|---|
| 2920 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa |
|---|
| 2921 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 |
|---|
| 2922 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 |
|---|
| 2923 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 |
|---|
| 2924 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 |
|---|
| 2925 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 |
|---|
| 2926 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 |
|---|
| 2927 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 |
|---|
| 2928 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c |
|---|
| 2929 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 |
|---|
| 2930 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e |
|---|
| 2931 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 |
|---|
| 2932 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 |
|---|
| 2933 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 |
|---|
| 2934 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 |
|---|
| 2935 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 |
|---|
| 2936 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 |
|---|
| 2937 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 |
|---|
| 2938 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa |
|---|
| 2939 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 |
|---|
| 2940 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 |
|---|
| 2941 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 |
|---|
| 2942 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 |
|---|
| 2943 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 |
|---|
| 2944 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 |
|---|
| 2945 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 |
|---|
| 2946 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c |
|---|
| 2947 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 |
|---|
| 2948 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e |
|---|
| 2949 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 |
|---|
| 2950 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 |
|---|
| 2951 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 |
|---|
| 2952 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 |
|---|
| 2953 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 |
|---|
| 2954 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 |
|---|
| 2955 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 |
|---|
| 2956 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa |
|---|
| 2957 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 |
|---|
| 2958 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 |
|---|
| 2959 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 |
|---|
| 2960 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 |
|---|
| 2961 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 |
|---|
| 2962 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 |
|---|
| 2963 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 |
|---|
| 2964 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c |
|---|
| 2965 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 |
|---|
| 2966 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e |
|---|
| 2967 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 |
|---|
| 2968 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 |
|---|
| 2969 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 |
|---|
| 2970 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 |
|---|
| 2971 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 |
|---|
| 2972 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 |
|---|
| 2973 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 |
|---|
| 2974 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa |
|---|
| 2975 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 |
|---|
| 2976 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 |
|---|
| 2977 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 |
|---|
| 2978 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 |
|---|
| 2979 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 |
|---|
| 2980 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 |
|---|
| 2981 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 |
|---|
| 2982 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c |
|---|
| 2983 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 |
|---|
| 2984 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e |
|---|
| 2985 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 |
|---|
| 2986 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 |
|---|
| 2987 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 |
|---|
| 2988 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 |
|---|
| 2989 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 |
|---|
| 2990 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 |
|---|
| 2991 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 |
|---|
| 2992 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa |
|---|
| 2993 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 |
|---|
| 2994 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 |
|---|
| 2995 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 |
|---|
| 2996 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 |
|---|
| 2997 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 |
|---|
| 2998 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 |
|---|
| 2999 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 |
|---|
| 3000 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c |
|---|
| 3001 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 |
|---|
| 3002 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e |
|---|
| 3003 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff |
|---|
| 3004 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 |
|---|
| 3005 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 |
|---|
| 3006 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 |
|---|
| 3007 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 |
|---|
| 3008 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 |
|---|
| 3009 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 |
|---|
| 3010 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 |
|---|
| 3011 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 |
|---|
| 3012 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa |
|---|
| 3013 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 |
|---|
| 3014 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 |
|---|
| 3015 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 |
|---|
| 3016 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 |
|---|
| 3017 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 |
|---|
| 3018 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 |
|---|
| 3019 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
|---|
| 3020 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
|---|
| 3021 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 |
|---|
| 3022 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 |
|---|
| 3023 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 |
|---|
| 3024 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 |
|---|
| 3025 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 |
|---|
| 3026 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 |
|---|
| 3027 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 |
|---|
| 3028 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa |
|---|
| 3029 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 |
|---|
| 3030 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 |
|---|
| 3031 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 |
|---|
| 3032 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 |
|---|
| 3033 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 |
|---|
| 3034 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 |
|---|
| 3035 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
|---|
| 3036 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
|---|
| 3037 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3038 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3039 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3040 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3041 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3042 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3043 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3044 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3045 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 |
|---|
| 3046 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf |
|---|
| 3047 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff |
|---|
| 3048 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 |
|---|
| 3049 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 |
|---|
| 3050 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 |
|---|
| 3051 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3052 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3053 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3054 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3055 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3056 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3057 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3058 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3059 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff |
|---|
| 3060 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 |
|---|
| 3061 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 |
|---|
| 3062 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 |
|---|
| 3063 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3064 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3065 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3066 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3067 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3068 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3069 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3070 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3071 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff |
|---|
| 3072 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 |
|---|
| 3073 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 |
|---|
| 3074 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 |
|---|
| 3075 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf |
|---|
| 3076 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 |
|---|
| 3077 | #define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 |
|---|
| 3078 | #define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 |
|---|
| 3079 | #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 |
|---|
| 3080 | #define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 |
|---|
| 3081 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 |
|---|
| 3082 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc |
|---|
| 3083 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 |
|---|
| 3084 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa |
|---|
| 3085 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 |
|---|
| 3086 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd |
|---|
| 3087 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 |
|---|
| 3088 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe |
|---|
| 3089 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 |
|---|
| 3090 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 |
|---|
| 3091 | #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 |
|---|
| 3092 | #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 |
|---|
| 3093 | #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 |
|---|
| 3094 | #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 |
|---|
| 3095 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 |
|---|
| 3096 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 |
|---|
| 3097 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 |
|---|
| 3098 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 |
|---|
| 3099 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 |
|---|
| 3100 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 |
|---|
| 3101 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 |
|---|
| 3102 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 |
|---|
| 3103 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 |
|---|
| 3104 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 |
|---|
| 3105 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 |
|---|
| 3106 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 |
|---|
| 3107 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 |
|---|
| 3108 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 |
|---|
| 3109 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 |
|---|
| 3110 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa |
|---|
| 3111 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 |
|---|
| 3112 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 |
|---|
| 3113 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 |
|---|
| 3114 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 |
|---|
| 3115 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 |
|---|
| 3116 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 |
|---|
| 3117 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 |
|---|
| 3118 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 |
|---|
| 3119 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 |
|---|
| 3120 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 |
|---|
| 3121 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 |
|---|
| 3122 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a |
|---|
| 3123 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 |
|---|
| 3124 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 |
|---|
| 3125 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 |
|---|
| 3126 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 |
|---|
| 3127 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 |
|---|
| 3128 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 |
|---|
| 3129 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 |
|---|
| 3130 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 |
|---|
| 3131 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 |
|---|
| 3132 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 |
|---|
| 3133 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 |
|---|
| 3134 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 |
|---|
| 3135 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff |
|---|
| 3136 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 |
|---|
| 3137 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 |
|---|
| 3138 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 |
|---|
| 3139 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff |
|---|
| 3140 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 |
|---|
| 3141 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 |
|---|
| 3142 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 |
|---|
| 3143 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 |
|---|
| 3144 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 |
|---|
| 3145 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 |
|---|
| 3146 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 |
|---|
| 3147 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff |
|---|
| 3148 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 |
|---|
| 3149 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 |
|---|
| 3150 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 |
|---|
| 3151 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 |
|---|
| 3152 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 |
|---|
| 3153 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 |
|---|
| 3154 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 |
|---|
| 3155 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff |
|---|
| 3156 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 |
|---|
| 3157 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 |
|---|
| 3158 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e |
|---|
| 3159 | #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 |
|---|
| 3160 | #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f |
|---|
| 3161 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff |
|---|
| 3162 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 |
|---|
| 3163 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 |
|---|
| 3164 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c |
|---|
| 3165 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 |
|---|
| 3166 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e |
|---|
| 3167 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 |
|---|
| 3168 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f |
|---|
| 3169 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff |
|---|
| 3170 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 |
|---|
| 3171 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 |
|---|
| 3172 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 |
|---|
| 3173 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 |
|---|
| 3174 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 |
|---|
| 3175 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 |
|---|
| 3176 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 |
|---|
| 3177 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 |
|---|
| 3178 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 |
|---|
| 3179 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 |
|---|
| 3180 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 |
|---|
| 3181 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
|---|
| 3182 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
|---|
| 3183 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
|---|
| 3184 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
|---|
| 3185 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 |
|---|
| 3186 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
|---|
| 3187 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 |
|---|
| 3188 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
|---|
| 3189 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 |
|---|
| 3190 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 |
|---|
| 3191 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
|---|
| 3192 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
|---|
| 3193 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
|---|
| 3194 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
|---|
| 3195 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 |
|---|
| 3196 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 |
|---|
| 3197 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 |
|---|
| 3198 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
|---|
| 3199 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 |
|---|
| 3200 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
|---|
| 3201 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 |
|---|
| 3202 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 |
|---|
| 3203 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
|---|
| 3204 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
|---|
| 3205 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
|---|
| 3206 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
|---|
| 3207 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 |
|---|
| 3208 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 |
|---|
| 3209 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 |
|---|
| 3210 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3211 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3212 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3213 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3214 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3215 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 |
|---|
| 3216 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3217 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3218 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3219 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3220 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3221 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 |
|---|
| 3222 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3223 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3224 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3225 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3226 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3227 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 |
|---|
| 3228 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 |
|---|
| 3229 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 |
|---|
| 3230 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 |
|---|
| 3231 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 |
|---|
| 3232 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 |
|---|
| 3233 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 |
|---|
| 3234 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc |
|---|
| 3235 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 |
|---|
| 3236 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 |
|---|
| 3237 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 |
|---|
| 3238 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 |
|---|
| 3239 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 |
|---|
| 3240 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 |
|---|
| 3241 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 |
|---|
| 3242 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 |
|---|
| 3243 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 |
|---|
| 3244 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 |
|---|
| 3245 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 |
|---|
| 3246 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc |
|---|
| 3247 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 |
|---|
| 3248 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 |
|---|
| 3249 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 |
|---|
| 3250 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 |
|---|
| 3251 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff |
|---|
| 3252 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 |
|---|
| 3253 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f |
|---|
| 3254 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 |
|---|
| 3255 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 |
|---|
| 3256 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 |
|---|
| 3257 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 |
|---|
| 3258 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb |
|---|
| 3259 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 |
|---|
| 3260 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe |
|---|
| 3261 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 |
|---|
| 3262 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 |
|---|
| 3263 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 |
|---|
| 3264 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 |
|---|
| 3265 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 |
|---|
| 3266 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 |
|---|
| 3267 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f |
|---|
| 3268 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 |
|---|
| 3269 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 |
|---|
| 3270 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 |
|---|
| 3271 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK 0x100 |
|---|
| 3272 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT 0x8 |
|---|
| 3273 | #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff |
|---|
| 3274 | #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 |
|---|
| 3275 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 |
|---|
| 3276 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 |
|---|
| 3277 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 |
|---|
| 3278 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 |
|---|
| 3279 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 |
|---|
| 3280 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 |
|---|
| 3281 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 |
|---|
| 3282 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc |
|---|
| 3283 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 |
|---|
| 3284 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 |
|---|
| 3285 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 |
|---|
| 3286 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 |
|---|
| 3287 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 |
|---|
| 3288 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 |
|---|
| 3289 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 |
|---|
| 3290 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c |
|---|
| 3291 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 |
|---|
| 3292 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f |
|---|
| 3293 | #define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 |
|---|
| 3294 | #define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 |
|---|
| 3295 | #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 |
|---|
| 3296 | #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 |
|---|
| 3297 | #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 |
|---|
| 3298 | #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 |
|---|
| 3299 | #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 |
|---|
| 3300 | #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc |
|---|
| 3301 | #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 |
|---|
| 3302 | #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 |
|---|
| 3303 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 |
|---|
| 3304 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 |
|---|
| 3305 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 |
|---|
| 3306 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 |
|---|
| 3307 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 |
|---|
| 3308 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 |
|---|
| 3309 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 |
|---|
| 3310 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 |
|---|
| 3311 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 |
|---|
| 3312 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 |
|---|
| 3313 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 |
|---|
| 3314 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 |
|---|
| 3315 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 |
|---|
| 3316 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 |
|---|
| 3317 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 |
|---|
| 3318 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 |
|---|
| 3319 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 |
|---|
| 3320 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 |
|---|
| 3321 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 |
|---|
| 3322 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 |
|---|
| 3323 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 |
|---|
| 3324 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa |
|---|
| 3325 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 |
|---|
| 3326 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb |
|---|
| 3327 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 |
|---|
| 3328 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc |
|---|
| 3329 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 |
|---|
| 3330 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd |
|---|
| 3331 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 |
|---|
| 3332 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 |
|---|
| 3333 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 |
|---|
| 3334 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 |
|---|
| 3335 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 |
|---|
| 3336 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 |
|---|
| 3337 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 |
|---|
| 3338 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 |
|---|
| 3339 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc |
|---|
| 3340 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 |
|---|
| 3341 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 |
|---|
| 3342 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 |
|---|
| 3343 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 |
|---|
| 3344 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 |
|---|
| 3345 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 3346 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 3347 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 3348 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 3349 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 3350 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 3351 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 |
|---|
| 3352 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 |
|---|
| 3353 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc |
|---|
| 3354 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 |
|---|
| 3355 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 |
|---|
| 3356 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 |
|---|
| 3357 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 |
|---|
| 3358 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 |
|---|
| 3359 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 |
|---|
| 3360 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 |
|---|
| 3361 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 |
|---|
| 3362 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa |
|---|
| 3363 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 |
|---|
| 3364 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc |
|---|
| 3365 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 |
|---|
| 3366 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd |
|---|
| 3367 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 |
|---|
| 3368 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe |
|---|
| 3369 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 |
|---|
| 3370 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf |
|---|
| 3371 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 |
|---|
| 3372 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 |
|---|
| 3373 | #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 |
|---|
| 3374 | #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 |
|---|
| 3375 | #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 |
|---|
| 3376 | #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 |
|---|
| 3377 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 |
|---|
| 3378 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 |
|---|
| 3379 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 |
|---|
| 3380 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 |
|---|
| 3381 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 |
|---|
| 3382 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 |
|---|
| 3383 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 |
|---|
| 3384 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 |
|---|
| 3385 | #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 |
|---|
| 3386 | #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 |
|---|
| 3387 | #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 |
|---|
| 3388 | #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 |
|---|
| 3389 | #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 |
|---|
| 3390 | #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 |
|---|
| 3391 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 |
|---|
| 3392 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a |
|---|
| 3393 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 |
|---|
| 3394 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b |
|---|
| 3395 | #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff |
|---|
| 3396 | #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 |
|---|
| 3397 | #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff |
|---|
| 3398 | #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 |
|---|
| 3399 | #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff |
|---|
| 3400 | #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 |
|---|
| 3401 | #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff |
|---|
| 3402 | #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 |
|---|
| 3403 | #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff |
|---|
| 3404 | #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 |
|---|
| 3405 | #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff |
|---|
| 3406 | #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 |
|---|
| 3407 | #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff |
|---|
| 3408 | #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 |
|---|
| 3409 | #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff |
|---|
| 3410 | #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 |
|---|
| 3411 | #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff |
|---|
| 3412 | #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 |
|---|
| 3413 | #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff |
|---|
| 3414 | #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 |
|---|
| 3415 | #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff |
|---|
| 3416 | #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 |
|---|
| 3417 | #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff |
|---|
| 3418 | #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 |
|---|
| 3419 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff |
|---|
| 3420 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 |
|---|
| 3421 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff |
|---|
| 3422 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 |
|---|
| 3423 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff |
|---|
| 3424 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 |
|---|
| 3425 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff |
|---|
| 3426 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 |
|---|
| 3427 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff |
|---|
| 3428 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 |
|---|
| 3429 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff |
|---|
| 3430 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 |
|---|
| 3431 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff |
|---|
| 3432 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 |
|---|
| 3433 | #define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff |
|---|
| 3434 | #define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 |
|---|
| 3435 | #define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff |
|---|
| 3436 | #define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 |
|---|
| 3437 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff |
|---|
| 3438 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 |
|---|
| 3439 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 |
|---|
| 3440 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 |
|---|
| 3441 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 |
|---|
| 3442 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 |
|---|
| 3443 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 |
|---|
| 3444 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 |
|---|
| 3445 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 |
|---|
| 3446 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 |
|---|
| 3447 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 |
|---|
| 3448 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 |
|---|
| 3449 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 |
|---|
| 3450 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 |
|---|
| 3451 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 |
|---|
| 3452 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 |
|---|
| 3453 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 |
|---|
| 3454 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 |
|---|
| 3455 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 |
|---|
| 3456 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa |
|---|
| 3457 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 |
|---|
| 3458 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc |
|---|
| 3459 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 |
|---|
| 3460 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd |
|---|
| 3461 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 |
|---|
| 3462 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe |
|---|
| 3463 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 |
|---|
| 3464 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 |
|---|
| 3465 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 |
|---|
| 3466 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 |
|---|
| 3467 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 |
|---|
| 3468 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 |
|---|
| 3469 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 |
|---|
| 3470 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 |
|---|
| 3471 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 |
|---|
| 3472 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 |
|---|
| 3473 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 |
|---|
| 3474 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 |
|---|
| 3475 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 |
|---|
| 3476 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 |
|---|
| 3477 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 |
|---|
| 3478 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 |
|---|
| 3479 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 |
|---|
| 3480 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a |
|---|
| 3481 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 |
|---|
| 3482 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 |
|---|
| 3483 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 |
|---|
| 3484 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 |
|---|
| 3485 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 |
|---|
| 3486 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 |
|---|
| 3487 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 |
|---|
| 3488 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 |
|---|
| 3489 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 |
|---|
| 3490 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 |
|---|
| 3491 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 |
|---|
| 3492 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 |
|---|
| 3493 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 |
|---|
| 3494 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 |
|---|
| 3495 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 |
|---|
| 3496 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 |
|---|
| 3497 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 |
|---|
| 3498 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 |
|---|
| 3499 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 |
|---|
| 3500 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 |
|---|
| 3501 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 |
|---|
| 3502 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 |
|---|
| 3503 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 |
|---|
| 3504 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 |
|---|
| 3505 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 |
|---|
| 3506 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 |
|---|
| 3507 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 |
|---|
| 3508 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 |
|---|
| 3509 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 |
|---|
| 3510 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 |
|---|
| 3511 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 |
|---|
| 3512 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 |
|---|
| 3513 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 |
|---|
| 3514 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 |
|---|
| 3515 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 |
|---|
| 3516 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 |
|---|
| 3517 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 |
|---|
| 3518 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 |
|---|
| 3519 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 |
|---|
| 3520 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 |
|---|
| 3521 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 |
|---|
| 3522 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 |
|---|
| 3523 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff |
|---|
| 3524 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 |
|---|
| 3525 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 |
|---|
| 3526 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 |
|---|
| 3527 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 |
|---|
| 3528 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d |
|---|
| 3529 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 |
|---|
| 3530 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e |
|---|
| 3531 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff |
|---|
| 3532 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 |
|---|
| 3533 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 |
|---|
| 3534 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 |
|---|
| 3535 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 |
|---|
| 3536 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d |
|---|
| 3537 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 |
|---|
| 3538 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e |
|---|
| 3539 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff |
|---|
| 3540 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 |
|---|
| 3541 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 |
|---|
| 3542 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 |
|---|
| 3543 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 |
|---|
| 3544 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d |
|---|
| 3545 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 |
|---|
| 3546 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e |
|---|
| 3547 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff |
|---|
| 3548 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 |
|---|
| 3549 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 |
|---|
| 3550 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 |
|---|
| 3551 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 |
|---|
| 3552 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d |
|---|
| 3553 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 |
|---|
| 3554 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e |
|---|
| 3555 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 |
|---|
| 3556 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 |
|---|
| 3557 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 |
|---|
| 3558 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 |
|---|
| 3559 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 |
|---|
| 3560 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 |
|---|
| 3561 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 |
|---|
| 3562 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 |
|---|
| 3563 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 |
|---|
| 3564 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc |
|---|
| 3565 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 |
|---|
| 3566 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe |
|---|
| 3567 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 |
|---|
| 3568 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 |
|---|
| 3569 | #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 |
|---|
| 3570 | #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 |
|---|
| 3571 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 |
|---|
| 3572 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 |
|---|
| 3573 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 |
|---|
| 3574 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 |
|---|
| 3575 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 |
|---|
| 3576 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c |
|---|
| 3577 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 |
|---|
| 3578 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 |
|---|
| 3579 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 |
|---|
| 3580 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 |
|---|
| 3581 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 |
|---|
| 3582 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 |
|---|
| 3583 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 |
|---|
| 3584 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 |
|---|
| 3585 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 |
|---|
| 3586 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 |
|---|
| 3587 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 |
|---|
| 3588 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 |
|---|
| 3589 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 |
|---|
| 3590 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 |
|---|
| 3591 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 |
|---|
| 3592 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 |
|---|
| 3593 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 |
|---|
| 3594 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 |
|---|
| 3595 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 |
|---|
| 3596 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 |
|---|
| 3597 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 |
|---|
| 3598 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc |
|---|
| 3599 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 |
|---|
| 3600 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe |
|---|
| 3601 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 |
|---|
| 3602 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 |
|---|
| 3603 | #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 |
|---|
| 3604 | #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 |
|---|
| 3605 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 |
|---|
| 3606 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 |
|---|
| 3607 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 |
|---|
| 3608 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 |
|---|
| 3609 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 |
|---|
| 3610 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c |
|---|
| 3611 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 |
|---|
| 3612 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 |
|---|
| 3613 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 |
|---|
| 3614 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 |
|---|
| 3615 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 |
|---|
| 3616 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 |
|---|
| 3617 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 |
|---|
| 3618 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 |
|---|
| 3619 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 |
|---|
| 3620 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 |
|---|
| 3621 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 |
|---|
| 3622 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 |
|---|
| 3623 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 |
|---|
| 3624 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 |
|---|
| 3625 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 |
|---|
| 3626 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 |
|---|
| 3627 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 |
|---|
| 3628 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 |
|---|
| 3629 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 |
|---|
| 3630 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 |
|---|
| 3631 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 |
|---|
| 3632 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc |
|---|
| 3633 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 |
|---|
| 3634 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe |
|---|
| 3635 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 |
|---|
| 3636 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 |
|---|
| 3637 | #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 |
|---|
| 3638 | #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 |
|---|
| 3639 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 |
|---|
| 3640 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 |
|---|
| 3641 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 |
|---|
| 3642 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 |
|---|
| 3643 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 |
|---|
| 3644 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c |
|---|
| 3645 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 |
|---|
| 3646 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 |
|---|
| 3647 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 |
|---|
| 3648 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 |
|---|
| 3649 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 |
|---|
| 3650 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 |
|---|
| 3651 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 |
|---|
| 3652 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 |
|---|
| 3653 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 |
|---|
| 3654 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 |
|---|
| 3655 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 |
|---|
| 3656 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 |
|---|
| 3657 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 |
|---|
| 3658 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 |
|---|
| 3659 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 |
|---|
| 3660 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 |
|---|
| 3661 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 |
|---|
| 3662 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 |
|---|
| 3663 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 |
|---|
| 3664 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 |
|---|
| 3665 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 |
|---|
| 3666 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc |
|---|
| 3667 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 |
|---|
| 3668 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe |
|---|
| 3669 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 |
|---|
| 3670 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 |
|---|
| 3671 | #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 |
|---|
| 3672 | #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 |
|---|
| 3673 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 |
|---|
| 3674 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 |
|---|
| 3675 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 |
|---|
| 3676 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 |
|---|
| 3677 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 |
|---|
| 3678 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c |
|---|
| 3679 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 |
|---|
| 3680 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 |
|---|
| 3681 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 |
|---|
| 3682 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 |
|---|
| 3683 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 |
|---|
| 3684 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 |
|---|
| 3685 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 |
|---|
| 3686 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 |
|---|
| 3687 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 |
|---|
| 3688 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 |
|---|
| 3689 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 |
|---|
| 3690 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 |
|---|
| 3691 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 |
|---|
| 3692 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 |
|---|
| 3693 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 |
|---|
| 3694 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 |
|---|
| 3695 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 |
|---|
| 3696 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 |
|---|
| 3697 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 |
|---|
| 3698 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 |
|---|
| 3699 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 |
|---|
| 3700 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc |
|---|
| 3701 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 |
|---|
| 3702 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe |
|---|
| 3703 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 |
|---|
| 3704 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 |
|---|
| 3705 | #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 |
|---|
| 3706 | #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 |
|---|
| 3707 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 |
|---|
| 3708 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 |
|---|
| 3709 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 |
|---|
| 3710 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 |
|---|
| 3711 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 |
|---|
| 3712 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c |
|---|
| 3713 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 |
|---|
| 3714 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 |
|---|
| 3715 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 |
|---|
| 3716 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 |
|---|
| 3717 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 |
|---|
| 3718 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 |
|---|
| 3719 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 |
|---|
| 3720 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 |
|---|
| 3721 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 |
|---|
| 3722 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 |
|---|
| 3723 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 |
|---|
| 3724 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 |
|---|
| 3725 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 |
|---|
| 3726 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 |
|---|
| 3727 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 |
|---|
| 3728 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 |
|---|
| 3729 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 |
|---|
| 3730 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 |
|---|
| 3731 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 |
|---|
| 3732 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 |
|---|
| 3733 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 |
|---|
| 3734 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc |
|---|
| 3735 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 |
|---|
| 3736 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe |
|---|
| 3737 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 |
|---|
| 3738 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 |
|---|
| 3739 | #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 |
|---|
| 3740 | #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 |
|---|
| 3741 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 |
|---|
| 3742 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 |
|---|
| 3743 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 |
|---|
| 3744 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 |
|---|
| 3745 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 |
|---|
| 3746 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c |
|---|
| 3747 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 |
|---|
| 3748 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 |
|---|
| 3749 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 |
|---|
| 3750 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 |
|---|
| 3751 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 |
|---|
| 3752 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 |
|---|
| 3753 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 |
|---|
| 3754 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 |
|---|
| 3755 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 |
|---|
| 3756 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 |
|---|
| 3757 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 |
|---|
| 3758 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 |
|---|
| 3759 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 |
|---|
| 3760 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 |
|---|
| 3761 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 |
|---|
| 3762 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 |
|---|
| 3763 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 |
|---|
| 3764 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 |
|---|
| 3765 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 |
|---|
| 3766 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc |
|---|
| 3767 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 |
|---|
| 3768 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe |
|---|
| 3769 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 |
|---|
| 3770 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 |
|---|
| 3771 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 |
|---|
| 3772 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 |
|---|
| 3773 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 |
|---|
| 3774 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 |
|---|
| 3775 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 |
|---|
| 3776 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 |
|---|
| 3777 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 |
|---|
| 3778 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c |
|---|
| 3779 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 |
|---|
| 3780 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 |
|---|
| 3781 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 |
|---|
| 3782 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 |
|---|
| 3783 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 |
|---|
| 3784 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 |
|---|
| 3785 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 |
|---|
| 3786 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 |
|---|
| 3787 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 |
|---|
| 3788 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 |
|---|
| 3789 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 |
|---|
| 3790 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 |
|---|
| 3791 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 |
|---|
| 3792 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 |
|---|
| 3793 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 |
|---|
| 3794 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 |
|---|
| 3795 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 |
|---|
| 3796 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 |
|---|
| 3797 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 |
|---|
| 3798 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 |
|---|
| 3799 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 |
|---|
| 3800 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc |
|---|
| 3801 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 |
|---|
| 3802 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe |
|---|
| 3803 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 |
|---|
| 3804 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 |
|---|
| 3805 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 |
|---|
| 3806 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c |
|---|
| 3807 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 |
|---|
| 3808 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 |
|---|
| 3809 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 |
|---|
| 3810 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 |
|---|
| 3811 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 |
|---|
| 3812 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 |
|---|
| 3813 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 |
|---|
| 3814 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 |
|---|
| 3815 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 |
|---|
| 3816 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 |
|---|
| 3817 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 |
|---|
| 3818 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 |
|---|
| 3819 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 |
|---|
| 3820 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 |
|---|
| 3821 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 |
|---|
| 3822 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 |
|---|
| 3823 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 |
|---|
| 3824 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 |
|---|
| 3825 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 |
|---|
| 3826 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 |
|---|
| 3827 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 |
|---|
| 3828 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 |
|---|
| 3829 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 |
|---|
| 3830 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 |
|---|
| 3831 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 |
|---|
| 3832 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa |
|---|
| 3833 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 |
|---|
| 3834 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb |
|---|
| 3835 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 |
|---|
| 3836 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 |
|---|
| 3837 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 |
|---|
| 3838 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 |
|---|
| 3839 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 |
|---|
| 3840 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 |
|---|
| 3841 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 |
|---|
| 3842 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 |
|---|
| 3843 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 |
|---|
| 3844 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 |
|---|
| 3845 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 |
|---|
| 3846 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 |
|---|
| 3847 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 |
|---|
| 3848 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a |
|---|
| 3849 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 |
|---|
| 3850 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b |
|---|
| 3851 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 |
|---|
| 3852 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 |
|---|
| 3853 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 |
|---|
| 3854 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 |
|---|
| 3855 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 |
|---|
| 3856 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 |
|---|
| 3857 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 |
|---|
| 3858 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 |
|---|
| 3859 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 |
|---|
| 3860 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 |
|---|
| 3861 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 |
|---|
| 3862 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 |
|---|
| 3863 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 |
|---|
| 3864 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 |
|---|
| 3865 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 |
|---|
| 3866 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 |
|---|
| 3867 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 |
|---|
| 3868 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 |
|---|
| 3869 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 |
|---|
| 3870 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 |
|---|
| 3871 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 |
|---|
| 3872 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 |
|---|
| 3873 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 |
|---|
| 3874 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 |
|---|
| 3875 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 |
|---|
| 3876 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 |
|---|
| 3877 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 |
|---|
| 3878 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 |
|---|
| 3879 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 |
|---|
| 3880 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 |
|---|
| 3881 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8 |
|---|
| 3882 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 |
|---|
| 3883 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 |
|---|
| 3884 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 |
|---|
| 3885 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 |
|---|
| 3886 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 |
|---|
| 3887 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 |
|---|
| 3888 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 |
|---|
| 3889 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 |
|---|
| 3890 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 |
|---|
| 3891 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 |
|---|
| 3892 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa |
|---|
| 3893 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 |
|---|
| 3894 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 |
|---|
| 3895 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 |
|---|
| 3896 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 |
|---|
| 3897 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 |
|---|
| 3898 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 |
|---|
| 3899 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 |
|---|
| 3900 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 |
|---|
| 3901 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 |
|---|
| 3902 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 |
|---|
| 3903 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 |
|---|
| 3904 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 |
|---|
| 3905 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 |
|---|
| 3906 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 |
|---|
| 3907 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 |
|---|
| 3908 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 |
|---|
| 3909 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 |
|---|
| 3910 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a |
|---|
| 3911 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 |
|---|
| 3912 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c |
|---|
| 3913 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 |
|---|
| 3914 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d |
|---|
| 3915 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 |
|---|
| 3916 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e |
|---|
| 3917 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 |
|---|
| 3918 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 |
|---|
| 3919 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 |
|---|
| 3920 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 |
|---|
| 3921 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 |
|---|
| 3922 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 |
|---|
| 3923 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 |
|---|
| 3924 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 |
|---|
| 3925 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 |
|---|
| 3926 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a |
|---|
| 3927 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 |
|---|
| 3928 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c |
|---|
| 3929 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 |
|---|
| 3930 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 |
|---|
| 3931 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 |
|---|
| 3932 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 |
|---|
| 3933 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 |
|---|
| 3934 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 |
|---|
| 3935 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 |
|---|
| 3936 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 |
|---|
| 3937 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 |
|---|
| 3938 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 |
|---|
| 3939 | #define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 |
|---|
| 3940 | #define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 |
|---|
| 3941 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 |
|---|
| 3942 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 |
|---|
| 3943 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 |
|---|
| 3944 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 |
|---|
| 3945 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 |
|---|
| 3946 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 |
|---|
| 3947 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 |
|---|
| 3948 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 |
|---|
| 3949 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 |
|---|
| 3950 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a |
|---|
| 3951 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 |
|---|
| 3952 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c |
|---|
| 3953 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 |
|---|
| 3954 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 |
|---|
| 3955 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 |
|---|
| 3956 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 |
|---|
| 3957 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 |
|---|
| 3958 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 |
|---|
| 3959 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 |
|---|
| 3960 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 |
|---|
| 3961 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 |
|---|
| 3962 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a |
|---|
| 3963 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 |
|---|
| 3964 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c |
|---|
| 3965 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 |
|---|
| 3966 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 |
|---|
| 3967 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 |
|---|
| 3968 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 |
|---|
| 3969 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 |
|---|
| 3970 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 |
|---|
| 3971 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 |
|---|
| 3972 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 |
|---|
| 3973 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 |
|---|
| 3974 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc |
|---|
| 3975 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 |
|---|
| 3976 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe |
|---|
| 3977 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 |
|---|
| 3978 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 |
|---|
| 3979 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 |
|---|
| 3980 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 |
|---|
| 3981 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 |
|---|
| 3982 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 |
|---|
| 3983 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 |
|---|
| 3984 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 |
|---|
| 3985 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 |
|---|
| 3986 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 |
|---|
| 3987 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 |
|---|
| 3988 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a |
|---|
| 3989 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 |
|---|
| 3990 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c |
|---|
| 3991 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 |
|---|
| 3992 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d |
|---|
| 3993 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 |
|---|
| 3994 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e |
|---|
| 3995 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 |
|---|
| 3996 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 |
|---|
| 3997 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 |
|---|
| 3998 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 |
|---|
| 3999 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 |
|---|
| 4000 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 |
|---|
| 4001 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 |
|---|
| 4002 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 |
|---|
| 4003 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 |
|---|
| 4004 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f |
|---|
| 4005 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 |
|---|
| 4006 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 |
|---|
| 4007 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 |
|---|
| 4008 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 |
|---|
| 4009 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 |
|---|
| 4010 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 |
|---|
| 4011 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 |
|---|
| 4012 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 |
|---|
| 4013 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 |
|---|
| 4014 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 |
|---|
| 4015 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 |
|---|
| 4016 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f |
|---|
| 4017 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 |
|---|
| 4018 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 |
|---|
| 4019 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 |
|---|
| 4020 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 |
|---|
| 4021 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 |
|---|
| 4022 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 |
|---|
| 4023 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 |
|---|
| 4024 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 |
|---|
| 4025 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 |
|---|
| 4026 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f |
|---|
| 4027 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf |
|---|
| 4028 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 |
|---|
| 4029 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 |
|---|
| 4030 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 |
|---|
| 4031 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 |
|---|
| 4032 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 |
|---|
| 4033 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 |
|---|
| 4034 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc |
|---|
| 4035 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 |
|---|
| 4036 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 |
|---|
| 4037 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 |
|---|
| 4038 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c |
|---|
| 4039 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf |
|---|
| 4040 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 |
|---|
| 4041 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 |
|---|
| 4042 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 |
|---|
| 4043 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 |
|---|
| 4044 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 |
|---|
| 4045 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 |
|---|
| 4046 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc |
|---|
| 4047 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 |
|---|
| 4048 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 |
|---|
| 4049 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 |
|---|
| 4050 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 |
|---|
| 4051 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 |
|---|
| 4052 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e |
|---|
| 4053 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 |
|---|
| 4054 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 |
|---|
| 4055 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 |
|---|
| 4056 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 |
|---|
| 4057 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 |
|---|
| 4058 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 |
|---|
| 4059 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 |
|---|
| 4060 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 |
|---|
| 4061 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 |
|---|
| 4062 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 |
|---|
| 4063 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 |
|---|
| 4064 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 |
|---|
| 4065 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 |
|---|
| 4066 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 |
|---|
| 4067 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 |
|---|
| 4068 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 |
|---|
| 4069 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 |
|---|
| 4070 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc |
|---|
| 4071 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 |
|---|
| 4072 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd |
|---|
| 4073 | #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 |
|---|
| 4074 | #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe |
|---|
| 4075 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 |
|---|
| 4076 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 |
|---|
| 4077 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 |
|---|
| 4078 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 |
|---|
| 4079 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 |
|---|
| 4080 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 |
|---|
| 4081 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 |
|---|
| 4082 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 |
|---|
| 4083 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 |
|---|
| 4084 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 |
|---|
| 4085 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 |
|---|
| 4086 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 |
|---|
| 4087 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 |
|---|
| 4088 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 |
|---|
| 4089 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf |
|---|
| 4090 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 |
|---|
| 4091 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 |
|---|
| 4092 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 |
|---|
| 4093 | #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf |
|---|
| 4094 | #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 |
|---|
| 4095 | #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0 |
|---|
| 4096 | #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 |
|---|
| 4097 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00 |
|---|
| 4098 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 |
|---|
| 4099 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000 |
|---|
| 4100 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc |
|---|
| 4101 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000 |
|---|
| 4102 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 |
|---|
| 4103 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000 |
|---|
| 4104 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 |
|---|
| 4105 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000 |
|---|
| 4106 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 |
|---|
| 4107 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000 |
|---|
| 4108 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c |
|---|
| 4109 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000 |
|---|
| 4110 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d |
|---|
| 4111 | #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 |
|---|
| 4112 | #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 |
|---|
| 4113 | #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 |
|---|
| 4114 | #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 |
|---|
| 4115 | #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 |
|---|
| 4116 | #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 |
|---|
| 4117 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff |
|---|
| 4118 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 |
|---|
| 4119 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4120 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4121 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4122 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4123 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4124 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4125 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4126 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4127 | #define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4128 | #define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4129 | #define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4130 | #define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4131 | #define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4132 | #define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4133 | #define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4134 | #define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4135 | #define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4136 | #define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4137 | #define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4138 | #define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4139 | #define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4140 | #define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4141 | #define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4142 | #define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4143 | #define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4144 | #define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4145 | #define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4146 | #define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4147 | #define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4148 | #define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4149 | #define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4150 | #define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4151 | #define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4152 | #define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4153 | #define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4154 | #define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4155 | #define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4156 | #define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4157 | #define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4158 | #define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4159 | #define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4160 | #define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4161 | #define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4162 | #define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4163 | #define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4164 | #define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4165 | #define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4166 | #define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4167 | #define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4168 | #define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4169 | #define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4170 | #define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4171 | #define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4172 | #define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4173 | #define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4174 | #define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4175 | #define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4176 | #define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4177 | #define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4178 | #define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4179 | #define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4180 | #define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4181 | #define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4182 | #define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4183 | #define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4184 | #define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4185 | #define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4186 | #define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4187 | #define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4188 | #define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4189 | #define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4190 | #define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4191 | #define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4192 | #define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4193 | #define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4194 | #define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4195 | #define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4196 | #define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4197 | #define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4198 | #define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4199 | #define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4200 | #define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4201 | #define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4202 | #define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4203 | #define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4204 | #define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4205 | #define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4206 | #define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4207 | #define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4208 | #define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4209 | #define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4210 | #define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4211 | #define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4212 | #define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4213 | #define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4214 | #define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4215 | #define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4216 | #define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4217 | #define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4218 | #define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4219 | #define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4220 | #define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4221 | #define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4222 | #define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4223 | #define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4224 | #define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4225 | #define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4226 | #define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4227 | #define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4228 | #define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4229 | #define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4230 | #define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4231 | #define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4232 | #define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4233 | #define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4234 | #define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4235 | #define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4236 | #define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4237 | #define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4238 | #define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4239 | #define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4240 | #define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4241 | #define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4242 | #define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4243 | #define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4244 | #define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4245 | #define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4246 | #define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4247 | #define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4248 | #define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4249 | #define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4250 | #define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4251 | #define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4252 | #define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4253 | #define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4254 | #define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4255 | #define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4256 | #define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4257 | #define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4258 | #define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4259 | #define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4260 | #define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4261 | #define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4262 | #define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4263 | #define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4264 | #define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4265 | #define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4266 | #define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4267 | #define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4268 | #define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4269 | #define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4270 | #define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4271 | #define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4272 | #define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4273 | #define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4274 | #define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4275 | #define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4276 | #define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4277 | #define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4278 | #define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4279 | #define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4280 | #define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4281 | #define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4282 | #define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4283 | #define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4284 | #define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4285 | #define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4286 | #define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4287 | #define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4288 | #define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4289 | #define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4290 | #define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4291 | #define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4292 | #define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4293 | #define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4294 | #define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4295 | #define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4296 | #define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4297 | #define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4298 | #define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4299 | #define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4300 | #define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4301 | #define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4302 | #define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4303 | #define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4304 | #define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4305 | #define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4306 | #define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4307 | #define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4308 | #define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4309 | #define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4310 | #define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4311 | #define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4312 | #define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4313 | #define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4314 | #define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4315 | #define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4316 | #define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4317 | #define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4318 | #define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4319 | #define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4320 | #define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4321 | #define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4322 | #define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4323 | #define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4324 | #define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4325 | #define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4326 | #define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4327 | #define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4328 | #define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4329 | #define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4330 | #define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4331 | #define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4332 | #define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4333 | #define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4334 | #define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4335 | #define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4336 | #define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4337 | #define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4338 | #define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4339 | #define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4340 | #define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4341 | #define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4342 | #define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4343 | #define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4344 | #define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4345 | #define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4346 | #define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4347 | #define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4348 | #define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4349 | #define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4350 | #define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4351 | #define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4352 | #define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4353 | #define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4354 | #define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4355 | #define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4356 | #define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4357 | #define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4358 | #define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4359 | #define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4360 | #define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4361 | #define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4362 | #define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4363 | #define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4364 | #define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4365 | #define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4366 | #define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4367 | #define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4368 | #define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4369 | #define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4370 | #define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4371 | #define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4372 | #define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4373 | #define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4374 | #define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4375 | #define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4376 | #define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4377 | #define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4378 | #define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4379 | #define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4380 | #define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4381 | #define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4382 | #define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4383 | #define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4384 | #define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4385 | #define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4386 | #define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4387 | #define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4388 | #define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4389 | #define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4390 | #define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4391 | #define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4392 | #define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4393 | #define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4394 | #define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4395 | #define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4396 | #define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4397 | #define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4398 | #define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4399 | #define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4400 | #define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4401 | #define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4402 | #define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4403 | #define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4404 | #define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4405 | #define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4406 | #define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4407 | #define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4408 | #define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4409 | #define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4410 | #define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4411 | #define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4412 | #define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4413 | #define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4414 | #define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4415 | #define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4416 | #define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4417 | #define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4418 | #define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4419 | #define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4420 | #define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4421 | #define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4422 | #define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4423 | #define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4424 | #define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4425 | #define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4426 | #define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4427 | #define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4428 | #define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4429 | #define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4430 | #define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4431 | #define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4432 | #define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4433 | #define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4434 | #define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4435 | #define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4436 | #define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4437 | #define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4438 | #define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4439 | #define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4440 | #define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4441 | #define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4442 | #define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4443 | #define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4444 | #define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4445 | #define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4446 | #define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4447 | #define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4448 | #define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4449 | #define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4450 | #define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4451 | #define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4452 | #define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4453 | #define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4454 | #define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4455 | #define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4456 | #define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4457 | #define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4458 | #define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4459 | #define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4460 | #define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4461 | #define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4462 | #define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4463 | #define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4464 | #define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4465 | #define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4466 | #define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4467 | #define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4468 | #define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4469 | #define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4470 | #define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4471 | #define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4472 | #define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4473 | #define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4474 | #define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4475 | #define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4476 | #define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4477 | #define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4478 | #define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4479 | #define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4480 | #define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4481 | #define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4482 | #define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4483 | #define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4484 | #define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4485 | #define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4486 | #define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4487 | #define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4488 | #define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4489 | #define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4490 | #define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4491 | #define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4492 | #define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4493 | #define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4494 | #define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4495 | #define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4496 | #define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4497 | #define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4498 | #define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4499 | #define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4500 | #define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4501 | #define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4502 | #define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4503 | #define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4504 | #define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4505 | #define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4506 | #define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4507 | #define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4508 | #define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4509 | #define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4510 | #define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4511 | #define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4512 | #define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4513 | #define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4514 | #define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4515 | #define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4516 | #define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4517 | #define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4518 | #define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4519 | #define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4520 | #define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4521 | #define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4522 | #define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4523 | #define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4524 | #define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4525 | #define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4526 | #define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4527 | #define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4528 | #define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4529 | #define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4530 | #define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4531 | #define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4532 | #define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4533 | #define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4534 | #define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4535 | #define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4536 | #define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4537 | #define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4538 | #define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4539 | #define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4540 | #define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4541 | #define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4542 | #define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4543 | #define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4544 | #define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4545 | #define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4546 | #define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4547 | #define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4548 | #define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4549 | #define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4550 | #define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4551 | #define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4552 | #define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4553 | #define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4554 | #define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4555 | #define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4556 | #define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4557 | #define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4558 | #define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4559 | #define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4560 | #define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4561 | #define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4562 | #define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4563 | #define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4564 | #define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4565 | #define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4566 | #define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4567 | #define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4568 | #define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4569 | #define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4570 | #define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4571 | #define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4572 | #define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4573 | #define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4574 | #define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4575 | #define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4576 | #define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4577 | #define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4578 | #define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4579 | #define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4580 | #define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4581 | #define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4582 | #define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4583 | #define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4584 | #define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4585 | #define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4586 | #define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4587 | #define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4588 | #define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4589 | #define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4590 | #define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4591 | #define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4592 | #define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4593 | #define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4594 | #define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4595 | #define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4596 | #define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4597 | #define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4598 | #define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4599 | #define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4600 | #define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4601 | #define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4602 | #define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4603 | #define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4604 | #define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4605 | #define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4606 | #define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4607 | #define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4608 | #define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4609 | #define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4610 | #define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4611 | #define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4612 | #define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4613 | #define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4614 | #define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4615 | #define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4616 | #define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4617 | #define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4618 | #define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4619 | #define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4620 | #define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4621 | #define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4622 | #define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4623 | #define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4624 | #define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4625 | #define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4626 | #define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4627 | #define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4628 | #define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4629 | #define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4630 | #define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4631 | #define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4632 | #define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4633 | #define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4634 | #define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4635 | #define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4636 | #define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4637 | #define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4638 | #define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4639 | #define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4640 | #define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4641 | #define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4642 | #define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4643 | #define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4644 | #define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4645 | #define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4646 | #define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4647 | #define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4648 | #define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4649 | #define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4650 | #define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4651 | #define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4652 | #define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4653 | #define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4654 | #define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4655 | #define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4656 | #define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4657 | #define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4658 | #define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4659 | #define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4660 | #define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4661 | #define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4662 | #define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4663 | #define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4664 | #define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4665 | #define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4666 | #define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4667 | #define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4668 | #define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4669 | #define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4670 | #define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4671 | #define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4672 | #define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4673 | #define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4674 | #define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4675 | #define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4676 | #define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4677 | #define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4678 | #define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4679 | #define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4680 | #define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4681 | #define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4682 | #define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4683 | #define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4684 | #define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4685 | #define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4686 | #define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4687 | #define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4688 | #define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4689 | #define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4690 | #define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4691 | #define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4692 | #define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4693 | #define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4694 | #define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4695 | #define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4696 | #define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4697 | #define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4698 | #define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4699 | #define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4700 | #define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4701 | #define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4702 | #define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4703 | #define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4704 | #define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4705 | #define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4706 | #define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4707 | #define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4708 | #define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4709 | #define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4710 | #define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4711 | #define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4712 | #define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4713 | #define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4714 | #define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4715 | #define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4716 | #define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4717 | #define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4718 | #define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4719 | #define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4720 | #define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4721 | #define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4722 | #define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4723 | #define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4724 | #define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4725 | #define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4726 | #define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4727 | #define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4728 | #define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4729 | #define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4730 | #define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4731 | #define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4732 | #define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4733 | #define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4734 | #define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4735 | #define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4736 | #define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4737 | #define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4738 | #define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4739 | #define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4740 | #define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4741 | #define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4742 | #define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4743 | #define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4744 | #define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4745 | #define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4746 | #define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4747 | #define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4748 | #define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4749 | #define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4750 | #define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4751 | #define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4752 | #define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4753 | #define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4754 | #define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4755 | #define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4756 | #define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4757 | #define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4758 | #define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4759 | #define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4760 | #define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4761 | #define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4762 | #define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4763 | #define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4764 | #define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4765 | #define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4766 | #define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4767 | #define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4768 | #define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4769 | #define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4770 | #define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4771 | #define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4772 | #define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4773 | #define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4774 | #define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4775 | #define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4776 | #define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4777 | #define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4778 | #define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4779 | #define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4780 | #define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4781 | #define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4782 | #define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4783 | #define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4784 | #define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4785 | #define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4786 | #define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4787 | #define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4788 | #define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4789 | #define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4790 | #define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4791 | #define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4792 | #define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4793 | #define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4794 | #define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4795 | #define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4796 | #define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4797 | #define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4798 | #define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4799 | #define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4800 | #define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4801 | #define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4802 | #define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4803 | #define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4804 | #define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4805 | #define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4806 | #define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4807 | #define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4808 | #define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4809 | #define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4810 | #define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4811 | #define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4812 | #define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4813 | #define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4814 | #define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4815 | #define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4816 | #define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4817 | #define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4818 | #define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4819 | #define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4820 | #define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4821 | #define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4822 | #define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4823 | #define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4824 | #define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4825 | #define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4826 | #define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4827 | #define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4828 | #define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4829 | #define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4830 | #define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4831 | #define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4832 | #define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4833 | #define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4834 | #define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4835 | #define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4836 | #define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4837 | #define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4838 | #define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4839 | #define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4840 | #define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4841 | #define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4842 | #define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4843 | #define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4844 | #define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4845 | #define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4846 | #define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4847 | #define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4848 | #define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4849 | #define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4850 | #define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4851 | #define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4852 | #define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4853 | #define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4854 | #define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4855 | #define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4856 | #define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4857 | #define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4858 | #define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4859 | #define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4860 | #define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4861 | #define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4862 | #define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4863 | #define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4864 | #define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4865 | #define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4866 | #define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4867 | #define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4868 | #define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4869 | #define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4870 | #define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4871 | #define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4872 | #define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4873 | #define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4874 | #define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4875 | #define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4876 | #define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4877 | #define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4878 | #define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4879 | #define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4880 | #define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4881 | #define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4882 | #define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4883 | #define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4884 | #define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4885 | #define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4886 | #define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4887 | #define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4888 | #define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4889 | #define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4890 | #define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4891 | #define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4892 | #define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4893 | #define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4894 | #define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4895 | #define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4896 | #define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4897 | #define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4898 | #define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4899 | #define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4900 | #define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4901 | #define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4902 | #define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4903 | #define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4904 | #define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4905 | #define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4906 | #define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4907 | #define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4908 | #define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4909 | #define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4910 | #define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4911 | #define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4912 | #define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4913 | #define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4914 | #define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4915 | #define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4916 | #define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4917 | #define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4918 | #define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4919 | #define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4920 | #define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4921 | #define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4922 | #define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4923 | #define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4924 | #define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4925 | #define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4926 | #define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4927 | #define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4928 | #define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4929 | #define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4930 | #define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4931 | #define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4932 | #define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4933 | #define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4934 | #define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4935 | #define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4936 | #define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4937 | #define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4938 | #define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4939 | #define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4940 | #define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4941 | #define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4942 | #define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4943 | #define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4944 | #define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4945 | #define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4946 | #define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4947 | #define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4948 | #define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4949 | #define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4950 | #define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4951 | #define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4952 | #define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4953 | #define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4954 | #define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4955 | #define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4956 | #define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4957 | #define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4958 | #define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4959 | #define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4960 | #define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4961 | #define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4962 | #define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4963 | #define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4964 | #define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4965 | #define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4966 | #define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4967 | #define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4968 | #define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4969 | #define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4970 | #define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4971 | #define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4972 | #define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4973 | #define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4974 | #define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4975 | #define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4976 | #define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4977 | #define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4978 | #define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4979 | #define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4980 | #define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4981 | #define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4982 | #define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4983 | #define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4984 | #define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4985 | #define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4986 | #define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4987 | #define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4988 | #define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4989 | #define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4990 | #define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4991 | #define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4992 | #define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4993 | #define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4994 | #define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4995 | #define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4996 | #define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4997 | #define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 4998 | #define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 4999 | #define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5000 | #define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5001 | #define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5002 | #define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5003 | #define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5004 | #define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5005 | #define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5006 | #define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5007 | #define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5008 | #define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5009 | #define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5010 | #define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5011 | #define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5012 | #define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5013 | #define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5014 | #define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5015 | #define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5016 | #define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5017 | #define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5018 | #define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5019 | #define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5020 | #define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5021 | #define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5022 | #define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5023 | #define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5024 | #define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5025 | #define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5026 | #define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5027 | #define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5028 | #define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5029 | #define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5030 | #define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5031 | #define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5032 | #define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5033 | #define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5034 | #define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5035 | #define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5036 | #define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5037 | #define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5038 | #define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5039 | #define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5040 | #define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5041 | #define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5042 | #define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5043 | #define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5044 | #define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5045 | #define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5046 | #define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5047 | #define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5048 | #define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5049 | #define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5050 | #define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5051 | #define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5052 | #define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5053 | #define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5054 | #define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5055 | #define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5056 | #define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5057 | #define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5058 | #define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5059 | #define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5060 | #define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5061 | #define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5062 | #define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5063 | #define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5064 | #define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5065 | #define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5066 | #define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5067 | #define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5068 | #define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5069 | #define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5070 | #define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5071 | #define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5072 | #define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5073 | #define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5074 | #define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5075 | #define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5076 | #define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5077 | #define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 5078 | #define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 5079 | #define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 |
|---|
| 5080 | #define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 |
|---|
| 5081 | #define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 |
|---|
| 5082 | #define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 |
|---|
| 5083 | #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc |
|---|
| 5084 | #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 |
|---|
| 5085 | #define GRPH_CONTROL__GRPH_Z_MASK 0x30 |
|---|
| 5086 | #define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 |
|---|
| 5087 | #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 |
|---|
| 5088 | #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 |
|---|
| 5089 | #define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 |
|---|
| 5090 | #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 |
|---|
| 5091 | #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 |
|---|
| 5092 | #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb |
|---|
| 5093 | #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 |
|---|
| 5094 | #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd |
|---|
| 5095 | #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 |
|---|
| 5096 | #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 |
|---|
| 5097 | #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 |
|---|
| 5098 | #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 |
|---|
| 5099 | #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 |
|---|
| 5100 | #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 |
|---|
| 5101 | #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 |
|---|
| 5102 | #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 |
|---|
| 5103 | #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 |
|---|
| 5104 | #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 |
|---|
| 5105 | #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 |
|---|
| 5106 | #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d |
|---|
| 5107 | #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 |
|---|
| 5108 | #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f |
|---|
| 5109 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 |
|---|
| 5110 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 |
|---|
| 5111 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 |
|---|
| 5112 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 |
|---|
| 5113 | #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 |
|---|
| 5114 | #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 |
|---|
| 5115 | #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 |
|---|
| 5116 | #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 |
|---|
| 5117 | #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 |
|---|
| 5118 | #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 |
|---|
| 5119 | #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 |
|---|
| 5120 | #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 |
|---|
| 5121 | #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 |
|---|
| 5122 | #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa |
|---|
| 5123 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 |
|---|
| 5124 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 |
|---|
| 5125 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5126 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5127 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 |
|---|
| 5128 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 |
|---|
| 5129 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5130 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5131 | #define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff |
|---|
| 5132 | #define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 |
|---|
| 5133 | #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5134 | #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5135 | #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5136 | #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5137 | #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff |
|---|
| 5138 | #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 |
|---|
| 5139 | #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff |
|---|
| 5140 | #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 |
|---|
| 5141 | #define GRPH_X_START__GRPH_X_START_MASK 0x3fff |
|---|
| 5142 | #define GRPH_X_START__GRPH_X_START__SHIFT 0x0 |
|---|
| 5143 | #define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff |
|---|
| 5144 | #define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 |
|---|
| 5145 | #define GRPH_X_END__GRPH_X_END_MASK 0x7fff |
|---|
| 5146 | #define GRPH_X_END__GRPH_X_END__SHIFT 0x0 |
|---|
| 5147 | #define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff |
|---|
| 5148 | #define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 |
|---|
| 5149 | #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3 |
|---|
| 5150 | #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 |
|---|
| 5151 | #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30 |
|---|
| 5152 | #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4 |
|---|
| 5153 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 |
|---|
| 5154 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 5155 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 |
|---|
| 5156 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 |
|---|
| 5157 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 |
|---|
| 5158 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 |
|---|
| 5159 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 |
|---|
| 5160 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 |
|---|
| 5161 | #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 |
|---|
| 5162 | #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 |
|---|
| 5163 | #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 |
|---|
| 5164 | #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 5165 | #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 |
|---|
| 5166 | #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 |
|---|
| 5167 | #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
|---|
| 5168 | #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
|---|
| 5169 | #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 |
|---|
| 5170 | #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c |
|---|
| 5171 | #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 |
|---|
| 5172 | #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 |
|---|
| 5173 | #define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2 |
|---|
| 5174 | #define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1 |
|---|
| 5175 | #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 |
|---|
| 5176 | #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 |
|---|
| 5177 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 |
|---|
| 5178 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 |
|---|
| 5179 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 |
|---|
| 5180 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 |
|---|
| 5181 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 |
|---|
| 5182 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 |
|---|
| 5183 | #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf |
|---|
| 5184 | #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 |
|---|
| 5185 | #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 |
|---|
| 5186 | #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 |
|---|
| 5187 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 |
|---|
| 5188 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 |
|---|
| 5189 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 |
|---|
| 5190 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 |
|---|
| 5191 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 |
|---|
| 5192 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 |
|---|
| 5193 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 |
|---|
| 5194 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 |
|---|
| 5195 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 |
|---|
| 5196 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 |
|---|
| 5197 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 |
|---|
| 5198 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 |
|---|
| 5199 | #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff |
|---|
| 5200 | #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 |
|---|
| 5201 | #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5202 | #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5203 | #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 |
|---|
| 5204 | #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 |
|---|
| 5205 | #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5206 | #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5207 | #define OVL_ENABLE__OVL_ENABLE_MASK 0x1 |
|---|
| 5208 | #define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0 |
|---|
| 5209 | #define OVL_ENABLE__OVLSCL_EN_MASK 0x100 |
|---|
| 5210 | #define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8 |
|---|
| 5211 | #define OVL_CONTROL1__OVL_DEPTH_MASK 0x3 |
|---|
| 5212 | #define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0 |
|---|
| 5213 | #define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc |
|---|
| 5214 | #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2 |
|---|
| 5215 | #define OVL_CONTROL1__OVL_Z_MASK 0x30 |
|---|
| 5216 | #define OVL_CONTROL1__OVL_Z__SHIFT 0x4 |
|---|
| 5217 | #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0 |
|---|
| 5218 | #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6 |
|---|
| 5219 | #define OVL_CONTROL1__OVL_FORMAT_MASK 0x700 |
|---|
| 5220 | #define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8 |
|---|
| 5221 | #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800 |
|---|
| 5222 | #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb |
|---|
| 5223 | #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000 |
|---|
| 5224 | #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd |
|---|
| 5225 | #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 |
|---|
| 5226 | #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 |
|---|
| 5227 | #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 |
|---|
| 5228 | #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 |
|---|
| 5229 | #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000 |
|---|
| 5230 | #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12 |
|---|
| 5231 | #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000 |
|---|
| 5232 | #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14 |
|---|
| 5233 | #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000 |
|---|
| 5234 | #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18 |
|---|
| 5235 | #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000 |
|---|
| 5236 | #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19 |
|---|
| 5237 | #define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000 |
|---|
| 5238 | #define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e |
|---|
| 5239 | #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1 |
|---|
| 5240 | #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0 |
|---|
| 5241 | #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3 |
|---|
| 5242 | #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0 |
|---|
| 5243 | #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30 |
|---|
| 5244 | #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4 |
|---|
| 5245 | #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0 |
|---|
| 5246 | #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6 |
|---|
| 5247 | #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300 |
|---|
| 5248 | #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8 |
|---|
| 5249 | #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00 |
|---|
| 5250 | #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa |
|---|
| 5251 | #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1 |
|---|
| 5252 | #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0 |
|---|
| 5253 | #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5254 | #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5255 | #define OVL_PITCH__OVL_PITCH_MASK 0x7fff |
|---|
| 5256 | #define OVL_PITCH__OVL_PITCH__SHIFT 0x0 |
|---|
| 5257 | #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5258 | #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5259 | #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff |
|---|
| 5260 | #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0 |
|---|
| 5261 | #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff |
|---|
| 5262 | #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0 |
|---|
| 5263 | #define OVL_START__OVL_Y_START_MASK 0x3fff |
|---|
| 5264 | #define OVL_START__OVL_Y_START__SHIFT 0x0 |
|---|
| 5265 | #define OVL_START__OVL_X_START_MASK 0x3fff0000 |
|---|
| 5266 | #define OVL_START__OVL_X_START__SHIFT 0x10 |
|---|
| 5267 | #define OVL_END__OVL_Y_END_MASK 0x7fff |
|---|
| 5268 | #define OVL_END__OVL_Y_END__SHIFT 0x0 |
|---|
| 5269 | #define OVL_END__OVL_X_END_MASK 0x7fff0000 |
|---|
| 5270 | #define OVL_END__OVL_X_END__SHIFT 0x10 |
|---|
| 5271 | #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1 |
|---|
| 5272 | #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 5273 | #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2 |
|---|
| 5274 | #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1 |
|---|
| 5275 | #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000 |
|---|
| 5276 | #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 5277 | #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
|---|
| 5278 | #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
|---|
| 5279 | #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 |
|---|
| 5280 | #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8 |
|---|
| 5281 | #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1 |
|---|
| 5282 | #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0 |
|---|
| 5283 | #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70 |
|---|
| 5284 | #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4 |
|---|
| 5285 | #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700 |
|---|
| 5286 | #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 |
|---|
| 5287 | #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf |
|---|
| 5288 | #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0 |
|---|
| 5289 | #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 |
|---|
| 5290 | #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 |
|---|
| 5291 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100 |
|---|
| 5292 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8 |
|---|
| 5293 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200 |
|---|
| 5294 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9 |
|---|
| 5295 | #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff |
|---|
| 5296 | #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 |
|---|
| 5297 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff |
|---|
| 5298 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0 |
|---|
| 5299 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00 |
|---|
| 5300 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa |
|---|
| 5301 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000 |
|---|
| 5302 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14 |
|---|
| 5303 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000 |
|---|
| 5304 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f |
|---|
| 5305 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 |
|---|
| 5306 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 |
|---|
| 5307 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 |
|---|
| 5308 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 |
|---|
| 5309 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 |
|---|
| 5310 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 |
|---|
| 5311 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 |
|---|
| 5312 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 |
|---|
| 5313 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 |
|---|
| 5314 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 |
|---|
| 5315 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff |
|---|
| 5316 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 |
|---|
| 5317 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 |
|---|
| 5318 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 |
|---|
| 5319 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff |
|---|
| 5320 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 |
|---|
| 5321 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 |
|---|
| 5322 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 |
|---|
| 5323 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff |
|---|
| 5324 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 |
|---|
| 5325 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 |
|---|
| 5326 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 |
|---|
| 5327 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1 |
|---|
| 5328 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0 |
|---|
| 5329 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2 |
|---|
| 5330 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1 |
|---|
| 5331 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4 |
|---|
| 5332 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2 |
|---|
| 5333 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8 |
|---|
| 5334 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3 |
|---|
| 5335 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10 |
|---|
| 5336 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4 |
|---|
| 5337 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff |
|---|
| 5338 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0 |
|---|
| 5339 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000 |
|---|
| 5340 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10 |
|---|
| 5341 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff |
|---|
| 5342 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0 |
|---|
| 5343 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000 |
|---|
| 5344 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10 |
|---|
| 5345 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff |
|---|
| 5346 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0 |
|---|
| 5347 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000 |
|---|
| 5348 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10 |
|---|
| 5349 | #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 |
|---|
| 5350 | #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 |
|---|
| 5351 | #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30 |
|---|
| 5352 | #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4 |
|---|
| 5353 | #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff |
|---|
| 5354 | #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 |
|---|
| 5355 | #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 |
|---|
| 5356 | #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 |
|---|
| 5357 | #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff |
|---|
| 5358 | #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 |
|---|
| 5359 | #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 |
|---|
| 5360 | #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 |
|---|
| 5361 | #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff |
|---|
| 5362 | #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 |
|---|
| 5363 | #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 |
|---|
| 5364 | #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 |
|---|
| 5365 | #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff |
|---|
| 5366 | #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 |
|---|
| 5367 | #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 |
|---|
| 5368 | #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 |
|---|
| 5369 | #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff |
|---|
| 5370 | #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 |
|---|
| 5371 | #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 |
|---|
| 5372 | #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 |
|---|
| 5373 | #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff |
|---|
| 5374 | #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 |
|---|
| 5375 | #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 |
|---|
| 5376 | #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 |
|---|
| 5377 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 |
|---|
| 5378 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 |
|---|
| 5379 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70 |
|---|
| 5380 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4 |
|---|
| 5381 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff |
|---|
| 5382 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 |
|---|
| 5383 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 |
|---|
| 5384 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 |
|---|
| 5385 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff |
|---|
| 5386 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 |
|---|
| 5387 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 |
|---|
| 5388 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 |
|---|
| 5389 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff |
|---|
| 5390 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 |
|---|
| 5391 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 |
|---|
| 5392 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 |
|---|
| 5393 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff |
|---|
| 5394 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 |
|---|
| 5395 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 |
|---|
| 5396 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 |
|---|
| 5397 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff |
|---|
| 5398 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 |
|---|
| 5399 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 |
|---|
| 5400 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 |
|---|
| 5401 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff |
|---|
| 5402 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 |
|---|
| 5403 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 |
|---|
| 5404 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 |
|---|
| 5405 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff |
|---|
| 5406 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 |
|---|
| 5407 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 |
|---|
| 5408 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 |
|---|
| 5409 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff |
|---|
| 5410 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 |
|---|
| 5411 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 |
|---|
| 5412 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 |
|---|
| 5413 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff |
|---|
| 5414 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 |
|---|
| 5415 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 |
|---|
| 5416 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 |
|---|
| 5417 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff |
|---|
| 5418 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 |
|---|
| 5419 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 |
|---|
| 5420 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 |
|---|
| 5421 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff |
|---|
| 5422 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 |
|---|
| 5423 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 |
|---|
| 5424 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 |
|---|
| 5425 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff |
|---|
| 5426 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 |
|---|
| 5427 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 |
|---|
| 5428 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 |
|---|
| 5429 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff |
|---|
| 5430 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 |
|---|
| 5431 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 |
|---|
| 5432 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 |
|---|
| 5433 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff |
|---|
| 5434 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 |
|---|
| 5435 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 |
|---|
| 5436 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 |
|---|
| 5437 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff |
|---|
| 5438 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 |
|---|
| 5439 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 |
|---|
| 5440 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 |
|---|
| 5441 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff |
|---|
| 5442 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 |
|---|
| 5443 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 |
|---|
| 5444 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 |
|---|
| 5445 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff |
|---|
| 5446 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 |
|---|
| 5447 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 |
|---|
| 5448 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 |
|---|
| 5449 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff |
|---|
| 5450 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 |
|---|
| 5451 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 |
|---|
| 5452 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 |
|---|
| 5453 | #define DENORM_CONTROL__DENORM_MODE_MASK 0x7 |
|---|
| 5454 | #define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 |
|---|
| 5455 | #define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 |
|---|
| 5456 | #define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 |
|---|
| 5457 | #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf |
|---|
| 5458 | #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
|---|
| 5459 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff |
|---|
| 5460 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 |
|---|
| 5461 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 |
|---|
| 5462 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 |
|---|
| 5463 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff |
|---|
| 5464 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 |
|---|
| 5465 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 |
|---|
| 5466 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 |
|---|
| 5467 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff |
|---|
| 5468 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 |
|---|
| 5469 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 |
|---|
| 5470 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 |
|---|
| 5471 | #define KEY_CONTROL__KEY_SELECT_MASK 0x1 |
|---|
| 5472 | #define KEY_CONTROL__KEY_SELECT__SHIFT 0x0 |
|---|
| 5473 | #define KEY_CONTROL__KEY_MODE_MASK 0x6 |
|---|
| 5474 | #define KEY_CONTROL__KEY_MODE__SHIFT 0x1 |
|---|
| 5475 | #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000 |
|---|
| 5476 | #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c |
|---|
| 5477 | #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff |
|---|
| 5478 | #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 |
|---|
| 5479 | #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 |
|---|
| 5480 | #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 |
|---|
| 5481 | #define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff |
|---|
| 5482 | #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 |
|---|
| 5483 | #define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 |
|---|
| 5484 | #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 |
|---|
| 5485 | #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff |
|---|
| 5486 | #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 |
|---|
| 5487 | #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 |
|---|
| 5488 | #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 |
|---|
| 5489 | #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff |
|---|
| 5490 | #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 |
|---|
| 5491 | #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 |
|---|
| 5492 | #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 |
|---|
| 5493 | #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 |
|---|
| 5494 | #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 |
|---|
| 5495 | #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30 |
|---|
| 5496 | #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4 |
|---|
| 5497 | #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 |
|---|
| 5498 | #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 |
|---|
| 5499 | #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 |
|---|
| 5500 | #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc |
|---|
| 5501 | #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 |
|---|
| 5502 | #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 |
|---|
| 5503 | #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30 |
|---|
| 5504 | #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4 |
|---|
| 5505 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff |
|---|
| 5506 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 |
|---|
| 5507 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 |
|---|
| 5508 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 |
|---|
| 5509 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff |
|---|
| 5510 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 |
|---|
| 5511 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 |
|---|
| 5512 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 |
|---|
| 5513 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff |
|---|
| 5514 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 |
|---|
| 5515 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 |
|---|
| 5516 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 |
|---|
| 5517 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff |
|---|
| 5518 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 |
|---|
| 5519 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 |
|---|
| 5520 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 |
|---|
| 5521 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff |
|---|
| 5522 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 |
|---|
| 5523 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 |
|---|
| 5524 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 |
|---|
| 5525 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff |
|---|
| 5526 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 |
|---|
| 5527 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 |
|---|
| 5528 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 |
|---|
| 5529 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 |
|---|
| 5530 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 |
|---|
| 5531 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 |
|---|
| 5532 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 |
|---|
| 5533 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 |
|---|
| 5534 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 |
|---|
| 5535 | #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 |
|---|
| 5536 | #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 |
|---|
| 5537 | #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 |
|---|
| 5538 | #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 |
|---|
| 5539 | #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 |
|---|
| 5540 | #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa |
|---|
| 5541 | #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff |
|---|
| 5542 | #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 |
|---|
| 5543 | #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 |
|---|
| 5544 | #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 |
|---|
| 5545 | #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 |
|---|
| 5546 | #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 |
|---|
| 5547 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff |
|---|
| 5548 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 |
|---|
| 5549 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 |
|---|
| 5550 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 |
|---|
| 5551 | #define CUR_CONTROL__CURSOR_EN_MASK 0x1 |
|---|
| 5552 | #define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 |
|---|
| 5553 | #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 |
|---|
| 5554 | #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 |
|---|
| 5555 | #define CUR_CONTROL__CURSOR_MODE_MASK 0x300 |
|---|
| 5556 | #define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
|---|
| 5557 | #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 |
|---|
| 5558 | #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 |
|---|
| 5559 | #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 |
|---|
| 5560 | #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 |
|---|
| 5561 | #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 |
|---|
| 5562 | #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 |
|---|
| 5563 | #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff |
|---|
| 5564 | #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
|---|
| 5565 | #define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f |
|---|
| 5566 | #define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
|---|
| 5567 | #define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 |
|---|
| 5568 | #define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
|---|
| 5569 | #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5570 | #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5571 | #define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff |
|---|
| 5572 | #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
|---|
| 5573 | #define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 |
|---|
| 5574 | #define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
|---|
| 5575 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f |
|---|
| 5576 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
|---|
| 5577 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 |
|---|
| 5578 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
|---|
| 5579 | #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff |
|---|
| 5580 | #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 |
|---|
| 5581 | #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 |
|---|
| 5582 | #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 |
|---|
| 5583 | #define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 |
|---|
| 5584 | #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 |
|---|
| 5585 | #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff |
|---|
| 5586 | #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 |
|---|
| 5587 | #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 |
|---|
| 5588 | #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 |
|---|
| 5589 | #define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 |
|---|
| 5590 | #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 |
|---|
| 5591 | #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 |
|---|
| 5592 | #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 5593 | #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 |
|---|
| 5594 | #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 |
|---|
| 5595 | #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 |
|---|
| 5596 | #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 5597 | #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
|---|
| 5598 | #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
|---|
| 5599 | #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 |
|---|
| 5600 | #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 |
|---|
| 5601 | #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 |
|---|
| 5602 | #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 |
|---|
| 5603 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 |
|---|
| 5604 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
|---|
| 5605 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 |
|---|
| 5606 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 |
|---|
| 5607 | #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 |
|---|
| 5608 | #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
|---|
| 5609 | #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 |
|---|
| 5610 | #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 |
|---|
| 5611 | #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 |
|---|
| 5612 | #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 |
|---|
| 5613 | #define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000 |
|---|
| 5614 | #define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10 |
|---|
| 5615 | #define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000 |
|---|
| 5616 | #define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11 |
|---|
| 5617 | #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff |
|---|
| 5618 | #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 |
|---|
| 5619 | #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff |
|---|
| 5620 | #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 |
|---|
| 5621 | #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff |
|---|
| 5622 | #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 |
|---|
| 5623 | #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 |
|---|
| 5624 | #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 |
|---|
| 5625 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff |
|---|
| 5626 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 |
|---|
| 5627 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 |
|---|
| 5628 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa |
|---|
| 5629 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 |
|---|
| 5630 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 |
|---|
| 5631 | #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 |
|---|
| 5632 | #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 |
|---|
| 5633 | #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 |
|---|
| 5634 | #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 |
|---|
| 5635 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 |
|---|
| 5636 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 |
|---|
| 5637 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 |
|---|
| 5638 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 |
|---|
| 5639 | #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf |
|---|
| 5640 | #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 |
|---|
| 5641 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 |
|---|
| 5642 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 |
|---|
| 5643 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 |
|---|
| 5644 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 |
|---|
| 5645 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 |
|---|
| 5646 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 |
|---|
| 5647 | #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 |
|---|
| 5648 | #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 |
|---|
| 5649 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 |
|---|
| 5650 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc |
|---|
| 5651 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 |
|---|
| 5652 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd |
|---|
| 5653 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 |
|---|
| 5654 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe |
|---|
| 5655 | #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 |
|---|
| 5656 | #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 |
|---|
| 5657 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 |
|---|
| 5658 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 |
|---|
| 5659 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 |
|---|
| 5660 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 |
|---|
| 5661 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 |
|---|
| 5662 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 |
|---|
| 5663 | #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff |
|---|
| 5664 | #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
|---|
| 5665 | #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff |
|---|
| 5666 | #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
|---|
| 5667 | #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff |
|---|
| 5668 | #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
|---|
| 5669 | #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff |
|---|
| 5670 | #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 |
|---|
| 5671 | #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff |
|---|
| 5672 | #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 |
|---|
| 5673 | #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff |
|---|
| 5674 | #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 |
|---|
| 5675 | #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 |
|---|
| 5676 | #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 |
|---|
| 5677 | #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c |
|---|
| 5678 | #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 |
|---|
| 5679 | #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 |
|---|
| 5680 | #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 |
|---|
| 5681 | #define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff |
|---|
| 5682 | #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 |
|---|
| 5683 | #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff |
|---|
| 5684 | #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 |
|---|
| 5685 | #define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff |
|---|
| 5686 | #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 |
|---|
| 5687 | #define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff |
|---|
| 5688 | #define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 |
|---|
| 5689 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 |
|---|
| 5690 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 |
|---|
| 5691 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 |
|---|
| 5692 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 |
|---|
| 5693 | #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 |
|---|
| 5694 | #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 |
|---|
| 5695 | #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 |
|---|
| 5696 | #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 |
|---|
| 5697 | #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 |
|---|
| 5698 | #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 |
|---|
| 5699 | #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300 |
|---|
| 5700 | #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8 |
|---|
| 5701 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 |
|---|
| 5702 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc |
|---|
| 5703 | #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 |
|---|
| 5704 | #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 |
|---|
| 5705 | #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000 |
|---|
| 5706 | #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11 |
|---|
| 5707 | #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000 |
|---|
| 5708 | #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13 |
|---|
| 5709 | #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 |
|---|
| 5710 | #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 |
|---|
| 5711 | #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 |
|---|
| 5712 | #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b |
|---|
| 5713 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 |
|---|
| 5714 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c |
|---|
| 5715 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf |
|---|
| 5716 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 |
|---|
| 5717 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0 |
|---|
| 5718 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 |
|---|
| 5719 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1 |
|---|
| 5720 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0 |
|---|
| 5721 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5722 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5723 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1 |
|---|
| 5724 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0 |
|---|
| 5725 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300 |
|---|
| 5726 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8 |
|---|
| 5727 | #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000 |
|---|
| 5728 | #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10 |
|---|
| 5729 | #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000 |
|---|
| 5730 | #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11 |
|---|
| 5731 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 |
|---|
| 5732 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c |
|---|
| 5733 | #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5734 | #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5735 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 5736 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 5737 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 5738 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 5739 | #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 5740 | #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 5741 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 |
|---|
| 5742 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 |
|---|
| 5743 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 |
|---|
| 5744 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 |
|---|
| 5745 | #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 |
|---|
| 5746 | #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 |
|---|
| 5747 | #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 |
|---|
| 5748 | #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 |
|---|
| 5749 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 |
|---|
| 5750 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c |
|---|
| 5751 | #define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff |
|---|
| 5752 | #define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 |
|---|
| 5753 | #define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 |
|---|
| 5754 | #define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 |
|---|
| 5755 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 |
|---|
| 5756 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 |
|---|
| 5757 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 |
|---|
| 5758 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 |
|---|
| 5759 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 |
|---|
| 5760 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 |
|---|
| 5761 | #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 |
|---|
| 5762 | #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 |
|---|
| 5763 | #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70 |
|---|
| 5764 | #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4 |
|---|
| 5765 | #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff |
|---|
| 5766 | #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 |
|---|
| 5767 | #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff |
|---|
| 5768 | #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 |
|---|
| 5769 | #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 |
|---|
| 5770 | #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 |
|---|
| 5771 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff |
|---|
| 5772 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 |
|---|
| 5773 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
|---|
| 5774 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
|---|
| 5775 | #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
|---|
| 5776 | #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
|---|
| 5777 | #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff |
|---|
| 5778 | #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 |
|---|
| 5779 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff |
|---|
| 5780 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 |
|---|
| 5781 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 |
|---|
| 5782 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 |
|---|
| 5783 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff |
|---|
| 5784 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5785 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5786 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5787 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5788 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5789 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5790 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5791 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff |
|---|
| 5792 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5793 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5794 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5795 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5796 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5797 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5798 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5799 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff |
|---|
| 5800 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5801 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5802 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5803 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5804 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5805 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5806 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5807 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff |
|---|
| 5808 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5809 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5810 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5811 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5812 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5813 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5814 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5815 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff |
|---|
| 5816 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5817 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5818 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5819 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5820 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5821 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5822 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5823 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff |
|---|
| 5824 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5825 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5826 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5827 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5828 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5829 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5830 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5831 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff |
|---|
| 5832 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5833 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5834 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5835 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5836 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5837 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5838 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5839 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff |
|---|
| 5840 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5841 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5842 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5843 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5844 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5845 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5846 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5847 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff |
|---|
| 5848 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 |
|---|
| 5849 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
|---|
| 5850 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
|---|
| 5851 | #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
|---|
| 5852 | #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
|---|
| 5853 | #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff |
|---|
| 5854 | #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 |
|---|
| 5855 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff |
|---|
| 5856 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 |
|---|
| 5857 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 |
|---|
| 5858 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 |
|---|
| 5859 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff |
|---|
| 5860 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5861 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5862 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5863 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5864 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5865 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5866 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5867 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff |
|---|
| 5868 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5869 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5870 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5871 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5872 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5873 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5874 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5875 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff |
|---|
| 5876 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5877 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5878 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5879 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5880 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5881 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5882 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5883 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff |
|---|
| 5884 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5885 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5886 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5887 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5888 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5889 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5890 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5891 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff |
|---|
| 5892 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5893 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5894 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5895 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5896 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5897 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5898 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5899 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff |
|---|
| 5900 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5901 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5902 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5903 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5904 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5905 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5906 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5907 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff |
|---|
| 5908 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5909 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5910 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5911 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5912 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5913 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5914 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5915 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff |
|---|
| 5916 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
|---|
| 5917 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 |
|---|
| 5918 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
|---|
| 5919 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 |
|---|
| 5920 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
|---|
| 5921 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 |
|---|
| 5922 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
|---|
| 5923 | #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 |
|---|
| 5924 | #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 |
|---|
| 5925 | #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 |
|---|
| 5926 | #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 |
|---|
| 5927 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 |
|---|
| 5928 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 |
|---|
| 5929 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff |
|---|
| 5930 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 5931 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff |
|---|
| 5932 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 |
|---|
| 5933 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 |
|---|
| 5934 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 |
|---|
| 5935 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 |
|---|
| 5936 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 |
|---|
| 5937 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 |
|---|
| 5938 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a |
|---|
| 5939 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 |
|---|
| 5940 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c |
|---|
| 5941 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 |
|---|
| 5942 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d |
|---|
| 5943 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 |
|---|
| 5944 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e |
|---|
| 5945 | #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 |
|---|
| 5946 | #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 5947 | #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 |
|---|
| 5948 | #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
|---|
| 5949 | #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 |
|---|
| 5950 | #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
|---|
| 5951 | #define DIG_FE_CNTL__DIG_START_MASK 0x400 |
|---|
| 5952 | #define DIG_FE_CNTL__DIG_START__SHIFT 0xa |
|---|
| 5953 | #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 |
|---|
| 5954 | #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
|---|
| 5955 | #define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000 |
|---|
| 5956 | #define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
|---|
| 5957 | #define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000 |
|---|
| 5958 | #define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
|---|
| 5959 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 |
|---|
| 5960 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
|---|
| 5961 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 |
|---|
| 5962 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
|---|
| 5963 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 |
|---|
| 5964 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
|---|
| 5965 | #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff |
|---|
| 5966 | #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
|---|
| 5967 | #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff |
|---|
| 5968 | #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
|---|
| 5969 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 |
|---|
| 5970 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
|---|
| 5971 | #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 |
|---|
| 5972 | #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
|---|
| 5973 | #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4 |
|---|
| 5974 | #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2 |
|---|
| 5975 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 |
|---|
| 5976 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
|---|
| 5977 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 |
|---|
| 5978 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
|---|
| 5979 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 |
|---|
| 5980 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
|---|
| 5981 | #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100 |
|---|
| 5982 | #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8 |
|---|
| 5983 | #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 |
|---|
| 5984 | #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
|---|
| 5985 | #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff |
|---|
| 5986 | #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
|---|
| 5987 | #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 |
|---|
| 5988 | #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
|---|
| 5989 | #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 |
|---|
| 5990 | #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
|---|
| 5991 | #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
|---|
| 5992 | #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
|---|
| 5993 | #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
|---|
| 5994 | #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
|---|
| 5995 | #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 |
|---|
| 5996 | #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
|---|
| 5997 | #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
|---|
| 5998 | #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
|---|
| 5999 | #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 |
|---|
| 6000 | #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
|---|
| 6001 | #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
|---|
| 6002 | #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
|---|
| 6003 | #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 |
|---|
| 6004 | #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
|---|
| 6005 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
|---|
| 6006 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
|---|
| 6007 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
|---|
| 6008 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
|---|
| 6009 | #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 |
|---|
| 6010 | #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 |
|---|
| 6011 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 |
|---|
| 6012 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 |
|---|
| 6013 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 |
|---|
| 6014 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 |
|---|
| 6015 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 |
|---|
| 6016 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 |
|---|
| 6017 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 |
|---|
| 6018 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc |
|---|
| 6019 | #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 |
|---|
| 6020 | #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
|---|
| 6021 | #define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 |
|---|
| 6022 | #define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
|---|
| 6023 | #define 0x8 |
|---|
| 6024 | #define 0x3 |
|---|
| 6025 | #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 |
|---|
| 6026 | #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
|---|
| 6027 | #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 |
|---|
| 6028 | #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
|---|
| 6029 | #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 |
|---|
| 6030 | #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
|---|
| 6031 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 |
|---|
| 6032 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
|---|
| 6033 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 |
|---|
| 6034 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
|---|
| 6035 | #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 |
|---|
| 6036 | #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
|---|
| 6037 | #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 |
|---|
| 6038 | #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
|---|
| 6039 | #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 |
|---|
| 6040 | #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
|---|
| 6041 | #define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 |
|---|
| 6042 | #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
|---|
| 6043 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 |
|---|
| 6044 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
|---|
| 6045 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 |
|---|
| 6046 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 |
|---|
| 6047 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 |
|---|
| 6048 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
|---|
| 6049 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 |
|---|
| 6050 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
|---|
| 6051 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 |
|---|
| 6052 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
|---|
| 6053 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 |
|---|
| 6054 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
|---|
| 6055 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 |
|---|
| 6056 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
|---|
| 6057 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 |
|---|
| 6058 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
|---|
| 6059 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 |
|---|
| 6060 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
|---|
| 6061 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 |
|---|
| 6062 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
|---|
| 6063 | #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 |
|---|
| 6064 | #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
|---|
| 6065 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 |
|---|
| 6066 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
|---|
| 6067 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 |
|---|
| 6068 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
|---|
| 6069 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 |
|---|
| 6070 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
|---|
| 6071 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 |
|---|
| 6072 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
|---|
| 6073 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 |
|---|
| 6074 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc |
|---|
| 6075 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 |
|---|
| 6076 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
|---|
| 6077 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 |
|---|
| 6078 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 |
|---|
| 6079 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 |
|---|
| 6080 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 |
|---|
| 6081 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 |
|---|
| 6082 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
|---|
| 6083 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 |
|---|
| 6084 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
|---|
| 6085 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 |
|---|
| 6086 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
|---|
| 6087 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 |
|---|
| 6088 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
|---|
| 6089 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f |
|---|
| 6090 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 |
|---|
| 6091 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 |
|---|
| 6092 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
|---|
| 6093 | #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 |
|---|
| 6094 | #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
|---|
| 6095 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 |
|---|
| 6096 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
|---|
| 6097 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 |
|---|
| 6098 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
|---|
| 6099 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 |
|---|
| 6100 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
|---|
| 6101 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 |
|---|
| 6102 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
|---|
| 6103 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 |
|---|
| 6104 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
|---|
| 6105 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 |
|---|
| 6106 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
|---|
| 6107 | #define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 |
|---|
| 6108 | #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
|---|
| 6109 | #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 |
|---|
| 6110 | #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
|---|
| 6111 | #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 |
|---|
| 6112 | #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
|---|
| 6113 | #define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 |
|---|
| 6114 | #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
|---|
| 6115 | #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 |
|---|
| 6116 | #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
|---|
| 6117 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 |
|---|
| 6118 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
|---|
| 6119 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 |
|---|
| 6120 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
|---|
| 6121 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 |
|---|
| 6122 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
|---|
| 6123 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 |
|---|
| 6124 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
|---|
| 6125 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 |
|---|
| 6126 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
|---|
| 6127 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 |
|---|
| 6128 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
|---|
| 6129 | #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 |
|---|
| 6130 | #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
|---|
| 6131 | #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 |
|---|
| 6132 | #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
|---|
| 6133 | #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 |
|---|
| 6134 | #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
|---|
| 6135 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff |
|---|
| 6136 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
|---|
| 6137 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 |
|---|
| 6138 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
|---|
| 6139 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 |
|---|
| 6140 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
|---|
| 6141 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 |
|---|
| 6142 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
|---|
| 6143 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff |
|---|
| 6144 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
|---|
| 6145 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 |
|---|
| 6146 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
|---|
| 6147 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 |
|---|
| 6148 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
|---|
| 6149 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 |
|---|
| 6150 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
|---|
| 6151 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff |
|---|
| 6152 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
|---|
| 6153 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 |
|---|
| 6154 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
|---|
| 6155 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 |
|---|
| 6156 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
|---|
| 6157 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 |
|---|
| 6158 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
|---|
| 6159 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff |
|---|
| 6160 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
|---|
| 6161 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 |
|---|
| 6162 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
|---|
| 6163 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 |
|---|
| 6164 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
|---|
| 6165 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 |
|---|
| 6166 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
|---|
| 6167 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff |
|---|
| 6168 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
|---|
| 6169 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 |
|---|
| 6170 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
|---|
| 6171 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 |
|---|
| 6172 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
|---|
| 6173 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 |
|---|
| 6174 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
|---|
| 6175 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff |
|---|
| 6176 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
|---|
| 6177 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 |
|---|
| 6178 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
|---|
| 6179 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 |
|---|
| 6180 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
|---|
| 6181 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 |
|---|
| 6182 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
|---|
| 6183 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff |
|---|
| 6184 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
|---|
| 6185 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 |
|---|
| 6186 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
|---|
| 6187 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 |
|---|
| 6188 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
|---|
| 6189 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 |
|---|
| 6190 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
|---|
| 6191 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff |
|---|
| 6192 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
|---|
| 6193 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 |
|---|
| 6194 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
|---|
| 6195 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 |
|---|
| 6196 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
|---|
| 6197 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 |
|---|
| 6198 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
|---|
| 6199 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff |
|---|
| 6200 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 |
|---|
| 6201 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 |
|---|
| 6202 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 |
|---|
| 6203 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 |
|---|
| 6204 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa |
|---|
| 6205 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 |
|---|
| 6206 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc |
|---|
| 6207 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 |
|---|
| 6208 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd |
|---|
| 6209 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 |
|---|
| 6210 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf |
|---|
| 6211 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 |
|---|
| 6212 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 |
|---|
| 6213 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 |
|---|
| 6214 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 |
|---|
| 6215 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 |
|---|
| 6216 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 |
|---|
| 6217 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 |
|---|
| 6218 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 |
|---|
| 6219 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 |
|---|
| 6220 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a |
|---|
| 6221 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 |
|---|
| 6222 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c |
|---|
| 6223 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 |
|---|
| 6224 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f |
|---|
| 6225 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f |
|---|
| 6226 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 |
|---|
| 6227 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 |
|---|
| 6228 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 |
|---|
| 6229 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 |
|---|
| 6230 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 |
|---|
| 6231 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 |
|---|
| 6232 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc |
|---|
| 6233 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 |
|---|
| 6234 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe |
|---|
| 6235 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 |
|---|
| 6236 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 |
|---|
| 6237 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff |
|---|
| 6238 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 |
|---|
| 6239 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 |
|---|
| 6240 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 |
|---|
| 6241 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff |
|---|
| 6242 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 |
|---|
| 6243 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 |
|---|
| 6244 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 |
|---|
| 6245 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff |
|---|
| 6246 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
|---|
| 6247 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 |
|---|
| 6248 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
|---|
| 6249 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 |
|---|
| 6250 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
|---|
| 6251 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 |
|---|
| 6252 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
|---|
| 6253 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff |
|---|
| 6254 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
|---|
| 6255 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 |
|---|
| 6256 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
|---|
| 6257 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 |
|---|
| 6258 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
|---|
| 6259 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff |
|---|
| 6260 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
|---|
| 6261 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 |
|---|
| 6262 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
|---|
| 6263 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 |
|---|
| 6264 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
|---|
| 6265 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 |
|---|
| 6266 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
|---|
| 6267 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff |
|---|
| 6268 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
|---|
| 6269 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 |
|---|
| 6270 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
|---|
| 6271 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 |
|---|
| 6272 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
|---|
| 6273 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 |
|---|
| 6274 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
|---|
| 6275 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff |
|---|
| 6276 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
|---|
| 6277 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 |
|---|
| 6278 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
|---|
| 6279 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 |
|---|
| 6280 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
|---|
| 6281 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 |
|---|
| 6282 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
|---|
| 6283 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff |
|---|
| 6284 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
|---|
| 6285 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 |
|---|
| 6286 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
|---|
| 6287 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 |
|---|
| 6288 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
|---|
| 6289 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 |
|---|
| 6290 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
|---|
| 6291 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff |
|---|
| 6292 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
|---|
| 6293 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 |
|---|
| 6294 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
|---|
| 6295 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 |
|---|
| 6296 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
|---|
| 6297 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 |
|---|
| 6298 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
|---|
| 6299 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff |
|---|
| 6300 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
|---|
| 6301 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 |
|---|
| 6302 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
|---|
| 6303 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 |
|---|
| 6304 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
|---|
| 6305 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 |
|---|
| 6306 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
|---|
| 6307 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff |
|---|
| 6308 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
|---|
| 6309 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 |
|---|
| 6310 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
|---|
| 6311 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 |
|---|
| 6312 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
|---|
| 6313 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 |
|---|
| 6314 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
|---|
| 6315 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff |
|---|
| 6316 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
|---|
| 6317 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 |
|---|
| 6318 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
|---|
| 6319 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 |
|---|
| 6320 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
|---|
| 6321 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 |
|---|
| 6322 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
|---|
| 6323 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff |
|---|
| 6324 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
|---|
| 6325 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 |
|---|
| 6326 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
|---|
| 6327 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 |
|---|
| 6328 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
|---|
| 6329 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 |
|---|
| 6330 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
|---|
| 6331 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 |
|---|
| 6332 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
|---|
| 6333 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 |
|---|
| 6334 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
|---|
| 6335 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 |
|---|
| 6336 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
|---|
| 6337 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 |
|---|
| 6338 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
|---|
| 6339 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 |
|---|
| 6340 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
|---|
| 6341 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 |
|---|
| 6342 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
|---|
| 6343 | #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 |
|---|
| 6344 | #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
|---|
| 6345 | #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff |
|---|
| 6346 | #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
|---|
| 6347 | #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 |
|---|
| 6348 | #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
|---|
| 6349 | #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff |
|---|
| 6350 | #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
|---|
| 6351 | #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 |
|---|
| 6352 | #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
|---|
| 6353 | #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff |
|---|
| 6354 | #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
|---|
| 6355 | #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 |
|---|
| 6356 | #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
|---|
| 6357 | #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff |
|---|
| 6358 | #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
|---|
| 6359 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff |
|---|
| 6360 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
|---|
| 6361 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 |
|---|
| 6362 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
|---|
| 6363 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 |
|---|
| 6364 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
|---|
| 6365 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 |
|---|
| 6366 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
|---|
| 6367 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 |
|---|
| 6368 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
|---|
| 6369 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff |
|---|
| 6370 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
|---|
| 6371 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 |
|---|
| 6372 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
|---|
| 6373 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 |
|---|
| 6374 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
|---|
| 6375 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 |
|---|
| 6376 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
|---|
| 6377 | #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 |
|---|
| 6378 | #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
|---|
| 6379 | #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 |
|---|
| 6380 | #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
|---|
| 6381 | #define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 |
|---|
| 6382 | #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
|---|
| 6383 | #define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 |
|---|
| 6384 | #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
|---|
| 6385 | #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 |
|---|
| 6386 | #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
|---|
| 6387 | #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 |
|---|
| 6388 | #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
|---|
| 6389 | #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 |
|---|
| 6390 | #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
|---|
| 6391 | #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 |
|---|
| 6392 | #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
|---|
| 6393 | #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 |
|---|
| 6394 | #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
|---|
| 6395 | #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 |
|---|
| 6396 | #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
|---|
| 6397 | #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf |
|---|
| 6398 | #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
|---|
| 6399 | #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 |
|---|
| 6400 | #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
|---|
| 6401 | #define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 |
|---|
| 6402 | #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
|---|
| 6403 | #define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 |
|---|
| 6404 | #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
|---|
| 6405 | #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 |
|---|
| 6406 | #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
|---|
| 6407 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 |
|---|
| 6408 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
|---|
| 6409 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 |
|---|
| 6410 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
|---|
| 6411 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 |
|---|
| 6412 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
|---|
| 6413 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 |
|---|
| 6414 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
|---|
| 6415 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 |
|---|
| 6416 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
|---|
| 6417 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff |
|---|
| 6418 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
|---|
| 6419 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 |
|---|
| 6420 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
|---|
| 6421 | #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff |
|---|
| 6422 | #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
|---|
| 6423 | #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 |
|---|
| 6424 | #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
|---|
| 6425 | #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff |
|---|
| 6426 | #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
|---|
| 6427 | #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff |
|---|
| 6428 | #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
|---|
| 6429 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
|---|
| 6430 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
|---|
| 6431 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
|---|
| 6432 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
|---|
| 6433 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 |
|---|
| 6434 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
|---|
| 6435 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 |
|---|
| 6436 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
|---|
| 6437 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 |
|---|
| 6438 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
|---|
| 6439 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 |
|---|
| 6440 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
|---|
| 6441 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 |
|---|
| 6442 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
|---|
| 6443 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 |
|---|
| 6444 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
|---|
| 6445 | #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 |
|---|
| 6446 | #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
|---|
| 6447 | #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 |
|---|
| 6448 | #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
|---|
| 6449 | #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 |
|---|
| 6450 | #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
|---|
| 6451 | #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 |
|---|
| 6452 | #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
|---|
| 6453 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 |
|---|
| 6454 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
|---|
| 6455 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 |
|---|
| 6456 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
|---|
| 6457 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 |
|---|
| 6458 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
|---|
| 6459 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 |
|---|
| 6460 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
|---|
| 6461 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 |
|---|
| 6462 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
|---|
| 6463 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 |
|---|
| 6464 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
|---|
| 6465 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 |
|---|
| 6466 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
|---|
| 6467 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 |
|---|
| 6468 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
|---|
| 6469 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 |
|---|
| 6470 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f |
|---|
| 6471 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 |
|---|
| 6472 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 |
|---|
| 6473 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 |
|---|
| 6474 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 |
|---|
| 6475 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 |
|---|
| 6476 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e |
|---|
| 6477 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 |
|---|
| 6478 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
|---|
| 6479 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 |
|---|
| 6480 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
|---|
| 6481 | #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 |
|---|
| 6482 | #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
|---|
| 6483 | #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 |
|---|
| 6484 | #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
|---|
| 6485 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 |
|---|
| 6486 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 |
|---|
| 6487 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 |
|---|
| 6488 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 |
|---|
| 6489 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 |
|---|
| 6490 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc |
|---|
| 6491 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 |
|---|
| 6492 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 |
|---|
| 6493 | #define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1 |
|---|
| 6494 | #define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
|---|
| 6495 | #define DIG_BE_CNTL__DIG_SWAP_MASK 0x2 |
|---|
| 6496 | #define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
|---|
| 6497 | #define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4 |
|---|
| 6498 | #define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 |
|---|
| 6499 | #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 |
|---|
| 6500 | #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
|---|
| 6501 | #define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 |
|---|
| 6502 | #define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
|---|
| 6503 | #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 |
|---|
| 6504 | #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
|---|
| 6505 | #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 |
|---|
| 6506 | #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
|---|
| 6507 | #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 |
|---|
| 6508 | #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
|---|
| 6509 | #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 |
|---|
| 6510 | #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
|---|
| 6511 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 |
|---|
| 6512 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
|---|
| 6513 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 |
|---|
| 6514 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
|---|
| 6515 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 |
|---|
| 6516 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
|---|
| 6517 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 |
|---|
| 6518 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
|---|
| 6519 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 |
|---|
| 6520 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
|---|
| 6521 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 |
|---|
| 6522 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
|---|
| 6523 | #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 |
|---|
| 6524 | #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
|---|
| 6525 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff |
|---|
| 6526 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
|---|
| 6527 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 |
|---|
| 6528 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
|---|
| 6529 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff |
|---|
| 6530 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
|---|
| 6531 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 |
|---|
| 6532 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
|---|
| 6533 | #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 |
|---|
| 6534 | #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 |
|---|
| 6535 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 |
|---|
| 6536 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 |
|---|
| 6537 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 |
|---|
| 6538 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 |
|---|
| 6539 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 |
|---|
| 6540 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 |
|---|
| 6541 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 |
|---|
| 6542 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 |
|---|
| 6543 | #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 |
|---|
| 6544 | #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 |
|---|
| 6545 | #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 |
|---|
| 6546 | #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 |
|---|
| 6547 | #define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 |
|---|
| 6548 | #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
|---|
| 6549 | #define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 |
|---|
| 6550 | #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
|---|
| 6551 | #define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 |
|---|
| 6552 | #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
|---|
| 6553 | #define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 |
|---|
| 6554 | #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
|---|
| 6555 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 |
|---|
| 6556 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
|---|
| 6557 | #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 |
|---|
| 6558 | #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 |
|---|
| 6559 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 |
|---|
| 6560 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
|---|
| 6561 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 |
|---|
| 6562 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
|---|
| 6563 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 |
|---|
| 6564 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
|---|
| 6565 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf |
|---|
| 6566 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
|---|
| 6567 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 |
|---|
| 6568 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
|---|
| 6569 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 |
|---|
| 6570 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
|---|
| 6571 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 |
|---|
| 6572 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
|---|
| 6573 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 |
|---|
| 6574 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
|---|
| 6575 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 |
|---|
| 6576 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
|---|
| 6577 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 |
|---|
| 6578 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
|---|
| 6579 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 |
|---|
| 6580 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
|---|
| 6581 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 |
|---|
| 6582 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
|---|
| 6583 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 |
|---|
| 6584 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
|---|
| 6585 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 |
|---|
| 6586 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
|---|
| 6587 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 |
|---|
| 6588 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
|---|
| 6589 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 |
|---|
| 6590 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
|---|
| 6591 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 |
|---|
| 6592 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
|---|
| 6593 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 |
|---|
| 6594 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
|---|
| 6595 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf |
|---|
| 6596 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
|---|
| 6597 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 |
|---|
| 6598 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
|---|
| 6599 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 |
|---|
| 6600 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
|---|
| 6601 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 |
|---|
| 6602 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
|---|
| 6603 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 |
|---|
| 6604 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
|---|
| 6605 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 |
|---|
| 6606 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
|---|
| 6607 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 |
|---|
| 6608 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
|---|
| 6609 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 |
|---|
| 6610 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
|---|
| 6611 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 |
|---|
| 6612 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
|---|
| 6613 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 |
|---|
| 6614 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
|---|
| 6615 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 |
|---|
| 6616 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
|---|
| 6617 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 |
|---|
| 6618 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
|---|
| 6619 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 |
|---|
| 6620 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
|---|
| 6621 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 |
|---|
| 6622 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
|---|
| 6623 | #define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK 0x1 |
|---|
| 6624 | #define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 |
|---|
| 6625 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK 0x2 |
|---|
| 6626 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT 0x1 |
|---|
| 6627 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK 0x4 |
|---|
| 6628 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT 0x2 |
|---|
| 6629 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK 0x8 |
|---|
| 6630 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT 0x3 |
|---|
| 6631 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK 0xff0 |
|---|
| 6632 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT 0x4 |
|---|
| 6633 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK 0x1000 |
|---|
| 6634 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT 0xc |
|---|
| 6635 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK 0x2000 |
|---|
| 6636 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT 0xd |
|---|
| 6637 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK 0x3fc000 |
|---|
| 6638 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT 0xe |
|---|
| 6639 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK 0x400000 |
|---|
| 6640 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT 0x16 |
|---|
| 6641 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK 0x800000 |
|---|
| 6642 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT 0x17 |
|---|
| 6643 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK 0x1000000 |
|---|
| 6644 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT 0x18 |
|---|
| 6645 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK 0x2000000 |
|---|
| 6646 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT 0x19 |
|---|
| 6647 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK 0x4000000 |
|---|
| 6648 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT 0x1a |
|---|
| 6649 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK 0x8000000 |
|---|
| 6650 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT 0x1b |
|---|
| 6651 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK 0x10000000 |
|---|
| 6652 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT 0x1c |
|---|
| 6653 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK 0x20000000 |
|---|
| 6654 | #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT 0x1d |
|---|
| 6655 | #define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK 0x1 |
|---|
| 6656 | #define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 |
|---|
| 6657 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK 0x2 |
|---|
| 6658 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT 0x1 |
|---|
| 6659 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK 0x4 |
|---|
| 6660 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT 0x2 |
|---|
| 6661 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK 0x8 |
|---|
| 6662 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT 0x3 |
|---|
| 6663 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK 0xff0 |
|---|
| 6664 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT 0x4 |
|---|
| 6665 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK 0x1ff000 |
|---|
| 6666 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT 0xc |
|---|
| 6667 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK 0x200000 |
|---|
| 6668 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT 0x15 |
|---|
| 6669 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK 0xffc00000 |
|---|
| 6670 | #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT 0x16 |
|---|
| 6671 | #define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK 0x1 |
|---|
| 6672 | #define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 |
|---|
| 6673 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK 0x2 |
|---|
| 6674 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT 0x1 |
|---|
| 6675 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK 0xffc |
|---|
| 6676 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT 0x2 |
|---|
| 6677 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK 0x1000 |
|---|
| 6678 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT 0xc |
|---|
| 6679 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK 0x2000 |
|---|
| 6680 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT 0xd |
|---|
| 6681 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK 0x4000 |
|---|
| 6682 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT 0xe |
|---|
| 6683 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK 0x8000 |
|---|
| 6684 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT 0xf |
|---|
| 6685 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK 0x100000 |
|---|
| 6686 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT 0x14 |
|---|
| 6687 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK 0x200000 |
|---|
| 6688 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT 0x15 |
|---|
| 6689 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK 0xffc00000 |
|---|
| 6690 | #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT 0x16 |
|---|
| 6691 | #define TMDS_DEBUG7__DBG_DIG_TMDS7_MASK 0xffffffff |
|---|
| 6692 | #define TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT 0x0 |
|---|
| 6693 | #define TMDS_DEBUG8__DBG_DIG_TMDS8_MASK 0xffffffff |
|---|
| 6694 | #define TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT 0x0 |
|---|
| 6695 | #define TMDS_DEBUG9__DBG_DIG_TMDS9_MASK 0xffffffff |
|---|
| 6696 | #define TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT 0x0 |
|---|
| 6697 | #define TMDS_DEBUG10__DBG_DIG_TMDS10_MASK 0xffffffff |
|---|
| 6698 | #define TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT 0x0 |
|---|
| 6699 | #define TMDS_DEBUG11__DBG_DIG_TMDS11_MASK 0xffffffff |
|---|
| 6700 | #define TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT 0x0 |
|---|
| 6701 | #define TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK 0xffffffff |
|---|
| 6702 | #define TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT 0x0 |
|---|
| 6703 | #define TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK 0xffffffff |
|---|
| 6704 | #define TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT 0x0 |
|---|
| 6705 | #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1 |
|---|
| 6706 | #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0 |
|---|
| 6707 | #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10 |
|---|
| 6708 | #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4 |
|---|
| 6709 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100 |
|---|
| 6710 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8 |
|---|
| 6711 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200 |
|---|
| 6712 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9 |
|---|
| 6713 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400 |
|---|
| 6714 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa |
|---|
| 6715 | #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000 |
|---|
| 6716 | #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc |
|---|
| 6717 | #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000 |
|---|
| 6718 | #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10 |
|---|
| 6719 | #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000 |
|---|
| 6720 | #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11 |
|---|
| 6721 | #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000 |
|---|
| 6722 | #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12 |
|---|
| 6723 | #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 |
|---|
| 6724 | #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
|---|
| 6725 | #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 |
|---|
| 6726 | #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
|---|
| 6727 | #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 |
|---|
| 6728 | #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
|---|
| 6729 | #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 |
|---|
| 6730 | #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
|---|
| 6731 | #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 |
|---|
| 6732 | #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
|---|
| 6733 | #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 6734 | #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 6735 | #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 6736 | #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 6737 | #define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 6738 | #define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 6739 | #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 6740 | #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 6741 | #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 6742 | #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 6743 | #define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 6744 | #define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 6745 | #define DMCU_CTRL__RESET_UC_MASK 0x1 |
|---|
| 6746 | #define DMCU_CTRL__RESET_UC__SHIFT 0x0 |
|---|
| 6747 | #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 |
|---|
| 6748 | #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 |
|---|
| 6749 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 |
|---|
| 6750 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 |
|---|
| 6751 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 |
|---|
| 6752 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 |
|---|
| 6753 | #define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 |
|---|
| 6754 | #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 |
|---|
| 6755 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000 |
|---|
| 6756 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 |
|---|
| 6757 | #define DMCU_STATUS__UC_IN_RESET_MASK 0x1 |
|---|
| 6758 | #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 |
|---|
| 6759 | #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 |
|---|
| 6760 | #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 |
|---|
| 6761 | #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 |
|---|
| 6762 | #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 |
|---|
| 6763 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff |
|---|
| 6764 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 |
|---|
| 6765 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 |
|---|
| 6766 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 |
|---|
| 6767 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff |
|---|
| 6768 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 |
|---|
| 6769 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 |
|---|
| 6770 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 |
|---|
| 6771 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff |
|---|
| 6772 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 |
|---|
| 6773 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 |
|---|
| 6774 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 |
|---|
| 6775 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff |
|---|
| 6776 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 |
|---|
| 6777 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 |
|---|
| 6778 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 |
|---|
| 6779 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff |
|---|
| 6780 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 |
|---|
| 6781 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff |
|---|
| 6782 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 |
|---|
| 6783 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 |
|---|
| 6784 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 |
|---|
| 6785 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 |
|---|
| 6786 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 |
|---|
| 6787 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 |
|---|
| 6788 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 |
|---|
| 6789 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 |
|---|
| 6790 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 |
|---|
| 6791 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 |
|---|
| 6792 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 |
|---|
| 6793 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 |
|---|
| 6794 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 |
|---|
| 6795 | #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00 |
|---|
| 6796 | #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8 |
|---|
| 6797 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff |
|---|
| 6798 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 |
|---|
| 6799 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 |
|---|
| 6800 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 |
|---|
| 6801 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 |
|---|
| 6802 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 |
|---|
| 6803 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff |
|---|
| 6804 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 |
|---|
| 6805 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff |
|---|
| 6806 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 |
|---|
| 6807 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 |
|---|
| 6808 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 |
|---|
| 6809 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 |
|---|
| 6810 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 |
|---|
| 6811 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff |
|---|
| 6812 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 |
|---|
| 6813 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff |
|---|
| 6814 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 |
|---|
| 6815 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff |
|---|
| 6816 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 |
|---|
| 6817 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff |
|---|
| 6818 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 |
|---|
| 6819 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff |
|---|
| 6820 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 |
|---|
| 6821 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 |
|---|
| 6822 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 |
|---|
| 6823 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 |
|---|
| 6824 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 |
|---|
| 6825 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 |
|---|
| 6826 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 |
|---|
| 6827 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 |
|---|
| 6828 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 |
|---|
| 6829 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 |
|---|
| 6830 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 |
|---|
| 6831 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 |
|---|
| 6832 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 |
|---|
| 6833 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 |
|---|
| 6834 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 |
|---|
| 6835 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 |
|---|
| 6836 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 |
|---|
| 6837 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 |
|---|
| 6838 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 |
|---|
| 6839 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 |
|---|
| 6840 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 |
|---|
| 6841 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 |
|---|
| 6842 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 |
|---|
| 6843 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 |
|---|
| 6844 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 |
|---|
| 6845 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 |
|---|
| 6846 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 |
|---|
| 6847 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 |
|---|
| 6848 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa |
|---|
| 6849 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 |
|---|
| 6850 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb |
|---|
| 6851 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 |
|---|
| 6852 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc |
|---|
| 6853 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 |
|---|
| 6854 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd |
|---|
| 6855 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 |
|---|
| 6856 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe |
|---|
| 6857 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 |
|---|
| 6858 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf |
|---|
| 6859 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 |
|---|
| 6860 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd |
|---|
| 6861 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 |
|---|
| 6862 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe |
|---|
| 6863 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 |
|---|
| 6864 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe |
|---|
| 6865 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 |
|---|
| 6866 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf |
|---|
| 6867 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 |
|---|
| 6868 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 |
|---|
| 6869 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 |
|---|
| 6870 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 |
|---|
| 6871 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 |
|---|
| 6872 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 |
|---|
| 6873 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 |
|---|
| 6874 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 |
|---|
| 6875 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 |
|---|
| 6876 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 |
|---|
| 6877 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 |
|---|
| 6878 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 |
|---|
| 6879 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 |
|---|
| 6880 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 |
|---|
| 6881 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 |
|---|
| 6882 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 |
|---|
| 6883 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 |
|---|
| 6884 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 |
|---|
| 6885 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 |
|---|
| 6886 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 |
|---|
| 6887 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 |
|---|
| 6888 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 |
|---|
| 6889 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 |
|---|
| 6890 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 |
|---|
| 6891 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 |
|---|
| 6892 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 |
|---|
| 6893 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 |
|---|
| 6894 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 |
|---|
| 6895 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 |
|---|
| 6896 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 |
|---|
| 6897 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 |
|---|
| 6898 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 |
|---|
| 6899 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 |
|---|
| 6900 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 |
|---|
| 6901 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 |
|---|
| 6902 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 |
|---|
| 6903 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 |
|---|
| 6904 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 |
|---|
| 6905 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 |
|---|
| 6906 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 |
|---|
| 6907 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 |
|---|
| 6908 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 |
|---|
| 6909 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10 |
|---|
| 6910 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4 |
|---|
| 6911 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10 |
|---|
| 6912 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4 |
|---|
| 6913 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20 |
|---|
| 6914 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 |
|---|
| 6915 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20 |
|---|
| 6916 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5 |
|---|
| 6917 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 |
|---|
| 6918 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 |
|---|
| 6919 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 |
|---|
| 6920 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 |
|---|
| 6921 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 |
|---|
| 6922 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 |
|---|
| 6923 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 |
|---|
| 6924 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa |
|---|
| 6925 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 |
|---|
| 6926 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa |
|---|
| 6927 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 |
|---|
| 6928 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb |
|---|
| 6929 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 |
|---|
| 6930 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb |
|---|
| 6931 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 |
|---|
| 6932 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc |
|---|
| 6933 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 |
|---|
| 6934 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc |
|---|
| 6935 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 |
|---|
| 6936 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd |
|---|
| 6937 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 |
|---|
| 6938 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd |
|---|
| 6939 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 |
|---|
| 6940 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe |
|---|
| 6941 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 |
|---|
| 6942 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe |
|---|
| 6943 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 |
|---|
| 6944 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf |
|---|
| 6945 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 |
|---|
| 6946 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf |
|---|
| 6947 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 |
|---|
| 6948 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 |
|---|
| 6949 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 |
|---|
| 6950 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 |
|---|
| 6951 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 |
|---|
| 6952 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 |
|---|
| 6953 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 |
|---|
| 6954 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 |
|---|
| 6955 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 |
|---|
| 6956 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 |
|---|
| 6957 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 |
|---|
| 6958 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 |
|---|
| 6959 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 |
|---|
| 6960 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 |
|---|
| 6961 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 |
|---|
| 6962 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
|---|
| 6963 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 |
|---|
| 6964 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 |
|---|
| 6965 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 |
|---|
| 6966 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 |
|---|
| 6967 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 |
|---|
| 6968 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 |
|---|
| 6969 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 |
|---|
| 6970 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 |
|---|
| 6971 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 |
|---|
| 6972 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 |
|---|
| 6973 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 |
|---|
| 6974 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 |
|---|
| 6975 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 |
|---|
| 6976 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 |
|---|
| 6977 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 |
|---|
| 6978 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 |
|---|
| 6979 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 |
|---|
| 6980 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 |
|---|
| 6981 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 |
|---|
| 6982 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 |
|---|
| 6983 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 |
|---|
| 6984 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 |
|---|
| 6985 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 |
|---|
| 6986 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 |
|---|
| 6987 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 |
|---|
| 6988 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a |
|---|
| 6989 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 |
|---|
| 6990 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a |
|---|
| 6991 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 |
|---|
| 6992 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b |
|---|
| 6993 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 |
|---|
| 6994 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b |
|---|
| 6995 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 |
|---|
| 6996 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c |
|---|
| 6997 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 |
|---|
| 6998 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c |
|---|
| 6999 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 |
|---|
| 7000 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d |
|---|
| 7001 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 |
|---|
| 7002 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d |
|---|
| 7003 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 |
|---|
| 7004 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 |
|---|
| 7005 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 |
|---|
| 7006 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 |
|---|
| 7007 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 |
|---|
| 7008 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 |
|---|
| 7009 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK 0x10 |
|---|
| 7010 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT 0x4 |
|---|
| 7011 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK 0x20 |
|---|
| 7012 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT 0x5 |
|---|
| 7013 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 |
|---|
| 7014 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 |
|---|
| 7015 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 |
|---|
| 7016 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa |
|---|
| 7017 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 |
|---|
| 7018 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb |
|---|
| 7019 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000 |
|---|
| 7020 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc |
|---|
| 7021 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000 |
|---|
| 7022 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd |
|---|
| 7023 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000 |
|---|
| 7024 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe |
|---|
| 7025 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000 |
|---|
| 7026 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf |
|---|
| 7027 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000 |
|---|
| 7028 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 |
|---|
| 7029 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000 |
|---|
| 7030 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11 |
|---|
| 7031 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000 |
|---|
| 7032 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12 |
|---|
| 7033 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000 |
|---|
| 7034 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13 |
|---|
| 7035 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000 |
|---|
| 7036 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14 |
|---|
| 7037 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000 |
|---|
| 7038 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15 |
|---|
| 7039 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000 |
|---|
| 7040 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16 |
|---|
| 7041 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000 |
|---|
| 7042 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17 |
|---|
| 7043 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 |
|---|
| 7044 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 |
|---|
| 7045 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 |
|---|
| 7046 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 7047 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 |
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| 7048 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 |
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| 7049 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 |
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| 7050 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 |
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| 7051 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10 |
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| 7052 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 |
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| 7053 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20 |
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| 7054 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5 |
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| 7055 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40 |
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| 7056 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 |
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| 7057 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80 |
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| 7058 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 |
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| 7059 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 |
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| 7060 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 |
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| 7061 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200 |
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| 7062 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 |
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| 7063 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400 |
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| 7064 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa |
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| 7065 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800 |
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| 7066 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb |
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| 7067 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 |
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| 7068 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc |
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| 7069 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 |
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| 7070 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd |
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| 7071 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 |
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| 7072 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe |
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| 7073 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 |
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| 7074 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf |
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| 7075 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 |
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| 7076 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 |
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| 7077 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 |
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| 7078 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 |
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| 7079 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 |
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| 7080 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 |
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| 7081 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 |
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| 7082 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 |
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| 7083 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 |
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| 7084 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 |
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| 7085 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 |
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| 7086 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 |
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| 7087 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 |
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| 7088 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 |
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| 7089 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 |
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| 7090 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 |
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| 7091 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 |
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| 7092 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 |
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| 7093 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 |
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| 7094 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 |
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| 7095 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 |
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| 7096 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a |
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| 7097 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 |
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| 7098 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b |
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| 7099 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 |
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| 7100 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c |
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| 7101 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 |
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| 7102 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d |
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| 7103 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000 |
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| 7104 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e |
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| 7105 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 |
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| 7106 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
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| 7107 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 |
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| 7108 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
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| 7109 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 |
|---|
| 7110 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
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| 7111 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 |
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| 7112 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
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| 7113 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10 |
|---|
| 7114 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
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| 7115 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20 |
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| 7116 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
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| 7117 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 7118 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 7119 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 7120 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 7121 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 7122 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 7123 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200 |
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| 7124 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
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| 7125 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400 |
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| 7126 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
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| 7127 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800 |
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| 7128 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
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| 7129 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
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| 7130 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
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| 7131 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
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| 7132 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
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| 7133 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
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| 7134 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
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| 7135 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
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| 7136 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
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| 7137 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
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| 7138 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
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| 7139 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
|---|
| 7140 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
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| 7141 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
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| 7142 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
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| 7143 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
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| 7144 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
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| 7145 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
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| 7146 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
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| 7147 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
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| 7148 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
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| 7149 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
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| 7150 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
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| 7151 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
|---|
| 7152 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
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| 7153 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
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| 7154 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
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| 7155 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
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| 7156 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
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| 7157 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
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| 7158 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
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| 7159 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 |
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| 7160 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
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| 7161 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 |
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| 7162 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
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| 7163 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 |
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| 7164 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d |
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| 7165 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000 |
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| 7166 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e |
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| 7167 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff |
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| 7168 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 |
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| 7169 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff |
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| 7170 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 |
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| 7171 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 |
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| 7172 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 |
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| 7173 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 |
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| 7174 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 |
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| 7175 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 |
|---|
| 7176 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 |
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| 7177 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc |
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| 7178 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 |
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| 7179 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 |
|---|
| 7180 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 |
|---|
| 7181 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 |
|---|
| 7182 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 |
|---|
| 7183 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 |
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| 7184 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 |
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| 7185 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff |
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| 7186 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
|---|
| 7187 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 |
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| 7188 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
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| 7189 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 |
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| 7190 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
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| 7191 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 |
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| 7192 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
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| 7193 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff |
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| 7194 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
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| 7195 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 |
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| 7196 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
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| 7197 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 |
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| 7198 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
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| 7199 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 |
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| 7200 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
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| 7201 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff |
|---|
| 7202 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
|---|
| 7203 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 |
|---|
| 7204 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
|---|
| 7205 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 |
|---|
| 7206 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
|---|
| 7207 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 |
|---|
| 7208 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
|---|
| 7209 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff |
|---|
| 7210 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
|---|
| 7211 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 |
|---|
| 7212 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
|---|
| 7213 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 |
|---|
| 7214 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
|---|
| 7215 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 |
|---|
| 7216 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
|---|
| 7217 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 |
|---|
| 7218 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 |
|---|
| 7219 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff |
|---|
| 7220 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
|---|
| 7221 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 |
|---|
| 7222 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
|---|
| 7223 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 |
|---|
| 7224 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
|---|
| 7225 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 |
|---|
| 7226 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
|---|
| 7227 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff |
|---|
| 7228 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
|---|
| 7229 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 |
|---|
| 7230 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
|---|
| 7231 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 |
|---|
| 7232 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
|---|
| 7233 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 |
|---|
| 7234 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
|---|
| 7235 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff |
|---|
| 7236 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
|---|
| 7237 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 |
|---|
| 7238 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
|---|
| 7239 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 |
|---|
| 7240 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
|---|
| 7241 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 |
|---|
| 7242 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
|---|
| 7243 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff |
|---|
| 7244 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
|---|
| 7245 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 |
|---|
| 7246 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
|---|
| 7247 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 |
|---|
| 7248 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
|---|
| 7249 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 |
|---|
| 7250 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
|---|
| 7251 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 |
|---|
| 7252 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 |
|---|
| 7253 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 |
|---|
| 7254 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 |
|---|
| 7255 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 7256 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 7257 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 7258 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 7259 | #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 7260 | #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 7261 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
|---|
| 7262 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
|---|
| 7263 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
|---|
| 7264 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
|---|
| 7265 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
|---|
| 7266 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
|---|
| 7267 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
|---|
| 7268 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
|---|
| 7269 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
|---|
| 7270 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
|---|
| 7271 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
|---|
| 7272 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
|---|
| 7273 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
|---|
| 7274 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
|---|
| 7275 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
|---|
| 7276 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
|---|
| 7277 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
|---|
| 7278 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
|---|
| 7279 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
|---|
| 7280 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
|---|
| 7281 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
|---|
| 7282 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
|---|
| 7283 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
|---|
| 7284 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
|---|
| 7285 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
|---|
| 7286 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
|---|
| 7287 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
|---|
| 7288 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
|---|
| 7289 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
|---|
| 7290 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
|---|
| 7291 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
|---|
| 7292 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
|---|
| 7293 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
|---|
| 7294 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
|---|
| 7295 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
|---|
| 7296 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
|---|
| 7297 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
|---|
| 7298 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
|---|
| 7299 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
|---|
| 7300 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
|---|
| 7301 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
|---|
| 7302 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
|---|
| 7303 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
|---|
| 7304 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
|---|
| 7305 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
|---|
| 7306 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
|---|
| 7307 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
|---|
| 7308 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
|---|
| 7309 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
|---|
| 7310 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
|---|
| 7311 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
|---|
| 7312 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
|---|
| 7313 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
|---|
| 7314 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
|---|
| 7315 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
|---|
| 7316 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
|---|
| 7317 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
|---|
| 7318 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
|---|
| 7319 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
|---|
| 7320 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
|---|
| 7321 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
|---|
| 7322 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
|---|
| 7323 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
|---|
| 7324 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
|---|
| 7325 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
|---|
| 7326 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
|---|
| 7327 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
|---|
| 7328 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
|---|
| 7329 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
|---|
| 7330 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
|---|
| 7331 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
|---|
| 7332 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
|---|
| 7333 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
|---|
| 7334 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
|---|
| 7335 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
|---|
| 7336 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
|---|
| 7337 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
|---|
| 7338 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
|---|
| 7339 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
|---|
| 7340 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
|---|
| 7341 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
|---|
| 7342 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
|---|
| 7343 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
|---|
| 7344 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
|---|
| 7345 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
|---|
| 7346 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
|---|
| 7347 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
|---|
| 7348 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
|---|
| 7349 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
|---|
| 7350 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
|---|
| 7351 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
|---|
| 7352 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
|---|
| 7353 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
|---|
| 7354 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
|---|
| 7355 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
|---|
| 7356 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
|---|
| 7357 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
|---|
| 7358 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
|---|
| 7359 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
|---|
| 7360 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
|---|
| 7361 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
|---|
| 7362 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
|---|
| 7363 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
|---|
| 7364 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
|---|
| 7365 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
|---|
| 7366 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
|---|
| 7367 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
|---|
| 7368 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
|---|
| 7369 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
|---|
| 7370 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
|---|
| 7371 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
|---|
| 7372 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
|---|
| 7373 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
|---|
| 7374 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
|---|
| 7375 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
|---|
| 7376 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
|---|
| 7377 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
|---|
| 7378 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
|---|
| 7379 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
|---|
| 7380 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
|---|
| 7381 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
|---|
| 7382 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
|---|
| 7383 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
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| 7384 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
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| 7385 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
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| 7386 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
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| 7387 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
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| 7388 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
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| 7389 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
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| 7390 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
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| 7391 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
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| 7392 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
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| 7393 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
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| 7394 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
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| 7395 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
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| 7396 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
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| 7397 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
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| 7398 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
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| 7399 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
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| 7400 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
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| 7401 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
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| 7402 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
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| 7403 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
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| 7404 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
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| 7405 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
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| 7406 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
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| 7407 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
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| 7408 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
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| 7409 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
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| 7410 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
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| 7411 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
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| 7412 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
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| 7413 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
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| 7414 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
|---|
| 7415 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
|---|
| 7416 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
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| 7417 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
|---|
| 7418 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
|---|
| 7419 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
|---|
| 7420 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
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| 7421 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
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| 7422 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
|---|
| 7423 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
|---|
| 7424 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
|---|
| 7425 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
|---|
| 7426 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
|---|
| 7427 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
|---|
| 7428 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
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| 7429 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
|---|
| 7430 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
|---|
| 7431 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
|---|
| 7432 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
|---|
| 7433 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
|---|
| 7434 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
|---|
| 7435 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
|---|
| 7436 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
|---|
| 7437 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
|---|
| 7438 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
|---|
| 7439 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
|---|
| 7440 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
|---|
| 7441 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
|---|
| 7442 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
|---|
| 7443 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
|---|
| 7444 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
|---|
| 7445 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
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| 7446 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
|---|
| 7447 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
|---|
| 7448 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
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| 7449 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
|---|
| 7450 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
|---|
| 7451 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
|---|
| 7452 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
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| 7453 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
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| 7454 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
|---|
| 7455 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
|---|
| 7456 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
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| 7457 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
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| 7458 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
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| 7459 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
|---|
| 7460 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
|---|
| 7461 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
|---|
| 7462 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
|---|
| 7463 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
|---|
| 7464 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
|---|
| 7465 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
|---|
| 7466 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
|---|
| 7467 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
|---|
| 7468 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
|---|
| 7469 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
|---|
| 7470 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
|---|
| 7471 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
|---|
| 7472 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
|---|
| 7473 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
|---|
| 7474 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
|---|
| 7475 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
|---|
| 7476 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
|---|
| 7477 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
|---|
| 7478 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
|---|
| 7479 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
|---|
| 7480 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
|---|
| 7481 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
|---|
| 7482 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
|---|
| 7483 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
|---|
| 7484 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
|---|
| 7485 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
|---|
| 7486 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
|---|
| 7487 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
|---|
| 7488 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
|---|
| 7489 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
|---|
| 7490 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
|---|
| 7491 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
|---|
| 7492 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
|---|
| 7493 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
|---|
| 7494 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
|---|
| 7495 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
|---|
| 7496 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
|---|
| 7497 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
|---|
| 7498 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
|---|
| 7499 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
|---|
| 7500 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
|---|
| 7501 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
|---|
| 7502 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
|---|
| 7503 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
|---|
| 7504 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
|---|
| 7505 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
|---|
| 7506 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
|---|
| 7507 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
|---|
| 7508 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
|---|
| 7509 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
|---|
| 7510 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
|---|
| 7511 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
|---|
| 7512 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
|---|
| 7513 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
|---|
| 7514 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
|---|
| 7515 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
|---|
| 7516 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
|---|
| 7517 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
|---|
| 7518 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
|---|
| 7519 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
|---|
| 7520 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
|---|
| 7521 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
|---|
| 7522 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
|---|
| 7523 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
|---|
| 7524 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
|---|
| 7525 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
|---|
| 7526 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
|---|
| 7527 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
|---|
| 7528 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
|---|
| 7529 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
|---|
| 7530 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
|---|
| 7531 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
|---|
| 7532 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
|---|
| 7533 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
|---|
| 7534 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
|---|
| 7535 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
|---|
| 7536 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
|---|
| 7537 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
|---|
| 7538 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
|---|
| 7539 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
|---|
| 7540 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
|---|
| 7541 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
|---|
| 7542 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
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| 7543 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
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| 7544 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
|---|
| 7545 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
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| 7546 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
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| 7547 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
|---|
| 7548 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
|---|
| 7549 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
|---|
| 7550 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
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| 7551 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
|---|
| 7552 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
|---|
| 7553 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
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| 7554 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
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| 7555 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
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| 7556 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
|---|
| 7557 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
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| 7558 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
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| 7559 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
|---|
| 7560 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
|---|
| 7561 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
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| 7562 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
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| 7563 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
|---|
| 7564 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
|---|
| 7565 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
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| 7566 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
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| 7567 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
|---|
| 7568 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
|---|
| 7569 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
|---|
| 7570 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
|---|
| 7571 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
|---|
| 7572 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
|---|
| 7573 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
|---|
| 7574 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
|---|
| 7575 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
|---|
| 7576 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
|---|
| 7577 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
|---|
| 7578 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
|---|
| 7579 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
|---|
| 7580 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
|---|
| 7581 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
|---|
| 7582 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
|---|
| 7583 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
|---|
| 7584 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
|---|
| 7585 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
|---|
| 7586 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
|---|
| 7587 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
|---|
| 7588 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
|---|
| 7589 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
|---|
| 7590 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
|---|
| 7591 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
|---|
| 7592 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
|---|
| 7593 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
|---|
| 7594 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
|---|
| 7595 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
|---|
| 7596 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
|---|
| 7597 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
|---|
| 7598 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
|---|
| 7599 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
|---|
| 7600 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
|---|
| 7601 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
|---|
| 7602 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
|---|
| 7603 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
|---|
| 7604 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
|---|
| 7605 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
|---|
| 7606 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
|---|
| 7607 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
|---|
| 7608 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
|---|
| 7609 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
|---|
| 7610 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
|---|
| 7611 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
|---|
| 7612 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
|---|
| 7613 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
|---|
| 7614 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
|---|
| 7615 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
|---|
| 7616 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
|---|
| 7617 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
|---|
| 7618 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
|---|
| 7619 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
|---|
| 7620 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
|---|
| 7621 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
|---|
| 7622 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
|---|
| 7623 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
|---|
| 7624 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
|---|
| 7625 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
|---|
| 7626 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
|---|
| 7627 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
|---|
| 7628 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
|---|
| 7629 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
|---|
| 7630 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
|---|
| 7631 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
|---|
| 7632 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
|---|
| 7633 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
|---|
| 7634 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
|---|
| 7635 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
|---|
| 7636 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
|---|
| 7637 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
|---|
| 7638 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
|---|
| 7639 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
|---|
| 7640 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
|---|
| 7641 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
|---|
| 7642 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
|---|
| 7643 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
|---|
| 7644 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
|---|
| 7645 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
|---|
| 7646 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
|---|
| 7647 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
|---|
| 7648 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
|---|
| 7649 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
|---|
| 7650 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
|---|
| 7651 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
|---|
| 7652 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
|---|
| 7653 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
|---|
| 7654 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
|---|
| 7655 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
|---|
| 7656 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
|---|
| 7657 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
|---|
| 7658 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
|---|
| 7659 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
|---|
| 7660 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
|---|
| 7661 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
|---|
| 7662 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
|---|
| 7663 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
|---|
| 7664 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
|---|
| 7665 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
|---|
| 7666 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
|---|
| 7667 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
|---|
| 7668 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
|---|
| 7669 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
|---|
| 7670 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
|---|
| 7671 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
|---|
| 7672 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
|---|
| 7673 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
|---|
| 7674 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
|---|
| 7675 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
|---|
| 7676 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
|---|
| 7677 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
|---|
| 7678 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
|---|
| 7679 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
|---|
| 7680 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
|---|
| 7681 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
|---|
| 7682 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
|---|
| 7683 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
|---|
| 7684 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
|---|
| 7685 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
|---|
| 7686 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
|---|
| 7687 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
|---|
| 7688 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
|---|
| 7689 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100 |
|---|
| 7690 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8 |
|---|
| 7691 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100 |
|---|
| 7692 | #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8 |
|---|
| 7693 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
|---|
| 7694 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
|---|
| 7695 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
|---|
| 7696 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 7697 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
|---|
| 7698 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
|---|
| 7699 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
|---|
| 7700 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
|---|
| 7701 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
|---|
| 7702 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
|---|
| 7703 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
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| 7704 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
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| 7705 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
|---|
| 7706 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 7707 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
|---|
| 7708 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
|---|
| 7709 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
|---|
| 7710 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
|---|
| 7711 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
|---|
| 7712 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
|---|
| 7713 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
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| 7714 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
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| 7715 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
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| 7716 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
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| 7717 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
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| 7718 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
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| 7719 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
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| 7720 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
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| 7721 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
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| 7722 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
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| 7723 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
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| 7724 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
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| 7725 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
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| 7726 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
|---|
| 7727 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
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| 7728 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
|---|
| 7729 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
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| 7730 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
|---|
| 7731 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
|---|
| 7732 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
|---|
| 7733 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
|---|
| 7734 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
|---|
| 7735 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
|---|
| 7736 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
|---|
| 7737 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
|---|
| 7738 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
|---|
| 7739 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
|---|
| 7740 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
|---|
| 7741 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
|---|
| 7742 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
|---|
| 7743 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
|---|
| 7744 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
|---|
| 7745 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
|---|
| 7746 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
|---|
| 7747 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
|---|
| 7748 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
|---|
| 7749 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
|---|
| 7750 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 7751 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
|---|
| 7752 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
|---|
| 7753 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
|---|
| 7754 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
|---|
| 7755 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
|---|
| 7756 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
|---|
| 7757 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
|---|
| 7758 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
|---|
| 7759 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
|---|
| 7760 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 7761 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
|---|
| 7762 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
|---|
| 7763 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
|---|
| 7764 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
|---|
| 7765 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
|---|
| 7766 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
|---|
| 7767 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
|---|
| 7768 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
|---|
| 7769 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
|---|
| 7770 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
|---|
| 7771 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
|---|
| 7772 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
|---|
| 7773 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
|---|
| 7774 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
|---|
| 7775 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
|---|
| 7776 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
|---|
| 7777 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
|---|
| 7778 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
|---|
| 7779 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
|---|
| 7780 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
|---|
| 7781 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
|---|
| 7782 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
|---|
| 7783 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
|---|
| 7784 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
|---|
| 7785 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
|---|
| 7786 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
|---|
| 7787 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
|---|
| 7788 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
|---|
| 7789 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
|---|
| 7790 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
|---|
| 7791 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
|---|
| 7792 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
|---|
| 7793 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
|---|
| 7794 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
|---|
| 7795 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
|---|
| 7796 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
|---|
| 7797 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
|---|
| 7798 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
|---|
| 7799 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
|---|
| 7800 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
|---|
| 7801 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
|---|
| 7802 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
|---|
| 7803 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
|---|
| 7804 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 7805 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
|---|
| 7806 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
|---|
| 7807 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
|---|
| 7808 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
|---|
| 7809 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
|---|
| 7810 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
|---|
| 7811 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
|---|
| 7812 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
|---|
| 7813 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
|---|
| 7814 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 7815 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
|---|
| 7816 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
|---|
| 7817 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
|---|
| 7818 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
|---|
| 7819 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
|---|
| 7820 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
|---|
| 7821 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
|---|
| 7822 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
|---|
| 7823 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
|---|
| 7824 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
|---|
| 7825 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
|---|
| 7826 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
|---|
| 7827 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
|---|
| 7828 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
|---|
| 7829 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
|---|
| 7830 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
|---|
| 7831 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
|---|
| 7832 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
|---|
| 7833 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
|---|
| 7834 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
|---|
| 7835 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
|---|
| 7836 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
|---|
| 7837 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
|---|
| 7838 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
|---|
| 7839 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
|---|
| 7840 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
|---|
| 7841 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
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| 7842 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
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| 7843 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
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| 7844 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
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| 7845 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
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| 7846 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
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| 7847 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
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| 7848 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
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| 7849 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
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| 7850 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
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| 7851 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
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| 7852 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
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| 7853 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
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| 7854 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
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| 7855 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
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| 7856 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
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| 7857 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
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| 7858 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
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| 7859 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
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| 7860 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
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| 7861 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
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| 7862 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
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| 7863 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
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| 7864 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
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| 7865 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
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| 7866 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
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| 7867 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
|---|
| 7868 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 7869 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
|---|
| 7870 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
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| 7871 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
|---|
| 7872 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
|---|
| 7873 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
|---|
| 7874 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
|---|
| 7875 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
|---|
| 7876 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
|---|
| 7877 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
|---|
| 7878 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
|---|
| 7879 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
|---|
| 7880 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
|---|
| 7881 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
|---|
| 7882 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
|---|
| 7883 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
|---|
| 7884 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
|---|
| 7885 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
|---|
| 7886 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
|---|
| 7887 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
|---|
| 7888 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
|---|
| 7889 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
|---|
| 7890 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
|---|
| 7891 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
|---|
| 7892 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
|---|
| 7893 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
|---|
| 7894 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 7895 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
|---|
| 7896 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
|---|
| 7897 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
|---|
| 7898 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
|---|
| 7899 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
|---|
| 7900 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
|---|
| 7901 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
|---|
| 7902 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
|---|
| 7903 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
|---|
| 7904 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 7905 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
|---|
| 7906 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
|---|
| 7907 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100 |
|---|
| 7908 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8 |
|---|
| 7909 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
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| 7910 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
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| 7911 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
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| 7912 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
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| 7913 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
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| 7914 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
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| 7915 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
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| 7916 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
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| 7917 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
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| 7918 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
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| 7919 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
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| 7920 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
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| 7921 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 7922 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 7923 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 7924 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 7925 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 7926 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 7927 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
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| 7928 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
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| 7929 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
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| 7930 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
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| 7931 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
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| 7932 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
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| 7933 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
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| 7934 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
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| 7935 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
|---|
| 7936 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
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| 7937 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
|---|
| 7938 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
|---|
| 7939 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
|---|
| 7940 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
|---|
| 7941 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
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| 7942 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
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| 7943 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
|---|
| 7944 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
|---|
| 7945 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
|---|
| 7946 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
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| 7947 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
|---|
| 7948 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
|---|
| 7949 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
|---|
| 7950 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
|---|
| 7951 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
|---|
| 7952 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
|---|
| 7953 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
|---|
| 7954 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
|---|
| 7955 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
|---|
| 7956 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
|---|
| 7957 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
|---|
| 7958 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
|---|
| 7959 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
|---|
| 7960 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
|---|
| 7961 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
|---|
| 7962 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
|---|
| 7963 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
|---|
| 7964 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
|---|
| 7965 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
|---|
| 7966 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
|---|
| 7967 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
|---|
| 7968 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
|---|
| 7969 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
|---|
| 7970 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
|---|
| 7971 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
|---|
| 7972 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
|---|
| 7973 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
|---|
| 7974 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
|---|
| 7975 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 7976 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 7977 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 7978 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 7979 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 7980 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 7981 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
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| 7982 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
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| 7983 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
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| 7984 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
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| 7985 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
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| 7986 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
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| 7987 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
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| 7988 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
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| 7989 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
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| 7990 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
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| 7991 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
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| 7992 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
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| 7993 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
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| 7994 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
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| 7995 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
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| 7996 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
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| 7997 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
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| 7998 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
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| 7999 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
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| 8000 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
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| 8001 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
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| 8002 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
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| 8003 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
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| 8004 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
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| 8005 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
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| 8006 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
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| 8007 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
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| 8008 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
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| 8009 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
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| 8010 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
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| 8011 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
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| 8012 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
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| 8013 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
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| 8014 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
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| 8015 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
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| 8016 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
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| 8017 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
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| 8018 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
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| 8019 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
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| 8020 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
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| 8021 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
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| 8022 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
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| 8023 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
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| 8024 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
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| 8025 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
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| 8026 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
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| 8027 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
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| 8028 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
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| 8029 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 8030 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 8031 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 8032 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 8033 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 8034 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 8035 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
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| 8036 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
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| 8037 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
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| 8038 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
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| 8039 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
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| 8040 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
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| 8041 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
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| 8042 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
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| 8043 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
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| 8044 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
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| 8045 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
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| 8046 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
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| 8047 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
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| 8048 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
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| 8049 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
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| 8050 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
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| 8051 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
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| 8052 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
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| 8053 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
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| 8054 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
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| 8055 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
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| 8056 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
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| 8057 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
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| 8058 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
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| 8059 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
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| 8060 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
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| 8061 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
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| 8062 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
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| 8063 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
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| 8064 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
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| 8065 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
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| 8066 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
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| 8067 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
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| 8068 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
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| 8069 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
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| 8070 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
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| 8071 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
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| 8072 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
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| 8073 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
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| 8074 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
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| 8075 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
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| 8076 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
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| 8077 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
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| 8078 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
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| 8079 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
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| 8080 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
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| 8081 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
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| 8082 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
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| 8083 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 8084 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 8085 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 8086 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 8087 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 8088 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 8089 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
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| 8090 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
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| 8091 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
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| 8092 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
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| 8093 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
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| 8094 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
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| 8095 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
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| 8096 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
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| 8097 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
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| 8098 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
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| 8099 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
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| 8100 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
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| 8101 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
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| 8102 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
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| 8103 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
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| 8104 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
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| 8105 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
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| 8106 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
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| 8107 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
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| 8108 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
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| 8109 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
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| 8110 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
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| 8111 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
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| 8112 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
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| 8113 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
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| 8114 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
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| 8115 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
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| 8116 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
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| 8117 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
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| 8118 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
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| 8119 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
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| 8120 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
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| 8121 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
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| 8122 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
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| 8123 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100 |
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| 8124 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
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| 8125 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
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| 8126 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
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| 8127 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
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| 8128 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
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| 8129 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
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| 8130 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
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| 8131 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
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| 8132 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
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| 8133 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
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| 8134 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
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| 8135 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
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| 8136 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
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| 8137 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
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| 8138 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
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| 8139 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
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| 8140 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
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| 8141 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
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| 8142 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
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| 8143 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
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| 8144 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
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| 8145 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
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| 8146 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
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| 8147 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
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| 8148 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
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| 8149 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
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| 8150 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
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| 8151 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
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| 8152 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
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| 8153 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
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| 8154 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
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| 8155 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
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| 8156 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
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| 8157 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
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| 8158 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
|---|
| 8159 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
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| 8160 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
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| 8161 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
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| 8162 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
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| 8163 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
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| 8164 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
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| 8165 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
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| 8166 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
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| 8167 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
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| 8168 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
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| 8169 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
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| 8170 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
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| 8171 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
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| 8172 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
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| 8173 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
|---|
| 8174 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
|---|
| 8175 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
|---|
| 8176 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
|---|
| 8177 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
|---|
| 8178 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
|---|
| 8179 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
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| 8180 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
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| 8181 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
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| 8182 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
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| 8183 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
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| 8184 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
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| 8185 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
|---|
| 8186 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
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| 8187 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
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| 8188 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
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| 8189 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
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| 8190 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
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| 8191 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
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| 8192 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
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| 8193 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
|---|
| 8194 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
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| 8195 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
|---|
| 8196 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
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| 8197 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
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| 8198 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
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| 8199 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
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| 8200 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
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| 8201 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
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| 8202 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
|---|
| 8203 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
|---|
| 8204 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
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| 8205 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
|---|
| 8206 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
|---|
| 8207 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
|---|
| 8208 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
|---|
| 8209 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
|---|
| 8210 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
|---|
| 8211 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
|---|
| 8212 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
|---|
| 8213 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
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| 8214 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
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| 8215 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
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| 8216 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
|---|
| 8217 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
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| 8218 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
|---|
| 8219 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
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| 8220 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
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| 8221 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
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| 8222 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
|---|
| 8223 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
|---|
| 8224 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
|---|
| 8225 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
|---|
| 8226 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
|---|
| 8227 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
|---|
| 8228 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
|---|
| 8229 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
|---|
| 8230 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
|---|
| 8231 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
|---|
| 8232 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
|---|
| 8233 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
|---|
| 8234 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
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| 8235 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
|---|
| 8236 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
|---|
| 8237 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
|---|
| 8238 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
|---|
| 8239 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
|---|
| 8240 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
|---|
| 8241 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
|---|
| 8242 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
|---|
| 8243 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
|---|
| 8244 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
|---|
| 8245 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
|---|
| 8246 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
|---|
| 8247 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
|---|
| 8248 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
|---|
| 8249 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
|---|
| 8250 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
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| 8251 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
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| 8252 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
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| 8253 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
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| 8254 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
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| 8255 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
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| 8256 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
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| 8257 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
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| 8258 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
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| 8259 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
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| 8260 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
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| 8261 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
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| 8262 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
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| 8263 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
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| 8264 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
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| 8265 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
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| 8266 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
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| 8267 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
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| 8268 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
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| 8269 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
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| 8270 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
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| 8271 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
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| 8272 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
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| 8273 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
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| 8274 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
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| 8275 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
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| 8276 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
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| 8277 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
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| 8278 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
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| 8279 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
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| 8280 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
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| 8281 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
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| 8282 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
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| 8283 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
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| 8284 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
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| 8285 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
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| 8286 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
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| 8287 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
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| 8288 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
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| 8289 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
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| 8290 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
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| 8291 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
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| 8292 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
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| 8293 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
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| 8294 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
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| 8295 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
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| 8296 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
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| 8297 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
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| 8298 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
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| 8299 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
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| 8300 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
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| 8301 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
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| 8302 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
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| 8303 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
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| 8304 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
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| 8305 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
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| 8306 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
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| 8307 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
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| 8308 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
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| 8309 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
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| 8310 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
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| 8311 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
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| 8312 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
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| 8313 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
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| 8314 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
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| 8315 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
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| 8316 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
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| 8317 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
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| 8318 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
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| 8319 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
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| 8320 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
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| 8321 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
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| 8322 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
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| 8323 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
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| 8324 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
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| 8325 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
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| 8326 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
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| 8327 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
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| 8328 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
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| 8329 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
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| 8330 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
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| 8331 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
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| 8332 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
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| 8333 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
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| 8334 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
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| 8335 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
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| 8336 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
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| 8337 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
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| 8338 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
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| 8339 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x100 |
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| 8340 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x8 |
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| 8341 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1 |
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| 8342 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 |
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| 8343 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1 |
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| 8344 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 |
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| 8345 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2 |
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| 8346 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 |
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| 8347 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2 |
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| 8348 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 |
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| 8349 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4 |
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| 8350 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 |
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| 8351 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4 |
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| 8352 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 |
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| 8353 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8 |
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| 8354 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 |
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| 8355 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8 |
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| 8356 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 |
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| 8357 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10 |
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| 8358 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 |
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| 8359 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10 |
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| 8360 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 |
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| 8361 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20 |
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| 8362 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 |
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| 8363 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20 |
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| 8364 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 |
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| 8365 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40 |
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| 8366 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 |
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| 8367 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40 |
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| 8368 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 |
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| 8369 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80 |
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| 8370 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 |
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| 8371 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80 |
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| 8372 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 |
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| 8373 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100 |
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| 8374 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 |
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| 8375 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100 |
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| 8376 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 |
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| 8377 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200 |
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| 8378 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 |
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| 8379 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200 |
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| 8380 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 |
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| 8381 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400 |
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| 8382 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa |
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| 8383 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400 |
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| 8384 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa |
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| 8385 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800 |
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| 8386 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb |
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| 8387 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800 |
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| 8388 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb |
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| 8389 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000 |
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| 8390 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc |
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| 8391 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000 |
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| 8392 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc |
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| 8393 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000 |
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| 8394 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd |
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| 8395 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000 |
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| 8396 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd |
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| 8397 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000 |
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| 8398 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe |
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| 8399 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000 |
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| 8400 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe |
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| 8401 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000 |
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| 8402 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf |
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| 8403 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000 |
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| 8404 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf |
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| 8405 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000 |
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| 8406 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 |
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| 8407 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000 |
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| 8408 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 |
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| 8409 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000 |
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| 8410 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 |
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| 8411 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000 |
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| 8412 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 |
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| 8413 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000 |
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| 8414 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 |
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| 8415 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000 |
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| 8416 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 |
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| 8417 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000 |
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| 8418 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 |
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| 8419 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000 |
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| 8420 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 |
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| 8421 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000 |
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| 8422 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 |
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| 8423 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000 |
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| 8424 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 |
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| 8425 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000 |
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| 8426 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 |
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| 8427 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000 |
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| 8428 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 |
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| 8429 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000 |
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| 8430 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 |
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| 8431 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000 |
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| 8432 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 |
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| 8433 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000 |
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| 8434 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 |
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| 8435 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000 |
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| 8436 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 |
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| 8437 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000 |
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| 8438 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 |
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| 8439 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000 |
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| 8440 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 |
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| 8441 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000 |
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| 8442 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 |
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| 8443 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 |
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| 8444 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 |
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| 8445 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000 |
|---|
| 8446 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a |
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| 8447 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000 |
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| 8448 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a |
|---|
| 8449 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000 |
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| 8450 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b |
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| 8451 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000 |
|---|
| 8452 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b |
|---|
| 8453 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000 |
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| 8454 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c |
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| 8455 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000 |
|---|
| 8456 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c |
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| 8457 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1 |
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| 8458 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 |
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| 8459 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2 |
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| 8460 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 |
|---|
| 8461 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4 |
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| 8462 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 |
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| 8463 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8 |
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| 8464 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 |
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| 8465 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10 |
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| 8466 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 |
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| 8467 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20 |
|---|
| 8468 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 |
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| 8469 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40 |
|---|
| 8470 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 |
|---|
| 8471 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80 |
|---|
| 8472 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 |
|---|
| 8473 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100 |
|---|
| 8474 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 |
|---|
| 8475 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200 |
|---|
| 8476 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 |
|---|
| 8477 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400 |
|---|
| 8478 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa |
|---|
| 8479 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800 |
|---|
| 8480 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb |
|---|
| 8481 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000 |
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| 8482 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc |
|---|
| 8483 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000 |
|---|
| 8484 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd |
|---|
| 8485 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000 |
|---|
| 8486 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe |
|---|
| 8487 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000 |
|---|
| 8488 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf |
|---|
| 8489 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000 |
|---|
| 8490 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 |
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| 8491 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000 |
|---|
| 8492 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 |
|---|
| 8493 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000 |
|---|
| 8494 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 |
|---|
| 8495 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000 |
|---|
| 8496 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 |
|---|
| 8497 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000 |
|---|
| 8498 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 |
|---|
| 8499 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000 |
|---|
| 8500 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 |
|---|
| 8501 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000 |
|---|
| 8502 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 |
|---|
| 8503 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000 |
|---|
| 8504 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 |
|---|
| 8505 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000 |
|---|
| 8506 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 |
|---|
| 8507 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000 |
|---|
| 8508 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 |
|---|
| 8509 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000 |
|---|
| 8510 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a |
|---|
| 8511 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000 |
|---|
| 8512 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b |
|---|
| 8513 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000 |
|---|
| 8514 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c |
|---|
| 8515 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1 |
|---|
| 8516 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
|---|
| 8517 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2 |
|---|
| 8518 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
|---|
| 8519 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4 |
|---|
| 8520 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 |
|---|
| 8521 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8 |
|---|
| 8522 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 |
|---|
| 8523 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10 |
|---|
| 8524 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
|---|
| 8525 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20 |
|---|
| 8526 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
|---|
| 8527 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40 |
|---|
| 8528 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
|---|
| 8529 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80 |
|---|
| 8530 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 |
|---|
| 8531 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100 |
|---|
| 8532 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 |
|---|
| 8533 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200 |
|---|
| 8534 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
|---|
| 8535 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400 |
|---|
| 8536 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
|---|
| 8537 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800 |
|---|
| 8538 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
|---|
| 8539 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
|---|
| 8540 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
|---|
| 8541 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
|---|
| 8542 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
|---|
| 8543 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
|---|
| 8544 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
|---|
| 8545 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
|---|
| 8546 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
|---|
| 8547 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
|---|
| 8548 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
|---|
| 8549 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
|---|
| 8550 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
|---|
| 8551 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
|---|
| 8552 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
|---|
| 8553 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
|---|
| 8554 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
|---|
| 8555 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
|---|
| 8556 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
|---|
| 8557 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
|---|
| 8558 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
|---|
| 8559 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
|---|
| 8560 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
|---|
| 8561 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
|---|
| 8562 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
|---|
| 8563 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
|---|
| 8564 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
|---|
| 8565 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
|---|
| 8566 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
|---|
| 8567 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
|---|
| 8568 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
|---|
| 8569 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000 |
|---|
| 8570 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
|---|
| 8571 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000 |
|---|
| 8572 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
|---|
| 8573 | #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 |
|---|
| 8574 | #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
|---|
| 8575 | #define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 |
|---|
| 8576 | #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
|---|
| 8577 | #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 |
|---|
| 8578 | #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
|---|
| 8579 | #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 |
|---|
| 8580 | #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
|---|
| 8581 | #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 |
|---|
| 8582 | #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 |
|---|
| 8583 | #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 |
|---|
| 8584 | #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 |
|---|
| 8585 | #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 |
|---|
| 8586 | #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
|---|
| 8587 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff |
|---|
| 8588 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 |
|---|
| 8589 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 |
|---|
| 8590 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 |
|---|
| 8591 | #define DP_CONFIG__DP_UDI_LANES_MASK 0x3 |
|---|
| 8592 | #define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
|---|
| 8593 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 |
|---|
| 8594 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
|---|
| 8595 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 |
|---|
| 8596 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
|---|
| 8597 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 |
|---|
| 8598 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
|---|
| 8599 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 |
|---|
| 8600 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
|---|
| 8601 | #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 |
|---|
| 8602 | #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
|---|
| 8603 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 |
|---|
| 8604 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
|---|
| 8605 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 |
|---|
| 8606 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
|---|
| 8607 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 |
|---|
| 8608 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
|---|
| 8609 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 |
|---|
| 8610 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
|---|
| 8611 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 |
|---|
| 8612 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
|---|
| 8613 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 |
|---|
| 8614 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
|---|
| 8615 | #define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 |
|---|
| 8616 | #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 |
|---|
| 8617 | #define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 |
|---|
| 8618 | #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
|---|
| 8619 | #define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 |
|---|
| 8620 | #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
|---|
| 8621 | #define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 |
|---|
| 8622 | #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
|---|
| 8623 | #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 |
|---|
| 8624 | #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 |
|---|
| 8625 | #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 |
|---|
| 8626 | #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
|---|
| 8627 | #define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 |
|---|
| 8628 | #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
|---|
| 8629 | #define DP_VID_N__DP_VID_N_MASK 0xffffff |
|---|
| 8630 | #define DP_VID_N__DP_VID_N__SHIFT 0x0 |
|---|
| 8631 | #define DP_VID_M__DP_VID_M_MASK 0xffffff |
|---|
| 8632 | #define DP_VID_M__DP_VID_M__SHIFT 0x0 |
|---|
| 8633 | #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff |
|---|
| 8634 | #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
|---|
| 8635 | #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 |
|---|
| 8636 | #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
|---|
| 8637 | #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 |
|---|
| 8638 | #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
|---|
| 8639 | #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 |
|---|
| 8640 | #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
|---|
| 8641 | #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff |
|---|
| 8642 | #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
|---|
| 8643 | #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 |
|---|
| 8644 | #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 |
|---|
| 8645 | #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 |
|---|
| 8646 | #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
|---|
| 8647 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 |
|---|
| 8648 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
|---|
| 8649 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 |
|---|
| 8650 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
|---|
| 8651 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 |
|---|
| 8652 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
|---|
| 8653 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 |
|---|
| 8654 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
|---|
| 8655 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 |
|---|
| 8656 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
|---|
| 8657 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 |
|---|
| 8658 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
|---|
| 8659 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 |
|---|
| 8660 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
|---|
| 8661 | #define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 |
|---|
| 8662 | #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
|---|
| 8663 | #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 |
|---|
| 8664 | #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
|---|
| 8665 | #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 |
|---|
| 8666 | #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
|---|
| 8667 | #define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff |
|---|
| 8668 | #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
|---|
| 8669 | #define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 |
|---|
| 8670 | #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
|---|
| 8671 | #define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 |
|---|
| 8672 | #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
|---|
| 8673 | #define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff |
|---|
| 8674 | #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
|---|
| 8675 | #define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 |
|---|
| 8676 | #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
|---|
| 8677 | #define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 |
|---|
| 8678 | #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
|---|
| 8679 | #define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff |
|---|
| 8680 | #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
|---|
| 8681 | #define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 |
|---|
| 8682 | #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
|---|
| 8683 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 |
|---|
| 8684 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
|---|
| 8685 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 |
|---|
| 8686 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
|---|
| 8687 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 |
|---|
| 8688 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
|---|
| 8689 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 |
|---|
| 8690 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
|---|
| 8691 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 |
|---|
| 8692 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
|---|
| 8693 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 |
|---|
| 8694 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
|---|
| 8695 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 |
|---|
| 8696 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
|---|
| 8697 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 |
|---|
| 8698 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
|---|
| 8699 | #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 |
|---|
| 8700 | #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
|---|
| 8701 | #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 |
|---|
| 8702 | #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
|---|
| 8703 | #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 |
|---|
| 8704 | #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
|---|
| 8705 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 |
|---|
| 8706 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
|---|
| 8707 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 |
|---|
| 8708 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
|---|
| 8709 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 |
|---|
| 8710 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
|---|
| 8711 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff |
|---|
| 8712 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
|---|
| 8713 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 |
|---|
| 8714 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
|---|
| 8715 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 |
|---|
| 8716 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
|---|
| 8717 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 |
|---|
| 8718 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
|---|
| 8719 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f |
|---|
| 8720 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
|---|
| 8721 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 |
|---|
| 8722 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
|---|
| 8723 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 |
|---|
| 8724 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
|---|
| 8725 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 |
|---|
| 8726 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
|---|
| 8727 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 |
|---|
| 8728 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
|---|
| 8729 | #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 |
|---|
| 8730 | #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
|---|
| 8731 | #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 |
|---|
| 8732 | #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
|---|
| 8733 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 |
|---|
| 8734 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
|---|
| 8735 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 |
|---|
| 8736 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
|---|
| 8737 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 |
|---|
| 8738 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
|---|
| 8739 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 |
|---|
| 8740 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
|---|
| 8741 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 |
|---|
| 8742 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
|---|
| 8743 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 |
|---|
| 8744 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
|---|
| 8745 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 |
|---|
| 8746 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
|---|
| 8747 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 |
|---|
| 8748 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 8749 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0 |
|---|
| 8750 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 |
|---|
| 8751 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff |
|---|
| 8752 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 |
|---|
| 8753 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000 |
|---|
| 8754 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 |
|---|
| 8755 | #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 |
|---|
| 8756 | #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
|---|
| 8757 | #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 |
|---|
| 8758 | #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
|---|
| 8759 | #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 |
|---|
| 8760 | #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
|---|
| 8761 | #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 |
|---|
| 8762 | #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
|---|
| 8763 | #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 |
|---|
| 8764 | #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
|---|
| 8765 | #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 |
|---|
| 8766 | #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
|---|
| 8767 | #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 |
|---|
| 8768 | #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
|---|
| 8769 | #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 |
|---|
| 8770 | #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
|---|
| 8771 | #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 |
|---|
| 8772 | #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
|---|
| 8773 | #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 |
|---|
| 8774 | #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 |
|---|
| 8775 | #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 |
|---|
| 8776 | #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
|---|
| 8777 | #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 |
|---|
| 8778 | #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
|---|
| 8779 | #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff |
|---|
| 8780 | #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
|---|
| 8781 | #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 |
|---|
| 8782 | #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
|---|
| 8783 | #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff |
|---|
| 8784 | #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
|---|
| 8785 | #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 |
|---|
| 8786 | #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
|---|
| 8787 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff |
|---|
| 8788 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
|---|
| 8789 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 |
|---|
| 8790 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
|---|
| 8791 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 |
|---|
| 8792 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
|---|
| 8793 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 |
|---|
| 8794 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
|---|
| 8795 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 |
|---|
| 8796 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
|---|
| 8797 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 |
|---|
| 8798 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
|---|
| 8799 | #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff |
|---|
| 8800 | #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
|---|
| 8801 | #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff |
|---|
| 8802 | #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
|---|
| 8803 | #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff |
|---|
| 8804 | #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
|---|
| 8805 | #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff |
|---|
| 8806 | #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
|---|
| 8807 | #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 |
|---|
| 8808 | #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
|---|
| 8809 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe |
|---|
| 8810 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
|---|
| 8811 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 |
|---|
| 8812 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
|---|
| 8813 | #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 |
|---|
| 8814 | #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
|---|
| 8815 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 |
|---|
| 8816 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
|---|
| 8817 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff |
|---|
| 8818 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
|---|
| 8819 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 |
|---|
| 8820 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
|---|
| 8821 | #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 |
|---|
| 8822 | #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 8823 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 |
|---|
| 8824 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
|---|
| 8825 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 |
|---|
| 8826 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
|---|
| 8827 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 |
|---|
| 8828 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
|---|
| 8829 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 |
|---|
| 8830 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
|---|
| 8831 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 |
|---|
| 8832 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
|---|
| 8833 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 |
|---|
| 8834 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
|---|
| 8835 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 |
|---|
| 8836 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
|---|
| 8837 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 |
|---|
| 8838 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
|---|
| 8839 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 |
|---|
| 8840 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
|---|
| 8841 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 |
|---|
| 8842 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
|---|
| 8843 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 |
|---|
| 8844 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
|---|
| 8845 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 |
|---|
| 8846 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
|---|
| 8847 | #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 |
|---|
| 8848 | #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
|---|
| 8849 | #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 |
|---|
| 8850 | #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
|---|
| 8851 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff |
|---|
| 8852 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
|---|
| 8853 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 |
|---|
| 8854 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
|---|
| 8855 | #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 |
|---|
| 8856 | #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
|---|
| 8857 | #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 |
|---|
| 8858 | #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
|---|
| 8859 | #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 |
|---|
| 8860 | #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
|---|
| 8861 | #define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000 |
|---|
| 8862 | #define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10 |
|---|
| 8863 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 8864 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 8865 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 8866 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 8867 | #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 8868 | #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 8869 | #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 8870 | #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 8871 | #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 8872 | #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 8873 | #define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 8874 | #define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 8875 | #define AUX_CONTROL__AUX_EN_MASK 0x1 |
|---|
| 8876 | #define AUX_CONTROL__AUX_EN__SHIFT 0x0 |
|---|
| 8877 | #define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 |
|---|
| 8878 | #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
|---|
| 8879 | #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 |
|---|
| 8880 | #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
|---|
| 8881 | #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 |
|---|
| 8882 | #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
|---|
| 8883 | #define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 |
|---|
| 8884 | #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
|---|
| 8885 | #define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 |
|---|
| 8886 | #define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
|---|
| 8887 | #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 |
|---|
| 8888 | #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
|---|
| 8889 | #define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 |
|---|
| 8890 | #define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
|---|
| 8891 | #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 |
|---|
| 8892 | #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
|---|
| 8893 | #define AUX_CONTROL__SPARE_0_MASK 0x40000000 |
|---|
| 8894 | #define AUX_CONTROL__SPARE_0__SHIFT 0x1e |
|---|
| 8895 | #define AUX_CONTROL__SPARE_1_MASK 0x80000000 |
|---|
| 8896 | #define AUX_CONTROL__SPARE_1__SHIFT 0x1f |
|---|
| 8897 | #define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 |
|---|
| 8898 | #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
|---|
| 8899 | #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 |
|---|
| 8900 | #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
|---|
| 8901 | #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 |
|---|
| 8902 | #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
|---|
| 8903 | #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 |
|---|
| 8904 | #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
|---|
| 8905 | #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 |
|---|
| 8906 | #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
|---|
| 8907 | #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc |
|---|
| 8908 | #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
|---|
| 8909 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 |
|---|
| 8910 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
|---|
| 8911 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 |
|---|
| 8912 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
|---|
| 8913 | #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 |
|---|
| 8914 | #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
|---|
| 8915 | #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 |
|---|
| 8916 | #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
|---|
| 8917 | #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 |
|---|
| 8918 | #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
|---|
| 8919 | #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 |
|---|
| 8920 | #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
|---|
| 8921 | #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 |
|---|
| 8922 | #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
|---|
| 8923 | #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 |
|---|
| 8924 | #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
|---|
| 8925 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 |
|---|
| 8926 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
|---|
| 8927 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 |
|---|
| 8928 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
|---|
| 8929 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 |
|---|
| 8930 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
|---|
| 8931 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 |
|---|
| 8932 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
|---|
| 8933 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 |
|---|
| 8934 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
|---|
| 8935 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 |
|---|
| 8936 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
|---|
| 8937 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 |
|---|
| 8938 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
|---|
| 8939 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 |
|---|
| 8940 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
|---|
| 8941 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 |
|---|
| 8942 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
|---|
| 8943 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 |
|---|
| 8944 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
|---|
| 8945 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 |
|---|
| 8946 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
|---|
| 8947 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 |
|---|
| 8948 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
|---|
| 8949 | #define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 |
|---|
| 8950 | #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
|---|
| 8951 | #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 |
|---|
| 8952 | #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
|---|
| 8953 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 |
|---|
| 8954 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
|---|
| 8955 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 |
|---|
| 8956 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
|---|
| 8957 | #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 |
|---|
| 8958 | #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
|---|
| 8959 | #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 |
|---|
| 8960 | #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
|---|
| 8961 | #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 |
|---|
| 8962 | #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
|---|
| 8963 | #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 |
|---|
| 8964 | #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
|---|
| 8965 | #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 |
|---|
| 8966 | #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
|---|
| 8967 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 |
|---|
| 8968 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
|---|
| 8969 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 |
|---|
| 8970 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
|---|
| 8971 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 |
|---|
| 8972 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
|---|
| 8973 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 |
|---|
| 8974 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
|---|
| 8975 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 |
|---|
| 8976 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
|---|
| 8977 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 |
|---|
| 8978 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
|---|
| 8979 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 |
|---|
| 8980 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
|---|
| 8981 | #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 |
|---|
| 8982 | #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
|---|
| 8983 | #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 |
|---|
| 8984 | #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
|---|
| 8985 | #define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 |
|---|
| 8986 | #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
|---|
| 8987 | #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 |
|---|
| 8988 | #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
|---|
| 8989 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 |
|---|
| 8990 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
|---|
| 8991 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 |
|---|
| 8992 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
|---|
| 8993 | #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 |
|---|
| 8994 | #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
|---|
| 8995 | #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 |
|---|
| 8996 | #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
|---|
| 8997 | #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 |
|---|
| 8998 | #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
|---|
| 8999 | #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 |
|---|
| 9000 | #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
|---|
| 9001 | #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 |
|---|
| 9002 | #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
|---|
| 9003 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 |
|---|
| 9004 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
|---|
| 9005 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 |
|---|
| 9006 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
|---|
| 9007 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 |
|---|
| 9008 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
|---|
| 9009 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 |
|---|
| 9010 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
|---|
| 9011 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 |
|---|
| 9012 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
|---|
| 9013 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 |
|---|
| 9014 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
|---|
| 9015 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 |
|---|
| 9016 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
|---|
| 9017 | #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 |
|---|
| 9018 | #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
|---|
| 9019 | #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 |
|---|
| 9020 | #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
|---|
| 9021 | #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 |
|---|
| 9022 | #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
|---|
| 9023 | #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 |
|---|
| 9024 | #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
|---|
| 9025 | #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 |
|---|
| 9026 | #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
|---|
| 9027 | #define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 |
|---|
| 9028 | #define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
|---|
| 9029 | #define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 |
|---|
| 9030 | #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
|---|
| 9031 | #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 |
|---|
| 9032 | #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
|---|
| 9033 | #define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 |
|---|
| 9034 | #define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
|---|
| 9035 | #define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 |
|---|
| 9036 | #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
|---|
| 9037 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 |
|---|
| 9038 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
|---|
| 9039 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 |
|---|
| 9040 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
|---|
| 9041 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 |
|---|
| 9042 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
|---|
| 9043 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 |
|---|
| 9044 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
|---|
| 9045 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 |
|---|
| 9046 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
|---|
| 9047 | #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 |
|---|
| 9048 | #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
|---|
| 9049 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 |
|---|
| 9050 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
|---|
| 9051 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 |
|---|
| 9052 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
|---|
| 9053 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 |
|---|
| 9054 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
|---|
| 9055 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 |
|---|
| 9056 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
|---|
| 9057 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 |
|---|
| 9058 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
|---|
| 9059 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 |
|---|
| 9060 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
|---|
| 9061 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 |
|---|
| 9062 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
|---|
| 9063 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 |
|---|
| 9064 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
|---|
| 9065 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 |
|---|
| 9066 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
|---|
| 9067 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 |
|---|
| 9068 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
|---|
| 9069 | #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff |
|---|
| 9070 | #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
|---|
| 9071 | #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 |
|---|
| 9072 | #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
|---|
| 9073 | #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 |
|---|
| 9074 | #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
|---|
| 9075 | #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 |
|---|
| 9076 | #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
|---|
| 9077 | #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 |
|---|
| 9078 | #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
|---|
| 9079 | #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 |
|---|
| 9080 | #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
|---|
| 9081 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 |
|---|
| 9082 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
|---|
| 9083 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 |
|---|
| 9084 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
|---|
| 9085 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 |
|---|
| 9086 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 |
|---|
| 9087 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 |
|---|
| 9088 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 |
|---|
| 9089 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 |
|---|
| 9090 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 |
|---|
| 9091 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 |
|---|
| 9092 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc |
|---|
| 9093 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 |
|---|
| 9094 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 |
|---|
| 9095 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 |
|---|
| 9096 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 |
|---|
| 9097 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 |
|---|
| 9098 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 |
|---|
| 9099 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 |
|---|
| 9100 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 |
|---|
| 9101 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 |
|---|
| 9102 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c |
|---|
| 9103 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f |
|---|
| 9104 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
|---|
| 9105 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 |
|---|
| 9106 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
|---|
| 9107 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 |
|---|
| 9108 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
|---|
| 9109 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 |
|---|
| 9110 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
|---|
| 9111 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 |
|---|
| 9112 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
|---|
| 9113 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 |
|---|
| 9114 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
|---|
| 9115 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 |
|---|
| 9116 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
|---|
| 9117 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 |
|---|
| 9118 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
|---|
| 9119 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 |
|---|
| 9120 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
|---|
| 9121 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 |
|---|
| 9122 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
|---|
| 9123 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 |
|---|
| 9124 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
|---|
| 9125 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 |
|---|
| 9126 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
|---|
| 9127 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 |
|---|
| 9128 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
|---|
| 9129 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 |
|---|
| 9130 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
|---|
| 9131 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 |
|---|
| 9132 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
|---|
| 9133 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 |
|---|
| 9134 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
|---|
| 9135 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 |
|---|
| 9136 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
|---|
| 9137 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 |
|---|
| 9138 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
|---|
| 9139 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 |
|---|
| 9140 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
|---|
| 9141 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 |
|---|
| 9142 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
|---|
| 9143 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 |
|---|
| 9144 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
|---|
| 9145 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 |
|---|
| 9146 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
|---|
| 9147 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 |
|---|
| 9148 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
|---|
| 9149 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 |
|---|
| 9150 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
|---|
| 9151 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 |
|---|
| 9152 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
|---|
| 9153 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 |
|---|
| 9154 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
|---|
| 9155 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 |
|---|
| 9156 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
|---|
| 9157 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 |
|---|
| 9158 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
|---|
| 9159 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 |
|---|
| 9160 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
|---|
| 9161 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 |
|---|
| 9162 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
|---|
| 9163 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 |
|---|
| 9164 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
|---|
| 9165 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 |
|---|
| 9166 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
|---|
| 9167 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 |
|---|
| 9168 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
|---|
| 9169 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 |
|---|
| 9170 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
|---|
| 9171 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 |
|---|
| 9172 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
|---|
| 9173 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 |
|---|
| 9174 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 |
|---|
| 9175 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 |
|---|
| 9176 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 |
|---|
| 9177 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 |
|---|
| 9178 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 |
|---|
| 9179 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 |
|---|
| 9180 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
|---|
| 9181 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 |
|---|
| 9182 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 9183 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 |
|---|
| 9184 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 |
|---|
| 9185 | #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9186 | #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9187 | #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9188 | #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9189 | #define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9190 | #define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9191 | #define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff |
|---|
| 9192 | #define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 |
|---|
| 9193 | #define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff |
|---|
| 9194 | #define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 |
|---|
| 9195 | #define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff |
|---|
| 9196 | #define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 |
|---|
| 9197 | #define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff |
|---|
| 9198 | #define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 |
|---|
| 9199 | #define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff |
|---|
| 9200 | #define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 |
|---|
| 9201 | #define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff |
|---|
| 9202 | #define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 |
|---|
| 9203 | #define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff |
|---|
| 9204 | #define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 |
|---|
| 9205 | #define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff |
|---|
| 9206 | #define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 |
|---|
| 9207 | #define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff |
|---|
| 9208 | #define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 |
|---|
| 9209 | #define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff |
|---|
| 9210 | #define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 |
|---|
| 9211 | #define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff |
|---|
| 9212 | #define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0 |
|---|
| 9213 | #define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff |
|---|
| 9214 | #define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0 |
|---|
| 9215 | #define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff |
|---|
| 9216 | #define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0 |
|---|
| 9217 | #define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff |
|---|
| 9218 | #define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0 |
|---|
| 9219 | #define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff |
|---|
| 9220 | #define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0 |
|---|
| 9221 | #define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff |
|---|
| 9222 | #define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0 |
|---|
| 9223 | #define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff |
|---|
| 9224 | #define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0 |
|---|
| 9225 | #define DVO_ENABLE__DVO_ENABLE_MASK 0x1 |
|---|
| 9226 | #define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 |
|---|
| 9227 | #define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 |
|---|
| 9228 | #define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 |
|---|
| 9229 | #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 |
|---|
| 9230 | #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 9231 | #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 |
|---|
| 9232 | #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 |
|---|
| 9233 | #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 |
|---|
| 9234 | #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 |
|---|
| 9235 | #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 |
|---|
| 9236 | #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 |
|---|
| 9237 | #define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 |
|---|
| 9238 | #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 |
|---|
| 9239 | #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 |
|---|
| 9240 | #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 |
|---|
| 9241 | #define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 |
|---|
| 9242 | #define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 |
|---|
| 9243 | #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 |
|---|
| 9244 | #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 |
|---|
| 9245 | #define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 |
|---|
| 9246 | #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 |
|---|
| 9247 | #define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 |
|---|
| 9248 | #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 |
|---|
| 9249 | #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 |
|---|
| 9250 | #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 |
|---|
| 9251 | #define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 |
|---|
| 9252 | #define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 |
|---|
| 9253 | #define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 |
|---|
| 9254 | #define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 |
|---|
| 9255 | #define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 |
|---|
| 9256 | #define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 |
|---|
| 9257 | #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 |
|---|
| 9258 | #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 |
|---|
| 9259 | #define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 |
|---|
| 9260 | #define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f |
|---|
| 9261 | #define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 |
|---|
| 9262 | #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 |
|---|
| 9263 | #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff |
|---|
| 9264 | #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 |
|---|
| 9265 | #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff |
|---|
| 9266 | #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 |
|---|
| 9267 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 |
|---|
| 9268 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 |
|---|
| 9269 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
|---|
| 9270 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
|---|
| 9271 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
|---|
| 9272 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
|---|
| 9273 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 |
|---|
| 9274 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 |
|---|
| 9275 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
|---|
| 9276 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
|---|
| 9277 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 |
|---|
| 9278 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
|---|
| 9279 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
|---|
| 9280 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
|---|
| 9281 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 |
|---|
| 9282 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d |
|---|
| 9283 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
|---|
| 9284 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
|---|
| 9285 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
|---|
| 9286 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
|---|
| 9287 | #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9288 | #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9289 | #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9290 | #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9291 | #define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9292 | #define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9293 | #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 |
|---|
| 9294 | #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 |
|---|
| 9295 | #define FBC_CNTL__FBC_SRC_SEL_MASK 0xe |
|---|
| 9296 | #define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 |
|---|
| 9297 | #define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 |
|---|
| 9298 | #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 |
|---|
| 9299 | #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 |
|---|
| 9300 | #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 |
|---|
| 9301 | #define FBC_CNTL__FBC_EN_MASK 0x80000000 |
|---|
| 9302 | #define FBC_CNTL__FBC_EN__SHIFT 0x1f |
|---|
| 9303 | #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff |
|---|
| 9304 | #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 |
|---|
| 9305 | #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff |
|---|
| 9306 | #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 |
|---|
| 9307 | #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f |
|---|
| 9308 | #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 |
|---|
| 9309 | #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 |
|---|
| 9310 | #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 |
|---|
| 9311 | #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 |
|---|
| 9312 | #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 |
|---|
| 9313 | #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf |
|---|
| 9314 | #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 |
|---|
| 9315 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 |
|---|
| 9316 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 |
|---|
| 9317 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 |
|---|
| 9318 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 |
|---|
| 9319 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 |
|---|
| 9320 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 |
|---|
| 9321 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 |
|---|
| 9322 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 |
|---|
| 9323 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 |
|---|
| 9324 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 |
|---|
| 9325 | #define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 |
|---|
| 9326 | #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 |
|---|
| 9327 | #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 |
|---|
| 9328 | #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 |
|---|
| 9329 | #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 |
|---|
| 9330 | #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 |
|---|
| 9331 | #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 |
|---|
| 9332 | #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa |
|---|
| 9333 | #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 |
|---|
| 9334 | #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb |
|---|
| 9335 | #define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 |
|---|
| 9336 | #define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 |
|---|
| 9337 | #define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff |
|---|
| 9338 | #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 |
|---|
| 9339 | #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 |
|---|
| 9340 | #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 |
|---|
| 9341 | #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 |
|---|
| 9342 | #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 |
|---|
| 9343 | #define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 |
|---|
| 9344 | #define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 |
|---|
| 9345 | #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 |
|---|
| 9346 | #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 |
|---|
| 9347 | #define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff |
|---|
| 9348 | #define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 |
|---|
| 9349 | #define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff |
|---|
| 9350 | #define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 |
|---|
| 9351 | #define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff |
|---|
| 9352 | #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 |
|---|
| 9353 | #define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff |
|---|
| 9354 | #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 |
|---|
| 9355 | #define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff |
|---|
| 9356 | #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 |
|---|
| 9357 | #define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff |
|---|
| 9358 | #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 |
|---|
| 9359 | #define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff |
|---|
| 9360 | #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 |
|---|
| 9361 | #define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff |
|---|
| 9362 | #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 |
|---|
| 9363 | #define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff |
|---|
| 9364 | #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 |
|---|
| 9365 | #define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff |
|---|
| 9366 | #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 |
|---|
| 9367 | #define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff |
|---|
| 9368 | #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 |
|---|
| 9369 | #define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff |
|---|
| 9370 | #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 |
|---|
| 9371 | #define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff |
|---|
| 9372 | #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 |
|---|
| 9373 | #define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff |
|---|
| 9374 | #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 |
|---|
| 9375 | #define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff |
|---|
| 9376 | #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 |
|---|
| 9377 | #define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff |
|---|
| 9378 | #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 |
|---|
| 9379 | #define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff |
|---|
| 9380 | #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 |
|---|
| 9381 | #define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff |
|---|
| 9382 | #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 |
|---|
| 9383 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff |
|---|
| 9384 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 |
|---|
| 9385 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000 |
|---|
| 9386 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 |
|---|
| 9387 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff |
|---|
| 9388 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 |
|---|
| 9389 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000 |
|---|
| 9390 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 |
|---|
| 9391 | #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 |
|---|
| 9392 | #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 |
|---|
| 9393 | #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 |
|---|
| 9394 | #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 |
|---|
| 9395 | #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 |
|---|
| 9396 | #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 |
|---|
| 9397 | #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 |
|---|
| 9398 | #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 |
|---|
| 9399 | #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 |
|---|
| 9400 | #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 |
|---|
| 9401 | #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 |
|---|
| 9402 | #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa |
|---|
| 9403 | #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 |
|---|
| 9404 | #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb |
|---|
| 9405 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff |
|---|
| 9406 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 |
|---|
| 9407 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 |
|---|
| 9408 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 |
|---|
| 9409 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 |
|---|
| 9410 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 |
|---|
| 9411 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 |
|---|
| 9412 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f |
|---|
| 9413 | #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff |
|---|
| 9414 | #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 |
|---|
| 9415 | #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff |
|---|
| 9416 | #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 |
|---|
| 9417 | #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff |
|---|
| 9418 | #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 |
|---|
| 9419 | #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff |
|---|
| 9420 | #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 |
|---|
| 9421 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 |
|---|
| 9422 | #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 |
|---|
| 9423 | #define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 |
|---|
| 9424 | #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 |
|---|
| 9425 | #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 |
|---|
| 9426 | #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 |
|---|
| 9427 | #define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 |
|---|
| 9428 | #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 |
|---|
| 9429 | #define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 |
|---|
| 9430 | #define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 |
|---|
| 9431 | #define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 |
|---|
| 9432 | #define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa |
|---|
| 9433 | #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 |
|---|
| 9434 | #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb |
|---|
| 9435 | #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 |
|---|
| 9436 | #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc |
|---|
| 9437 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 |
|---|
| 9438 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 |
|---|
| 9439 | #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 |
|---|
| 9440 | #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 |
|---|
| 9441 | #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 |
|---|
| 9442 | #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 |
|---|
| 9443 | #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000 |
|---|
| 9444 | #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18 |
|---|
| 9445 | #define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 |
|---|
| 9446 | #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 |
|---|
| 9447 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9448 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9449 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9450 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9451 | #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9452 | #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9453 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff |
|---|
| 9454 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
|---|
| 9455 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 |
|---|
| 9456 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
|---|
| 9457 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff |
|---|
| 9458 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
|---|
| 9459 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 |
|---|
| 9460 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
|---|
| 9461 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff |
|---|
| 9462 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
|---|
| 9463 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 |
|---|
| 9464 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
|---|
| 9465 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 |
|---|
| 9466 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
|---|
| 9467 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 |
|---|
| 9468 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
|---|
| 9469 | #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 |
|---|
| 9470 | #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
|---|
| 9471 | #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 |
|---|
| 9472 | #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 |
|---|
| 9473 | #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00 |
|---|
| 9474 | #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
|---|
| 9475 | #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000 |
|---|
| 9476 | #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
|---|
| 9477 | #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 |
|---|
| 9478 | #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
|---|
| 9479 | #define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 |
|---|
| 9480 | #define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 |
|---|
| 9481 | #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 |
|---|
| 9482 | #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 |
|---|
| 9483 | #define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 |
|---|
| 9484 | #define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 |
|---|
| 9485 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1 |
|---|
| 9486 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0 |
|---|
| 9487 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700 |
|---|
| 9488 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8 |
|---|
| 9489 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000 |
|---|
| 9490 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc |
|---|
| 9491 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x10000 |
|---|
| 9492 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x10 |
|---|
| 9493 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff |
|---|
| 9494 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0 |
|---|
| 9495 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000 |
|---|
| 9496 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10 |
|---|
| 9497 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff |
|---|
| 9498 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0 |
|---|
| 9499 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000 |
|---|
| 9500 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10 |
|---|
| 9501 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 |
|---|
| 9502 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
|---|
| 9503 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 |
|---|
| 9504 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
|---|
| 9505 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 |
|---|
| 9506 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
|---|
| 9507 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 |
|---|
| 9508 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
|---|
| 9509 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 |
|---|
| 9510 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
|---|
| 9511 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 |
|---|
| 9512 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
|---|
| 9513 | #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 |
|---|
| 9514 | #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
|---|
| 9515 | #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 |
|---|
| 9516 | #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
|---|
| 9517 | #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 |
|---|
| 9518 | #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
|---|
| 9519 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 |
|---|
| 9520 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
|---|
| 9521 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 |
|---|
| 9522 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
|---|
| 9523 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 |
|---|
| 9524 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
|---|
| 9525 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 |
|---|
| 9526 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
|---|
| 9527 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 |
|---|
| 9528 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
|---|
| 9529 | #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 |
|---|
| 9530 | #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
|---|
| 9531 | #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 |
|---|
| 9532 | #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
|---|
| 9533 | #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 |
|---|
| 9534 | #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
|---|
| 9535 | #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff |
|---|
| 9536 | #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
|---|
| 9537 | #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 |
|---|
| 9538 | #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
|---|
| 9539 | #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff |
|---|
| 9540 | #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
|---|
| 9541 | #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 |
|---|
| 9542 | #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
|---|
| 9543 | #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff |
|---|
| 9544 | #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
|---|
| 9545 | #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 |
|---|
| 9546 | #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
|---|
| 9547 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 |
|---|
| 9548 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 |
|---|
| 9549 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 |
|---|
| 9550 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 |
|---|
| 9551 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff |
|---|
| 9552 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 |
|---|
| 9553 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff |
|---|
| 9554 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 |
|---|
| 9555 | #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 |
|---|
| 9556 | #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
|---|
| 9557 | #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 |
|---|
| 9558 | #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
|---|
| 9559 | #define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 |
|---|
| 9560 | #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 |
|---|
| 9561 | #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 |
|---|
| 9562 | #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 |
|---|
| 9563 | #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 |
|---|
| 9564 | #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 |
|---|
| 9565 | #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100 |
|---|
| 9566 | #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8 |
|---|
| 9567 | #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 |
|---|
| 9568 | #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc |
|---|
| 9569 | #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 |
|---|
| 9570 | #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 |
|---|
| 9571 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 |
|---|
| 9572 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 |
|---|
| 9573 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 |
|---|
| 9574 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 |
|---|
| 9575 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff |
|---|
| 9576 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 |
|---|
| 9577 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 |
|---|
| 9578 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
|---|
| 9579 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff |
|---|
| 9580 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
|---|
| 9581 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 |
|---|
| 9582 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
|---|
| 9583 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff |
|---|
| 9584 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 |
|---|
| 9585 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 |
|---|
| 9586 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 |
|---|
| 9587 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff |
|---|
| 9588 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 |
|---|
| 9589 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 |
|---|
| 9590 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 |
|---|
| 9591 | #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 |
|---|
| 9592 | #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 |
|---|
| 9593 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9594 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9595 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9596 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9597 | #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9598 | #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9599 | #define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff |
|---|
| 9600 | #define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 |
|---|
| 9601 | #define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff |
|---|
| 9602 | #define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 |
|---|
| 9603 | #define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff |
|---|
| 9604 | #define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 |
|---|
| 9605 | #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff |
|---|
| 9606 | #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 |
|---|
| 9607 | #define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 |
|---|
| 9608 | #define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
|---|
| 9609 | #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 |
|---|
| 9610 | #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 |
|---|
| 9611 | #define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 |
|---|
| 9612 | #define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 |
|---|
| 9613 | #define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 |
|---|
| 9614 | #define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 |
|---|
| 9615 | #define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 |
|---|
| 9616 | #define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 |
|---|
| 9617 | #define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 |
|---|
| 9618 | #define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc |
|---|
| 9619 | #define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 |
|---|
| 9620 | #define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 |
|---|
| 9621 | #define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 |
|---|
| 9622 | #define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
|---|
| 9623 | #define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff |
|---|
| 9624 | #define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 |
|---|
| 9625 | #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 |
|---|
| 9626 | #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
|---|
| 9627 | #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 |
|---|
| 9628 | #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 |
|---|
| 9629 | #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff |
|---|
| 9630 | #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 |
|---|
| 9631 | #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff |
|---|
| 9632 | #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 |
|---|
| 9633 | #define LB_VLINE_START_END__VLINE_START_MASK 0x3fff |
|---|
| 9634 | #define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 |
|---|
| 9635 | #define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 |
|---|
| 9636 | #define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 |
|---|
| 9637 | #define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 |
|---|
| 9638 | #define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f |
|---|
| 9639 | #define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff |
|---|
| 9640 | #define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 |
|---|
| 9641 | #define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 |
|---|
| 9642 | #define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 |
|---|
| 9643 | #define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 |
|---|
| 9644 | #define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f |
|---|
| 9645 | #define LB_V_COUNTER__V_COUNTER_MASK 0x7fff |
|---|
| 9646 | #define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
|---|
| 9647 | #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff |
|---|
| 9648 | #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 |
|---|
| 9649 | #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 |
|---|
| 9650 | #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 |
|---|
| 9651 | #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 |
|---|
| 9652 | #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 |
|---|
| 9653 | #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 |
|---|
| 9654 | #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 |
|---|
| 9655 | #define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 |
|---|
| 9656 | #define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 |
|---|
| 9657 | #define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 |
|---|
| 9658 | #define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 |
|---|
| 9659 | #define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 |
|---|
| 9660 | #define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc |
|---|
| 9661 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 |
|---|
| 9662 | #define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 |
|---|
| 9663 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9664 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9665 | #define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 |
|---|
| 9666 | #define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 |
|---|
| 9667 | #define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 |
|---|
| 9668 | #define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 |
|---|
| 9669 | #define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 |
|---|
| 9670 | #define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc |
|---|
| 9671 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 |
|---|
| 9672 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 |
|---|
| 9673 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9674 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9675 | #define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 |
|---|
| 9676 | #define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 |
|---|
| 9677 | #define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 |
|---|
| 9678 | #define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 |
|---|
| 9679 | #define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 |
|---|
| 9680 | #define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc |
|---|
| 9681 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 |
|---|
| 9682 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 |
|---|
| 9683 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9684 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9685 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 |
|---|
| 9686 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 |
|---|
| 9687 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 |
|---|
| 9688 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 |
|---|
| 9689 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 |
|---|
| 9690 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 |
|---|
| 9691 | #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 |
|---|
| 9692 | #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 |
|---|
| 9693 | #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 |
|---|
| 9694 | #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 |
|---|
| 9695 | #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 |
|---|
| 9696 | #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 |
|---|
| 9697 | #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 |
|---|
| 9698 | #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 |
|---|
| 9699 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 |
|---|
| 9700 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 |
|---|
| 9701 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 |
|---|
| 9702 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 |
|---|
| 9703 | #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 |
|---|
| 9704 | #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 |
|---|
| 9705 | #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 |
|---|
| 9706 | #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 |
|---|
| 9707 | #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 |
|---|
| 9708 | #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 |
|---|
| 9709 | #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 |
|---|
| 9710 | #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 |
|---|
| 9711 | #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 |
|---|
| 9712 | #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 |
|---|
| 9713 | #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 |
|---|
| 9714 | #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 |
|---|
| 9715 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f |
|---|
| 9716 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 |
|---|
| 9717 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 |
|---|
| 9718 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa |
|---|
| 9719 | #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 |
|---|
| 9720 | #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 |
|---|
| 9721 | #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 |
|---|
| 9722 | #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c |
|---|
| 9723 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff |
|---|
| 9724 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 |
|---|
| 9725 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 |
|---|
| 9726 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 |
|---|
| 9727 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff |
|---|
| 9728 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 |
|---|
| 9729 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 |
|---|
| 9730 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 |
|---|
| 9731 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf |
|---|
| 9732 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 |
|---|
| 9733 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 |
|---|
| 9734 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 |
|---|
| 9735 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 |
|---|
| 9736 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 |
|---|
| 9737 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 |
|---|
| 9738 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc |
|---|
| 9739 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 |
|---|
| 9740 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 |
|---|
| 9741 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 |
|---|
| 9742 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 |
|---|
| 9743 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 |
|---|
| 9744 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 |
|---|
| 9745 | #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 |
|---|
| 9746 | #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 |
|---|
| 9747 | #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 |
|---|
| 9748 | #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 |
|---|
| 9749 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf |
|---|
| 9750 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 |
|---|
| 9751 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 |
|---|
| 9752 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 |
|---|
| 9753 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 |
|---|
| 9754 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 |
|---|
| 9755 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 |
|---|
| 9756 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc |
|---|
| 9757 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 |
|---|
| 9758 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 |
|---|
| 9759 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 |
|---|
| 9760 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 |
|---|
| 9761 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 |
|---|
| 9762 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 |
|---|
| 9763 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 |
|---|
| 9764 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e |
|---|
| 9765 | #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 |
|---|
| 9766 | #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 |
|---|
| 9767 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 |
|---|
| 9768 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 |
|---|
| 9769 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 |
|---|
| 9770 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc |
|---|
| 9771 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 |
|---|
| 9772 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 |
|---|
| 9773 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 |
|---|
| 9774 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 |
|---|
| 9775 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 |
|---|
| 9776 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c |
|---|
| 9777 | #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 |
|---|
| 9778 | #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f |
|---|
| 9779 | #define LB_DEBUG__LB_DEBUG_MASK 0xffffffff |
|---|
| 9780 | #define LB_DEBUG__LB_DEBUG__SHIFT 0x0 |
|---|
| 9781 | #define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff |
|---|
| 9782 | #define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 |
|---|
| 9783 | #define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff |
|---|
| 9784 | #define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 |
|---|
| 9785 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9786 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9787 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9788 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9789 | #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9790 | #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9791 | #define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 |
|---|
| 9792 | #define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
|---|
| 9793 | #define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 |
|---|
| 9794 | #define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 |
|---|
| 9795 | #define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 |
|---|
| 9796 | #define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 |
|---|
| 9797 | #define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 |
|---|
| 9798 | #define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 |
|---|
| 9799 | #define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 |
|---|
| 9800 | #define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 |
|---|
| 9801 | #define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40 |
|---|
| 9802 | #define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6 |
|---|
| 9803 | #define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80 |
|---|
| 9804 | #define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7 |
|---|
| 9805 | #define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000 |
|---|
| 9806 | #define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc |
|---|
| 9807 | #define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 |
|---|
| 9808 | #define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 |
|---|
| 9809 | #define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 |
|---|
| 9810 | #define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
|---|
| 9811 | #define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff |
|---|
| 9812 | #define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 |
|---|
| 9813 | #define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 |
|---|
| 9814 | #define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
|---|
| 9815 | #define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 |
|---|
| 9816 | #define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 |
|---|
| 9817 | #define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff |
|---|
| 9818 | #define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 |
|---|
| 9819 | #define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff |
|---|
| 9820 | #define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 |
|---|
| 9821 | #define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff |
|---|
| 9822 | #define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0 |
|---|
| 9823 | #define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000 |
|---|
| 9824 | #define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10 |
|---|
| 9825 | #define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000 |
|---|
| 9826 | #define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f |
|---|
| 9827 | #define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff |
|---|
| 9828 | #define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0 |
|---|
| 9829 | #define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 |
|---|
| 9830 | #define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10 |
|---|
| 9831 | #define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 |
|---|
| 9832 | #define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f |
|---|
| 9833 | #define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff |
|---|
| 9834 | #define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0 |
|---|
| 9835 | #define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff |
|---|
| 9836 | #define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 |
|---|
| 9837 | #define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff |
|---|
| 9838 | #define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0 |
|---|
| 9839 | #define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff |
|---|
| 9840 | #define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0 |
|---|
| 9841 | #define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 |
|---|
| 9842 | #define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 |
|---|
| 9843 | #define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 |
|---|
| 9844 | #define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 |
|---|
| 9845 | #define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 |
|---|
| 9846 | #define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 |
|---|
| 9847 | #define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 |
|---|
| 9848 | #define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 |
|---|
| 9849 | #define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10 |
|---|
| 9850 | #define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 |
|---|
| 9851 | #define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000 |
|---|
| 9852 | #define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc |
|---|
| 9853 | #define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 |
|---|
| 9854 | #define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 |
|---|
| 9855 | #define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9856 | #define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9857 | #define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 |
|---|
| 9858 | #define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 |
|---|
| 9859 | #define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 |
|---|
| 9860 | #define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 |
|---|
| 9861 | #define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 |
|---|
| 9862 | #define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc |
|---|
| 9863 | #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 |
|---|
| 9864 | #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 |
|---|
| 9865 | #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9866 | #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9867 | #define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 |
|---|
| 9868 | #define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 |
|---|
| 9869 | #define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 |
|---|
| 9870 | #define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 |
|---|
| 9871 | #define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 |
|---|
| 9872 | #define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc |
|---|
| 9873 | #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 |
|---|
| 9874 | #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 |
|---|
| 9875 | #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 |
|---|
| 9876 | #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 |
|---|
| 9877 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 |
|---|
| 9878 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 |
|---|
| 9879 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 |
|---|
| 9880 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 |
|---|
| 9881 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 |
|---|
| 9882 | #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 |
|---|
| 9883 | #define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 |
|---|
| 9884 | #define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 |
|---|
| 9885 | #define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 |
|---|
| 9886 | #define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 |
|---|
| 9887 | #define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 |
|---|
| 9888 | #define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 |
|---|
| 9889 | #define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 |
|---|
| 9890 | #define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 |
|---|
| 9891 | #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 |
|---|
| 9892 | #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 |
|---|
| 9893 | #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 |
|---|
| 9894 | #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 |
|---|
| 9895 | #define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 |
|---|
| 9896 | #define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 |
|---|
| 9897 | #define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 |
|---|
| 9898 | #define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 |
|---|
| 9899 | #define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 |
|---|
| 9900 | #define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 |
|---|
| 9901 | #define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 |
|---|
| 9902 | #define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 |
|---|
| 9903 | #define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 |
|---|
| 9904 | #define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 |
|---|
| 9905 | #define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 |
|---|
| 9906 | #define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 |
|---|
| 9907 | #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f |
|---|
| 9908 | #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 |
|---|
| 9909 | #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 |
|---|
| 9910 | #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa |
|---|
| 9911 | #define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 |
|---|
| 9912 | #define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 |
|---|
| 9913 | #define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 |
|---|
| 9914 | #define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c |
|---|
| 9915 | #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff |
|---|
| 9916 | #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 |
|---|
| 9917 | #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 |
|---|
| 9918 | #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 |
|---|
| 9919 | #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff |
|---|
| 9920 | #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 |
|---|
| 9921 | #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 |
|---|
| 9922 | #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 |
|---|
| 9923 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf |
|---|
| 9924 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 |
|---|
| 9925 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 |
|---|
| 9926 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 |
|---|
| 9927 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 |
|---|
| 9928 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 |
|---|
| 9929 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 |
|---|
| 9930 | #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc |
|---|
| 9931 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 |
|---|
| 9932 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 |
|---|
| 9933 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 |
|---|
| 9934 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 |
|---|
| 9935 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 |
|---|
| 9936 | #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 |
|---|
| 9937 | #define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 |
|---|
| 9938 | #define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 |
|---|
| 9939 | #define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff |
|---|
| 9940 | #define LBV_DEBUG__LB_DEBUG__SHIFT 0x0 |
|---|
| 9941 | #define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff |
|---|
| 9942 | #define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0 |
|---|
| 9943 | #define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff |
|---|
| 9944 | #define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0 |
|---|
| 9945 | #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 9946 | #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 9947 | #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 9948 | #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 9949 | #define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 9950 | #define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 9951 | #define MVP_CONTROL1__MVP_EN_MASK 0x1 |
|---|
| 9952 | #define MVP_CONTROL1__MVP_EN__SHIFT 0x0 |
|---|
| 9953 | #define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 |
|---|
| 9954 | #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 |
|---|
| 9955 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 |
|---|
| 9956 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 |
|---|
| 9957 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 |
|---|
| 9958 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 |
|---|
| 9959 | #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 |
|---|
| 9960 | #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa |
|---|
| 9961 | #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 |
|---|
| 9962 | #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc |
|---|
| 9963 | #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 |
|---|
| 9964 | #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 |
|---|
| 9965 | #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 |
|---|
| 9966 | #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 |
|---|
| 9967 | #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 |
|---|
| 9968 | #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 |
|---|
| 9969 | #define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 |
|---|
| 9970 | #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c |
|---|
| 9971 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 |
|---|
| 9972 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e |
|---|
| 9973 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 |
|---|
| 9974 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f |
|---|
| 9975 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 |
|---|
| 9976 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 |
|---|
| 9977 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 |
|---|
| 9978 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 |
|---|
| 9979 | #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 |
|---|
| 9980 | #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 |
|---|
| 9981 | #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 |
|---|
| 9982 | #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc |
|---|
| 9983 | #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 |
|---|
| 9984 | #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 |
|---|
| 9985 | #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 |
|---|
| 9986 | #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 |
|---|
| 9987 | #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 |
|---|
| 9988 | #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 |
|---|
| 9989 | #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 |
|---|
| 9990 | #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c |
|---|
| 9991 | #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff |
|---|
| 9992 | #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 |
|---|
| 9993 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 |
|---|
| 9994 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 |
|---|
| 9995 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 |
|---|
| 9996 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 |
|---|
| 9997 | #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff |
|---|
| 9998 | #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 |
|---|
| 9999 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 |
|---|
| 10000 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 |
|---|
| 10001 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 |
|---|
| 10002 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc |
|---|
| 10003 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 |
|---|
| 10004 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 |
|---|
| 10005 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 |
|---|
| 10006 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 |
|---|
| 10007 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 |
|---|
| 10008 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 |
|---|
| 10009 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 |
|---|
| 10010 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c |
|---|
| 10011 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 |
|---|
| 10012 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e |
|---|
| 10013 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 |
|---|
| 10014 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f |
|---|
| 10015 | #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff |
|---|
| 10016 | #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 |
|---|
| 10017 | #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 |
|---|
| 10018 | #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 |
|---|
| 10019 | #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 |
|---|
| 10020 | #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 |
|---|
| 10021 | #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 |
|---|
| 10022 | #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 |
|---|
| 10023 | #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 |
|---|
| 10024 | #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 |
|---|
| 10025 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff |
|---|
| 10026 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 |
|---|
| 10027 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 |
|---|
| 10028 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa |
|---|
| 10029 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 |
|---|
| 10030 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 |
|---|
| 10031 | #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff |
|---|
| 10032 | #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 |
|---|
| 10033 | #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 |
|---|
| 10034 | #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 |
|---|
| 10035 | #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 |
|---|
| 10036 | #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 |
|---|
| 10037 | #define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 |
|---|
| 10038 | #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c |
|---|
| 10039 | #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 |
|---|
| 10040 | #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d |
|---|
| 10041 | #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 |
|---|
| 10042 | #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e |
|---|
| 10043 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff |
|---|
| 10044 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 |
|---|
| 10045 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 |
|---|
| 10046 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 |
|---|
| 10047 | #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff |
|---|
| 10048 | #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 |
|---|
| 10049 | #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 |
|---|
| 10050 | #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 |
|---|
| 10051 | #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 |
|---|
| 10052 | #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 |
|---|
| 10053 | #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 |
|---|
| 10054 | #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 |
|---|
| 10055 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 |
|---|
| 10056 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc |
|---|
| 10057 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 |
|---|
| 10058 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 |
|---|
| 10059 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 |
|---|
| 10060 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 |
|---|
| 10061 | #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 |
|---|
| 10062 | #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 |
|---|
| 10063 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 |
|---|
| 10064 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c |
|---|
| 10065 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff |
|---|
| 10066 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 |
|---|
| 10067 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 |
|---|
| 10068 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 |
|---|
| 10069 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 |
|---|
| 10070 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f |
|---|
| 10071 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff |
|---|
| 10072 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 |
|---|
| 10073 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 |
|---|
| 10074 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f |
|---|
| 10075 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 |
|---|
| 10076 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 |
|---|
| 10077 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 |
|---|
| 10078 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 |
|---|
| 10079 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 |
|---|
| 10080 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 |
|---|
| 10081 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 |
|---|
| 10082 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 |
|---|
| 10083 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 |
|---|
| 10084 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 |
|---|
| 10085 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 |
|---|
| 10086 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 |
|---|
| 10087 | #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 |
|---|
| 10088 | #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 |
|---|
| 10089 | #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 |
|---|
| 10090 | #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 |
|---|
| 10091 | #define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 |
|---|
| 10092 | #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 |
|---|
| 10093 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 10094 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 10095 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 10096 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 10097 | #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 10098 | #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 10099 | #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 |
|---|
| 10100 | #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 |
|---|
| 10101 | #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 |
|---|
| 10102 | #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 |
|---|
| 10103 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 |
|---|
| 10104 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 |
|---|
| 10105 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe |
|---|
| 10106 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 |
|---|
| 10107 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 |
|---|
| 10108 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 |
|---|
| 10109 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe |
|---|
| 10110 | #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 |
|---|
| 10111 | #define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 |
|---|
| 10112 | #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 |
|---|
| 10113 | #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 |
|---|
| 10114 | #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a |
|---|
| 10115 | #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 |
|---|
| 10116 | #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b |
|---|
| 10117 | #define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 |
|---|
| 10118 | #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 |
|---|
| 10119 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 |
|---|
| 10120 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 |
|---|
| 10121 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 |
|---|
| 10122 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 |
|---|
| 10123 | #define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 |
|---|
| 10124 | #define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 |
|---|
| 10125 | #define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 |
|---|
| 10126 | #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa |
|---|
| 10127 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 |
|---|
| 10128 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb |
|---|
| 10129 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 |
|---|
| 10130 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc |
|---|
| 10131 | #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 |
|---|
| 10132 | #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd |
|---|
| 10133 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 |
|---|
| 10134 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe |
|---|
| 10135 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 |
|---|
| 10136 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf |
|---|
| 10137 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 |
|---|
| 10138 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 |
|---|
| 10139 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 |
|---|
| 10140 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 |
|---|
| 10141 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 |
|---|
| 10142 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 |
|---|
| 10143 | #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 |
|---|
| 10144 | #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 |
|---|
| 10145 | #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 |
|---|
| 10146 | #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 |
|---|
| 10147 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 |
|---|
| 10148 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 |
|---|
| 10149 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 |
|---|
| 10150 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 |
|---|
| 10151 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 |
|---|
| 10152 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 |
|---|
| 10153 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 |
|---|
| 10154 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 |
|---|
| 10155 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 |
|---|
| 10156 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 |
|---|
| 10157 | #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 |
|---|
| 10158 | #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 |
|---|
| 10159 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 |
|---|
| 10160 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 |
|---|
| 10161 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 |
|---|
| 10162 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc |
|---|
| 10163 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 |
|---|
| 10164 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd |
|---|
| 10165 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 |
|---|
| 10166 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 |
|---|
| 10167 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 |
|---|
| 10168 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 |
|---|
| 10169 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 |
|---|
| 10170 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 |
|---|
| 10171 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 |
|---|
| 10172 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 |
|---|
| 10173 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc |
|---|
| 10174 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 |
|---|
| 10175 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf |
|---|
| 10176 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
|---|
| 10177 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 |
|---|
| 10178 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 |
|---|
| 10179 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 |
|---|
| 10180 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 |
|---|
| 10181 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff |
|---|
| 10182 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
|---|
| 10183 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 |
|---|
| 10184 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
|---|
| 10185 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 |
|---|
| 10186 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 |
|---|
| 10187 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 |
|---|
| 10188 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
|---|
| 10189 | #define SCL_MODE__SCL_MODE_MASK 0x3 |
|---|
| 10190 | #define SCL_MODE__SCL_MODE__SHIFT 0x0 |
|---|
| 10191 | #define SCL_MODE__SCL_PSCL_EN_MASK 0x10 |
|---|
| 10192 | #define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4 |
|---|
| 10193 | #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 |
|---|
| 10194 | #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 |
|---|
| 10195 | #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 |
|---|
| 10196 | #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 |
|---|
| 10197 | #define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 |
|---|
| 10198 | #define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
|---|
| 10199 | #define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 |
|---|
| 10200 | #define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 |
|---|
| 10201 | #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 |
|---|
| 10202 | #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 |
|---|
| 10203 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf |
|---|
| 10204 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
|---|
| 10205 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 |
|---|
| 10206 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
|---|
| 10207 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 |
|---|
| 10208 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 |
|---|
| 10209 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 |
|---|
| 10210 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 |
|---|
| 10211 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 |
|---|
| 10212 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 |
|---|
| 10213 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
|---|
| 10214 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
|---|
| 10215 | #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff |
|---|
| 10216 | #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10217 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff |
|---|
| 10218 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
|---|
| 10219 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 |
|---|
| 10220 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
|---|
| 10221 | #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 |
|---|
| 10222 | #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 |
|---|
| 10223 | #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
|---|
| 10224 | #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
|---|
| 10225 | #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff |
|---|
| 10226 | #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10227 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff |
|---|
| 10228 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
|---|
| 10229 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 |
|---|
| 10230 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
|---|
| 10231 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff |
|---|
| 10232 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
|---|
| 10233 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 |
|---|
| 10234 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
|---|
| 10235 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff |
|---|
| 10236 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 |
|---|
| 10237 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 |
|---|
| 10238 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
|---|
| 10239 | #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 |
|---|
| 10240 | #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 10241 | #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 |
|---|
| 10242 | #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 |
|---|
| 10243 | #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 |
|---|
| 10244 | #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 10245 | #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 |
|---|
| 10246 | #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 |
|---|
| 10247 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 |
|---|
| 10248 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 |
|---|
| 10249 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 |
|---|
| 10250 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 |
|---|
| 10251 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 |
|---|
| 10252 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 |
|---|
| 10253 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 |
|---|
| 10254 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc |
|---|
| 10255 | #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 |
|---|
| 10256 | #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 |
|---|
| 10257 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 |
|---|
| 10258 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 |
|---|
| 10259 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 |
|---|
| 10260 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 |
|---|
| 10261 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 |
|---|
| 10262 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc |
|---|
| 10263 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 |
|---|
| 10264 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 |
|---|
| 10265 | #define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff |
|---|
| 10266 | #define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 |
|---|
| 10267 | #define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 |
|---|
| 10268 | #define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 |
|---|
| 10269 | #define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff |
|---|
| 10270 | #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 |
|---|
| 10271 | #define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 |
|---|
| 10272 | #define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 |
|---|
| 10273 | #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff |
|---|
| 10274 | #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 |
|---|
| 10275 | #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 |
|---|
| 10276 | #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 |
|---|
| 10277 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff |
|---|
| 10278 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
|---|
| 10279 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 |
|---|
| 10280 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
|---|
| 10281 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff |
|---|
| 10282 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
|---|
| 10283 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 |
|---|
| 10284 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
|---|
| 10285 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 |
|---|
| 10286 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 |
|---|
| 10287 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 |
|---|
| 10288 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 |
|---|
| 10289 | #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 |
|---|
| 10290 | #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 |
|---|
| 10291 | #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff |
|---|
| 10292 | #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10293 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff |
|---|
| 10294 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 |
|---|
| 10295 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 |
|---|
| 10296 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 |
|---|
| 10297 | #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 |
|---|
| 10298 | #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 |
|---|
| 10299 | #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 |
|---|
| 10300 | #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 |
|---|
| 10301 | #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 |
|---|
| 10302 | #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 |
|---|
| 10303 | #define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 |
|---|
| 10304 | #define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 |
|---|
| 10305 | #define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff |
|---|
| 10306 | #define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 |
|---|
| 10307 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 10308 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 10309 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 10310 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 10311 | #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 10312 | #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 10313 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3 |
|---|
| 10314 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
|---|
| 10315 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00 |
|---|
| 10316 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 |
|---|
| 10317 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000 |
|---|
| 10318 | #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 |
|---|
| 10319 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff |
|---|
| 10320 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
|---|
| 10321 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 |
|---|
| 10322 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
|---|
| 10323 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 |
|---|
| 10324 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 |
|---|
| 10325 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 |
|---|
| 10326 | #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
|---|
| 10327 | #define SCLV_MODE__SCL_MODE_MASK 0x1 |
|---|
| 10328 | #define SCLV_MODE__SCL_MODE__SHIFT 0x0 |
|---|
| 10329 | #define SCLV_MODE__SCL_PSCL_EN_MASK 0x10 |
|---|
| 10330 | #define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4 |
|---|
| 10331 | #define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300 |
|---|
| 10332 | #define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8 |
|---|
| 10333 | #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 |
|---|
| 10334 | #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 |
|---|
| 10335 | #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70 |
|---|
| 10336 | #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4 |
|---|
| 10337 | #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700 |
|---|
| 10338 | #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8 |
|---|
| 10339 | #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000 |
|---|
| 10340 | #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc |
|---|
| 10341 | #define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 |
|---|
| 10342 | #define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
|---|
| 10343 | #define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 |
|---|
| 10344 | #define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 |
|---|
| 10345 | #define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100 |
|---|
| 10346 | #define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8 |
|---|
| 10347 | #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf |
|---|
| 10348 | #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
|---|
| 10349 | #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 |
|---|
| 10350 | #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
|---|
| 10351 | #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 |
|---|
| 10352 | #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 |
|---|
| 10353 | #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 |
|---|
| 10354 | #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 |
|---|
| 10355 | #define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
|---|
| 10356 | #define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
|---|
| 10357 | #define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff |
|---|
| 10358 | #define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10359 | #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff |
|---|
| 10360 | #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
|---|
| 10361 | #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 |
|---|
| 10362 | #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
|---|
| 10363 | #define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff |
|---|
| 10364 | #define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 |
|---|
| 10365 | #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff |
|---|
| 10366 | #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 |
|---|
| 10367 | #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000 |
|---|
| 10368 | #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 |
|---|
| 10369 | #define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
|---|
| 10370 | #define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
|---|
| 10371 | #define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff |
|---|
| 10372 | #define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10373 | #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff |
|---|
| 10374 | #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
|---|
| 10375 | #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 |
|---|
| 10376 | #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
|---|
| 10377 | #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff |
|---|
| 10378 | #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
|---|
| 10379 | #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 |
|---|
| 10380 | #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
|---|
| 10381 | #define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff |
|---|
| 10382 | #define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 |
|---|
| 10383 | #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff |
|---|
| 10384 | #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 |
|---|
| 10385 | #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000 |
|---|
| 10386 | #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 |
|---|
| 10387 | #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff |
|---|
| 10388 | #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 |
|---|
| 10389 | #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000 |
|---|
| 10390 | #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 |
|---|
| 10391 | #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff |
|---|
| 10392 | #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 |
|---|
| 10393 | #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 |
|---|
| 10394 | #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
|---|
| 10395 | #define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 |
|---|
| 10396 | #define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 10397 | #define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 |
|---|
| 10398 | #define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 |
|---|
| 10399 | #define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 |
|---|
| 10400 | #define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 10401 | #define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 |
|---|
| 10402 | #define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 |
|---|
| 10403 | #define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 |
|---|
| 10404 | #define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 |
|---|
| 10405 | #define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff |
|---|
| 10406 | #define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 |
|---|
| 10407 | #define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 |
|---|
| 10408 | #define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 |
|---|
| 10409 | #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff |
|---|
| 10410 | #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 |
|---|
| 10411 | #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 |
|---|
| 10412 | #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 |
|---|
| 10413 | #define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff |
|---|
| 10414 | #define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 |
|---|
| 10415 | #define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000 |
|---|
| 10416 | #define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 |
|---|
| 10417 | #define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff |
|---|
| 10418 | #define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0 |
|---|
| 10419 | #define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000 |
|---|
| 10420 | #define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10 |
|---|
| 10421 | #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff |
|---|
| 10422 | #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0 |
|---|
| 10423 | #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000 |
|---|
| 10424 | #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10 |
|---|
| 10425 | #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff |
|---|
| 10426 | #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0 |
|---|
| 10427 | #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000 |
|---|
| 10428 | #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10 |
|---|
| 10429 | #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff |
|---|
| 10430 | #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
|---|
| 10431 | #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 |
|---|
| 10432 | #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
|---|
| 10433 | #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff |
|---|
| 10434 | #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
|---|
| 10435 | #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 |
|---|
| 10436 | #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
|---|
| 10437 | #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 |
|---|
| 10438 | #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 |
|---|
| 10439 | #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 |
|---|
| 10440 | #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 |
|---|
| 10441 | #define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 |
|---|
| 10442 | #define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 |
|---|
| 10443 | #define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff |
|---|
| 10444 | #define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 |
|---|
| 10445 | #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff |
|---|
| 10446 | #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 |
|---|
| 10447 | #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 |
|---|
| 10448 | #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 |
|---|
| 10449 | #define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 |
|---|
| 10450 | #define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 |
|---|
| 10451 | #define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 |
|---|
| 10452 | #define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 |
|---|
| 10453 | #define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 |
|---|
| 10454 | #define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 |
|---|
| 10455 | #define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 |
|---|
| 10456 | #define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3 |
|---|
| 10457 | #define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff |
|---|
| 10458 | #define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0 |
|---|
| 10459 | #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 10460 | #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 10461 | #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 10462 | #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 10463 | #define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 10464 | #define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 10465 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1 |
|---|
| 10466 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 10467 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2 |
|---|
| 10468 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1 |
|---|
| 10469 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000 |
|---|
| 10470 | #define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 10471 | #define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
|---|
| 10472 | #define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
|---|
| 10473 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3 |
|---|
| 10474 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0 |
|---|
| 10475 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0xc |
|---|
| 10476 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x2 |
|---|
| 10477 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10 |
|---|
| 10478 | #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x4 |
|---|
| 10479 | #define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff |
|---|
| 10480 | #define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0 |
|---|
| 10481 | #define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000 |
|---|
| 10482 | #define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10 |
|---|
| 10483 | #define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff |
|---|
| 10484 | #define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0 |
|---|
| 10485 | #define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000 |
|---|
| 10486 | #define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10 |
|---|
| 10487 | #define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff |
|---|
| 10488 | #define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0 |
|---|
| 10489 | #define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000 |
|---|
| 10490 | #define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10 |
|---|
| 10491 | #define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff |
|---|
| 10492 | #define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0 |
|---|
| 10493 | #define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000 |
|---|
| 10494 | #define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10 |
|---|
| 10495 | #define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff |
|---|
| 10496 | #define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0 |
|---|
| 10497 | #define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000 |
|---|
| 10498 | #define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10 |
|---|
| 10499 | #define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff |
|---|
| 10500 | #define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0 |
|---|
| 10501 | #define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000 |
|---|
| 10502 | #define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10 |
|---|
| 10503 | #define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff |
|---|
| 10504 | #define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0 |
|---|
| 10505 | #define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000 |
|---|
| 10506 | #define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10 |
|---|
| 10507 | #define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff |
|---|
| 10508 | #define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0 |
|---|
| 10509 | #define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000 |
|---|
| 10510 | #define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10 |
|---|
| 10511 | #define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff |
|---|
| 10512 | #define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0 |
|---|
| 10513 | #define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000 |
|---|
| 10514 | #define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10 |
|---|
| 10515 | #define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff |
|---|
| 10516 | #define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0 |
|---|
| 10517 | #define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000 |
|---|
| 10518 | #define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10 |
|---|
| 10519 | #define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff |
|---|
| 10520 | #define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0 |
|---|
| 10521 | #define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000 |
|---|
| 10522 | #define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10 |
|---|
| 10523 | #define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff |
|---|
| 10524 | #define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0 |
|---|
| 10525 | #define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000 |
|---|
| 10526 | #define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10 |
|---|
| 10527 | #define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3 |
|---|
| 10528 | #define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0 |
|---|
| 10529 | #define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff |
|---|
| 10530 | #define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0 |
|---|
| 10531 | #define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000 |
|---|
| 10532 | #define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10 |
|---|
| 10533 | #define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff |
|---|
| 10534 | #define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0 |
|---|
| 10535 | #define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000 |
|---|
| 10536 | #define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10 |
|---|
| 10537 | #define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff |
|---|
| 10538 | #define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0 |
|---|
| 10539 | #define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000 |
|---|
| 10540 | #define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10 |
|---|
| 10541 | #define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7 |
|---|
| 10542 | #define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0 |
|---|
| 10543 | #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff |
|---|
| 10544 | #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0 |
|---|
| 10545 | #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000 |
|---|
| 10546 | #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10 |
|---|
| 10547 | #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff |
|---|
| 10548 | #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0 |
|---|
| 10549 | #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000 |
|---|
| 10550 | #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10 |
|---|
| 10551 | #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff |
|---|
| 10552 | #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0 |
|---|
| 10553 | #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000 |
|---|
| 10554 | #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10 |
|---|
| 10555 | #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff |
|---|
| 10556 | #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0 |
|---|
| 10557 | #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000 |
|---|
| 10558 | #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10 |
|---|
| 10559 | #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff |
|---|
| 10560 | #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0 |
|---|
| 10561 | #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000 |
|---|
| 10562 | #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10 |
|---|
| 10563 | #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff |
|---|
| 10564 | #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0 |
|---|
| 10565 | #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000 |
|---|
| 10566 | #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10 |
|---|
| 10567 | #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff |
|---|
| 10568 | #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0 |
|---|
| 10569 | #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000 |
|---|
| 10570 | #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10 |
|---|
| 10571 | #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff |
|---|
| 10572 | #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0 |
|---|
| 10573 | #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000 |
|---|
| 10574 | #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10 |
|---|
| 10575 | #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff |
|---|
| 10576 | #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0 |
|---|
| 10577 | #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000 |
|---|
| 10578 | #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10 |
|---|
| 10579 | #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff |
|---|
| 10580 | #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0 |
|---|
| 10581 | #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000 |
|---|
| 10582 | #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10 |
|---|
| 10583 | #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff |
|---|
| 10584 | #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0 |
|---|
| 10585 | #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000 |
|---|
| 10586 | #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10 |
|---|
| 10587 | #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff |
|---|
| 10588 | #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0 |
|---|
| 10589 | #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000 |
|---|
| 10590 | #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10 |
|---|
| 10591 | #define DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK 0x3 |
|---|
| 10592 | #define DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT 0x0 |
|---|
| 10593 | #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff |
|---|
| 10594 | #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0 |
|---|
| 10595 | #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000 |
|---|
| 10596 | #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc |
|---|
| 10597 | #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff |
|---|
| 10598 | #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0 |
|---|
| 10599 | #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000 |
|---|
| 10600 | #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc |
|---|
| 10601 | #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff |
|---|
| 10602 | #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0 |
|---|
| 10603 | #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000 |
|---|
| 10604 | #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc |
|---|
| 10605 | #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff |
|---|
| 10606 | #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 |
|---|
| 10607 | #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000 |
|---|
| 10608 | #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 |
|---|
| 10609 | #define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3 |
|---|
| 10610 | #define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0 |
|---|
| 10611 | #define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0x1ff |
|---|
| 10612 | #define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0 |
|---|
| 10613 | #define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff |
|---|
| 10614 | #define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0 |
|---|
| 10615 | #define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7 |
|---|
| 10616 | #define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0 |
|---|
| 10617 | #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff |
|---|
| 10618 | #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0 |
|---|
| 10619 | #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
|---|
| 10620 | #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
|---|
| 10621 | #define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
|---|
| 10622 | #define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
|---|
| 10623 | #define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff |
|---|
| 10624 | #define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0 |
|---|
| 10625 | #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff |
|---|
| 10626 | #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 |
|---|
| 10627 | #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 |
|---|
| 10628 | #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 |
|---|
| 10629 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff |
|---|
| 10630 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10631 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10632 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10633 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10634 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf |
|---|
| 10635 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10636 | #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10637 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff |
|---|
| 10638 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10639 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10640 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10641 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10642 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf |
|---|
| 10643 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10644 | #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10645 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff |
|---|
| 10646 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10647 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10648 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10649 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10650 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf |
|---|
| 10651 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10652 | #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10653 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff |
|---|
| 10654 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10655 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10656 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10657 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10658 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf |
|---|
| 10659 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10660 | #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10661 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff |
|---|
| 10662 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10663 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10664 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10665 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10666 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf |
|---|
| 10667 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10668 | #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10669 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff |
|---|
| 10670 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10671 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10672 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10673 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10674 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf |
|---|
| 10675 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10676 | #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10677 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff |
|---|
| 10678 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10679 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10680 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10681 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10682 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf |
|---|
| 10683 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10684 | #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10685 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff |
|---|
| 10686 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10687 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10688 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10689 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10690 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf |
|---|
| 10691 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10692 | #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10693 | #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff |
|---|
| 10694 | #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0 |
|---|
| 10695 | #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
|---|
| 10696 | #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
|---|
| 10697 | #define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
|---|
| 10698 | #define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
|---|
| 10699 | #define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff |
|---|
| 10700 | #define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0 |
|---|
| 10701 | #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff |
|---|
| 10702 | #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 |
|---|
| 10703 | #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 |
|---|
| 10704 | #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 |
|---|
| 10705 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff |
|---|
| 10706 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10707 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10708 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10709 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10710 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf |
|---|
| 10711 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10712 | #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10713 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff |
|---|
| 10714 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10715 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10716 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10717 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10718 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf |
|---|
| 10719 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10720 | #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10721 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff |
|---|
| 10722 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10723 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10724 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10725 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10726 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf |
|---|
| 10727 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10728 | #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10729 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff |
|---|
| 10730 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10731 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10732 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10733 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10734 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf |
|---|
| 10735 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10736 | #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10737 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff |
|---|
| 10738 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10739 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10740 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10741 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10742 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf |
|---|
| 10743 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10744 | #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10745 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff |
|---|
| 10746 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10747 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10748 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10749 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10750 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf |
|---|
| 10751 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10752 | #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10753 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff |
|---|
| 10754 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10755 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10756 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10757 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10758 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf |
|---|
| 10759 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10760 | #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10761 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff |
|---|
| 10762 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
|---|
| 10763 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 |
|---|
| 10764 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb |
|---|
| 10765 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 |
|---|
| 10766 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf |
|---|
| 10767 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 |
|---|
| 10768 | #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b |
|---|
| 10769 | #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 10770 | #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 10771 | #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 10772 | #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 10773 | #define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 10774 | #define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 10775 | #define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1 |
|---|
| 10776 | #define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0 |
|---|
| 10777 | #define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 |
|---|
| 10778 | #define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 |
|---|
| 10779 | #define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 |
|---|
| 10780 | #define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 |
|---|
| 10781 | #define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc |
|---|
| 10782 | #define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 |
|---|
| 10783 | #define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30 |
|---|
| 10784 | #define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4 |
|---|
| 10785 | #define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 |
|---|
| 10786 | #define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 |
|---|
| 10787 | #define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 |
|---|
| 10788 | #define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 |
|---|
| 10789 | #define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 |
|---|
| 10790 | #define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb |
|---|
| 10791 | #define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 |
|---|
| 10792 | #define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd |
|---|
| 10793 | #define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 |
|---|
| 10794 | #define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 |
|---|
| 10795 | #define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 |
|---|
| 10796 | #define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 |
|---|
| 10797 | #define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 |
|---|
| 10798 | #define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 |
|---|
| 10799 | #define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 |
|---|
| 10800 | #define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 |
|---|
| 10801 | #define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 |
|---|
| 10802 | #define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 |
|---|
| 10803 | #define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 |
|---|
| 10804 | #define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d |
|---|
| 10805 | #define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 |
|---|
| 10806 | #define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f |
|---|
| 10807 | #define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7 |
|---|
| 10808 | #define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0 |
|---|
| 10809 | #define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 |
|---|
| 10810 | #define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 |
|---|
| 10811 | #define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 |
|---|
| 10812 | #define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 |
|---|
| 10813 | #define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 |
|---|
| 10814 | #define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 |
|---|
| 10815 | #define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 |
|---|
| 10816 | #define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 |
|---|
| 10817 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK 0x1 |
|---|
| 10818 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT 0x0 |
|---|
| 10819 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00 |
|---|
| 10820 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8 |
|---|
| 10821 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK 0x1 |
|---|
| 10822 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT 0x0 |
|---|
| 10823 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00 |
|---|
| 10824 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8 |
|---|
| 10825 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff |
|---|
| 10826 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 |
|---|
| 10827 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff |
|---|
| 10828 | #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
|---|
| 10829 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1 |
|---|
| 10830 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0 |
|---|
| 10831 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 |
|---|
| 10832 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 |
|---|
| 10833 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1 |
|---|
| 10834 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0 |
|---|
| 10835 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 |
|---|
| 10836 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 |
|---|
| 10837 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff |
|---|
| 10838 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 |
|---|
| 10839 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff |
|---|
| 10840 | #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
|---|
| 10841 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK 0x1 |
|---|
| 10842 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT 0x0 |
|---|
| 10843 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00 |
|---|
| 10844 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8 |
|---|
| 10845 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK 0x1 |
|---|
| 10846 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT 0x0 |
|---|
| 10847 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00 |
|---|
| 10848 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8 |
|---|
| 10849 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff |
|---|
| 10850 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 |
|---|
| 10851 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff |
|---|
| 10852 | #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
|---|
| 10853 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1 |
|---|
| 10854 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0 |
|---|
| 10855 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 |
|---|
| 10856 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 |
|---|
| 10857 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1 |
|---|
| 10858 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0 |
|---|
| 10859 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 |
|---|
| 10860 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 |
|---|
| 10861 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff |
|---|
| 10862 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 |
|---|
| 10863 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff |
|---|
| 10864 | #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
|---|
| 10865 | #define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff |
|---|
| 10866 | #define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0 |
|---|
| 10867 | #define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff |
|---|
| 10868 | #define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0 |
|---|
| 10869 | #define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff |
|---|
| 10870 | #define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0 |
|---|
| 10871 | #define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff |
|---|
| 10872 | #define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0 |
|---|
| 10873 | #define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff |
|---|
| 10874 | #define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0 |
|---|
| 10875 | #define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff |
|---|
| 10876 | #define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0 |
|---|
| 10877 | #define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff |
|---|
| 10878 | #define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0 |
|---|
| 10879 | #define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff |
|---|
| 10880 | #define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0 |
|---|
| 10881 | #define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff |
|---|
| 10882 | #define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0 |
|---|
| 10883 | #define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff |
|---|
| 10884 | #define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0 |
|---|
| 10885 | #define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff |
|---|
| 10886 | #define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0 |
|---|
| 10887 | #define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff |
|---|
| 10888 | #define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0 |
|---|
| 10889 | #define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff |
|---|
| 10890 | #define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0 |
|---|
| 10891 | #define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff |
|---|
| 10892 | #define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0 |
|---|
| 10893 | #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 |
|---|
| 10894 | #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 10895 | #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 |
|---|
| 10896 | #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 |
|---|
| 10897 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 |
|---|
| 10898 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 |
|---|
| 10899 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 |
|---|
| 10900 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 |
|---|
| 10901 | #define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 |
|---|
| 10902 | #define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 10903 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 |
|---|
| 10904 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 |
|---|
| 10905 | #define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
|---|
| 10906 | #define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
|---|
| 10907 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 |
|---|
| 10908 | #define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c |
|---|
| 10909 | #define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00 |
|---|
| 10910 | #define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8 |
|---|
| 10911 | #define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00 |
|---|
| 10912 | #define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8 |
|---|
| 10913 | #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff |
|---|
| 10914 | #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0 |
|---|
| 10915 | #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff |
|---|
| 10916 | #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0 |
|---|
| 10917 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 |
|---|
| 10918 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 |
|---|
| 10919 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 |
|---|
| 10920 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 |
|---|
| 10921 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 |
|---|
| 10922 | #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 |
|---|
| 10923 | #define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf |
|---|
| 10924 | #define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 |
|---|
| 10925 | #define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 |
|---|
| 10926 | #define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 |
|---|
| 10927 | #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 |
|---|
| 10928 | #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 |
|---|
| 10929 | #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 |
|---|
| 10930 | #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 |
|---|
| 10931 | #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 |
|---|
| 10932 | #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 |
|---|
| 10933 | #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 |
|---|
| 10934 | #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 |
|---|
| 10935 | #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 |
|---|
| 10936 | #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 |
|---|
| 10937 | #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 |
|---|
| 10938 | #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 |
|---|
| 10939 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 |
|---|
| 10940 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 |
|---|
| 10941 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30 |
|---|
| 10942 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4 |
|---|
| 10943 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100 |
|---|
| 10944 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8 |
|---|
| 10945 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000 |
|---|
| 10946 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc |
|---|
| 10947 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 |
|---|
| 10948 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 |
|---|
| 10949 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 |
|---|
| 10950 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 |
|---|
| 10951 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000 |
|---|
| 10952 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12 |
|---|
| 10953 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000 |
|---|
| 10954 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13 |
|---|
| 10955 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 |
|---|
| 10956 | #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c |
|---|
| 10957 | #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 |
|---|
| 10958 | #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 |
|---|
| 10959 | #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 |
|---|
| 10960 | #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 |
|---|
| 10961 | #define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1 |
|---|
| 10962 | #define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0 |
|---|
| 10963 | #define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c |
|---|
| 10964 | #define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2 |
|---|
| 10965 | #define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300 |
|---|
| 10966 | #define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8 |
|---|
| 10967 | #define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff |
|---|
| 10968 | #define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0 |
|---|
| 10969 | #define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff |
|---|
| 10970 | #define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0 |
|---|
| 10971 | #define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff |
|---|
| 10972 | #define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0 |
|---|
| 10973 | #define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0 |
|---|
| 10974 | #define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4 |
|---|
| 10975 | #define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7 |
|---|
| 10976 | #define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0 |
|---|
| 10977 | #define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10 |
|---|
| 10978 | #define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4 |
|---|
| 10979 | #define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100 |
|---|
| 10980 | #define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8 |
|---|
| 10981 | #define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff |
|---|
| 10982 | #define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0 |
|---|
| 10983 | #define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff |
|---|
| 10984 | #define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0 |
|---|
| 10985 | #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 10986 | #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 10987 | #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 10988 | #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 10989 | #define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 10990 | #define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 10991 | #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 |
|---|
| 10992 | #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
|---|
| 10993 | #define GENMO_WT__VGA_RAM_EN_MASK 0x2 |
|---|
| 10994 | #define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 |
|---|
| 10995 | #define GENMO_WT__VGA_CKSEL_MASK 0xc |
|---|
| 10996 | #define GENMO_WT__VGA_CKSEL__SHIFT 0x2 |
|---|
| 10997 | #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 |
|---|
| 10998 | #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
|---|
| 10999 | #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 |
|---|
| 11000 | #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 |
|---|
| 11001 | #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 |
|---|
| 11002 | #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 |
|---|
| 11003 | #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 |
|---|
| 11004 | #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
|---|
| 11005 | #define GENMO_RD__VGA_RAM_EN_MASK 0x2 |
|---|
| 11006 | #define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 |
|---|
| 11007 | #define GENMO_RD__VGA_CKSEL_MASK 0xc |
|---|
| 11008 | #define GENMO_RD__VGA_CKSEL__SHIFT 0x2 |
|---|
| 11009 | #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 |
|---|
| 11010 | #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
|---|
| 11011 | #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 |
|---|
| 11012 | #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 |
|---|
| 11013 | #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 |
|---|
| 11014 | #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 |
|---|
| 11015 | #define GENENB__BLK_IO_BASE_MASK 0xff |
|---|
| 11016 | #define GENENB__BLK_IO_BASE__SHIFT 0x0 |
|---|
| 11017 | #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 |
|---|
| 11018 | #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 |
|---|
| 11019 | #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 |
|---|
| 11020 | #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 |
|---|
| 11021 | #define GENS0__SENSE_SWITCH_MASK 0x10 |
|---|
| 11022 | #define GENS0__SENSE_SWITCH__SHIFT 0x4 |
|---|
| 11023 | #define GENS0__CRT_INTR_MASK 0x80 |
|---|
| 11024 | #define GENS0__CRT_INTR__SHIFT 0x7 |
|---|
| 11025 | #define GENS1__NO_DISPLAY_MASK 0x1 |
|---|
| 11026 | #define GENS1__NO_DISPLAY__SHIFT 0x0 |
|---|
| 11027 | #define GENS1__VGA_VSTATUS_MASK 0x8 |
|---|
| 11028 | #define GENS1__VGA_VSTATUS__SHIFT 0x3 |
|---|
| 11029 | #define GENS1__PIXEL_READ_BACK_MASK 0x30 |
|---|
| 11030 | #define GENS1__PIXEL_READ_BACK__SHIFT 0x4 |
|---|
| 11031 | #define DAC_DATA__DAC_DATA_MASK 0x3f |
|---|
| 11032 | #define DAC_DATA__DAC_DATA__SHIFT 0x0 |
|---|
| 11033 | #define DAC_MASK__DAC_MASK_MASK 0xff |
|---|
| 11034 | #define DAC_MASK__DAC_MASK__SHIFT 0x0 |
|---|
| 11035 | #define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff |
|---|
| 11036 | #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 |
|---|
| 11037 | #define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff |
|---|
| 11038 | #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 |
|---|
| 11039 | #define SEQ8_IDX__SEQ_IDX_MASK 0x7 |
|---|
| 11040 | #define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 |
|---|
| 11041 | #define SEQ8_DATA__SEQ_DATA_MASK 0xff |
|---|
| 11042 | #define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 |
|---|
| 11043 | #define SEQ00__SEQ_RST0B_MASK 0x1 |
|---|
| 11044 | #define SEQ00__SEQ_RST0B__SHIFT 0x0 |
|---|
| 11045 | #define SEQ00__SEQ_RST1B_MASK 0x2 |
|---|
| 11046 | #define SEQ00__SEQ_RST1B__SHIFT 0x1 |
|---|
| 11047 | #define SEQ01__SEQ_DOT8_MASK 0x1 |
|---|
| 11048 | #define SEQ01__SEQ_DOT8__SHIFT 0x0 |
|---|
| 11049 | #define SEQ01__SEQ_SHIFT2_MASK 0x4 |
|---|
| 11050 | #define SEQ01__SEQ_SHIFT2__SHIFT 0x2 |
|---|
| 11051 | #define SEQ01__SEQ_PCLKBY2_MASK 0x8 |
|---|
| 11052 | #define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 |
|---|
| 11053 | #define SEQ01__SEQ_SHIFT4_MASK 0x10 |
|---|
| 11054 | #define SEQ01__SEQ_SHIFT4__SHIFT 0x4 |
|---|
| 11055 | #define SEQ01__SEQ_MAXBW_MASK 0x20 |
|---|
| 11056 | #define SEQ01__SEQ_MAXBW__SHIFT 0x5 |
|---|
| 11057 | #define SEQ02__SEQ_MAP0_EN_MASK 0x1 |
|---|
| 11058 | #define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 |
|---|
| 11059 | #define SEQ02__SEQ_MAP1_EN_MASK 0x2 |
|---|
| 11060 | #define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 |
|---|
| 11061 | #define SEQ02__SEQ_MAP2_EN_MASK 0x4 |
|---|
| 11062 | #define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 |
|---|
| 11063 | #define SEQ02__SEQ_MAP3_EN_MASK 0x8 |
|---|
| 11064 | #define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 |
|---|
| 11065 | #define SEQ03__SEQ_FONT_B1_MASK 0x1 |
|---|
| 11066 | #define SEQ03__SEQ_FONT_B1__SHIFT 0x0 |
|---|
| 11067 | #define SEQ03__SEQ_FONT_B2_MASK 0x2 |
|---|
| 11068 | #define SEQ03__SEQ_FONT_B2__SHIFT 0x1 |
|---|
| 11069 | #define SEQ03__SEQ_FONT_A1_MASK 0x4 |
|---|
| 11070 | #define SEQ03__SEQ_FONT_A1__SHIFT 0x2 |
|---|
| 11071 | #define SEQ03__SEQ_FONT_A2_MASK 0x8 |
|---|
| 11072 | #define SEQ03__SEQ_FONT_A2__SHIFT 0x3 |
|---|
| 11073 | #define SEQ03__SEQ_FONT_B0_MASK 0x10 |
|---|
| 11074 | #define SEQ03__SEQ_FONT_B0__SHIFT 0x4 |
|---|
| 11075 | #define SEQ03__SEQ_FONT_A0_MASK 0x20 |
|---|
| 11076 | #define SEQ03__SEQ_FONT_A0__SHIFT 0x5 |
|---|
| 11077 | #define SEQ04__SEQ_256K_MASK 0x2 |
|---|
| 11078 | #define SEQ04__SEQ_256K__SHIFT 0x1 |
|---|
| 11079 | #define SEQ04__SEQ_ODDEVEN_MASK 0x4 |
|---|
| 11080 | #define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 |
|---|
| 11081 | #define SEQ04__SEQ_CHAIN_MASK 0x8 |
|---|
| 11082 | #define SEQ04__SEQ_CHAIN__SHIFT 0x3 |
|---|
| 11083 | #define CRTC8_IDX__VCRTC_IDX_MASK 0x3f |
|---|
| 11084 | #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 |
|---|
| 11085 | #define CRTC8_DATA__VCRTC_DATA_MASK 0xff |
|---|
| 11086 | #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 |
|---|
| 11087 | #define CRT00__H_TOTAL_MASK 0xff |
|---|
| 11088 | #define CRT00__H_TOTAL__SHIFT 0x0 |
|---|
| 11089 | #define CRT01__H_DISP_END_MASK 0xff |
|---|
| 11090 | #define CRT01__H_DISP_END__SHIFT 0x0 |
|---|
| 11091 | #define CRT02__H_BLANK_START_MASK 0xff |
|---|
| 11092 | #define CRT02__H_BLANK_START__SHIFT 0x0 |
|---|
| 11093 | #define CRT03__H_BLANK_END_MASK 0x1f |
|---|
| 11094 | #define CRT03__H_BLANK_END__SHIFT 0x0 |
|---|
| 11095 | #define CRT03__H_DE_SKEW_MASK 0x60 |
|---|
| 11096 | #define CRT03__H_DE_SKEW__SHIFT 0x5 |
|---|
| 11097 | #define CRT03__CR10CR11_R_DIS_B_MASK 0x80 |
|---|
| 11098 | #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 |
|---|
| 11099 | #define CRT04__H_SYNC_START_MASK 0xff |
|---|
| 11100 | #define CRT04__H_SYNC_START__SHIFT 0x0 |
|---|
| 11101 | #define CRT05__H_SYNC_END_MASK 0x1f |
|---|
| 11102 | #define CRT05__H_SYNC_END__SHIFT 0x0 |
|---|
| 11103 | #define CRT05__H_SYNC_SKEW_MASK 0x60 |
|---|
| 11104 | #define CRT05__H_SYNC_SKEW__SHIFT 0x5 |
|---|
| 11105 | #define CRT05__H_BLANK_END_B5_MASK 0x80 |
|---|
| 11106 | #define CRT05__H_BLANK_END_B5__SHIFT 0x7 |
|---|
| 11107 | #define CRT06__V_TOTAL_MASK 0xff |
|---|
| 11108 | #define CRT06__V_TOTAL__SHIFT 0x0 |
|---|
| 11109 | #define CRT07__V_TOTAL_B8_MASK 0x1 |
|---|
| 11110 | #define CRT07__V_TOTAL_B8__SHIFT 0x0 |
|---|
| 11111 | #define CRT07__V_DISP_END_B8_MASK 0x2 |
|---|
| 11112 | #define CRT07__V_DISP_END_B8__SHIFT 0x1 |
|---|
| 11113 | #define CRT07__V_SYNC_START_B8_MASK 0x4 |
|---|
| 11114 | #define CRT07__V_SYNC_START_B8__SHIFT 0x2 |
|---|
| 11115 | #define CRT07__V_BLANK_START_B8_MASK 0x8 |
|---|
| 11116 | #define CRT07__V_BLANK_START_B8__SHIFT 0x3 |
|---|
| 11117 | #define CRT07__LINE_CMP_B8_MASK 0x10 |
|---|
| 11118 | #define CRT07__LINE_CMP_B8__SHIFT 0x4 |
|---|
| 11119 | #define CRT07__V_TOTAL_B9_MASK 0x20 |
|---|
| 11120 | #define CRT07__V_TOTAL_B9__SHIFT 0x5 |
|---|
| 11121 | #define CRT07__V_DISP_END_B9_MASK 0x40 |
|---|
| 11122 | #define CRT07__V_DISP_END_B9__SHIFT 0x6 |
|---|
| 11123 | #define CRT07__V_SYNC_START_B9_MASK 0x80 |
|---|
| 11124 | #define CRT07__V_SYNC_START_B9__SHIFT 0x7 |
|---|
| 11125 | #define CRT08__ROW_SCAN_START_MASK 0x1f |
|---|
| 11126 | #define CRT08__ROW_SCAN_START__SHIFT 0x0 |
|---|
| 11127 | #define CRT08__BYTE_PAN_MASK 0x60 |
|---|
| 11128 | #define CRT08__BYTE_PAN__SHIFT 0x5 |
|---|
| 11129 | #define CRT09__MAX_ROW_SCAN_MASK 0x1f |
|---|
| 11130 | #define CRT09__MAX_ROW_SCAN__SHIFT 0x0 |
|---|
| 11131 | #define CRT09__V_BLANK_START_B9_MASK 0x20 |
|---|
| 11132 | #define CRT09__V_BLANK_START_B9__SHIFT 0x5 |
|---|
| 11133 | #define CRT09__LINE_CMP_B9_MASK 0x40 |
|---|
| 11134 | #define CRT09__LINE_CMP_B9__SHIFT 0x6 |
|---|
| 11135 | #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 |
|---|
| 11136 | #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 |
|---|
| 11137 | #define CRT0A__CURSOR_START_MASK 0x1f |
|---|
| 11138 | #define CRT0A__CURSOR_START__SHIFT 0x0 |
|---|
| 11139 | #define CRT0A__CURSOR_DISABLE_MASK 0x20 |
|---|
| 11140 | #define CRT0A__CURSOR_DISABLE__SHIFT 0x5 |
|---|
| 11141 | #define CRT0B__CURSOR_END_MASK 0x1f |
|---|
| 11142 | #define CRT0B__CURSOR_END__SHIFT 0x0 |
|---|
| 11143 | #define CRT0B__CURSOR_SKEW_MASK 0x60 |
|---|
| 11144 | #define CRT0B__CURSOR_SKEW__SHIFT 0x5 |
|---|
| 11145 | #define CRT0C__DISP_START_MASK 0xff |
|---|
| 11146 | #define CRT0C__DISP_START__SHIFT 0x0 |
|---|
| 11147 | #define CRT0D__DISP_START_MASK 0xff |
|---|
| 11148 | #define CRT0D__DISP_START__SHIFT 0x0 |
|---|
| 11149 | #define CRT0E__CURSOR_LOC_HI_MASK 0xff |
|---|
| 11150 | #define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 |
|---|
| 11151 | #define CRT0F__CURSOR_LOC_LO_MASK 0xff |
|---|
| 11152 | #define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 |
|---|
| 11153 | #define CRT10__V_SYNC_START_MASK 0xff |
|---|
| 11154 | #define CRT10__V_SYNC_START__SHIFT 0x0 |
|---|
| 11155 | #define CRT11__V_SYNC_END_MASK 0xf |
|---|
| 11156 | #define CRT11__V_SYNC_END__SHIFT 0x0 |
|---|
| 11157 | #define CRT11__V_INTR_CLR_MASK 0x10 |
|---|
| 11158 | #define CRT11__V_INTR_CLR__SHIFT 0x4 |
|---|
| 11159 | #define CRT11__V_INTR_EN_MASK 0x20 |
|---|
| 11160 | #define CRT11__V_INTR_EN__SHIFT 0x5 |
|---|
| 11161 | #define CRT11__SEL5_REFRESH_CYC_MASK 0x40 |
|---|
| 11162 | #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 |
|---|
| 11163 | #define CRT11__C0T7_WR_ONLY_MASK 0x80 |
|---|
| 11164 | #define CRT11__C0T7_WR_ONLY__SHIFT 0x7 |
|---|
| 11165 | #define CRT12__V_DISP_END_MASK 0xff |
|---|
| 11166 | #define CRT12__V_DISP_END__SHIFT 0x0 |
|---|
| 11167 | #define CRT13__DISP_PITCH_MASK 0xff |
|---|
| 11168 | #define CRT13__DISP_PITCH__SHIFT 0x0 |
|---|
| 11169 | #define CRT14__UNDRLN_LOC_MASK 0x1f |
|---|
| 11170 | #define CRT14__UNDRLN_LOC__SHIFT 0x0 |
|---|
| 11171 | #define CRT14__ADDR_CNT_BY4_MASK 0x20 |
|---|
| 11172 | #define CRT14__ADDR_CNT_BY4__SHIFT 0x5 |
|---|
| 11173 | #define CRT14__DOUBLE_WORD_MASK 0x40 |
|---|
| 11174 | #define CRT14__DOUBLE_WORD__SHIFT 0x6 |
|---|
| 11175 | #define CRT15__V_BLANK_START_MASK 0xff |
|---|
| 11176 | #define CRT15__V_BLANK_START__SHIFT 0x0 |
|---|
| 11177 | #define CRT16__V_BLANK_END_MASK 0xff |
|---|
| 11178 | #define CRT16__V_BLANK_END__SHIFT 0x0 |
|---|
| 11179 | #define CRT17__RA0_AS_A13B_MASK 0x1 |
|---|
| 11180 | #define CRT17__RA0_AS_A13B__SHIFT 0x0 |
|---|
| 11181 | #define CRT17__RA1_AS_A14B_MASK 0x2 |
|---|
| 11182 | #define CRT17__RA1_AS_A14B__SHIFT 0x1 |
|---|
| 11183 | #define CRT17__VCOUNT_BY2_MASK 0x4 |
|---|
| 11184 | #define CRT17__VCOUNT_BY2__SHIFT 0x2 |
|---|
| 11185 | #define CRT17__ADDR_CNT_BY2_MASK 0x8 |
|---|
| 11186 | #define CRT17__ADDR_CNT_BY2__SHIFT 0x3 |
|---|
| 11187 | #define CRT17__WRAP_A15TOA0_MASK 0x20 |
|---|
| 11188 | #define CRT17__WRAP_A15TOA0__SHIFT 0x5 |
|---|
| 11189 | #define CRT17__BYTE_MODE_MASK 0x40 |
|---|
| 11190 | #define CRT17__BYTE_MODE__SHIFT 0x6 |
|---|
| 11191 | #define CRT17__CRTC_SYNC_EN_MASK 0x80 |
|---|
| 11192 | #define CRT17__CRTC_SYNC_EN__SHIFT 0x7 |
|---|
| 11193 | #define CRT18__LINE_CMP_MASK 0xff |
|---|
| 11194 | #define CRT18__LINE_CMP__SHIFT 0x0 |
|---|
| 11195 | #define CRT1E__GRPH_DEC_RD1_MASK 0x2 |
|---|
| 11196 | #define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 |
|---|
| 11197 | #define CRT1F__GRPH_DEC_RD0_MASK 0xff |
|---|
| 11198 | #define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 |
|---|
| 11199 | #define CRT22__GRPH_LATCH_DATA_MASK 0xff |
|---|
| 11200 | #define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 |
|---|
| 11201 | #define GRPH8_IDX__GRPH_IDX_MASK 0xf |
|---|
| 11202 | #define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 |
|---|
| 11203 | #define GRPH8_DATA__GRPH_DATA_MASK 0xff |
|---|
| 11204 | #define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 |
|---|
| 11205 | #define GRA00__GRPH_SET_RESET0_MASK 0x1 |
|---|
| 11206 | #define GRA00__GRPH_SET_RESET0__SHIFT 0x0 |
|---|
| 11207 | #define GRA00__GRPH_SET_RESET1_MASK 0x2 |
|---|
| 11208 | #define GRA00__GRPH_SET_RESET1__SHIFT 0x1 |
|---|
| 11209 | #define GRA00__GRPH_SET_RESET2_MASK 0x4 |
|---|
| 11210 | #define GRA00__GRPH_SET_RESET2__SHIFT 0x2 |
|---|
| 11211 | #define GRA00__GRPH_SET_RESET3_MASK 0x8 |
|---|
| 11212 | #define GRA00__GRPH_SET_RESET3__SHIFT 0x3 |
|---|
| 11213 | #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 |
|---|
| 11214 | #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 |
|---|
| 11215 | #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 |
|---|
| 11216 | #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 |
|---|
| 11217 | #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 |
|---|
| 11218 | #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 |
|---|
| 11219 | #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 |
|---|
| 11220 | #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 |
|---|
| 11221 | #define GRA02__GRPH_CCOMP_MASK 0xf |
|---|
| 11222 | #define GRA02__GRPH_CCOMP__SHIFT 0x0 |
|---|
| 11223 | #define GRA03__GRPH_ROTATE_MASK 0x7 |
|---|
| 11224 | #define GRA03__GRPH_ROTATE__SHIFT 0x0 |
|---|
| 11225 | #define GRA03__GRPH_FN_SEL_MASK 0x18 |
|---|
| 11226 | #define GRA03__GRPH_FN_SEL__SHIFT 0x3 |
|---|
| 11227 | #define GRA04__GRPH_RMAP_MASK 0x3 |
|---|
| 11228 | #define GRA04__GRPH_RMAP__SHIFT 0x0 |
|---|
| 11229 | #define GRA05__GRPH_WRITE_MODE_MASK 0x3 |
|---|
| 11230 | #define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 |
|---|
| 11231 | #define GRA05__GRPH_READ1_MASK 0x8 |
|---|
| 11232 | #define GRA05__GRPH_READ1__SHIFT 0x3 |
|---|
| 11233 | #define GRA05__CGA_ODDEVEN_MASK 0x10 |
|---|
| 11234 | #define GRA05__CGA_ODDEVEN__SHIFT 0x4 |
|---|
| 11235 | #define GRA05__GRPH_OES_MASK 0x20 |
|---|
| 11236 | #define GRA05__GRPH_OES__SHIFT 0x5 |
|---|
| 11237 | #define GRA05__GRPH_PACK_MASK 0x40 |
|---|
| 11238 | #define GRA05__GRPH_PACK__SHIFT 0x6 |
|---|
| 11239 | #define GRA06__GRPH_GRAPHICS_MASK 0x1 |
|---|
| 11240 | #define GRA06__GRPH_GRAPHICS__SHIFT 0x0 |
|---|
| 11241 | #define GRA06__GRPH_ODDEVEN_MASK 0x2 |
|---|
| 11242 | #define GRA06__GRPH_ODDEVEN__SHIFT 0x1 |
|---|
| 11243 | #define GRA06__GRPH_ADRSEL_MASK 0xc |
|---|
| 11244 | #define GRA06__GRPH_ADRSEL__SHIFT 0x2 |
|---|
| 11245 | #define GRA07__GRPH_XCARE0_MASK 0x1 |
|---|
| 11246 | #define GRA07__GRPH_XCARE0__SHIFT 0x0 |
|---|
| 11247 | #define GRA07__GRPH_XCARE1_MASK 0x2 |
|---|
| 11248 | #define GRA07__GRPH_XCARE1__SHIFT 0x1 |
|---|
| 11249 | #define GRA07__GRPH_XCARE2_MASK 0x4 |
|---|
| 11250 | #define GRA07__GRPH_XCARE2__SHIFT 0x2 |
|---|
| 11251 | #define GRA07__GRPH_XCARE3_MASK 0x8 |
|---|
| 11252 | #define GRA07__GRPH_XCARE3__SHIFT 0x3 |
|---|
| 11253 | #define GRA08__GRPH_BMSK_MASK 0xff |
|---|
| 11254 | #define GRA08__GRPH_BMSK__SHIFT 0x0 |
|---|
| 11255 | #define ATTRX__ATTR_IDX_MASK 0x1f |
|---|
| 11256 | #define ATTRX__ATTR_IDX__SHIFT 0x0 |
|---|
| 11257 | #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 |
|---|
| 11258 | #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 |
|---|
| 11259 | #define ATTRDW__ATTR_DATA_MASK 0xff |
|---|
| 11260 | #define ATTRDW__ATTR_DATA__SHIFT 0x0 |
|---|
| 11261 | #define ATTRDR__ATTR_DATA_MASK 0xff |
|---|
| 11262 | #define ATTRDR__ATTR_DATA__SHIFT 0x0 |
|---|
| 11263 | #define ATTR00__ATTR_PAL_MASK 0x3f |
|---|
| 11264 | #define ATTR00__ATTR_PAL__SHIFT 0x0 |
|---|
| 11265 | #define ATTR01__ATTR_PAL_MASK 0x3f |
|---|
| 11266 | #define ATTR01__ATTR_PAL__SHIFT 0x0 |
|---|
| 11267 | #define ATTR02__ATTR_PAL_MASK 0x3f |
|---|
| 11268 | #define ATTR02__ATTR_PAL__SHIFT 0x0 |
|---|
| 11269 | #define ATTR03__ATTR_PAL_MASK 0x3f |
|---|
| 11270 | #define ATTR03__ATTR_PAL__SHIFT 0x0 |
|---|
| 11271 | #define ATTR04__ATTR_PAL_MASK 0x3f |
|---|
| 11272 | #define ATTR04__ATTR_PAL__SHIFT 0x0 |
|---|
| 11273 | #define ATTR05__ATTR_PAL_MASK 0x3f |
|---|
| 11274 | #define ATTR05__ATTR_PAL__SHIFT 0x0 |
|---|
| 11275 | #define ATTR06__ATTR_PAL_MASK 0x3f |
|---|
| 11276 | #define ATTR06__ATTR_PAL__SHIFT 0x0 |
|---|
| 11277 | #define ATTR07__ATTR_PAL_MASK 0x3f |
|---|
| 11278 | #define ATTR07__ATTR_PAL__SHIFT 0x0 |
|---|
| 11279 | #define ATTR08__ATTR_PAL_MASK 0x3f |
|---|
| 11280 | #define ATTR08__ATTR_PAL__SHIFT 0x0 |
|---|
| 11281 | #define ATTR09__ATTR_PAL_MASK 0x3f |
|---|
| 11282 | #define ATTR09__ATTR_PAL__SHIFT 0x0 |
|---|
| 11283 | #define ATTR0A__ATTR_PAL_MASK 0x3f |
|---|
| 11284 | #define ATTR0A__ATTR_PAL__SHIFT 0x0 |
|---|
| 11285 | #define ATTR0B__ATTR_PAL_MASK 0x3f |
|---|
| 11286 | #define ATTR0B__ATTR_PAL__SHIFT 0x0 |
|---|
| 11287 | #define ATTR0C__ATTR_PAL_MASK 0x3f |
|---|
| 11288 | #define ATTR0C__ATTR_PAL__SHIFT 0x0 |
|---|
| 11289 | #define ATTR0D__ATTR_PAL_MASK 0x3f |
|---|
| 11290 | #define ATTR0D__ATTR_PAL__SHIFT 0x0 |
|---|
| 11291 | #define ATTR0E__ATTR_PAL_MASK 0x3f |
|---|
| 11292 | #define ATTR0E__ATTR_PAL__SHIFT 0x0 |
|---|
| 11293 | #define ATTR0F__ATTR_PAL_MASK 0x3f |
|---|
| 11294 | #define ATTR0F__ATTR_PAL__SHIFT 0x0 |
|---|
| 11295 | #define ATTR10__ATTR_GRPH_MODE_MASK 0x1 |
|---|
| 11296 | #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 |
|---|
| 11297 | #define ATTR10__ATTR_MONO_EN_MASK 0x2 |
|---|
| 11298 | #define ATTR10__ATTR_MONO_EN__SHIFT 0x1 |
|---|
| 11299 | #define ATTR10__ATTR_LGRPH_EN_MASK 0x4 |
|---|
| 11300 | #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 |
|---|
| 11301 | #define ATTR10__ATTR_BLINK_EN_MASK 0x8 |
|---|
| 11302 | #define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 |
|---|
| 11303 | #define ATTR10__ATTR_PANTOPONLY_MASK 0x20 |
|---|
| 11304 | #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 |
|---|
| 11305 | #define ATTR10__ATTR_PCLKBY2_MASK 0x40 |
|---|
| 11306 | #define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 |
|---|
| 11307 | #define ATTR10__ATTR_CSEL_EN_MASK 0x80 |
|---|
| 11308 | #define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 |
|---|
| 11309 | #define ATTR11__ATTR_OVSC_MASK 0xff |
|---|
| 11310 | #define ATTR11__ATTR_OVSC__SHIFT 0x0 |
|---|
| 11311 | #define ATTR12__ATTR_MAP_EN_MASK 0xf |
|---|
| 11312 | #define ATTR12__ATTR_MAP_EN__SHIFT 0x0 |
|---|
| 11313 | #define ATTR12__ATTR_VSMUX_MASK 0x30 |
|---|
| 11314 | #define ATTR12__ATTR_VSMUX__SHIFT 0x4 |
|---|
| 11315 | #define ATTR13__ATTR_PPAN_MASK 0xf |
|---|
| 11316 | #define ATTR13__ATTR_PPAN__SHIFT 0x0 |
|---|
| 11317 | #define ATTR14__ATTR_CSEL1_MASK 0x3 |
|---|
| 11318 | #define ATTR14__ATTR_CSEL1__SHIFT 0x0 |
|---|
| 11319 | #define ATTR14__ATTR_CSEL2_MASK 0xc |
|---|
| 11320 | #define ATTR14__ATTR_CSEL2__SHIFT 0x2 |
|---|
| 11321 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f |
|---|
| 11322 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 |
|---|
| 11323 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 |
|---|
| 11324 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 |
|---|
| 11325 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 |
|---|
| 11326 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 |
|---|
| 11327 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 |
|---|
| 11328 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 |
|---|
| 11329 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 |
|---|
| 11330 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 |
|---|
| 11331 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 |
|---|
| 11332 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 |
|---|
| 11333 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 |
|---|
| 11334 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 |
|---|
| 11335 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 |
|---|
| 11336 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 |
|---|
| 11337 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 |
|---|
| 11338 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 |
|---|
| 11339 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 |
|---|
| 11340 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 |
|---|
| 11341 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 |
|---|
| 11342 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 |
|---|
| 11343 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 |
|---|
| 11344 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 |
|---|
| 11345 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 |
|---|
| 11346 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 |
|---|
| 11347 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 |
|---|
| 11348 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 |
|---|
| 11349 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 |
|---|
| 11350 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 |
|---|
| 11351 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 |
|---|
| 11352 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 |
|---|
| 11353 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 |
|---|
| 11354 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 |
|---|
| 11355 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 |
|---|
| 11356 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa |
|---|
| 11357 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 |
|---|
| 11358 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb |
|---|
| 11359 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 |
|---|
| 11360 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc |
|---|
| 11361 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 |
|---|
| 11362 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd |
|---|
| 11363 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 |
|---|
| 11364 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 |
|---|
| 11365 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 |
|---|
| 11366 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 |
|---|
| 11367 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 |
|---|
| 11368 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 |
|---|
| 11369 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 |
|---|
| 11370 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 |
|---|
| 11371 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 |
|---|
| 11372 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 |
|---|
| 11373 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 |
|---|
| 11374 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 |
|---|
| 11375 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 |
|---|
| 11376 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 |
|---|
| 11377 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 |
|---|
| 11378 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 |
|---|
| 11379 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 |
|---|
| 11380 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 |
|---|
| 11381 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff |
|---|
| 11382 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 |
|---|
| 11383 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff |
|---|
| 11384 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 11385 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff |
|---|
| 11386 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 |
|---|
| 11387 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff |
|---|
| 11388 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 |
|---|
| 11389 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 |
|---|
| 11390 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 |
|---|
| 11391 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 |
|---|
| 11392 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 |
|---|
| 11393 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 |
|---|
| 11394 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 |
|---|
| 11395 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 |
|---|
| 11396 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 |
|---|
| 11397 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 |
|---|
| 11398 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 |
|---|
| 11399 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 |
|---|
| 11400 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 |
|---|
| 11401 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 |
|---|
| 11402 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 |
|---|
| 11403 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 |
|---|
| 11404 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 |
|---|
| 11405 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 |
|---|
| 11406 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 |
|---|
| 11407 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 |
|---|
| 11408 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 |
|---|
| 11409 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11410 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11411 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11412 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11413 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11414 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11415 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11416 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11417 | #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 |
|---|
| 11418 | #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 |
|---|
| 11419 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11420 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11421 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11422 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11423 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11424 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11425 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11426 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11427 | #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 |
|---|
| 11428 | #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 |
|---|
| 11429 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11430 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11431 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11432 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11433 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11434 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11435 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11436 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11437 | #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 |
|---|
| 11438 | #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 |
|---|
| 11439 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11440 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11441 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11442 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11443 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11444 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11445 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11446 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11447 | #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 |
|---|
| 11448 | #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 |
|---|
| 11449 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11450 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11451 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11452 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11453 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11454 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11455 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11456 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11457 | #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 |
|---|
| 11458 | #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 |
|---|
| 11459 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 |
|---|
| 11460 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 |
|---|
| 11461 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 |
|---|
| 11462 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 |
|---|
| 11463 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
|---|
| 11464 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
|---|
| 11465 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
|---|
| 11466 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
|---|
| 11467 | #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 |
|---|
| 11468 | #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 |
|---|
| 11469 | #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff |
|---|
| 11470 | #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 |
|---|
| 11471 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 |
|---|
| 11472 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 |
|---|
| 11473 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 |
|---|
| 11474 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 11475 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 |
|---|
| 11476 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 |
|---|
| 11477 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 |
|---|
| 11478 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 |
|---|
| 11479 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 |
|---|
| 11480 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 |
|---|
| 11481 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 |
|---|
| 11482 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 |
|---|
| 11483 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 |
|---|
| 11484 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 |
|---|
| 11485 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 |
|---|
| 11486 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 |
|---|
| 11487 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 |
|---|
| 11488 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 |
|---|
| 11489 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 |
|---|
| 11490 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 |
|---|
| 11491 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 |
|---|
| 11492 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 |
|---|
| 11493 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 |
|---|
| 11494 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 |
|---|
| 11495 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 |
|---|
| 11496 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 |
|---|
| 11497 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 |
|---|
| 11498 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 |
|---|
| 11499 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 |
|---|
| 11500 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 |
|---|
| 11501 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 |
|---|
| 11502 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 |
|---|
| 11503 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 |
|---|
| 11504 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 |
|---|
| 11505 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 |
|---|
| 11506 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 |
|---|
| 11507 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 |
|---|
| 11508 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 |
|---|
| 11509 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 |
|---|
| 11510 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 |
|---|
| 11511 | #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000 |
|---|
| 11512 | #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc |
|---|
| 11513 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 |
|---|
| 11514 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 |
|---|
| 11515 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 |
|---|
| 11516 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 |
|---|
| 11517 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 |
|---|
| 11518 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a |
|---|
| 11519 | #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 |
|---|
| 11520 | #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b |
|---|
| 11521 | #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 |
|---|
| 11522 | #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c |
|---|
| 11523 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 |
|---|
| 11524 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d |
|---|
| 11525 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 |
|---|
| 11526 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f |
|---|
| 11527 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 |
|---|
| 11528 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 |
|---|
| 11529 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 |
|---|
| 11530 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 |
|---|
| 11531 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 |
|---|
| 11532 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 |
|---|
| 11533 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 |
|---|
| 11534 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 |
|---|
| 11535 | #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff |
|---|
| 11536 | #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 |
|---|
| 11537 | #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff |
|---|
| 11538 | #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 |
|---|
| 11539 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff |
|---|
| 11540 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 |
|---|
| 11541 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 |
|---|
| 11542 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 |
|---|
| 11543 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff |
|---|
| 11544 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 |
|---|
| 11545 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 |
|---|
| 11546 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 |
|---|
| 11547 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 11548 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 11549 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 11550 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 11551 | #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 11552 | #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 11553 | #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff |
|---|
| 11554 | #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 |
|---|
| 11555 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 |
|---|
| 11556 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 |
|---|
| 11557 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 |
|---|
| 11558 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 |
|---|
| 11559 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 |
|---|
| 11560 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 |
|---|
| 11561 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 |
|---|
| 11562 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 |
|---|
| 11563 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 |
|---|
| 11564 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c |
|---|
| 11565 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 |
|---|
| 11566 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 |
|---|
| 11567 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 |
|---|
| 11568 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 |
|---|
| 11569 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 |
|---|
| 11570 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 |
|---|
| 11571 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 |
|---|
| 11572 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 |
|---|
| 11573 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 |
|---|
| 11574 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 |
|---|
| 11575 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 |
|---|
| 11576 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c |
|---|
| 11577 | #define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff |
|---|
| 11578 | #define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 |
|---|
| 11579 | #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 |
|---|
| 11580 | #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc |
|---|
| 11581 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf |
|---|
| 11582 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 |
|---|
| 11583 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
|---|
| 11584 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
|---|
| 11585 | #define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 |
|---|
| 11586 | #define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 |
|---|
| 11587 | #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f |
|---|
| 11588 | #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 |
|---|
| 11589 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 |
|---|
| 11590 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 |
|---|
| 11591 | #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 |
|---|
| 11592 | #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 |
|---|
| 11593 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 |
|---|
| 11594 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf |
|---|
| 11595 | #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 |
|---|
| 11596 | #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 |
|---|
| 11597 | #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff |
|---|
| 11598 | #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 |
|---|
| 11599 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff |
|---|
| 11600 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 |
|---|
| 11601 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 |
|---|
| 11602 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 |
|---|
| 11603 | #define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 |
|---|
| 11604 | #define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc |
|---|
| 11605 | #define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 |
|---|
| 11606 | #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd |
|---|
| 11607 | #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 |
|---|
| 11608 | #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 |
|---|
| 11609 | #define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff |
|---|
| 11610 | #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 |
|---|
| 11611 | #define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 |
|---|
| 11612 | #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 |
|---|
| 11613 | #define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 |
|---|
| 11614 | #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 |
|---|
| 11615 | #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 |
|---|
| 11616 | #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 |
|---|
| 11617 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 |
|---|
| 11618 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 |
|---|
| 11619 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 |
|---|
| 11620 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 |
|---|
| 11621 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 |
|---|
| 11622 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 |
|---|
| 11623 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 |
|---|
| 11624 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 |
|---|
| 11625 | #define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10 |
|---|
| 11626 | #define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4 |
|---|
| 11627 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 |
|---|
| 11628 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 |
|---|
| 11629 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 |
|---|
| 11630 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc |
|---|
| 11631 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 |
|---|
| 11632 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 |
|---|
| 11633 | #define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 |
|---|
| 11634 | #define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 |
|---|
| 11635 | #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 |
|---|
| 11636 | #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 |
|---|
| 11637 | #define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 |
|---|
| 11638 | #define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 |
|---|
| 11639 | #define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000 |
|---|
| 11640 | #define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a |
|---|
| 11641 | #define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000 |
|---|
| 11642 | #define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c |
|---|
| 11643 | #define PLL_CNTL__PLL_RESET_MASK 0x1 |
|---|
| 11644 | #define PLL_CNTL__PLL_RESET__SHIFT 0x0 |
|---|
| 11645 | #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 |
|---|
| 11646 | #define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 |
|---|
| 11647 | #define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 |
|---|
| 11648 | #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 |
|---|
| 11649 | #define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 |
|---|
| 11650 | #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 |
|---|
| 11651 | #define PLL_CNTL__PLL_VCOREF_MASK 0x30 |
|---|
| 11652 | #define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 |
|---|
| 11653 | #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 |
|---|
| 11654 | #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 |
|---|
| 11655 | #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 |
|---|
| 11656 | #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 |
|---|
| 11657 | #define PLL_CNTL__PLL_CALREF_MASK 0x300 |
|---|
| 11658 | #define PLL_CNTL__PLL_CALREF__SHIFT 0x8 |
|---|
| 11659 | #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 |
|---|
| 11660 | #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa |
|---|
| 11661 | #define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 |
|---|
| 11662 | #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb |
|---|
| 11663 | #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 |
|---|
| 11664 | #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd |
|---|
| 11665 | #define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 |
|---|
| 11666 | #define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe |
|---|
| 11667 | #define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 |
|---|
| 11668 | #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 |
|---|
| 11669 | #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 |
|---|
| 11670 | #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 |
|---|
| 11671 | #define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 |
|---|
| 11672 | #define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 |
|---|
| 11673 | #define PLL_CNTL__PLL_LOCKED_MASK 0x200000 |
|---|
| 11674 | #define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 |
|---|
| 11675 | #define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000 |
|---|
| 11676 | #define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16 |
|---|
| 11677 | #define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000 |
|---|
| 11678 | #define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17 |
|---|
| 11679 | #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 |
|---|
| 11680 | #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 |
|---|
| 11681 | #define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 |
|---|
| 11682 | #define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a |
|---|
| 11683 | #define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f |
|---|
| 11684 | #define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 |
|---|
| 11685 | #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 |
|---|
| 11686 | #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 |
|---|
| 11687 | #define PLL_ANALOG__PLL_CP_MASK 0xf00 |
|---|
| 11688 | #define PLL_ANALOG__PLL_CP__SHIFT 0x8 |
|---|
| 11689 | #define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 |
|---|
| 11690 | #define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc |
|---|
| 11691 | #define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 |
|---|
| 11692 | #define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 |
|---|
| 11693 | #define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 |
|---|
| 11694 | #define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 |
|---|
| 11695 | #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff |
|---|
| 11696 | #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 |
|---|
| 11697 | #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 |
|---|
| 11698 | #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 |
|---|
| 11699 | #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 |
|---|
| 11700 | #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a |
|---|
| 11701 | #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 |
|---|
| 11702 | #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c |
|---|
| 11703 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 |
|---|
| 11704 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 |
|---|
| 11705 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 |
|---|
| 11706 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 |
|---|
| 11707 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 |
|---|
| 11708 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 |
|---|
| 11709 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 |
|---|
| 11710 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 |
|---|
| 11711 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 |
|---|
| 11712 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 |
|---|
| 11713 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 |
|---|
| 11714 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 |
|---|
| 11715 | #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 |
|---|
| 11716 | #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 |
|---|
| 11717 | #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 |
|---|
| 11718 | #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 |
|---|
| 11719 | #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 |
|---|
| 11720 | #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 |
|---|
| 11721 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 |
|---|
| 11722 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 |
|---|
| 11723 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 |
|---|
| 11724 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 |
|---|
| 11725 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 |
|---|
| 11726 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b |
|---|
| 11727 | #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 |
|---|
| 11728 | #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 11729 | #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 |
|---|
| 11730 | #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 11731 | #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 |
|---|
| 11732 | #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 |
|---|
| 11733 | #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 |
|---|
| 11734 | #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 |
|---|
| 11735 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 |
|---|
| 11736 | #define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 |
|---|
| 11737 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 |
|---|
| 11738 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 |
|---|
| 11739 | #define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 |
|---|
| 11740 | #define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 |
|---|
| 11741 | #define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000 |
|---|
| 11742 | #define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10 |
|---|
| 11743 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000 |
|---|
| 11744 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14 |
|---|
| 11745 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000 |
|---|
| 11746 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17 |
|---|
| 11747 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000 |
|---|
| 11748 | #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a |
|---|
| 11749 | #define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000 |
|---|
| 11750 | #define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c |
|---|
| 11751 | #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 |
|---|
| 11752 | #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 |
|---|
| 11753 | #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e |
|---|
| 11754 | #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 |
|---|
| 11755 | #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 |
|---|
| 11756 | #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 |
|---|
| 11757 | #define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00 |
|---|
| 11758 | #define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9 |
|---|
| 11759 | #define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000 |
|---|
| 11760 | #define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe |
|---|
| 11761 | #define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000 |
|---|
| 11762 | #define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11 |
|---|
| 11763 | #define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000 |
|---|
| 11764 | #define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12 |
|---|
| 11765 | #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff |
|---|
| 11766 | #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 |
|---|
| 11767 | #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff |
|---|
| 11768 | #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 |
|---|
| 11769 | #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff |
|---|
| 11770 | #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 |
|---|
| 11771 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf |
|---|
| 11772 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
|---|
| 11773 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
|---|
| 11774 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
|---|
| 11775 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 |
|---|
| 11776 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 |
|---|
| 11777 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf |
|---|
| 11778 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
|---|
| 11779 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
|---|
| 11780 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
|---|
| 11781 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 |
|---|
| 11782 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 |
|---|
| 11783 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf |
|---|
| 11784 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
|---|
| 11785 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
|---|
| 11786 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
|---|
| 11787 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 |
|---|
| 11788 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 |
|---|
| 11789 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
|---|
| 11790 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
|---|
| 11791 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
|---|
| 11792 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
|---|
| 11793 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
|---|
| 11794 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
|---|
| 11795 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
|---|
| 11796 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
|---|
| 11797 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
|---|
| 11798 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
|---|
| 11799 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
|---|
| 11800 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
|---|
| 11801 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
|---|
| 11802 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
|---|
| 11803 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
|---|
| 11804 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
|---|
| 11805 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
|---|
| 11806 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
|---|
| 11807 | #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f |
|---|
| 11808 | #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 |
|---|
| 11809 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 |
|---|
| 11810 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
|---|
| 11811 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 |
|---|
| 11812 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 |
|---|
| 11813 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 |
|---|
| 11814 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc |
|---|
| 11815 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 |
|---|
| 11816 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 |
|---|
| 11817 | #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f |
|---|
| 11818 | #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 |
|---|
| 11819 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 |
|---|
| 11820 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
|---|
| 11821 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 |
|---|
| 11822 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 |
|---|
| 11823 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 |
|---|
| 11824 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc |
|---|
| 11825 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 |
|---|
| 11826 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 |
|---|
| 11827 | #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f |
|---|
| 11828 | #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 |
|---|
| 11829 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 |
|---|
| 11830 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
|---|
| 11831 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 |
|---|
| 11832 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 |
|---|
| 11833 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 |
|---|
| 11834 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc |
|---|
| 11835 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 |
|---|
| 11836 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 |
|---|
| 11837 | #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 |
|---|
| 11838 | #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 |
|---|
| 11839 | #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 |
|---|
| 11840 | #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 |
|---|
| 11841 | #define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1 |
|---|
| 11842 | #define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0 |
|---|
| 11843 | #define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2 |
|---|
| 11844 | #define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1 |
|---|
| 11845 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4 |
|---|
| 11846 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2 |
|---|
| 11847 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18 |
|---|
| 11848 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3 |
|---|
| 11849 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20 |
|---|
| 11850 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5 |
|---|
| 11851 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40 |
|---|
| 11852 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6 |
|---|
| 11853 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80 |
|---|
| 11854 | #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7 |
|---|
| 11855 | #define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff |
|---|
| 11856 | #define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0 |
|---|
| 11857 | #define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000 |
|---|
| 11858 | #define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10 |
|---|
| 11859 | #define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000 |
|---|
| 11860 | #define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11 |
|---|
| 11861 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000 |
|---|
| 11862 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18 |
|---|
| 11863 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000 |
|---|
| 11864 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19 |
|---|
| 11865 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000 |
|---|
| 11866 | #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a |
|---|
| 11867 | #define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f |
|---|
| 11868 | #define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0 |
|---|
| 11869 | #define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff |
|---|
| 11870 | #define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0 |
|---|
| 11871 | #define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff |
|---|
| 11872 | #define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0 |
|---|
| 11873 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 |
|---|
| 11874 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 |
|---|
| 11875 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 |
|---|
| 11876 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 |
|---|
| 11877 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 |
|---|
| 11878 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 |
|---|
| 11879 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 |
|---|
| 11880 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc |
|---|
| 11881 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 |
|---|
| 11882 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 |
|---|
| 11883 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 |
|---|
| 11884 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 |
|---|
| 11885 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 |
|---|
| 11886 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 |
|---|
| 11887 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 |
|---|
| 11888 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 |
|---|
| 11889 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 |
|---|
| 11890 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a |
|---|
| 11891 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 |
|---|
| 11892 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c |
|---|
| 11893 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 |
|---|
| 11894 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 |
|---|
| 11895 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 |
|---|
| 11896 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 |
|---|
| 11897 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 |
|---|
| 11898 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 |
|---|
| 11899 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 |
|---|
| 11900 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc |
|---|
| 11901 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 |
|---|
| 11902 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 |
|---|
| 11903 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 |
|---|
| 11904 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 |
|---|
| 11905 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 |
|---|
| 11906 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 |
|---|
| 11907 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 |
|---|
| 11908 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 |
|---|
| 11909 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 |
|---|
| 11910 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 |
|---|
| 11911 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 |
|---|
| 11912 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b |
|---|
| 11913 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 |
|---|
| 11914 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d |
|---|
| 11915 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 |
|---|
| 11916 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 |
|---|
| 11917 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc |
|---|
| 11918 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 |
|---|
| 11919 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 |
|---|
| 11920 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 |
|---|
| 11921 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 |
|---|
| 11922 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 |
|---|
| 11923 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000 |
|---|
| 11924 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc |
|---|
| 11925 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000 |
|---|
| 11926 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 |
|---|
| 11927 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 |
|---|
| 11928 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 |
|---|
| 11929 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 |
|---|
| 11930 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 |
|---|
| 11931 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 |
|---|
| 11932 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 |
|---|
| 11933 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 |
|---|
| 11934 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 |
|---|
| 11935 | #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 |
|---|
| 11936 | #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 |
|---|
| 11937 | #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 |
|---|
| 11938 | #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f |
|---|
| 11939 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f |
|---|
| 11940 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 |
|---|
| 11941 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 |
|---|
| 11942 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 |
|---|
| 11943 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 |
|---|
| 11944 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc |
|---|
| 11945 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 |
|---|
| 11946 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 |
|---|
| 11947 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 |
|---|
| 11948 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 |
|---|
| 11949 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 |
|---|
| 11950 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c |
|---|
| 11951 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 |
|---|
| 11952 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 |
|---|
| 11953 | #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 |
|---|
| 11954 | #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 |
|---|
| 11955 | #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc |
|---|
| 11956 | #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 |
|---|
| 11957 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 |
|---|
| 11958 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 |
|---|
| 11959 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 |
|---|
| 11960 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc |
|---|
| 11961 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 |
|---|
| 11962 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 |
|---|
| 11963 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc |
|---|
| 11964 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 |
|---|
| 11965 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 |
|---|
| 11966 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 |
|---|
| 11967 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 |
|---|
| 11968 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 |
|---|
| 11969 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 |
|---|
| 11970 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 |
|---|
| 11971 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 |
|---|
| 11972 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 |
|---|
| 11973 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 |
|---|
| 11974 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 |
|---|
| 11975 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 |
|---|
| 11976 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 |
|---|
| 11977 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 |
|---|
| 11978 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 |
|---|
| 11979 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 |
|---|
| 11980 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 |
|---|
| 11981 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 |
|---|
| 11982 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 |
|---|
| 11983 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 |
|---|
| 11984 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 |
|---|
| 11985 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 |
|---|
| 11986 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a |
|---|
| 11987 | #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 |
|---|
| 11988 | #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c |
|---|
| 11989 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 |
|---|
| 11990 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 |
|---|
| 11991 | #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc |
|---|
| 11992 | #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 |
|---|
| 11993 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 |
|---|
| 11994 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 |
|---|
| 11995 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 |
|---|
| 11996 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 |
|---|
| 11997 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 |
|---|
| 11998 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 |
|---|
| 11999 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 |
|---|
| 12000 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 |
|---|
| 12001 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 |
|---|
| 12002 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb |
|---|
| 12003 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 |
|---|
| 12004 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc |
|---|
| 12005 | #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 |
|---|
| 12006 | #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd |
|---|
| 12007 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 |
|---|
| 12008 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 |
|---|
| 12009 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 |
|---|
| 12010 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 |
|---|
| 12011 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 |
|---|
| 12012 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 |
|---|
| 12013 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 |
|---|
| 12014 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 |
|---|
| 12015 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 |
|---|
| 12016 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d |
|---|
| 12017 | #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff |
|---|
| 12018 | #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 |
|---|
| 12019 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff |
|---|
| 12020 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 |
|---|
| 12021 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 |
|---|
| 12022 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc |
|---|
| 12023 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 |
|---|
| 12024 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd |
|---|
| 12025 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 |
|---|
| 12026 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 |
|---|
| 12027 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 |
|---|
| 12028 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 |
|---|
| 12029 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 |
|---|
| 12030 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 |
|---|
| 12031 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 |
|---|
| 12032 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 |
|---|
| 12033 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 |
|---|
| 12034 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 |
|---|
| 12035 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f |
|---|
| 12036 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 |
|---|
| 12037 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 |
|---|
| 12038 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 |
|---|
| 12039 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 |
|---|
| 12040 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 |
|---|
| 12041 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 |
|---|
| 12042 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa |
|---|
| 12043 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 |
|---|
| 12044 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf |
|---|
| 12045 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 |
|---|
| 12046 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 |
|---|
| 12047 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 |
|---|
| 12048 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 |
|---|
| 12049 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 |
|---|
| 12050 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 |
|---|
| 12051 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 |
|---|
| 12052 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 |
|---|
| 12053 | #define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000 |
|---|
| 12054 | #define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c |
|---|
| 12055 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 |
|---|
| 12056 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d |
|---|
| 12057 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 |
|---|
| 12058 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e |
|---|
| 12059 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 |
|---|
| 12060 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f |
|---|
| 12061 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 |
|---|
| 12062 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 |
|---|
| 12063 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 |
|---|
| 12064 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 |
|---|
| 12065 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 |
|---|
| 12066 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 |
|---|
| 12067 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 |
|---|
| 12068 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 |
|---|
| 12069 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 |
|---|
| 12070 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 |
|---|
| 12071 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 |
|---|
| 12072 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 |
|---|
| 12073 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 |
|---|
| 12074 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a |
|---|
| 12075 | #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff |
|---|
| 12076 | #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 |
|---|
| 12077 | #define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1 |
|---|
| 12078 | #define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0 |
|---|
| 12079 | #define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2 |
|---|
| 12080 | #define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1 |
|---|
| 12081 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc |
|---|
| 12082 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2 |
|---|
| 12083 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800 |
|---|
| 12084 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb |
|---|
| 12085 | #define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000 |
|---|
| 12086 | #define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14 |
|---|
| 12087 | #define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000 |
|---|
| 12088 | #define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15 |
|---|
| 12089 | #define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000 |
|---|
| 12090 | #define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16 |
|---|
| 12091 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000 |
|---|
| 12092 | #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17 |
|---|
| 12093 | #define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000 |
|---|
| 12094 | #define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18 |
|---|
| 12095 | #define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000 |
|---|
| 12096 | #define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a |
|---|
| 12097 | #define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000 |
|---|
| 12098 | #define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b |
|---|
| 12099 | #define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000 |
|---|
| 12100 | #define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f |
|---|
| 12101 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f |
|---|
| 12102 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0 |
|---|
| 12103 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0 |
|---|
| 12104 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5 |
|---|
| 12105 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00 |
|---|
| 12106 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9 |
|---|
| 12107 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000 |
|---|
| 12108 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd |
|---|
| 12109 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000 |
|---|
| 12110 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11 |
|---|
| 12111 | #define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000 |
|---|
| 12112 | #define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12 |
|---|
| 12113 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000 |
|---|
| 12114 | #define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c |
|---|
| 12115 | #define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000 |
|---|
| 12116 | #define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d |
|---|
| 12117 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1 |
|---|
| 12118 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0 |
|---|
| 12119 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2 |
|---|
| 12120 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1 |
|---|
| 12121 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c |
|---|
| 12122 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2 |
|---|
| 12123 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40 |
|---|
| 12124 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6 |
|---|
| 12125 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80 |
|---|
| 12126 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7 |
|---|
| 12127 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000 |
|---|
| 12128 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe |
|---|
| 12129 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000 |
|---|
| 12130 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10 |
|---|
| 12131 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000 |
|---|
| 12132 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11 |
|---|
| 12133 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000 |
|---|
| 12134 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12 |
|---|
| 12135 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000 |
|---|
| 12136 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16 |
|---|
| 12137 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000 |
|---|
| 12138 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17 |
|---|
| 12139 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000 |
|---|
| 12140 | #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e |
|---|
| 12141 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1 |
|---|
| 12142 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0 |
|---|
| 12143 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2 |
|---|
| 12144 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1 |
|---|
| 12145 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c |
|---|
| 12146 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2 |
|---|
| 12147 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40 |
|---|
| 12148 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6 |
|---|
| 12149 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80 |
|---|
| 12150 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7 |
|---|
| 12151 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000 |
|---|
| 12152 | #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe |
|---|
| 12153 | #define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000 |
|---|
| 12154 | #define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf |
|---|
| 12155 | #define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000 |
|---|
| 12156 | #define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14 |
|---|
| 12157 | #define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000 |
|---|
| 12158 | #define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19 |
|---|
| 12159 | #define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff |
|---|
| 12160 | #define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0 |
|---|
| 12161 | #define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000 |
|---|
| 12162 | #define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16 |
|---|
| 12163 | #define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1 |
|---|
| 12164 | #define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0 |
|---|
| 12165 | #define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2 |
|---|
| 12166 | #define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1 |
|---|
| 12167 | #define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4 |
|---|
| 12168 | #define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2 |
|---|
| 12169 | #define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8 |
|---|
| 12170 | #define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3 |
|---|
| 12171 | #define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10 |
|---|
| 12172 | #define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4 |
|---|
| 12173 | #define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20 |
|---|
| 12174 | #define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5 |
|---|
| 12175 | #define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40 |
|---|
| 12176 | #define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6 |
|---|
| 12177 | #define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80 |
|---|
| 12178 | #define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7 |
|---|
| 12179 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00 |
|---|
| 12180 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8 |
|---|
| 12181 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000 |
|---|
| 12182 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11 |
|---|
| 12183 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000 |
|---|
| 12184 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12 |
|---|
| 12185 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000 |
|---|
| 12186 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13 |
|---|
| 12187 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000 |
|---|
| 12188 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17 |
|---|
| 12189 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000 |
|---|
| 12190 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18 |
|---|
| 12191 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000 |
|---|
| 12192 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19 |
|---|
| 12193 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000 |
|---|
| 12194 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e |
|---|
| 12195 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000 |
|---|
| 12196 | #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f |
|---|
| 12197 | #define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1 |
|---|
| 12198 | #define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0 |
|---|
| 12199 | #define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2 |
|---|
| 12200 | #define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1 |
|---|
| 12201 | #define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4 |
|---|
| 12202 | #define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2 |
|---|
| 12203 | #define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78 |
|---|
| 12204 | #define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3 |
|---|
| 12205 | #define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780 |
|---|
| 12206 | #define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7 |
|---|
| 12207 | #define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800 |
|---|
| 12208 | #define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb |
|---|
| 12209 | #define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff |
|---|
| 12210 | #define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0 |
|---|
| 12211 | #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000 |
|---|
| 12212 | #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10 |
|---|
| 12213 | #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000 |
|---|
| 12214 | #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11 |
|---|
| 12215 | #define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff |
|---|
| 12216 | #define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0 |
|---|
| 12217 | #define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000 |
|---|
| 12218 | #define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc |
|---|
| 12219 | #define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000 |
|---|
| 12220 | #define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16 |
|---|
| 12221 | #define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000 |
|---|
| 12222 | #define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19 |
|---|
| 12223 | #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff |
|---|
| 12224 | #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 |
|---|
| 12225 | #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 |
|---|
| 12226 | #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 |
|---|
| 12227 | #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff |
|---|
| 12228 | #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 |
|---|
| 12229 | #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 |
|---|
| 12230 | #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 |
|---|
| 12231 | #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 |
|---|
| 12232 | #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 |
|---|
| 12233 | #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 |
|---|
| 12234 | #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 |
|---|
| 12235 | #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 |
|---|
| 12236 | #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 |
|---|
| 12237 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff |
|---|
| 12238 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 |
|---|
| 12239 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 |
|---|
| 12240 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 |
|---|
| 12241 | #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 |
|---|
| 12242 | #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 |
|---|
| 12243 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 |
|---|
| 12244 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 |
|---|
| 12245 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 |
|---|
| 12246 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 |
|---|
| 12247 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 |
|---|
| 12248 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc |
|---|
| 12249 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 |
|---|
| 12250 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 |
|---|
| 12251 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 |
|---|
| 12252 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 |
|---|
| 12253 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 |
|---|
| 12254 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 |
|---|
| 12255 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 |
|---|
| 12256 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 |
|---|
| 12257 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 |
|---|
| 12258 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 |
|---|
| 12259 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 |
|---|
| 12260 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 |
|---|
| 12261 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 |
|---|
| 12262 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 |
|---|
| 12263 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 |
|---|
| 12264 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 |
|---|
| 12265 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 |
|---|
| 12266 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa |
|---|
| 12267 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 |
|---|
| 12268 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb |
|---|
| 12269 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 |
|---|
| 12270 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 |
|---|
| 12271 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 |
|---|
| 12272 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 |
|---|
| 12273 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 |
|---|
| 12274 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 |
|---|
| 12275 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 |
|---|
| 12276 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 |
|---|
| 12277 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 |
|---|
| 12278 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 |
|---|
| 12279 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 |
|---|
| 12280 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa |
|---|
| 12281 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 |
|---|
| 12282 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 |
|---|
| 12283 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 |
|---|
| 12284 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 |
|---|
| 12285 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 |
|---|
| 12286 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 |
|---|
| 12287 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 |
|---|
| 12288 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 |
|---|
| 12289 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 |
|---|
| 12290 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 |
|---|
| 12291 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 |
|---|
| 12292 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 |
|---|
| 12293 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 |
|---|
| 12294 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 |
|---|
| 12295 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 |
|---|
| 12296 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 |
|---|
| 12297 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 |
|---|
| 12298 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa |
|---|
| 12299 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 |
|---|
| 12300 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb |
|---|
| 12301 | #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 |
|---|
| 12302 | #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 |
|---|
| 12303 | #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 |
|---|
| 12304 | #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 |
|---|
| 12305 | #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff |
|---|
| 12306 | #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 |
|---|
| 12307 | #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff |
|---|
| 12308 | #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 |
|---|
| 12309 | #define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 |
|---|
| 12310 | #define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 |
|---|
| 12311 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 12312 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 12313 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 12314 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 12315 | #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 12316 | #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 12317 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff |
|---|
| 12318 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12319 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
|---|
| 12320 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12321 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff |
|---|
| 12322 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
|---|
| 12323 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff |
|---|
| 12324 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
|---|
| 12325 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff |
|---|
| 12326 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
|---|
| 12327 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff |
|---|
| 12328 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
|---|
| 12329 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff |
|---|
| 12330 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
|---|
| 12331 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 12332 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 12333 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 12334 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 12335 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff |
|---|
| 12336 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
|---|
| 12337 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff |
|---|
| 12338 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
|---|
| 12339 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 |
|---|
| 12340 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
|---|
| 12341 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 |
|---|
| 12342 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
|---|
| 12343 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf |
|---|
| 12344 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
|---|
| 12345 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 |
|---|
| 12346 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
|---|
| 12347 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 |
|---|
| 12348 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
|---|
| 12349 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 |
|---|
| 12350 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
|---|
| 12351 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 |
|---|
| 12352 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
|---|
| 12353 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff |
|---|
| 12354 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
|---|
| 12355 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 |
|---|
| 12356 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
|---|
| 12357 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 |
|---|
| 12358 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
|---|
| 12359 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 |
|---|
| 12360 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
|---|
| 12361 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff |
|---|
| 12362 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 |
|---|
| 12363 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff |
|---|
| 12364 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 |
|---|
| 12365 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff |
|---|
| 12366 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 |
|---|
| 12367 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f |
|---|
| 12368 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
|---|
| 12369 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff |
|---|
| 12370 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
|---|
| 12371 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff |
|---|
| 12372 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
|---|
| 12373 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 |
|---|
| 12374 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 |
|---|
| 12375 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 |
|---|
| 12376 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 |
|---|
| 12377 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f |
|---|
| 12378 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 |
|---|
| 12379 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff |
|---|
| 12380 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
|---|
| 12381 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 12382 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 12383 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 12384 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 12385 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff |
|---|
| 12386 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
|---|
| 12387 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff |
|---|
| 12388 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
|---|
| 12389 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 |
|---|
| 12390 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
|---|
| 12391 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 |
|---|
| 12392 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
|---|
| 12393 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf |
|---|
| 12394 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
|---|
| 12395 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 |
|---|
| 12396 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
|---|
| 12397 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 |
|---|
| 12398 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
|---|
| 12399 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 |
|---|
| 12400 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
|---|
| 12401 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 |
|---|
| 12402 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
|---|
| 12403 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff |
|---|
| 12404 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
|---|
| 12405 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 |
|---|
| 12406 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
|---|
| 12407 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 |
|---|
| 12408 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
|---|
| 12409 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 |
|---|
| 12410 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
|---|
| 12411 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f |
|---|
| 12412 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
|---|
| 12413 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 |
|---|
| 12414 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 |
|---|
| 12415 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 |
|---|
| 12416 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
|---|
| 12417 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7 |
|---|
| 12418 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 |
|---|
| 12419 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 |
|---|
| 12420 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
|---|
| 12421 | #define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f |
|---|
| 12422 | #define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0 |
|---|
| 12423 | #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0 |
|---|
| 12424 | #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6 |
|---|
| 12425 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff |
|---|
| 12426 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 |
|---|
| 12427 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff |
|---|
| 12428 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 |
|---|
| 12429 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff |
|---|
| 12430 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 |
|---|
| 12431 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff |
|---|
| 12432 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 |
|---|
| 12433 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff |
|---|
| 12434 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 |
|---|
| 12435 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff |
|---|
| 12436 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 |
|---|
| 12437 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff |
|---|
| 12438 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 |
|---|
| 12439 | #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 |
|---|
| 12440 | #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 |
|---|
| 12441 | #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 |
|---|
| 12442 | #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
|---|
| 12443 | #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 |
|---|
| 12444 | #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 |
|---|
| 12445 | #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 |
|---|
| 12446 | #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 |
|---|
| 12447 | #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 |
|---|
| 12448 | #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc |
|---|
| 12449 | #define MINOR_VERSION__MINOR_VERSION_MASK 0xff |
|---|
| 12450 | #define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 |
|---|
| 12451 | #define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff |
|---|
| 12452 | #define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 |
|---|
| 12453 | #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
|---|
| 12454 | #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
|---|
| 12455 | #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
|---|
| 12456 | #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
|---|
| 12457 | #define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 |
|---|
| 12458 | #define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 |
|---|
| 12459 | #define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 |
|---|
| 12460 | #define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 |
|---|
| 12461 | #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 |
|---|
| 12462 | #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 |
|---|
| 12463 | #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 |
|---|
| 12464 | #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 |
|---|
| 12465 | #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 |
|---|
| 12466 | #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 |
|---|
| 12467 | #define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 |
|---|
| 12468 | #define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 |
|---|
| 12469 | #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff |
|---|
| 12470 | #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 |
|---|
| 12471 | #define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff |
|---|
| 12472 | #define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 |
|---|
| 12473 | #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 |
|---|
| 12474 | #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 |
|---|
| 12475 | #define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2 |
|---|
| 12476 | #define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 |
|---|
| 12477 | #define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4 |
|---|
| 12478 | #define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 |
|---|
| 12479 | #define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8 |
|---|
| 12480 | #define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 |
|---|
| 12481 | #define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10 |
|---|
| 12482 | #define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 |
|---|
| 12483 | #define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20 |
|---|
| 12484 | #define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 |
|---|
| 12485 | #define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40 |
|---|
| 12486 | #define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 |
|---|
| 12487 | #define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80 |
|---|
| 12488 | #define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 |
|---|
| 12489 | #define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100 |
|---|
| 12490 | #define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 |
|---|
| 12491 | #define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200 |
|---|
| 12492 | #define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 |
|---|
| 12493 | #define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400 |
|---|
| 12494 | #define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa |
|---|
| 12495 | #define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800 |
|---|
| 12496 | #define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb |
|---|
| 12497 | #define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000 |
|---|
| 12498 | #define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc |
|---|
| 12499 | #define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000 |
|---|
| 12500 | #define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd |
|---|
| 12501 | #define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000 |
|---|
| 12502 | #define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe |
|---|
| 12503 | #define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000 |
|---|
| 12504 | #define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf |
|---|
| 12505 | #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 |
|---|
| 12506 | #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e |
|---|
| 12507 | #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 |
|---|
| 12508 | #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f |
|---|
| 12509 | #define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1 |
|---|
| 12510 | #define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 |
|---|
| 12511 | #define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2 |
|---|
| 12512 | #define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 |
|---|
| 12513 | #define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4 |
|---|
| 12514 | #define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 |
|---|
| 12515 | #define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8 |
|---|
| 12516 | #define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 |
|---|
| 12517 | #define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10 |
|---|
| 12518 | #define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 |
|---|
| 12519 | #define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20 |
|---|
| 12520 | #define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 |
|---|
| 12521 | #define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40 |
|---|
| 12522 | #define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 |
|---|
| 12523 | #define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80 |
|---|
| 12524 | #define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 |
|---|
| 12525 | #define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100 |
|---|
| 12526 | #define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 |
|---|
| 12527 | #define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200 |
|---|
| 12528 | #define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 |
|---|
| 12529 | #define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400 |
|---|
| 12530 | #define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa |
|---|
| 12531 | #define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800 |
|---|
| 12532 | #define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb |
|---|
| 12533 | #define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000 |
|---|
| 12534 | #define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc |
|---|
| 12535 | #define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000 |
|---|
| 12536 | #define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd |
|---|
| 12537 | #define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000 |
|---|
| 12538 | #define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe |
|---|
| 12539 | #define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000 |
|---|
| 12540 | #define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf |
|---|
| 12541 | #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 |
|---|
| 12542 | #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e |
|---|
| 12543 | #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 |
|---|
| 12544 | #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f |
|---|
| 12545 | #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff |
|---|
| 12546 | #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 |
|---|
| 12547 | #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 |
|---|
| 12548 | #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 |
|---|
| 12549 | #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 |
|---|
| 12550 | #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 |
|---|
| 12551 | #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 |
|---|
| 12552 | #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 |
|---|
| 12553 | #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 |
|---|
| 12554 | #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 |
|---|
| 12555 | #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 |
|---|
| 12556 | #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 |
|---|
| 12557 | #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 |
|---|
| 12558 | #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 |
|---|
| 12559 | #define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40 |
|---|
| 12560 | #define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 |
|---|
| 12561 | #define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80 |
|---|
| 12562 | #define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 |
|---|
| 12563 | #define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100 |
|---|
| 12564 | #define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 |
|---|
| 12565 | #define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200 |
|---|
| 12566 | #define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 |
|---|
| 12567 | #define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400 |
|---|
| 12568 | #define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa |
|---|
| 12569 | #define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800 |
|---|
| 12570 | #define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb |
|---|
| 12571 | #define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000 |
|---|
| 12572 | #define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc |
|---|
| 12573 | #define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000 |
|---|
| 12574 | #define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd |
|---|
| 12575 | #define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000 |
|---|
| 12576 | #define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe |
|---|
| 12577 | #define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000 |
|---|
| 12578 | #define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf |
|---|
| 12579 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f |
|---|
| 12580 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
|---|
| 12581 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
|---|
| 12582 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
|---|
| 12583 | #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff |
|---|
| 12584 | #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
|---|
| 12585 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff |
|---|
| 12586 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 |
|---|
| 12587 | #define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff |
|---|
| 12588 | #define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 |
|---|
| 12589 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 |
|---|
| 12590 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf |
|---|
| 12591 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 |
|---|
| 12592 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 |
|---|
| 12593 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 |
|---|
| 12594 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 |
|---|
| 12595 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 |
|---|
| 12596 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 |
|---|
| 12597 | #define CORB_SIZE__CORB_SIZE_MASK 0x3 |
|---|
| 12598 | #define CORB_SIZE__CORB_SIZE__SHIFT 0x0 |
|---|
| 12599 | #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 |
|---|
| 12600 | #define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 |
|---|
| 12601 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f |
|---|
| 12602 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
|---|
| 12603 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
|---|
| 12604 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
|---|
| 12605 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff |
|---|
| 12606 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
|---|
| 12607 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff |
|---|
| 12608 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 |
|---|
| 12609 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 |
|---|
| 12610 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf |
|---|
| 12611 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff |
|---|
| 12612 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 |
|---|
| 12613 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 |
|---|
| 12614 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 |
|---|
| 12615 | #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 |
|---|
| 12616 | #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 |
|---|
| 12617 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 |
|---|
| 12618 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 |
|---|
| 12619 | #define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 |
|---|
| 12620 | #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 |
|---|
| 12621 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 |
|---|
| 12622 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 |
|---|
| 12623 | #define RIRB_SIZE__RIRB_SIZE_MASK 0x3 |
|---|
| 12624 | #define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 |
|---|
| 12625 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 |
|---|
| 12626 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 |
|---|
| 12627 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff |
|---|
| 12628 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 |
|---|
| 12629 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 |
|---|
| 12630 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c |
|---|
| 12631 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff |
|---|
| 12632 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12633 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
|---|
| 12634 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12635 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff |
|---|
| 12636 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 |
|---|
| 12637 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 |
|---|
| 12638 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 |
|---|
| 12639 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 |
|---|
| 12640 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 |
|---|
| 12641 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 |
|---|
| 12642 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 |
|---|
| 12643 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e |
|---|
| 12644 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 |
|---|
| 12645 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
|---|
| 12646 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 |
|---|
| 12647 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff |
|---|
| 12648 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 |
|---|
| 12649 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff |
|---|
| 12650 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 |
|---|
| 12651 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 |
|---|
| 12652 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
|---|
| 12653 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 |
|---|
| 12654 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
|---|
| 12655 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 |
|---|
| 12656 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
|---|
| 12657 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 |
|---|
| 12658 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
|---|
| 12659 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 |
|---|
| 12660 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
|---|
| 12661 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 |
|---|
| 12662 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
|---|
| 12663 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 |
|---|
| 12664 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
|---|
| 12665 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 |
|---|
| 12666 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
|---|
| 12667 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 |
|---|
| 12668 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
|---|
| 12669 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 |
|---|
| 12670 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
|---|
| 12671 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 |
|---|
| 12672 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
|---|
| 12673 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 |
|---|
| 12674 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
|---|
| 12675 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff |
|---|
| 12676 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
|---|
| 12677 | #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff |
|---|
| 12678 | #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
|---|
| 12679 | #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff |
|---|
| 12680 | #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
|---|
| 12681 | #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff |
|---|
| 12682 | #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
|---|
| 12683 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
|---|
| 12684 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
|---|
| 12685 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
|---|
| 12686 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
|---|
| 12687 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
|---|
| 12688 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
|---|
| 12689 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
|---|
| 12690 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
|---|
| 12691 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
|---|
| 12692 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
|---|
| 12693 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f |
|---|
| 12694 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
|---|
| 12695 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
|---|
| 12696 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
|---|
| 12697 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff |
|---|
| 12698 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
|---|
| 12699 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff |
|---|
| 12700 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
|---|
| 12701 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff |
|---|
| 12702 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12703 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
|---|
| 12704 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 12705 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 12706 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 12707 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 12708 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 12709 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 12710 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 12711 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 12712 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 12713 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
|---|
| 12714 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
|---|
| 12715 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 12716 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 12717 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 12718 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 12719 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 12720 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 12721 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 12722 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 12723 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 12724 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 12725 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 12726 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 12727 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 12728 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 12729 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 12730 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 12731 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 12732 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 12733 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 12734 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 12735 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 12736 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 12737 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
|---|
| 12738 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
|---|
| 12739 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
|---|
| 12740 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
|---|
| 12741 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
|---|
| 12742 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
|---|
| 12743 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
|---|
| 12744 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
|---|
| 12745 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
|---|
| 12746 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
|---|
| 12747 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
|---|
| 12748 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
|---|
| 12749 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
|---|
| 12750 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
|---|
| 12751 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 |
|---|
| 12752 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf |
|---|
| 12753 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
|---|
| 12754 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
|---|
| 12755 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
|---|
| 12756 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
|---|
| 12757 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
|---|
| 12758 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
|---|
| 12759 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
|---|
| 12760 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
|---|
| 12761 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
|---|
| 12762 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
|---|
| 12763 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
|---|
| 12764 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
|---|
| 12765 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
|---|
| 12766 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
|---|
| 12767 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
|---|
| 12768 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
|---|
| 12769 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
|---|
| 12770 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
|---|
| 12771 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
|---|
| 12772 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
|---|
| 12773 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
|---|
| 12774 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
|---|
| 12775 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
|---|
| 12776 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
|---|
| 12777 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f |
|---|
| 12778 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 |
|---|
| 12779 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 |
|---|
| 12780 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 |
|---|
| 12781 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 |
|---|
| 12782 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
|---|
| 12783 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 |
|---|
| 12784 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
|---|
| 12785 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff |
|---|
| 12786 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
|---|
| 12787 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 |
|---|
| 12788 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
|---|
| 12789 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 |
|---|
| 12790 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
|---|
| 12791 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 |
|---|
| 12792 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
|---|
| 12793 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 12794 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 12795 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 12796 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 12797 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 12798 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 12799 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 12800 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 12801 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 12802 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 12803 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 12804 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 12805 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 12806 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 12807 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 12808 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 12809 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 12810 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 12811 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 12812 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 12813 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 12814 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 12815 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 12816 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 12817 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 12818 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 12819 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
|---|
| 12820 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
|---|
| 12821 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
|---|
| 12822 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
|---|
| 12823 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
|---|
| 12824 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
|---|
| 12825 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
|---|
| 12826 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
|---|
| 12827 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
|---|
| 12828 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
|---|
| 12829 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
|---|
| 12830 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
|---|
| 12831 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
|---|
| 12832 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
|---|
| 12833 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
|---|
| 12834 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
|---|
| 12835 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
|---|
| 12836 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
|---|
| 12837 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
|---|
| 12838 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
|---|
| 12839 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
|---|
| 12840 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
|---|
| 12841 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff |
|---|
| 12842 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 |
|---|
| 12843 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff |
|---|
| 12844 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 |
|---|
| 12845 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 |
|---|
| 12846 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
|---|
| 12847 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
|---|
| 12848 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
|---|
| 12849 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
|---|
| 12850 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
|---|
| 12851 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
|---|
| 12852 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
|---|
| 12853 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 |
|---|
| 12854 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
|---|
| 12855 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
|---|
| 12856 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
|---|
| 12857 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
|---|
| 12858 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
|---|
| 12859 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
|---|
| 12860 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
|---|
| 12861 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
|---|
| 12862 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
|---|
| 12863 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
|---|
| 12864 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
|---|
| 12865 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
|---|
| 12866 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
|---|
| 12867 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
|---|
| 12868 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
|---|
| 12869 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
|---|
| 12870 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
|---|
| 12871 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf |
|---|
| 12872 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 |
|---|
| 12873 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 |
|---|
| 12874 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 |
|---|
| 12875 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf |
|---|
| 12876 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 |
|---|
| 12877 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 |
|---|
| 12878 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 |
|---|
| 12879 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f |
|---|
| 12880 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 |
|---|
| 12881 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 |
|---|
| 12882 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 |
|---|
| 12883 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f |
|---|
| 12884 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 |
|---|
| 12885 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 |
|---|
| 12886 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 |
|---|
| 12887 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 |
|---|
| 12888 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 |
|---|
| 12889 | #define 0xfc00 |
|---|
| 12890 | #define 0xa |
|---|
| 12891 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff |
|---|
| 12892 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
|---|
| 12893 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3 |
|---|
| 12894 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 |
|---|
| 12895 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 |
|---|
| 12896 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 |
|---|
| 12897 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 |
|---|
| 12898 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 |
|---|
| 12899 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 |
|---|
| 12900 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12901 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 |
|---|
| 12902 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 |
|---|
| 12903 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12904 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12905 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12906 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12907 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12908 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12909 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff |
|---|
| 12910 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 |
|---|
| 12911 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 |
|---|
| 12912 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12913 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12914 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12915 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12916 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12917 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12918 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12919 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 |
|---|
| 12920 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12921 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12922 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12923 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12924 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12925 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12926 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12927 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 |
|---|
| 12928 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12929 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12930 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12931 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12932 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12933 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12934 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12935 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 |
|---|
| 12936 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12937 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12938 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12939 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12940 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12941 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12942 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12943 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 |
|---|
| 12944 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12945 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12946 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12947 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12948 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12949 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12950 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12951 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 |
|---|
| 12952 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12953 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12954 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12955 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12956 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12957 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12958 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12959 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 |
|---|
| 12960 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12961 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12962 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12963 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12964 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12965 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12966 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12967 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 |
|---|
| 12968 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12969 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12970 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12971 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12972 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12973 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12974 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12975 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 |
|---|
| 12976 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12977 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12978 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12979 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12980 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12981 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12982 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12983 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 |
|---|
| 12984 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12985 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12986 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12987 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12988 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12989 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12990 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12991 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 |
|---|
| 12992 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 12993 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 12994 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 12995 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 12996 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 12997 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 12998 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 12999 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 |
|---|
| 13000 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13001 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13002 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13003 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13004 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13005 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 13006 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 13007 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 |
|---|
| 13008 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13009 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13010 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13011 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13012 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13013 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 13014 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 13015 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 |
|---|
| 13016 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13017 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13018 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13019 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13020 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13021 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 13022 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 13023 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 |
|---|
| 13024 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
|---|
| 13025 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 |
|---|
| 13026 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
|---|
| 13027 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 |
|---|
| 13028 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13029 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 |
|---|
| 13030 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 |
|---|
| 13031 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 |
|---|
| 13032 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 |
|---|
| 13033 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 |
|---|
| 13034 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13035 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 |
|---|
| 13036 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 |
|---|
| 13037 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 |
|---|
| 13038 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 |
|---|
| 13039 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 |
|---|
| 13040 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13041 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 |
|---|
| 13042 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 |
|---|
| 13043 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 |
|---|
| 13044 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 |
|---|
| 13045 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 |
|---|
| 13046 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13047 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff |
|---|
| 13048 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
|---|
| 13049 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 |
|---|
| 13050 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
|---|
| 13051 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 |
|---|
| 13052 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 |
|---|
| 13053 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 |
|---|
| 13054 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 |
|---|
| 13055 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff |
|---|
| 13056 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 |
|---|
| 13057 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff |
|---|
| 13058 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 |
|---|
| 13059 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff |
|---|
| 13060 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 |
|---|
| 13061 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff |
|---|
| 13062 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 |
|---|
| 13063 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff |
|---|
| 13064 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
|---|
| 13065 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff |
|---|
| 13066 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 |
|---|
| 13067 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff |
|---|
| 13068 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 |
|---|
| 13069 | #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff |
|---|
| 13070 | #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 |
|---|
| 13071 | #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff |
|---|
| 13072 | #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 |
|---|
| 13073 | #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff |
|---|
| 13074 | #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 |
|---|
| 13075 | #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff |
|---|
| 13076 | #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 |
|---|
| 13077 | #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff |
|---|
| 13078 | #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 |
|---|
| 13079 | #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff |
|---|
| 13080 | #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 |
|---|
| 13081 | #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff |
|---|
| 13082 | #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 |
|---|
| 13083 | #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff |
|---|
| 13084 | #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 |
|---|
| 13085 | #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff |
|---|
| 13086 | #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 |
|---|
| 13087 | #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff |
|---|
| 13088 | #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 |
|---|
| 13089 | #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff |
|---|
| 13090 | #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 |
|---|
| 13091 | #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff |
|---|
| 13092 | #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 |
|---|
| 13093 | #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff |
|---|
| 13094 | #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 |
|---|
| 13095 | #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff |
|---|
| 13096 | #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 |
|---|
| 13097 | #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff |
|---|
| 13098 | #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 |
|---|
| 13099 | #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff |
|---|
| 13100 | #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 |
|---|
| 13101 | #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff |
|---|
| 13102 | #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 |
|---|
| 13103 | #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff |
|---|
| 13104 | #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 |
|---|
| 13105 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 |
|---|
| 13106 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
|---|
| 13107 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 |
|---|
| 13108 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 |
|---|
| 13109 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 |
|---|
| 13110 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13111 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 |
|---|
| 13112 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 |
|---|
| 13113 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 |
|---|
| 13114 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 |
|---|
| 13115 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 |
|---|
| 13116 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13117 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 |
|---|
| 13118 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 |
|---|
| 13119 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 |
|---|
| 13120 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 |
|---|
| 13121 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 |
|---|
| 13122 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13123 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 |
|---|
| 13124 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 |
|---|
| 13125 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 |
|---|
| 13126 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 |
|---|
| 13127 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 |
|---|
| 13128 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13129 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 |
|---|
| 13130 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
|---|
| 13131 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 |
|---|
| 13132 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
|---|
| 13133 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c |
|---|
| 13134 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
|---|
| 13135 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 |
|---|
| 13136 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
|---|
| 13137 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 |
|---|
| 13138 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
|---|
| 13139 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 |
|---|
| 13140 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
|---|
| 13141 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 |
|---|
| 13142 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
|---|
| 13143 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f |
|---|
| 13144 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
|---|
| 13145 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 |
|---|
| 13146 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
|---|
| 13147 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf |
|---|
| 13148 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
|---|
| 13149 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 |
|---|
| 13150 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
|---|
| 13151 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf |
|---|
| 13152 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
|---|
| 13153 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 |
|---|
| 13154 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
|---|
| 13155 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 |
|---|
| 13156 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
|---|
| 13157 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 |
|---|
| 13158 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
|---|
| 13159 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf |
|---|
| 13160 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
|---|
| 13161 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 |
|---|
| 13162 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
|---|
| 13163 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
|---|
| 13164 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
|---|
| 13165 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
|---|
| 13166 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
|---|
| 13167 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf |
|---|
| 13168 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
|---|
| 13169 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 |
|---|
| 13170 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
|---|
| 13171 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf |
|---|
| 13172 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
|---|
| 13173 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 |
|---|
| 13174 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
|---|
| 13175 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff |
|---|
| 13176 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
|---|
| 13177 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 |
|---|
| 13178 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
|---|
| 13179 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 |
|---|
| 13180 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
|---|
| 13181 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 |
|---|
| 13182 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
|---|
| 13183 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff |
|---|
| 13184 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
|---|
| 13185 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff |
|---|
| 13186 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
|---|
| 13187 | #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff |
|---|
| 13188 | #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
|---|
| 13189 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 |
|---|
| 13190 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
|---|
| 13191 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 |
|---|
| 13192 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
|---|
| 13193 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 |
|---|
| 13194 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
|---|
| 13195 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 |
|---|
| 13196 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
|---|
| 13197 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 |
|---|
| 13198 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
|---|
| 13199 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 |
|---|
| 13200 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
|---|
| 13201 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 |
|---|
| 13202 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
|---|
| 13203 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 |
|---|
| 13204 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 |
|---|
| 13205 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 |
|---|
| 13206 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 |
|---|
| 13207 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff |
|---|
| 13208 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 |
|---|
| 13209 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 |
|---|
| 13210 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 |
|---|
| 13211 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 |
|---|
| 13212 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 |
|---|
| 13213 | #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 |
|---|
| 13214 | #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 |
|---|
| 13215 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff |
|---|
| 13216 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 |
|---|
| 13217 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 |
|---|
| 13218 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 |
|---|
| 13219 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc |
|---|
| 13220 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 |
|---|
| 13221 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 |
|---|
| 13222 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 |
|---|
| 13223 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0 |
|---|
| 13224 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 |
|---|
| 13225 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 |
|---|
| 13226 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 |
|---|
| 13227 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 |
|---|
| 13228 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 |
|---|
| 13229 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 |
|---|
| 13230 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 |
|---|
| 13231 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc |
|---|
| 13232 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 |
|---|
| 13233 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 |
|---|
| 13234 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 |
|---|
| 13235 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0 |
|---|
| 13236 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 |
|---|
| 13237 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 |
|---|
| 13238 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 |
|---|
| 13239 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 |
|---|
| 13240 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 |
|---|
| 13241 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0 |
|---|
| 13242 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 |
|---|
| 13243 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 |
|---|
| 13244 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 |
|---|
| 13245 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 |
|---|
| 13246 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 |
|---|
| 13247 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff |
|---|
| 13248 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 |
|---|
| 13249 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 |
|---|
| 13250 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 |
|---|
| 13251 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 |
|---|
| 13252 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
|---|
| 13253 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
|---|
| 13254 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
|---|
| 13255 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 |
|---|
| 13256 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 |
|---|
| 13257 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff |
|---|
| 13258 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 |
|---|
| 13259 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 |
|---|
| 13260 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 |
|---|
| 13261 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000 |
|---|
| 13262 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 |
|---|
| 13263 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
|---|
| 13264 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
|---|
| 13265 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000 |
|---|
| 13266 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 |
|---|
| 13267 | #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff |
|---|
| 13268 | #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 |
|---|
| 13269 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 13270 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 13271 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4 |
|---|
| 13272 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 13273 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18 |
|---|
| 13274 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 13275 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20 |
|---|
| 13276 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 |
|---|
| 13277 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0 |
|---|
| 13278 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 |
|---|
| 13279 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100 |
|---|
| 13280 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 |
|---|
| 13281 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600 |
|---|
| 13282 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 |
|---|
| 13283 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800 |
|---|
| 13284 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb |
|---|
| 13285 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000 |
|---|
| 13286 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc |
|---|
| 13287 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000 |
|---|
| 13288 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe |
|---|
| 13289 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000 |
|---|
| 13290 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf |
|---|
| 13291 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000 |
|---|
| 13292 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 |
|---|
| 13293 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000 |
|---|
| 13294 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 |
|---|
| 13295 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000 |
|---|
| 13296 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 |
|---|
| 13297 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000 |
|---|
| 13298 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c |
|---|
| 13299 | #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3 |
|---|
| 13300 | #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 |
|---|
| 13301 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc |
|---|
| 13302 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 |
|---|
| 13303 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30 |
|---|
| 13304 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 13305 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0 |
|---|
| 13306 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 |
|---|
| 13307 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300 |
|---|
| 13308 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 |
|---|
| 13309 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00 |
|---|
| 13310 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa |
|---|
| 13311 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 13312 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 13313 | #define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1 |
|---|
| 13314 | #define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0 |
|---|
| 13315 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1 |
|---|
| 13316 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 |
|---|
| 13317 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 |
|---|
| 13318 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 |
|---|
| 13319 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 |
|---|
| 13320 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 |
|---|
| 13321 | #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff |
|---|
| 13322 | #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 |
|---|
| 13323 | #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff |
|---|
| 13324 | #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 |
|---|
| 13325 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 |
|---|
| 13326 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 |
|---|
| 13327 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
|---|
| 13328 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
|---|
| 13329 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
|---|
| 13330 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
|---|
| 13331 | #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff |
|---|
| 13332 | #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 |
|---|
| 13333 | #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff |
|---|
| 13334 | #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 |
|---|
| 13335 | #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff |
|---|
| 13336 | #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 |
|---|
| 13337 | #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff |
|---|
| 13338 | #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 |
|---|
| 13339 | #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff |
|---|
| 13340 | #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 |
|---|
| 13341 | #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff |
|---|
| 13342 | #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 |
|---|
| 13343 | #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff |
|---|
| 13344 | #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 |
|---|
| 13345 | #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff |
|---|
| 13346 | #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 |
|---|
| 13347 | #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff |
|---|
| 13348 | #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 |
|---|
| 13349 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1 |
|---|
| 13350 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 |
|---|
| 13351 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 |
|---|
| 13352 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 |
|---|
| 13353 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 |
|---|
| 13354 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 |
|---|
| 13355 | #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff |
|---|
| 13356 | #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 |
|---|
| 13357 | #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff |
|---|
| 13358 | #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 |
|---|
| 13359 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 |
|---|
| 13360 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 |
|---|
| 13361 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
|---|
| 13362 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
|---|
| 13363 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
|---|
| 13364 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
|---|
| 13365 | #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff |
|---|
| 13366 | #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 |
|---|
| 13367 | #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff |
|---|
| 13368 | #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 |
|---|
| 13369 | #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff |
|---|
| 13370 | #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 |
|---|
| 13371 | #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff |
|---|
| 13372 | #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 |
|---|
| 13373 | #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff |
|---|
| 13374 | #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 |
|---|
| 13375 | #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff |
|---|
| 13376 | #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 |
|---|
| 13377 | #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff |
|---|
| 13378 | #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 |
|---|
| 13379 | #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff |
|---|
| 13380 | #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 |
|---|
| 13381 | #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff |
|---|
| 13382 | #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 |
|---|
| 13383 | #define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 |
|---|
| 13384 | #define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 |
|---|
| 13385 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 |
|---|
| 13386 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
|---|
| 13387 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 |
|---|
| 13388 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
|---|
| 13389 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 |
|---|
| 13390 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
|---|
| 13391 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff |
|---|
| 13392 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
|---|
| 13393 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff |
|---|
| 13394 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
|---|
| 13395 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 |
|---|
| 13396 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
|---|
| 13397 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
|---|
| 13398 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
|---|
| 13399 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
|---|
| 13400 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
|---|
| 13401 | #define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff |
|---|
| 13402 | #define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 |
|---|
| 13403 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff |
|---|
| 13404 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
|---|
| 13405 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff |
|---|
| 13406 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
|---|
| 13407 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff |
|---|
| 13408 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
|---|
| 13409 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff |
|---|
| 13410 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
|---|
| 13411 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff |
|---|
| 13412 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
|---|
| 13413 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff |
|---|
| 13414 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
|---|
| 13415 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff |
|---|
| 13416 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
|---|
| 13417 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff |
|---|
| 13418 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
|---|
| 13419 | #define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 |
|---|
| 13420 | #define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 |
|---|
| 13421 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 |
|---|
| 13422 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
|---|
| 13423 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 |
|---|
| 13424 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
|---|
| 13425 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 |
|---|
| 13426 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
|---|
| 13427 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff |
|---|
| 13428 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
|---|
| 13429 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff |
|---|
| 13430 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
|---|
| 13431 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 |
|---|
| 13432 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
|---|
| 13433 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
|---|
| 13434 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
|---|
| 13435 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
|---|
| 13436 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
|---|
| 13437 | #define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff |
|---|
| 13438 | #define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 |
|---|
| 13439 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff |
|---|
| 13440 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
|---|
| 13441 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff |
|---|
| 13442 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
|---|
| 13443 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff |
|---|
| 13444 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
|---|
| 13445 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff |
|---|
| 13446 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
|---|
| 13447 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff |
|---|
| 13448 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
|---|
| 13449 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff |
|---|
| 13450 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
|---|
| 13451 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff |
|---|
| 13452 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
|---|
| 13453 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff |
|---|
| 13454 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
|---|
| 13455 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 13456 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 13457 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 13458 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 13459 | #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 13460 | #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 13461 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff |
|---|
| 13462 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
|---|
| 13463 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 |
|---|
| 13464 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
|---|
| 13465 | #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff |
|---|
| 13466 | #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
|---|
| 13467 | #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f |
|---|
| 13468 | #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
|---|
| 13469 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 |
|---|
| 13470 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
|---|
| 13471 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 |
|---|
| 13472 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
|---|
| 13473 | #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 |
|---|
| 13474 | #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
|---|
| 13475 | #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff |
|---|
| 13476 | #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
|---|
| 13477 | #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff |
|---|
| 13478 | #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
|---|
| 13479 | #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff |
|---|
| 13480 | #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
|---|
| 13481 | #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff |
|---|
| 13482 | #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 |
|---|
| 13483 | #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff |
|---|
| 13484 | #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
|---|
| 13485 | #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff |
|---|
| 13486 | #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
|---|
| 13487 | #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 |
|---|
| 13488 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 13489 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 13490 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 13491 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 13492 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 13493 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 13494 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 13495 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 13496 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
|---|
| 13497 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
|---|
| 13498 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 13499 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 13500 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 13501 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 13502 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 13503 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 13504 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 13505 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 13506 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 13507 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 13508 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 13509 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 13510 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 13511 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 13512 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 13513 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 13514 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 13515 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 13516 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
|---|
| 13517 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
|---|
| 13518 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
|---|
| 13519 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
|---|
| 13520 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
|---|
| 13521 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
|---|
| 13522 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
|---|
| 13523 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
|---|
| 13524 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
|---|
| 13525 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
|---|
| 13526 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
|---|
| 13527 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
|---|
| 13528 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
|---|
| 13529 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
|---|
| 13530 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
|---|
| 13531 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
|---|
| 13532 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
|---|
| 13533 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
|---|
| 13534 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
|---|
| 13535 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
|---|
| 13536 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
|---|
| 13537 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
|---|
| 13538 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
|---|
| 13539 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
|---|
| 13540 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
|---|
| 13541 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
|---|
| 13542 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
|---|
| 13543 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
|---|
| 13544 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
|---|
| 13545 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
|---|
| 13546 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
|---|
| 13547 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
|---|
| 13548 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
|---|
| 13549 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
|---|
| 13550 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
|---|
| 13551 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
|---|
| 13552 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
|---|
| 13553 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
|---|
| 13554 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 13555 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 13556 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 13557 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 13558 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 |
|---|
| 13559 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
|---|
| 13560 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 |
|---|
| 13561 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
|---|
| 13562 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff |
|---|
| 13563 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
|---|
| 13564 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 |
|---|
| 13565 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
|---|
| 13566 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 |
|---|
| 13567 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
|---|
| 13568 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 |
|---|
| 13569 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
|---|
| 13570 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 |
|---|
| 13571 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
|---|
| 13572 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff |
|---|
| 13573 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 |
|---|
| 13574 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff |
|---|
| 13575 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
|---|
| 13576 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff |
|---|
| 13577 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
|---|
| 13578 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff |
|---|
| 13579 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
|---|
| 13580 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 13581 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 13582 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 13583 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 13584 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 13585 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 13586 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 13587 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 13588 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 13589 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 13590 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 13591 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 13592 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 13593 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 13594 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 13595 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 13596 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 13597 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 13598 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 13599 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 13600 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 13601 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 13602 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 13603 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 13604 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 13605 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 13606 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
|---|
| 13607 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
|---|
| 13608 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
|---|
| 13609 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
|---|
| 13610 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
|---|
| 13611 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
|---|
| 13612 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
|---|
| 13613 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
|---|
| 13614 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
|---|
| 13615 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
|---|
| 13616 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
|---|
| 13617 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
|---|
| 13618 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
|---|
| 13619 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
|---|
| 13620 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
|---|
| 13621 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
|---|
| 13622 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
|---|
| 13623 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
|---|
| 13624 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
|---|
| 13625 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
|---|
| 13626 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
|---|
| 13627 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
|---|
| 13628 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
|---|
| 13629 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
|---|
| 13630 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
|---|
| 13631 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
|---|
| 13632 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
|---|
| 13633 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
|---|
| 13634 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 |
|---|
| 13635 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
|---|
| 13636 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f |
|---|
| 13637 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
|---|
| 13638 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 |
|---|
| 13639 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
|---|
| 13640 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 |
|---|
| 13641 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
|---|
| 13642 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 |
|---|
| 13643 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
|---|
| 13644 | #define 0xfc0000 |
|---|
| 13645 | #define 0x12 |
|---|
| 13646 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000 |
|---|
| 13647 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
|---|
| 13648 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 |
|---|
| 13649 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
|---|
| 13650 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 |
|---|
| 13651 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
|---|
| 13652 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 |
|---|
| 13653 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13654 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13655 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13656 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13657 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13658 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
|---|
| 13659 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
|---|
| 13660 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 |
|---|
| 13661 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13662 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13663 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13664 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13665 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13666 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 |
|---|
| 13667 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13668 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13669 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13670 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13671 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13672 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 |
|---|
| 13673 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13674 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13675 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13676 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13677 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13678 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 |
|---|
| 13679 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13680 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13681 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13682 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13683 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13684 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 |
|---|
| 13685 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13686 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13687 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13688 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13689 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13690 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 |
|---|
| 13691 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13692 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13693 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13694 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13695 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13696 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 |
|---|
| 13697 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13698 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13699 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13700 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13701 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13702 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 |
|---|
| 13703 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13704 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13705 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13706 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13707 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13708 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 |
|---|
| 13709 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13710 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13711 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13712 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13713 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13714 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 |
|---|
| 13715 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13716 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13717 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13718 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13719 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13720 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 |
|---|
| 13721 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13722 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13723 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13724 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13725 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13726 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 |
|---|
| 13727 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13728 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13729 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13730 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13731 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13732 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 |
|---|
| 13733 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
|---|
| 13734 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 |
|---|
| 13735 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
|---|
| 13736 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
|---|
| 13737 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
|---|
| 13738 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 |
|---|
| 13739 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
|---|
| 13740 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 |
|---|
| 13741 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
|---|
| 13742 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 |
|---|
| 13743 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13744 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 |
|---|
| 13745 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
|---|
| 13746 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 |
|---|
| 13747 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
|---|
| 13748 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 |
|---|
| 13749 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
|---|
| 13750 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 |
|---|
| 13751 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
|---|
| 13752 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 |
|---|
| 13753 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
|---|
| 13754 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 |
|---|
| 13755 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
|---|
| 13756 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 |
|---|
| 13757 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
|---|
| 13758 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 |
|---|
| 13759 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
|---|
| 13760 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 |
|---|
| 13761 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
|---|
| 13762 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 |
|---|
| 13763 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
|---|
| 13764 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 |
|---|
| 13765 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
|---|
| 13766 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 |
|---|
| 13767 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
|---|
| 13768 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 |
|---|
| 13769 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
|---|
| 13770 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 |
|---|
| 13771 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
|---|
| 13772 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 |
|---|
| 13773 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
|---|
| 13774 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 |
|---|
| 13775 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
|---|
| 13776 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 |
|---|
| 13777 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
|---|
| 13778 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 |
|---|
| 13779 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
|---|
| 13780 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 |
|---|
| 13781 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
|---|
| 13782 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 |
|---|
| 13783 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
|---|
| 13784 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 |
|---|
| 13785 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
|---|
| 13786 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 |
|---|
| 13787 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
|---|
| 13788 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff |
|---|
| 13789 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
|---|
| 13790 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 |
|---|
| 13791 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
|---|
| 13792 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 |
|---|
| 13793 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
|---|
| 13794 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 |
|---|
| 13795 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
|---|
| 13796 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff |
|---|
| 13797 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
|---|
| 13798 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 |
|---|
| 13799 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
|---|
| 13800 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff |
|---|
| 13801 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
|---|
| 13802 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff |
|---|
| 13803 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
|---|
| 13804 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff |
|---|
| 13805 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
|---|
| 13806 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff |
|---|
| 13807 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
|---|
| 13808 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 |
|---|
| 13809 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
|---|
| 13810 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 |
|---|
| 13811 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
|---|
| 13812 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 |
|---|
| 13813 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
|---|
| 13814 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff |
|---|
| 13815 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
|---|
| 13816 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 |
|---|
| 13817 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
|---|
| 13818 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 |
|---|
| 13819 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
|---|
| 13820 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 |
|---|
| 13821 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
|---|
| 13822 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff |
|---|
| 13823 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
|---|
| 13824 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 |
|---|
| 13825 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
|---|
| 13826 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 |
|---|
| 13827 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
|---|
| 13828 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 |
|---|
| 13829 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
|---|
| 13830 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff |
|---|
| 13831 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
|---|
| 13832 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 |
|---|
| 13833 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
|---|
| 13834 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 |
|---|
| 13835 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
|---|
| 13836 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 |
|---|
| 13837 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
|---|
| 13838 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff |
|---|
| 13839 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
|---|
| 13840 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 |
|---|
| 13841 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
|---|
| 13842 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 |
|---|
| 13843 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
|---|
| 13844 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 |
|---|
| 13845 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
|---|
| 13846 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 |
|---|
| 13847 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
|---|
| 13848 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff |
|---|
| 13849 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
|---|
| 13850 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 |
|---|
| 13851 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
|---|
| 13852 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
|---|
| 13853 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
|---|
| 13854 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
|---|
| 13855 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
|---|
| 13856 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
|---|
| 13857 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
|---|
| 13858 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
|---|
| 13859 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
|---|
| 13860 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
|---|
| 13861 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
|---|
| 13862 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
|---|
| 13863 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
|---|
| 13864 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
|---|
| 13865 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
|---|
| 13866 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
|---|
| 13867 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
|---|
| 13868 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 |
|---|
| 13869 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
|---|
| 13870 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c |
|---|
| 13871 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
|---|
| 13872 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 |
|---|
| 13873 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
|---|
| 13874 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 |
|---|
| 13875 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
|---|
| 13876 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 |
|---|
| 13877 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
|---|
| 13878 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 |
|---|
| 13879 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
|---|
| 13880 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f |
|---|
| 13881 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
|---|
| 13882 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 |
|---|
| 13883 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
|---|
| 13884 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf |
|---|
| 13885 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
|---|
| 13886 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 |
|---|
| 13887 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
|---|
| 13888 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf |
|---|
| 13889 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
|---|
| 13890 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 |
|---|
| 13891 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
|---|
| 13892 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 |
|---|
| 13893 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
|---|
| 13894 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 |
|---|
| 13895 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
|---|
| 13896 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf |
|---|
| 13897 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
|---|
| 13898 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 |
|---|
| 13899 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
|---|
| 13900 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
|---|
| 13901 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
|---|
| 13902 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
|---|
| 13903 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
|---|
| 13904 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf |
|---|
| 13905 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
|---|
| 13906 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 |
|---|
| 13907 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
|---|
| 13908 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf |
|---|
| 13909 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
|---|
| 13910 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 |
|---|
| 13911 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
|---|
| 13912 | #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff |
|---|
| 13913 | #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
|---|
| 13914 | #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 |
|---|
| 13915 | #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
|---|
| 13916 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 |
|---|
| 13917 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
|---|
| 13918 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 |
|---|
| 13919 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
|---|
| 13920 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff |
|---|
| 13921 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
|---|
| 13922 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff |
|---|
| 13923 | #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
|---|
| 13924 | #define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff |
|---|
| 13925 | #define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
|---|
| 13926 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 |
|---|
| 13927 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
|---|
| 13928 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 |
|---|
| 13929 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
|---|
| 13930 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 |
|---|
| 13931 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
|---|
| 13932 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 |
|---|
| 13933 | #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
|---|
| 13934 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 |
|---|
| 13935 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
|---|
| 13936 | #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 |
|---|
| 13937 | #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
|---|
| 13938 | #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 |
|---|
| 13939 | #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
|---|
| 13940 | #define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1 |
|---|
| 13941 | #define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
|---|
| 13942 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1 |
|---|
| 13943 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
|---|
| 13944 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10 |
|---|
| 13945 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
|---|
| 13946 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100 |
|---|
| 13947 | #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
|---|
| 13948 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1 |
|---|
| 13949 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
|---|
| 13950 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10 |
|---|
| 13951 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
|---|
| 13952 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100 |
|---|
| 13953 | #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
|---|
| 13954 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1 |
|---|
| 13955 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
|---|
| 13956 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10 |
|---|
| 13957 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
|---|
| 13958 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100 |
|---|
| 13959 | #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
|---|
| 13960 | #define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff |
|---|
| 13961 | #define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
|---|
| 13962 | #define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff |
|---|
| 13963 | #define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
|---|
| 13964 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff |
|---|
| 13965 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 |
|---|
| 13966 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 13967 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 13968 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 13969 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 13970 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 13971 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 13972 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 13973 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 13974 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
|---|
| 13975 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
|---|
| 13976 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 13977 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 13978 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 13979 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 13980 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 13981 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 13982 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 13983 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 13984 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 13985 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 13986 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 13987 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 13988 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 13989 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 13990 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 13991 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 13992 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 13993 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 13994 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
|---|
| 13995 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
|---|
| 13996 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
|---|
| 13997 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
|---|
| 13998 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
|---|
| 13999 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
|---|
| 14000 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
|---|
| 14001 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
|---|
| 14002 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
|---|
| 14003 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
|---|
| 14004 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
|---|
| 14005 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
|---|
| 14006 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
|---|
| 14007 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
|---|
| 14008 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
|---|
| 14009 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
|---|
| 14010 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
|---|
| 14011 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
|---|
| 14012 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
|---|
| 14013 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
|---|
| 14014 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
|---|
| 14015 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
|---|
| 14016 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
|---|
| 14017 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
|---|
| 14018 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
|---|
| 14019 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
|---|
| 14020 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
|---|
| 14021 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
|---|
| 14022 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
|---|
| 14023 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
|---|
| 14024 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
|---|
| 14025 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
|---|
| 14026 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
|---|
| 14027 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
|---|
| 14028 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
|---|
| 14029 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
|---|
| 14030 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
|---|
| 14031 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
|---|
| 14032 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 14033 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 14034 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 14035 | #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 14036 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 14037 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 14038 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 14039 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 14040 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 14041 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 14042 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 14043 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 14044 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 14045 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 14046 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 14047 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 14048 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 14049 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 14050 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 14051 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 14052 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 14053 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 14054 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 14055 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 14056 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 14057 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 14058 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 14059 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 14060 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 14061 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 14062 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
|---|
| 14063 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
|---|
| 14064 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
|---|
| 14065 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
|---|
| 14066 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
|---|
| 14067 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
|---|
| 14068 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
|---|
| 14069 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
|---|
| 14070 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
|---|
| 14071 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
|---|
| 14072 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
|---|
| 14073 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
|---|
| 14074 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
|---|
| 14075 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
|---|
| 14076 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
|---|
| 14077 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
|---|
| 14078 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
|---|
| 14079 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
|---|
| 14080 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
|---|
| 14081 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
|---|
| 14082 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
|---|
| 14083 | #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
|---|
| 14084 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
|---|
| 14085 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
|---|
| 14086 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
|---|
| 14087 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
|---|
| 14088 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
|---|
| 14089 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
|---|
| 14090 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 |
|---|
| 14091 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
|---|
| 14092 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 |
|---|
| 14093 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
|---|
| 14094 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 |
|---|
| 14095 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
|---|
| 14096 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 |
|---|
| 14097 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
|---|
| 14098 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 |
|---|
| 14099 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14100 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100 |
|---|
| 14101 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
|---|
| 14102 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200 |
|---|
| 14103 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
|---|
| 14104 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000 |
|---|
| 14105 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
|---|
| 14106 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000 |
|---|
| 14107 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
|---|
| 14108 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000 |
|---|
| 14109 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
|---|
| 14110 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000 |
|---|
| 14111 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
|---|
| 14112 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000 |
|---|
| 14113 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
|---|
| 14114 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000 |
|---|
| 14115 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
|---|
| 14116 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000 |
|---|
| 14117 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
|---|
| 14118 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1 |
|---|
| 14119 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
|---|
| 14120 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2 |
|---|
| 14121 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
|---|
| 14122 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 |
|---|
| 14123 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14124 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100 |
|---|
| 14125 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
|---|
| 14126 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200 |
|---|
| 14127 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
|---|
| 14128 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000 |
|---|
| 14129 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
|---|
| 14130 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000 |
|---|
| 14131 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
|---|
| 14132 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000 |
|---|
| 14133 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
|---|
| 14134 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000 |
|---|
| 14135 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
|---|
| 14136 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 |
|---|
| 14137 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
|---|
| 14138 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 |
|---|
| 14139 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
|---|
| 14140 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 |
|---|
| 14141 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
|---|
| 14142 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 |
|---|
| 14143 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
|---|
| 14144 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 |
|---|
| 14145 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
|---|
| 14146 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff |
|---|
| 14147 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
|---|
| 14148 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 |
|---|
| 14149 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
|---|
| 14150 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 |
|---|
| 14151 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
|---|
| 14152 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 |
|---|
| 14153 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
|---|
| 14154 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff |
|---|
| 14155 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
|---|
| 14156 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 |
|---|
| 14157 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
|---|
| 14158 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
|---|
| 14159 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
|---|
| 14160 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
|---|
| 14161 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
|---|
| 14162 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
|---|
| 14163 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
|---|
| 14164 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
|---|
| 14165 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
|---|
| 14166 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
|---|
| 14167 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
|---|
| 14168 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
|---|
| 14169 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
|---|
| 14170 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
|---|
| 14171 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
|---|
| 14172 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
|---|
| 14173 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
|---|
| 14174 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 |
|---|
| 14175 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
|---|
| 14176 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 |
|---|
| 14177 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
|---|
| 14178 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 |
|---|
| 14179 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
|---|
| 14180 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 |
|---|
| 14181 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
|---|
| 14182 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 |
|---|
| 14183 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
|---|
| 14184 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 |
|---|
| 14185 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
|---|
| 14186 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 |
|---|
| 14187 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
|---|
| 14188 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 |
|---|
| 14189 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
|---|
| 14190 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 |
|---|
| 14191 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
|---|
| 14192 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 |
|---|
| 14193 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
|---|
| 14194 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff |
|---|
| 14195 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
|---|
| 14196 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff |
|---|
| 14197 | #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
|---|
| 14198 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff |
|---|
| 14199 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 14200 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
|---|
| 14201 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
|---|
| 14202 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 14203 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 14204 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 14205 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 14206 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 14207 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 14208 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 14209 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 14210 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
|---|
| 14211 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
|---|
| 14212 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 14213 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 14214 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 14215 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 14216 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 14217 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 14218 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 14219 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 14220 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 14221 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 14222 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 14223 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 14224 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 14225 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 14226 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 14227 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 14228 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 14229 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 14230 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
|---|
| 14231 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
|---|
| 14232 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
|---|
| 14233 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
|---|
| 14234 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
|---|
| 14235 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
|---|
| 14236 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
|---|
| 14237 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
|---|
| 14238 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
|---|
| 14239 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
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| 14240 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
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| 14241 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
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| 14242 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
|---|
| 14243 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
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| 14244 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
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| 14245 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
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| 14246 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
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| 14247 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
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| 14248 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
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| 14249 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
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| 14250 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
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| 14251 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
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| 14252 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
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| 14253 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
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| 14254 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
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| 14255 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
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| 14256 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
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| 14257 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
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| 14258 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
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| 14259 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
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| 14260 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
|---|
| 14261 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
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| 14262 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
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| 14263 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
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| 14264 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
|---|
| 14265 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
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| 14266 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
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| 14267 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
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| 14268 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
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| 14269 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
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| 14270 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
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| 14271 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
|---|
| 14272 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
|---|
| 14273 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
|---|
| 14274 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
|---|
| 14275 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
|---|
| 14276 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
|---|
| 14277 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
|---|
| 14278 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
|---|
| 14279 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
|---|
| 14280 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
|---|
| 14281 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
|---|
| 14282 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
|---|
| 14283 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
|---|
| 14284 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
|---|
| 14285 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
|---|
| 14286 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
|---|
| 14287 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
|---|
| 14288 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
|---|
| 14289 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
|---|
| 14290 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
|---|
| 14291 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
|---|
| 14292 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
|---|
| 14293 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
|---|
| 14294 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
|---|
| 14295 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
|---|
| 14296 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
|---|
| 14297 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
|---|
| 14298 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
|---|
| 14299 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
|---|
| 14300 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
|---|
| 14301 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
|---|
| 14302 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
|---|
| 14303 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
|---|
| 14304 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
|---|
| 14305 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
|---|
| 14306 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
|---|
| 14307 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
|---|
| 14308 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
|---|
| 14309 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
|---|
| 14310 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
|---|
| 14311 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
|---|
| 14312 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
|---|
| 14313 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
|---|
| 14314 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
|---|
| 14315 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
|---|
| 14316 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
|---|
| 14317 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
|---|
| 14318 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
|---|
| 14319 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
|---|
| 14320 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 |
|---|
| 14321 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
|---|
| 14322 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
|---|
| 14323 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
|---|
| 14324 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
|---|
| 14325 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
|---|
| 14326 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
|---|
| 14327 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
|---|
| 14328 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 |
|---|
| 14329 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
|---|
| 14330 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
|---|
| 14331 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
|---|
| 14332 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
|---|
| 14333 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
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| 14334 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
|---|
| 14335 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
|---|
| 14336 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
|---|
| 14337 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
|---|
| 14338 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
|---|
| 14339 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
|---|
| 14340 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
|---|
| 14341 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
|---|
| 14342 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
|---|
| 14343 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
|---|
| 14344 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
|---|
| 14345 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
|---|
| 14346 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf |
|---|
| 14347 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 |
|---|
| 14348 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 |
|---|
| 14349 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 |
|---|
| 14350 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf |
|---|
| 14351 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 |
|---|
| 14352 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 |
|---|
| 14353 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 |
|---|
| 14354 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f |
|---|
| 14355 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 |
|---|
| 14356 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 |
|---|
| 14357 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 |
|---|
| 14358 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 |
|---|
| 14359 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
|---|
| 14360 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 |
|---|
| 14361 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
|---|
| 14362 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 |
|---|
| 14363 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14364 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 |
|---|
| 14365 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
|---|
| 14366 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 |
|---|
| 14367 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 |
|---|
| 14368 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 |
|---|
| 14369 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14370 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1 |
|---|
| 14371 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 |
|---|
| 14372 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2 |
|---|
| 14373 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 |
|---|
| 14374 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0 |
|---|
| 14375 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14376 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 |
|---|
| 14377 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 |
|---|
| 14378 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 |
|---|
| 14379 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 |
|---|
| 14380 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 |
|---|
| 14381 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14382 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 |
|---|
| 14383 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 |
|---|
| 14384 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 |
|---|
| 14385 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 |
|---|
| 14386 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1 |
|---|
| 14387 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
|---|
| 14388 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2 |
|---|
| 14389 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 |
|---|
| 14390 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 |
|---|
| 14391 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14392 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 |
|---|
| 14393 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 |
|---|
| 14394 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 |
|---|
| 14395 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 |
|---|
| 14396 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 |
|---|
| 14397 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14398 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1 |
|---|
| 14399 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 |
|---|
| 14400 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2 |
|---|
| 14401 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 |
|---|
| 14402 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0 |
|---|
| 14403 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14404 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 |
|---|
| 14405 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 |
|---|
| 14406 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 |
|---|
| 14407 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 |
|---|
| 14408 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 |
|---|
| 14409 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 |
|---|
| 14410 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff |
|---|
| 14411 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
|---|
| 14412 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 |
|---|
| 14413 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
|---|
| 14414 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 |
|---|
| 14415 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
|---|
| 14416 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 |
|---|
| 14417 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
|---|
| 14418 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 |
|---|
| 14419 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
|---|
| 14420 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 |
|---|
| 14421 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
|---|
| 14422 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 |
|---|
| 14423 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
|---|
| 14424 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 |
|---|
| 14425 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
|---|
| 14426 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 |
|---|
| 14427 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
|---|
| 14428 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff |
|---|
| 14429 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 |
|---|
| 14430 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff |
|---|
| 14431 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 |
|---|
| 14432 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 |
|---|
| 14433 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
|---|
| 14434 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 |
|---|
| 14435 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
|---|
| 14436 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff |
|---|
| 14437 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
|---|
| 14438 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff |
|---|
| 14439 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
|---|
| 14440 | #define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff |
|---|
| 14441 | #define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 |
|---|
| 14442 | #define BLND_CONTROL__BLND_MODE_MASK 0x300 |
|---|
| 14443 | #define BLND_CONTROL__BLND_MODE__SHIFT 0x8 |
|---|
| 14444 | #define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 |
|---|
| 14445 | #define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa |
|---|
| 14446 | #define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 |
|---|
| 14447 | #define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc |
|---|
| 14448 | #define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 |
|---|
| 14449 | #define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd |
|---|
| 14450 | #define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 |
|---|
| 14451 | #define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 |
|---|
| 14452 | #define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 |
|---|
| 14453 | #define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 |
|---|
| 14454 | #define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 |
|---|
| 14455 | #define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 |
|---|
| 14456 | #define SM_CONTROL2__SM_MODE_MASK 0x7 |
|---|
| 14457 | #define SM_CONTROL2__SM_MODE__SHIFT 0x0 |
|---|
| 14458 | #define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 |
|---|
| 14459 | #define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 |
|---|
| 14460 | #define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 |
|---|
| 14461 | #define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 |
|---|
| 14462 | #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 |
|---|
| 14463 | #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
|---|
| 14464 | #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 |
|---|
| 14465 | #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
|---|
| 14466 | #define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 |
|---|
| 14467 | #define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 |
|---|
| 14468 | #define BLND_CONTROL2__PTI_ENABLE_MASK 0x1 |
|---|
| 14469 | #define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0 |
|---|
| 14470 | #define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 |
|---|
| 14471 | #define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 |
|---|
| 14472 | #define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 |
|---|
| 14473 | #define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 |
|---|
| 14474 | #define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 |
|---|
| 14475 | #define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 |
|---|
| 14476 | #define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 |
|---|
| 14477 | #define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 |
|---|
| 14478 | #define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 |
|---|
| 14479 | #define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 14480 | #define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 |
|---|
| 14481 | #define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 |
|---|
| 14482 | #define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 |
|---|
| 14483 | #define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 14484 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 |
|---|
| 14485 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 |
|---|
| 14486 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 |
|---|
| 14487 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 |
|---|
| 14488 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 |
|---|
| 14489 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc |
|---|
| 14490 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 |
|---|
| 14491 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 |
|---|
| 14492 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 |
|---|
| 14493 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 14494 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 |
|---|
| 14495 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 |
|---|
| 14496 | #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100 |
|---|
| 14497 | #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8 |
|---|
| 14498 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 |
|---|
| 14499 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 14500 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 |
|---|
| 14501 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 |
|---|
| 14502 | #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 |
|---|
| 14503 | #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c |
|---|
| 14504 | #define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 |
|---|
| 14505 | #define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d |
|---|
| 14506 | #define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 |
|---|
| 14507 | #define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f |
|---|
| 14508 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 |
|---|
| 14509 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 14510 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 |
|---|
| 14511 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 |
|---|
| 14512 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 |
|---|
| 14513 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 |
|---|
| 14514 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 |
|---|
| 14515 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 |
|---|
| 14516 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK 0x10 |
|---|
| 14517 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT 0x4 |
|---|
| 14518 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK 0x20 |
|---|
| 14519 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT 0x5 |
|---|
| 14520 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 |
|---|
| 14521 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 |
|---|
| 14522 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 |
|---|
| 14523 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 |
|---|
| 14524 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 |
|---|
| 14525 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 |
|---|
| 14526 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 |
|---|
| 14527 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 |
|---|
| 14528 | #define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 |
|---|
| 14529 | #define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa |
|---|
| 14530 | #define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 |
|---|
| 14531 | #define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb |
|---|
| 14532 | #define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 |
|---|
| 14533 | #define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 |
|---|
| 14534 | #define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe |
|---|
| 14535 | #define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 |
|---|
| 14536 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 14537 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 14538 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 14539 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 14540 | #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 14541 | #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 14542 | #define WB_ENABLE__WB_ENABLE_MASK 0x1 |
|---|
| 14543 | #define WB_ENABLE__WB_ENABLE__SHIFT 0x0 |
|---|
| 14544 | #define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1 |
|---|
| 14545 | #define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 |
|---|
| 14546 | #define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2 |
|---|
| 14547 | #define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 |
|---|
| 14548 | #define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4 |
|---|
| 14549 | #define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 |
|---|
| 14550 | #define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS_MASK 0x8 |
|---|
| 14551 | #define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS__SHIFT 0x3 |
|---|
| 14552 | #define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS_MASK 0x10 |
|---|
| 14553 | #define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS__SHIFT 0x4 |
|---|
| 14554 | #define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS_MASK 0x20 |
|---|
| 14555 | #define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS__SHIFT 0x5 |
|---|
| 14556 | #define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40 |
|---|
| 14557 | #define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6 |
|---|
| 14558 | #define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80 |
|---|
| 14559 | #define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7 |
|---|
| 14560 | #define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100 |
|---|
| 14561 | #define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8 |
|---|
| 14562 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 |
|---|
| 14563 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9 |
|---|
| 14564 | #define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000 |
|---|
| 14565 | #define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc |
|---|
| 14566 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000 |
|---|
| 14567 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10 |
|---|
| 14568 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000 |
|---|
| 14569 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11 |
|---|
| 14570 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000 |
|---|
| 14571 | #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13 |
|---|
| 14572 | #define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000 |
|---|
| 14573 | #define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 |
|---|
| 14574 | #define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 |
|---|
| 14575 | #define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c |
|---|
| 14576 | #define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 |
|---|
| 14577 | #define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e |
|---|
| 14578 | #define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300 |
|---|
| 14579 | #define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 |
|---|
| 14580 | #define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000 |
|---|
| 14581 | #define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc |
|---|
| 14582 | #define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000 |
|---|
| 14583 | #define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd |
|---|
| 14584 | #define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000 |
|---|
| 14585 | #define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf |
|---|
| 14586 | #define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 |
|---|
| 14587 | #define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 |
|---|
| 14588 | #define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000 |
|---|
| 14589 | #define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 |
|---|
| 14590 | #define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000 |
|---|
| 14591 | #define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 |
|---|
| 14592 | #define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000 |
|---|
| 14593 | #define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 |
|---|
| 14594 | #define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 |
|---|
| 14595 | #define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 |
|---|
| 14596 | #define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000 |
|---|
| 14597 | #define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f |
|---|
| 14598 | #define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff |
|---|
| 14599 | #define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 |
|---|
| 14600 | #define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 |
|---|
| 14601 | #define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 |
|---|
| 14602 | #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff |
|---|
| 14603 | #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 |
|---|
| 14604 | #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 |
|---|
| 14605 | #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 |
|---|
| 14606 | #define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 |
|---|
| 14607 | #define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 14608 | #define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 |
|---|
| 14609 | #define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 |
|---|
| 14610 | #define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 |
|---|
| 14611 | #define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 |
|---|
| 14612 | #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff |
|---|
| 14613 | #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 |
|---|
| 14614 | #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 |
|---|
| 14615 | #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 |
|---|
| 14616 | #define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1 |
|---|
| 14617 | #define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 |
|---|
| 14618 | #define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff |
|---|
| 14619 | #define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 |
|---|
| 14620 | #define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 |
|---|
| 14621 | #define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 |
|---|
| 14622 | #define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff |
|---|
| 14623 | #define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 |
|---|
| 14624 | #define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 |
|---|
| 14625 | #define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 |
|---|
| 14626 | #define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff |
|---|
| 14627 | #define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 |
|---|
| 14628 | #define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 |
|---|
| 14629 | #define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 |
|---|
| 14630 | #define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff |
|---|
| 14631 | #define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 |
|---|
| 14632 | #define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 |
|---|
| 14633 | #define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 |
|---|
| 14634 | #define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff |
|---|
| 14635 | #define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 |
|---|
| 14636 | #define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 |
|---|
| 14637 | #define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 |
|---|
| 14638 | #define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff |
|---|
| 14639 | #define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 |
|---|
| 14640 | #define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 |
|---|
| 14641 | #define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 |
|---|
| 14642 | #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff |
|---|
| 14643 | #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 |
|---|
| 14644 | #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff |
|---|
| 14645 | #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 |
|---|
| 14646 | #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff |
|---|
| 14647 | #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 |
|---|
| 14648 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff |
|---|
| 14649 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 |
|---|
| 14650 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 |
|---|
| 14651 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 |
|---|
| 14652 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff |
|---|
| 14653 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 |
|---|
| 14654 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 |
|---|
| 14655 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 |
|---|
| 14656 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff |
|---|
| 14657 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 |
|---|
| 14658 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 |
|---|
| 14659 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 |
|---|
| 14660 | #define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 |
|---|
| 14661 | #define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 |
|---|
| 14662 | #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 |
|---|
| 14663 | #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 |
|---|
| 14664 | #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 |
|---|
| 14665 | #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 |
|---|
| 14666 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0 |
|---|
| 14667 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 |
|---|
| 14668 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 |
|---|
| 14669 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 |
|---|
| 14670 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0 |
|---|
| 14671 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 |
|---|
| 14672 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 |
|---|
| 14673 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
|---|
| 14674 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0 |
|---|
| 14675 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 |
|---|
| 14676 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 |
|---|
| 14677 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
|---|
| 14678 | #define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1 |
|---|
| 14679 | #define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 |
|---|
| 14680 | #define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0 |
|---|
| 14681 | #define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 |
|---|
| 14682 | #define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1 |
|---|
| 14683 | #define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 |
|---|
| 14684 | #define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2 |
|---|
| 14685 | #define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 |
|---|
| 14686 | #define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4 |
|---|
| 14687 | #define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 |
|---|
| 14688 | #define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8 |
|---|
| 14689 | #define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 |
|---|
| 14690 | #define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100 |
|---|
| 14691 | #define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 |
|---|
| 14692 | #define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000 |
|---|
| 14693 | #define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 |
|---|
| 14694 | #define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff |
|---|
| 14695 | #define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 |
|---|
| 14696 | #define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3 |
|---|
| 14697 | #define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 |
|---|
| 14698 | #define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c |
|---|
| 14699 | #define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 |
|---|
| 14700 | #define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1 |
|---|
| 14701 | #define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 |
|---|
| 14702 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 14703 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 14704 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 14705 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 14706 | #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 14707 | #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 14708 | #define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 |
|---|
| 14709 | #define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 |
|---|
| 14710 | #define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 |
|---|
| 14711 | #define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 |
|---|
| 14712 | #define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 |
|---|
| 14713 | #define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc |
|---|
| 14714 | #define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000 |
|---|
| 14715 | #define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18 |
|---|
| 14716 | #define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000 |
|---|
| 14717 | #define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f |
|---|
| 14718 | #define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1 |
|---|
| 14719 | #define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
|---|
| 14720 | #define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2 |
|---|
| 14721 | #define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1 |
|---|
| 14722 | #define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4 |
|---|
| 14723 | #define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2 |
|---|
| 14724 | #define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8 |
|---|
| 14725 | #define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3 |
|---|
| 14726 | #define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 |
|---|
| 14727 | #define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 |
|---|
| 14728 | #define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1 |
|---|
| 14729 | #define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0 |
|---|
| 14730 | #define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0 |
|---|
| 14731 | #define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4 |
|---|
| 14732 | #define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8 |
|---|
| 14733 | #define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3 |
|---|
| 14734 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80 |
|---|
| 14735 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7 |
|---|
| 14736 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200 |
|---|
| 14737 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9 |
|---|
| 14738 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800 |
|---|
| 14739 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb |
|---|
| 14740 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000 |
|---|
| 14741 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd |
|---|
| 14742 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000 |
|---|
| 14743 | #define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf |
|---|
| 14744 | #define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000 |
|---|
| 14745 | #define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18 |
|---|
| 14746 | #define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000 |
|---|
| 14747 | #define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f |
|---|
| 14748 | #define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1 |
|---|
| 14749 | #define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
|---|
| 14750 | #define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2 |
|---|
| 14751 | #define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1 |
|---|
| 14752 | #define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4 |
|---|
| 14753 | #define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2 |
|---|
| 14754 | #define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8 |
|---|
| 14755 | #define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3 |
|---|
| 14756 | #define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 |
|---|
| 14757 | #define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 |
|---|
| 14758 | #define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20 |
|---|
| 14759 | #define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5 |
|---|
| 14760 | #define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40 |
|---|
| 14761 | #define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6 |
|---|
| 14762 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8 |
|---|
| 14763 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3 |
|---|
| 14764 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10 |
|---|
| 14765 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4 |
|---|
| 14766 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20 |
|---|
| 14767 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5 |
|---|
| 14768 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40 |
|---|
| 14769 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6 |
|---|
| 14770 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000 |
|---|
| 14771 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18 |
|---|
| 14772 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000 |
|---|
| 14773 | #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f |
|---|
| 14774 | #define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1 |
|---|
| 14775 | #define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0 |
|---|
| 14776 | #define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0 |
|---|
| 14777 | #define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4 |
|---|
| 14778 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3 |
|---|
| 14779 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0 |
|---|
| 14780 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4 |
|---|
| 14781 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2 |
|---|
| 14782 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8 |
|---|
| 14783 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3 |
|---|
| 14784 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10 |
|---|
| 14785 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4 |
|---|
| 14786 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20 |
|---|
| 14787 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5 |
|---|
| 14788 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40 |
|---|
| 14789 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6 |
|---|
| 14790 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80 |
|---|
| 14791 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7 |
|---|
| 14792 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100 |
|---|
| 14793 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8 |
|---|
| 14794 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200 |
|---|
| 14795 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9 |
|---|
| 14796 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400 |
|---|
| 14797 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa |
|---|
| 14798 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800 |
|---|
| 14799 | #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb |
|---|
| 14800 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3 |
|---|
| 14801 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0 |
|---|
| 14802 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc |
|---|
| 14803 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2 |
|---|
| 14804 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30 |
|---|
| 14805 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4 |
|---|
| 14806 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0 |
|---|
| 14807 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6 |
|---|
| 14808 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300 |
|---|
| 14809 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8 |
|---|
| 14810 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00 |
|---|
| 14811 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa |
|---|
| 14812 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000 |
|---|
| 14813 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc |
|---|
| 14814 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000 |
|---|
| 14815 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe |
|---|
| 14816 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000 |
|---|
| 14817 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10 |
|---|
| 14818 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000 |
|---|
| 14819 | #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12 |
|---|
| 14820 | #define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1 |
|---|
| 14821 | #define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
|---|
| 14822 | #define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2 |
|---|
| 14823 | #define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
|---|
| 14824 | #define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10 |
|---|
| 14825 | #define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
|---|
| 14826 | #define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100 |
|---|
| 14827 | #define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
|---|
| 14828 | #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
|---|
| 14829 | #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
|---|
| 14830 | #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
|---|
| 14831 | #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
|---|
| 14832 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1 |
|---|
| 14833 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
|---|
| 14834 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100 |
|---|
| 14835 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
|---|
| 14836 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000 |
|---|
| 14837 | #define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
|---|
| 14838 | #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000 |
|---|
| 14839 | #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
|---|
| 14840 | #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000 |
|---|
| 14841 | #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
|---|
| 14842 | #define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff |
|---|
| 14843 | #define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
|---|
| 14844 | #define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000 |
|---|
| 14845 | #define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
|---|
| 14846 | #define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000 |
|---|
| 14847 | #define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
|---|
| 14848 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff |
|---|
| 14849 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
|---|
| 14850 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
|---|
| 14851 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
|---|
| 14852 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000 |
|---|
| 14853 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
|---|
| 14854 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
|---|
| 14855 | #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
|---|
| 14856 | #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff |
|---|
| 14857 | #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
|---|
| 14858 | #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000 |
|---|
| 14859 | #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
|---|
| 14860 | #define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff |
|---|
| 14861 | #define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0 |
|---|
| 14862 | #define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff |
|---|
| 14863 | #define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0 |
|---|
| 14864 | #define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff |
|---|
| 14865 | #define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0 |
|---|
| 14866 | #define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff |
|---|
| 14867 | #define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0 |
|---|
| 14868 | #define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff |
|---|
| 14869 | #define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0 |
|---|
| 14870 | #define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff |
|---|
| 14871 | #define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0 |
|---|
| 14872 | #define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff |
|---|
| 14873 | #define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0 |
|---|
| 14874 | #define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff |
|---|
| 14875 | #define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0 |
|---|
| 14876 | #define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 |
|---|
| 14877 | #define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 |
|---|
| 14878 | #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 |
|---|
| 14879 | #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 |
|---|
| 14880 | #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 14881 | #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 14882 | #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 14883 | #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 14884 | #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 14885 | #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 14886 | #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 14887 | #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 14888 | #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 14889 | #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 14890 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 14891 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 14892 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 14893 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 14894 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 14895 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 14896 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 14897 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 14898 | #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 14899 | #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 14900 | #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 14901 | #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 14902 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 14903 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 14904 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 14905 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 14906 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 |
|---|
| 14907 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 |
|---|
| 14908 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 |
|---|
| 14909 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 14910 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 14911 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 14912 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 14913 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 14914 | #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 |
|---|
| 14915 | #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 |
|---|
| 14916 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 |
|---|
| 14917 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 |
|---|
| 14918 | #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 |
|---|
| 14919 | #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 |
|---|
| 14920 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 |
|---|
| 14921 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 |
|---|
| 14922 | #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 |
|---|
| 14923 | #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 |
|---|
| 14924 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 |
|---|
| 14925 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a |
|---|
| 14926 | #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 |
|---|
| 14927 | #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b |
|---|
| 14928 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 |
|---|
| 14929 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c |
|---|
| 14930 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 |
|---|
| 14931 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d |
|---|
| 14932 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 |
|---|
| 14933 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e |
|---|
| 14934 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 |
|---|
| 14935 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f |
|---|
| 14936 | #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 14937 | #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 14938 | #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 14939 | #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 14940 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 14941 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 14942 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 14943 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 14944 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 14945 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 14946 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 14947 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 14948 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 14949 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 14950 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 14951 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 14952 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 14953 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 14954 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 14955 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 14956 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 14957 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 14958 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 14959 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 14960 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 14961 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 14962 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 |
|---|
| 14963 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 |
|---|
| 14964 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 |
|---|
| 14965 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 14966 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 14967 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 14968 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 14969 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 14970 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 |
|---|
| 14971 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 |
|---|
| 14972 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 |
|---|
| 14973 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 |
|---|
| 14974 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 |
|---|
| 14975 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 |
|---|
| 14976 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
|---|
| 14977 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
|---|
| 14978 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
|---|
| 14979 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
|---|
| 14980 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
|---|
| 14981 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
|---|
| 14982 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 |
|---|
| 14983 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c |
|---|
| 14984 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 |
|---|
| 14985 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d |
|---|
| 14986 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 |
|---|
| 14987 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e |
|---|
| 14988 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 |
|---|
| 14989 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f |
|---|
| 14990 | #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 14991 | #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 14992 | #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 14993 | #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 14994 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 14995 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 14996 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 14997 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 14998 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 14999 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 15000 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 15001 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 15002 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 15003 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 15004 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 15005 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 15006 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 15007 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 15008 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 15009 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 15010 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 15011 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 15012 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 15013 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 15014 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 15015 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 15016 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 |
|---|
| 15017 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 |
|---|
| 15018 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 |
|---|
| 15019 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 15020 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 15021 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 15022 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 15023 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 15024 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 |
|---|
| 15025 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 |
|---|
| 15026 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 |
|---|
| 15027 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 |
|---|
| 15028 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 |
|---|
| 15029 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 |
|---|
| 15030 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
|---|
| 15031 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
|---|
| 15032 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
|---|
| 15033 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
|---|
| 15034 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
|---|
| 15035 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
|---|
| 15036 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 |
|---|
| 15037 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c |
|---|
| 15038 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 |
|---|
| 15039 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d |
|---|
| 15040 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 |
|---|
| 15041 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e |
|---|
| 15042 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 |
|---|
| 15043 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f |
|---|
| 15044 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 15045 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 15046 | #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 15047 | #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 15048 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 15049 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 15050 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 15051 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 15052 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 15053 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 15054 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 15055 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 15056 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 15057 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 15058 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 15059 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 15060 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 15061 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 15062 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 15063 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 15064 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 15065 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 15066 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 15067 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 15068 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 15069 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 15070 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 |
|---|
| 15071 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 |
|---|
| 15072 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 |
|---|
| 15073 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 15074 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 15075 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 15076 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 15077 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 15078 | #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 |
|---|
| 15079 | #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 |
|---|
| 15080 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 |
|---|
| 15081 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 |
|---|
| 15082 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 |
|---|
| 15083 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 |
|---|
| 15084 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
|---|
| 15085 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
|---|
| 15086 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
|---|
| 15087 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
|---|
| 15088 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
|---|
| 15089 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
|---|
| 15090 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 |
|---|
| 15091 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c |
|---|
| 15092 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 |
|---|
| 15093 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d |
|---|
| 15094 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 |
|---|
| 15095 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e |
|---|
| 15096 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 |
|---|
| 15097 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f |
|---|
| 15098 | #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 15099 | #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 15100 | #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 15101 | #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 15102 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 15103 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 15104 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 15105 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 15106 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 15107 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 15108 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 15109 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 15110 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 15111 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 15112 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 15113 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 15114 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 15115 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 15116 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 15117 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 15118 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 15119 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 15120 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 15121 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 15122 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 15123 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 15124 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 |
|---|
| 15125 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 |
|---|
| 15126 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 |
|---|
| 15127 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 15128 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 15129 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 15130 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 15131 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 15132 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 |
|---|
| 15133 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
|---|
| 15134 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 |
|---|
| 15135 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
|---|
| 15136 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 |
|---|
| 15137 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
|---|
| 15138 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
|---|
| 15139 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
|---|
| 15140 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
|---|
| 15141 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
|---|
| 15142 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
|---|
| 15143 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
|---|
| 15144 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 |
|---|
| 15145 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c |
|---|
| 15146 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 |
|---|
| 15147 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d |
|---|
| 15148 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 |
|---|
| 15149 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e |
|---|
| 15150 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 |
|---|
| 15151 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f |
|---|
| 15152 | #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 |
|---|
| 15153 | #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
|---|
| 15154 | #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
|---|
| 15155 | #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
|---|
| 15156 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 |
|---|
| 15157 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 |
|---|
| 15158 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 |
|---|
| 15159 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 |
|---|
| 15160 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 |
|---|
| 15161 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
|---|
| 15162 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
|---|
| 15163 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
|---|
| 15164 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
|---|
| 15165 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
|---|
| 15166 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 |
|---|
| 15167 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 |
|---|
| 15168 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 |
|---|
| 15169 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 |
|---|
| 15170 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 |
|---|
| 15171 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
|---|
| 15172 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
|---|
| 15173 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
|---|
| 15174 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 15175 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 15176 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 15177 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 15178 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 |
|---|
| 15179 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 |
|---|
| 15180 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 |
|---|
| 15181 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 |
|---|
| 15182 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 15183 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 15184 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 |
|---|
| 15185 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 |
|---|
| 15186 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 |
|---|
| 15187 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
|---|
| 15188 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 |
|---|
| 15189 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
|---|
| 15190 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 |
|---|
| 15191 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
|---|
| 15192 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 |
|---|
| 15193 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 |
|---|
| 15194 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 |
|---|
| 15195 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a |
|---|
| 15196 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 |
|---|
| 15197 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b |
|---|
| 15198 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 |
|---|
| 15199 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c |
|---|
| 15200 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 |
|---|
| 15201 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d |
|---|
| 15202 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 |
|---|
| 15203 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e |
|---|
| 15204 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 |
|---|
| 15205 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f |
|---|
| 15206 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
|---|
| 15207 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
|---|
| 15208 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
|---|
| 15209 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
|---|
| 15210 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
|---|
| 15211 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
|---|
| 15212 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
|---|
| 15213 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
|---|
| 15214 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
|---|
| 15215 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
|---|
| 15216 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
|---|
| 15217 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
|---|
| 15218 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
|---|
| 15219 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
|---|
| 15220 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
|---|
| 15221 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
|---|
| 15222 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
|---|
| 15223 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
|---|
| 15224 | #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200 |
|---|
| 15225 | #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9 |
|---|
| 15226 | #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400 |
|---|
| 15227 | #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa |
|---|
| 15228 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
|---|
| 15229 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
|---|
| 15230 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
|---|
| 15231 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
|---|
| 15232 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 |
|---|
| 15233 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 |
|---|
| 15234 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 |
|---|
| 15235 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 |
|---|
| 15236 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 |
|---|
| 15237 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 |
|---|
| 15238 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 |
|---|
| 15239 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 |
|---|
| 15240 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 |
|---|
| 15241 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 |
|---|
| 15242 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 |
|---|
| 15243 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 |
|---|
| 15244 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 |
|---|
| 15245 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 |
|---|
| 15246 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 |
|---|
| 15247 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 |
|---|
| 15248 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 |
|---|
| 15249 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 |
|---|
| 15250 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 |
|---|
| 15251 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a |
|---|
| 15252 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 |
|---|
| 15253 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b |
|---|
| 15254 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 |
|---|
| 15255 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c |
|---|
| 15256 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 |
|---|
| 15257 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f |
|---|
| 15258 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
|---|
| 15259 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
|---|
| 15260 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
|---|
| 15261 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
|---|
| 15262 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
|---|
| 15263 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
|---|
| 15264 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
|---|
| 15265 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
|---|
| 15266 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
|---|
| 15267 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
|---|
| 15268 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
|---|
| 15269 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
|---|
| 15270 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
|---|
| 15271 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
|---|
| 15272 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
|---|
| 15273 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
|---|
| 15274 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
|---|
| 15275 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
|---|
| 15276 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
|---|
| 15277 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
|---|
| 15278 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
|---|
| 15279 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
|---|
| 15280 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
|---|
| 15281 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
|---|
| 15282 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
|---|
| 15283 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
|---|
| 15284 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
|---|
| 15285 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
|---|
| 15286 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
|---|
| 15287 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
|---|
| 15288 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
|---|
| 15289 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
|---|
| 15290 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
|---|
| 15291 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
|---|
| 15292 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
|---|
| 15293 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
|---|
| 15294 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
|---|
| 15295 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
|---|
| 15296 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
|---|
| 15297 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
|---|
| 15298 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
|---|
| 15299 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
|---|
| 15300 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
|---|
| 15301 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
|---|
| 15302 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
|---|
| 15303 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
|---|
| 15304 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
|---|
| 15305 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
|---|
| 15306 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
|---|
| 15307 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
|---|
| 15308 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
|---|
| 15309 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
|---|
| 15310 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
|---|
| 15311 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
|---|
| 15312 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 |
|---|
| 15313 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b |
|---|
| 15314 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 |
|---|
| 15315 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c |
|---|
| 15316 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 |
|---|
| 15317 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d |
|---|
| 15318 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 |
|---|
| 15319 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e |
|---|
| 15320 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 |
|---|
| 15321 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f |
|---|
| 15322 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
|---|
| 15323 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
|---|
| 15324 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
|---|
| 15325 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
|---|
| 15326 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
|---|
| 15327 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
|---|
| 15328 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
|---|
| 15329 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
|---|
| 15330 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
|---|
| 15331 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
|---|
| 15332 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
|---|
| 15333 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
|---|
| 15334 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
|---|
| 15335 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
|---|
| 15336 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
|---|
| 15337 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
|---|
| 15338 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
|---|
| 15339 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
|---|
| 15340 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
|---|
| 15341 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
|---|
| 15342 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
|---|
| 15343 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
|---|
| 15344 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
|---|
| 15345 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
|---|
| 15346 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
|---|
| 15347 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
|---|
| 15348 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
|---|
| 15349 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
|---|
| 15350 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
|---|
| 15351 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
|---|
| 15352 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
|---|
| 15353 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
|---|
| 15354 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
|---|
| 15355 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
|---|
| 15356 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
|---|
| 15357 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
|---|
| 15358 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
|---|
| 15359 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
|---|
| 15360 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
|---|
| 15361 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
|---|
| 15362 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
|---|
| 15363 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
|---|
| 15364 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
|---|
| 15365 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
|---|
| 15366 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
|---|
| 15367 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
|---|
| 15368 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
|---|
| 15369 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
|---|
| 15370 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
|---|
| 15371 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
|---|
| 15372 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
|---|
| 15373 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
|---|
| 15374 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
|---|
| 15375 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
|---|
| 15376 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 |
|---|
| 15377 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b |
|---|
| 15378 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 |
|---|
| 15379 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c |
|---|
| 15380 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 |
|---|
| 15381 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d |
|---|
| 15382 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 |
|---|
| 15383 | #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e |
|---|
| 15384 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 |
|---|
| 15385 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f |
|---|
| 15386 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
|---|
| 15387 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
|---|
| 15388 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
|---|
| 15389 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
|---|
| 15390 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
|---|
| 15391 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
|---|
| 15392 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
|---|
| 15393 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
|---|
| 15394 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
|---|
| 15395 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
|---|
| 15396 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
|---|
| 15397 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
|---|
| 15398 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
|---|
| 15399 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
|---|
| 15400 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
|---|
| 15401 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
|---|
| 15402 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
|---|
| 15403 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
|---|
| 15404 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
|---|
| 15405 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
|---|
| 15406 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
|---|
| 15407 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
|---|
| 15408 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
|---|
| 15409 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
|---|
| 15410 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
|---|
| 15411 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
|---|
| 15412 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
|---|
| 15413 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
|---|
| 15414 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
|---|
| 15415 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
|---|
| 15416 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
|---|
| 15417 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
|---|
| 15418 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
|---|
| 15419 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
|---|
| 15420 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
|---|
| 15421 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
|---|
| 15422 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
|---|
| 15423 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
|---|
| 15424 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
|---|
| 15425 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
|---|
| 15426 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
|---|
| 15427 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
|---|
| 15428 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
|---|
| 15429 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
|---|
| 15430 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
|---|
| 15431 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
|---|
| 15432 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
|---|
| 15433 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
|---|
| 15434 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
|---|
| 15435 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
|---|
| 15436 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
|---|
| 15437 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
|---|
| 15438 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
|---|
| 15439 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
|---|
| 15440 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 |
|---|
| 15441 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b |
|---|
| 15442 | #define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1 |
|---|
| 15443 | #define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 |
|---|
| 15444 | #define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK 0x2 |
|---|
| 15445 | #define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT 0x1 |
|---|
| 15446 | #define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4 |
|---|
| 15447 | #define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2 |
|---|
| 15448 | #define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8 |
|---|
| 15449 | #define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 |
|---|
| 15450 | #define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10 |
|---|
| 15451 | #define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 15452 | #define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20 |
|---|
| 15453 | #define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 |
|---|
| 15454 | #define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40 |
|---|
| 15455 | #define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 |
|---|
| 15456 | #define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80 |
|---|
| 15457 | #define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 |
|---|
| 15458 | #define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100 |
|---|
| 15459 | #define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 |
|---|
| 15460 | #define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200 |
|---|
| 15461 | #define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 |
|---|
| 15462 | #define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00 |
|---|
| 15463 | #define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa |
|---|
| 15464 | #define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 15465 | #define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 15466 | #define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000 |
|---|
| 15467 | #define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe |
|---|
| 15468 | #define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000 |
|---|
| 15469 | #define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 |
|---|
| 15470 | #define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000 |
|---|
| 15471 | #define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 |
|---|
| 15472 | #define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000 |
|---|
| 15473 | #define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 |
|---|
| 15474 | #define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000 |
|---|
| 15475 | #define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 |
|---|
| 15476 | #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1 |
|---|
| 15477 | #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 |
|---|
| 15478 | #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2 |
|---|
| 15479 | #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 |
|---|
| 15480 | #define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK 0x4 |
|---|
| 15481 | #define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x2 |
|---|
| 15482 | #define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8 |
|---|
| 15483 | #define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3 |
|---|
| 15484 | #define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10 |
|---|
| 15485 | #define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 |
|---|
| 15486 | #define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20 |
|---|
| 15487 | #define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 |
|---|
| 15488 | #define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40 |
|---|
| 15489 | #define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 |
|---|
| 15490 | #define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80 |
|---|
| 15491 | #define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 |
|---|
| 15492 | #define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100 |
|---|
| 15493 | #define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 |
|---|
| 15494 | #define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200 |
|---|
| 15495 | #define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 |
|---|
| 15496 | #define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400 |
|---|
| 15497 | #define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa |
|---|
| 15498 | #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800 |
|---|
| 15499 | #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb |
|---|
| 15500 | #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 15501 | #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 15502 | #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000 |
|---|
| 15503 | #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 15504 | #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000 |
|---|
| 15505 | #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 |
|---|
| 15506 | #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000 |
|---|
| 15507 | #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 |
|---|
| 15508 | #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000 |
|---|
| 15509 | #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 |
|---|
| 15510 | #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000 |
|---|
| 15511 | #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 |
|---|
| 15512 | #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000 |
|---|
| 15513 | #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 |
|---|
| 15514 | #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000 |
|---|
| 15515 | #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 |
|---|
| 15516 | #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000 |
|---|
| 15517 | #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 |
|---|
| 15518 | #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000 |
|---|
| 15519 | #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a |
|---|
| 15520 | #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000 |
|---|
| 15521 | #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c |
|---|
| 15522 | #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000 |
|---|
| 15523 | #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d |
|---|
| 15524 | #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000 |
|---|
| 15525 | #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f |
|---|
| 15526 | #define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3 |
|---|
| 15527 | #define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 |
|---|
| 15528 | #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f |
|---|
| 15529 | #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0 |
|---|
| 15530 | #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 |
|---|
| 15531 | #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 |
|---|
| 15532 | #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 |
|---|
| 15533 | #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 |
|---|
| 15534 | #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 |
|---|
| 15535 | #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 |
|---|
| 15536 | #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 |
|---|
| 15537 | #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 |
|---|
| 15538 | #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 |
|---|
| 15539 | #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 |
|---|
| 15540 | #define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400 |
|---|
| 15541 | #define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa |
|---|
| 15542 | #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 |
|---|
| 15543 | #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 |
|---|
| 15544 | #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 |
|---|
| 15545 | #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 |
|---|
| 15546 | #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 |
|---|
| 15547 | #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 |
|---|
| 15548 | #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 |
|---|
| 15549 | #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 |
|---|
| 15550 | #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 |
|---|
| 15551 | #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 |
|---|
| 15552 | #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 |
|---|
| 15553 | #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 |
|---|
| 15554 | #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 |
|---|
| 15555 | #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 |
|---|
| 15556 | #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 |
|---|
| 15557 | #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 |
|---|
| 15558 | #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 |
|---|
| 15559 | #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a |
|---|
| 15560 | #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 |
|---|
| 15561 | #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b |
|---|
| 15562 | #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 |
|---|
| 15563 | #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c |
|---|
| 15564 | #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 |
|---|
| 15565 | #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d |
|---|
| 15566 | #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 |
|---|
| 15567 | #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e |
|---|
| 15568 | #define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK 0x10 |
|---|
| 15569 | #define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT 0x4 |
|---|
| 15570 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20 |
|---|
| 15571 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5 |
|---|
| 15572 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40 |
|---|
| 15573 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6 |
|---|
| 15574 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80 |
|---|
| 15575 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7 |
|---|
| 15576 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100 |
|---|
| 15577 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8 |
|---|
| 15578 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200 |
|---|
| 15579 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9 |
|---|
| 15580 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000 |
|---|
| 15581 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10 |
|---|
| 15582 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000 |
|---|
| 15583 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11 |
|---|
| 15584 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000 |
|---|
| 15585 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12 |
|---|
| 15586 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000 |
|---|
| 15587 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13 |
|---|
| 15588 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000 |
|---|
| 15589 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14 |
|---|
| 15590 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000 |
|---|
| 15591 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15 |
|---|
| 15592 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000 |
|---|
| 15593 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18 |
|---|
| 15594 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000 |
|---|
| 15595 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19 |
|---|
| 15596 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000 |
|---|
| 15597 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a |
|---|
| 15598 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000 |
|---|
| 15599 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b |
|---|
| 15600 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000 |
|---|
| 15601 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c |
|---|
| 15602 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000 |
|---|
| 15603 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d |
|---|
| 15604 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000 |
|---|
| 15605 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e |
|---|
| 15606 | #define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1 |
|---|
| 15607 | #define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0 |
|---|
| 15608 | #define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2 |
|---|
| 15609 | #define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1 |
|---|
| 15610 | #define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10 |
|---|
| 15611 | #define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4 |
|---|
| 15612 | #define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100 |
|---|
| 15613 | #define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8 |
|---|
| 15614 | #define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000 |
|---|
| 15615 | #define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10 |
|---|
| 15616 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1 |
|---|
| 15617 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0 |
|---|
| 15618 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2 |
|---|
| 15619 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1 |
|---|
| 15620 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100 |
|---|
| 15621 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8 |
|---|
| 15622 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000 |
|---|
| 15623 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10 |
|---|
| 15624 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000 |
|---|
| 15625 | #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18 |
|---|
| 15626 | #define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 |
|---|
| 15627 | #define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 |
|---|
| 15628 | #define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 |
|---|
| 15629 | #define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 |
|---|
| 15630 | #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 |
|---|
| 15631 | #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 |
|---|
| 15632 | #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 |
|---|
| 15633 | #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 |
|---|
| 15634 | #define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 |
|---|
| 15635 | #define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 |
|---|
| 15636 | #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 |
|---|
| 15637 | #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 |
|---|
| 15638 | #define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000 |
|---|
| 15639 | #define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc |
|---|
| 15640 | #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 |
|---|
| 15641 | #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 |
|---|
| 15642 | #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 |
|---|
| 15643 | #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 |
|---|
| 15644 | #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 |
|---|
| 15645 | #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 |
|---|
| 15646 | #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 |
|---|
| 15647 | #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 |
|---|
| 15648 | #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 |
|---|
| 15649 | #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 |
|---|
| 15650 | #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 |
|---|
| 15651 | #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 |
|---|
| 15652 | #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 |
|---|
| 15653 | #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 |
|---|
| 15654 | #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 |
|---|
| 15655 | #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 |
|---|
| 15656 | #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 |
|---|
| 15657 | #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b |
|---|
| 15658 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 |
|---|
| 15659 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 |
|---|
| 15660 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 |
|---|
| 15661 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 |
|---|
| 15662 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 |
|---|
| 15663 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 |
|---|
| 15664 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 |
|---|
| 15665 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 |
|---|
| 15666 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 |
|---|
| 15667 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 |
|---|
| 15668 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 |
|---|
| 15669 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 |
|---|
| 15670 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 |
|---|
| 15671 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc |
|---|
| 15672 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 |
|---|
| 15673 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd |
|---|
| 15674 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 |
|---|
| 15675 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 |
|---|
| 15676 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 |
|---|
| 15677 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 |
|---|
| 15678 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 |
|---|
| 15679 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 |
|---|
| 15680 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 |
|---|
| 15681 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 |
|---|
| 15682 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 |
|---|
| 15683 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 |
|---|
| 15684 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 |
|---|
| 15685 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 |
|---|
| 15686 | #define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000 |
|---|
| 15687 | #define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f |
|---|
| 15688 | #define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 |
|---|
| 15689 | #define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 |
|---|
| 15690 | #define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 |
|---|
| 15691 | #define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 |
|---|
| 15692 | #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 15693 | #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 15694 | #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 15695 | #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 15696 | #define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 15697 | #define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 15698 | #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 |
|---|
| 15699 | #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 |
|---|
| 15700 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 |
|---|
| 15701 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 |
|---|
| 15702 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 |
|---|
| 15703 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 |
|---|
| 15704 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 |
|---|
| 15705 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 |
|---|
| 15706 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 |
|---|
| 15707 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 |
|---|
| 15708 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 |
|---|
| 15709 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 |
|---|
| 15710 | #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 |
|---|
| 15711 | #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f |
|---|
| 15712 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 |
|---|
| 15713 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 |
|---|
| 15714 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc |
|---|
| 15715 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 |
|---|
| 15716 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 |
|---|
| 15717 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 |
|---|
| 15718 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 |
|---|
| 15719 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 |
|---|
| 15720 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 |
|---|
| 15721 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc |
|---|
| 15722 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 |
|---|
| 15723 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 |
|---|
| 15724 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 |
|---|
| 15725 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 |
|---|
| 15726 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 |
|---|
| 15727 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 |
|---|
| 15728 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 |
|---|
| 15729 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 |
|---|
| 15730 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 |
|---|
| 15731 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 |
|---|
| 15732 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 |
|---|
| 15733 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 |
|---|
| 15734 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 |
|---|
| 15735 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 |
|---|
| 15736 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 |
|---|
| 15737 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 |
|---|
| 15738 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 |
|---|
| 15739 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 |
|---|
| 15740 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 |
|---|
| 15741 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 |
|---|
| 15742 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 |
|---|
| 15743 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 |
|---|
| 15744 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 |
|---|
| 15745 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 |
|---|
| 15746 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 |
|---|
| 15747 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa |
|---|
| 15748 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 |
|---|
| 15749 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc |
|---|
| 15750 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 |
|---|
| 15751 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd |
|---|
| 15752 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 |
|---|
| 15753 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe |
|---|
| 15754 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 |
|---|
| 15755 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 |
|---|
| 15756 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 |
|---|
| 15757 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 |
|---|
| 15758 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 |
|---|
| 15759 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 |
|---|
| 15760 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 |
|---|
| 15761 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 |
|---|
| 15762 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 |
|---|
| 15763 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 |
|---|
| 15764 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 |
|---|
| 15765 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 |
|---|
| 15766 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 |
|---|
| 15767 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 |
|---|
| 15768 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 |
|---|
| 15769 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 |
|---|
| 15770 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 |
|---|
| 15771 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a |
|---|
| 15772 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 |
|---|
| 15773 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b |
|---|
| 15774 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 |
|---|
| 15775 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c |
|---|
| 15776 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 |
|---|
| 15777 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d |
|---|
| 15778 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 |
|---|
| 15779 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 |
|---|
| 15780 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 |
|---|
| 15781 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 |
|---|
| 15782 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 |
|---|
| 15783 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 |
|---|
| 15784 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 |
|---|
| 15785 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 |
|---|
| 15786 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 |
|---|
| 15787 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 |
|---|
| 15788 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 |
|---|
| 15789 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 |
|---|
| 15790 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 |
|---|
| 15791 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 |
|---|
| 15792 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 |
|---|
| 15793 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc |
|---|
| 15794 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 |
|---|
| 15795 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd |
|---|
| 15796 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 |
|---|
| 15797 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe |
|---|
| 15798 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 |
|---|
| 15799 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf |
|---|
| 15800 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 |
|---|
| 15801 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 |
|---|
| 15802 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 |
|---|
| 15803 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 |
|---|
| 15804 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 |
|---|
| 15805 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 |
|---|
| 15806 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 |
|---|
| 15807 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 |
|---|
| 15808 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 |
|---|
| 15809 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 |
|---|
| 15810 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15811 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15812 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15813 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15814 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15815 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15816 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 |
|---|
| 15817 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 |
|---|
| 15818 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 |
|---|
| 15819 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 |
|---|
| 15820 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 |
|---|
| 15821 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 |
|---|
| 15822 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 |
|---|
| 15823 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 |
|---|
| 15824 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15825 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15826 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15827 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15828 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15829 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15830 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 |
|---|
| 15831 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 |
|---|
| 15832 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 |
|---|
| 15833 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 |
|---|
| 15834 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 |
|---|
| 15835 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 |
|---|
| 15836 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 |
|---|
| 15837 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 |
|---|
| 15838 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15839 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15840 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15841 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15842 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15843 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15844 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 |
|---|
| 15845 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 |
|---|
| 15846 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 |
|---|
| 15847 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 |
|---|
| 15848 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 |
|---|
| 15849 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 |
|---|
| 15850 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 |
|---|
| 15851 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 |
|---|
| 15852 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15853 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15854 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15855 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15856 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15857 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15858 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 |
|---|
| 15859 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 |
|---|
| 15860 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 |
|---|
| 15861 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 |
|---|
| 15862 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 |
|---|
| 15863 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 |
|---|
| 15864 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 |
|---|
| 15865 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 |
|---|
| 15866 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15867 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15868 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15869 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15870 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15871 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15872 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 |
|---|
| 15873 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 |
|---|
| 15874 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 |
|---|
| 15875 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 |
|---|
| 15876 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 |
|---|
| 15877 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 |
|---|
| 15878 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 |
|---|
| 15879 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 |
|---|
| 15880 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 15881 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 15882 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 15883 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 15884 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 15885 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 15886 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 |
|---|
| 15887 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 |
|---|
| 15888 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 15889 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 15890 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 15891 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 15892 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 |
|---|
| 15893 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 |
|---|
| 15894 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 15895 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 15896 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 15897 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 15898 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 15899 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 15900 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 15901 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 15902 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 |
|---|
| 15903 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 |
|---|
| 15904 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 15905 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 15906 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 15907 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 15908 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 15909 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 15910 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 |
|---|
| 15911 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 |
|---|
| 15912 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 |
|---|
| 15913 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 |
|---|
| 15914 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 15915 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 15916 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 15917 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 15918 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 |
|---|
| 15919 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 |
|---|
| 15920 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 15921 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 15922 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 15923 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 15924 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 15925 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 15926 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 15927 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 15928 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 |
|---|
| 15929 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 |
|---|
| 15930 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 15931 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 15932 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 15933 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 15934 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 15935 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 15936 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 |
|---|
| 15937 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 |
|---|
| 15938 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 |
|---|
| 15939 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 |
|---|
| 15940 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 15941 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 15942 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 15943 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 15944 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 |
|---|
| 15945 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 |
|---|
| 15946 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 15947 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 15948 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 15949 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 15950 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 15951 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 15952 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 15953 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 15954 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 |
|---|
| 15955 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 |
|---|
| 15956 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 15957 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 15958 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 15959 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 15960 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 15961 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 15962 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 |
|---|
| 15963 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 |
|---|
| 15964 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 |
|---|
| 15965 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 |
|---|
| 15966 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 15967 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 15968 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 15969 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 15970 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 |
|---|
| 15971 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 |
|---|
| 15972 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 15973 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 15974 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 15975 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 15976 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 15977 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 15978 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 15979 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 15980 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 |
|---|
| 15981 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 |
|---|
| 15982 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 15983 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 15984 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 15985 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 15986 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 15987 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 15988 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 |
|---|
| 15989 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 |
|---|
| 15990 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 |
|---|
| 15991 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 |
|---|
| 15992 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 15993 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 15994 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 15995 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 15996 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 |
|---|
| 15997 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 |
|---|
| 15998 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 15999 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 16000 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 16001 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 16002 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 16003 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 16004 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 16005 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 16006 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 |
|---|
| 16007 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 |
|---|
| 16008 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 16009 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 16010 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 16011 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 16012 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 16013 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 16014 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 |
|---|
| 16015 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 |
|---|
| 16016 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 |
|---|
| 16017 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 |
|---|
| 16018 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 16019 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 16020 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 16021 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 16022 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 |
|---|
| 16023 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 |
|---|
| 16024 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 16025 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 16026 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 16027 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 16028 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 16029 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 16030 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 16031 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 16032 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 |
|---|
| 16033 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 |
|---|
| 16034 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 16035 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 16036 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 16037 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 16038 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 16039 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 16040 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 |
|---|
| 16041 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 |
|---|
| 16042 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 |
|---|
| 16043 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 |
|---|
| 16044 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 |
|---|
| 16045 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 |
|---|
| 16046 | #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 |
|---|
| 16047 | #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc |
|---|
| 16048 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 |
|---|
| 16049 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd |
|---|
| 16050 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 |
|---|
| 16051 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 |
|---|
| 16052 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 |
|---|
| 16053 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 |
|---|
| 16054 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 |
|---|
| 16055 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 |
|---|
| 16056 | #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 |
|---|
| 16057 | #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc |
|---|
| 16058 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 |
|---|
| 16059 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd |
|---|
| 16060 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 |
|---|
| 16061 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 |
|---|
| 16062 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 |
|---|
| 16063 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 |
|---|
| 16064 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 |
|---|
| 16065 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 |
|---|
| 16066 | #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 |
|---|
| 16067 | #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc |
|---|
| 16068 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 |
|---|
| 16069 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd |
|---|
| 16070 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 |
|---|
| 16071 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 |
|---|
| 16072 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 |
|---|
| 16073 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 |
|---|
| 16074 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 |
|---|
| 16075 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 |
|---|
| 16076 | #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 |
|---|
| 16077 | #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc |
|---|
| 16078 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 |
|---|
| 16079 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd |
|---|
| 16080 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 |
|---|
| 16081 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 |
|---|
| 16082 | #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 |
|---|
| 16083 | #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 |
|---|
| 16084 | #define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 |
|---|
| 16085 | #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 |
|---|
| 16086 | #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 |
|---|
| 16087 | #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 |
|---|
| 16088 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 |
|---|
| 16089 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f |
|---|
| 16090 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 |
|---|
| 16091 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 |
|---|
| 16092 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 |
|---|
| 16093 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 |
|---|
| 16094 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 |
|---|
| 16095 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 |
|---|
| 16096 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 |
|---|
| 16097 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 |
|---|
| 16098 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 |
|---|
| 16099 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 |
|---|
| 16100 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
|---|
| 16101 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
|---|
| 16102 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 |
|---|
| 16103 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c |
|---|
| 16104 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 |
|---|
| 16105 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 |
|---|
| 16106 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 16107 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 16108 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 16109 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 16110 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 |
|---|
| 16111 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 |
|---|
| 16112 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 16113 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 16114 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 16115 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 16116 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 |
|---|
| 16117 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 |
|---|
| 16118 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 |
|---|
| 16119 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 |
|---|
| 16120 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 |
|---|
| 16121 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 |
|---|
| 16122 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 16123 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 16124 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 16125 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 16126 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
|---|
| 16127 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
|---|
| 16128 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 |
|---|
| 16129 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 |
|---|
| 16130 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff |
|---|
| 16131 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 |
|---|
| 16132 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 |
|---|
| 16133 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 |
|---|
| 16134 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 |
|---|
| 16135 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c |
|---|
| 16136 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1 |
|---|
| 16137 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 |
|---|
| 16138 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2 |
|---|
| 16139 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 |
|---|
| 16140 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4 |
|---|
| 16141 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 |
|---|
| 16142 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8 |
|---|
| 16143 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 |
|---|
| 16144 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10 |
|---|
| 16145 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 |
|---|
| 16146 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20 |
|---|
| 16147 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 |
|---|
| 16148 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40 |
|---|
| 16149 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 |
|---|
| 16150 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80 |
|---|
| 16151 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 |
|---|
| 16152 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100 |
|---|
| 16153 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 |
|---|
| 16154 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200 |
|---|
| 16155 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 |
|---|
| 16156 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400 |
|---|
| 16157 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa |
|---|
| 16158 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800 |
|---|
| 16159 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb |
|---|
| 16160 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000 |
|---|
| 16161 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc |
|---|
| 16162 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000 |
|---|
| 16163 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd |
|---|
| 16164 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000 |
|---|
| 16165 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe |
|---|
| 16166 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000 |
|---|
| 16167 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf |
|---|
| 16168 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000 |
|---|
| 16169 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 |
|---|
| 16170 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000 |
|---|
| 16171 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 |
|---|
| 16172 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000 |
|---|
| 16173 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 |
|---|
| 16174 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000 |
|---|
| 16175 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 |
|---|
| 16176 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000 |
|---|
| 16177 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 |
|---|
| 16178 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000 |
|---|
| 16179 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 |
|---|
| 16180 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000 |
|---|
| 16181 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 |
|---|
| 16182 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000 |
|---|
| 16183 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 |
|---|
| 16184 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000 |
|---|
| 16185 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 |
|---|
| 16186 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000 |
|---|
| 16187 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 |
|---|
| 16188 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000 |
|---|
| 16189 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a |
|---|
| 16190 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000 |
|---|
| 16191 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b |
|---|
| 16192 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000 |
|---|
| 16193 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e |
|---|
| 16194 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000 |
|---|
| 16195 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f |
|---|
| 16196 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 |
|---|
| 16197 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 |
|---|
| 16198 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 |
|---|
| 16199 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 |
|---|
| 16200 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 |
|---|
| 16201 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 |
|---|
| 16202 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 |
|---|
| 16203 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 |
|---|
| 16204 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 |
|---|
| 16205 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f |
|---|
| 16206 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 |
|---|
| 16207 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 |
|---|
| 16208 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 |
|---|
| 16209 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 |
|---|
| 16210 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 |
|---|
| 16211 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 |
|---|
| 16212 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100 |
|---|
| 16213 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8 |
|---|
| 16214 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200 |
|---|
| 16215 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9 |
|---|
| 16216 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400 |
|---|
| 16217 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa |
|---|
| 16218 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800 |
|---|
| 16219 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb |
|---|
| 16220 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000 |
|---|
| 16221 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc |
|---|
| 16222 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf |
|---|
| 16223 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 |
|---|
| 16224 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 |
|---|
| 16225 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 |
|---|
| 16226 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 |
|---|
| 16227 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 |
|---|
| 16228 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 |
|---|
| 16229 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 |
|---|
| 16230 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 |
|---|
| 16231 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 |
|---|
| 16232 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 |
|---|
| 16233 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa |
|---|
| 16234 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 |
|---|
| 16235 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 |
|---|
| 16236 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
|---|
| 16237 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
|---|
| 16238 | #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300 |
|---|
| 16239 | #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 |
|---|
| 16240 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 |
|---|
| 16241 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 |
|---|
| 16242 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 |
|---|
| 16243 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 |
|---|
| 16244 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 |
|---|
| 16245 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 |
|---|
| 16246 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 |
|---|
| 16247 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 |
|---|
| 16248 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 |
|---|
| 16249 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 |
|---|
| 16250 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 |
|---|
| 16251 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 |
|---|
| 16252 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 |
|---|
| 16253 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 |
|---|
| 16254 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 |
|---|
| 16255 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 |
|---|
| 16256 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 |
|---|
| 16257 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 |
|---|
| 16258 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 |
|---|
| 16259 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc |
|---|
| 16260 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 |
|---|
| 16261 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd |
|---|
| 16262 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 |
|---|
| 16263 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 |
|---|
| 16264 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 |
|---|
| 16265 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 |
|---|
| 16266 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 |
|---|
| 16267 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 |
|---|
| 16268 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 |
|---|
| 16269 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 |
|---|
| 16270 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 |
|---|
| 16271 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f |
|---|
| 16272 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f |
|---|
| 16273 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 |
|---|
| 16274 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 |
|---|
| 16275 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 |
|---|
| 16276 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 |
|---|
| 16277 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 |
|---|
| 16278 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 |
|---|
| 16279 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 |
|---|
| 16280 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 |
|---|
| 16281 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 |
|---|
| 16282 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 |
|---|
| 16283 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 |
|---|
| 16284 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 |
|---|
| 16285 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 |
|---|
| 16286 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 |
|---|
| 16287 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 |
|---|
| 16288 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 |
|---|
| 16289 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 |
|---|
| 16290 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 |
|---|
| 16291 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc |
|---|
| 16292 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 |
|---|
| 16293 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 |
|---|
| 16294 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf |
|---|
| 16295 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 |
|---|
| 16296 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 |
|---|
| 16297 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 |
|---|
| 16298 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 |
|---|
| 16299 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 |
|---|
| 16300 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 |
|---|
| 16301 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa |
|---|
| 16302 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 |
|---|
| 16303 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc |
|---|
| 16304 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 |
|---|
| 16305 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 |
|---|
| 16306 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 |
|---|
| 16307 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 |
|---|
| 16308 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 |
|---|
| 16309 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 |
|---|
| 16310 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 |
|---|
| 16311 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b |
|---|
| 16312 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 |
|---|
| 16313 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 |
|---|
| 16314 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 |
|---|
| 16315 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 |
|---|
| 16316 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 |
|---|
| 16317 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa |
|---|
| 16318 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 |
|---|
| 16319 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 |
|---|
| 16320 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 |
|---|
| 16321 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 |
|---|
| 16322 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 |
|---|
| 16323 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 |
|---|
| 16324 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 |
|---|
| 16325 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 |
|---|
| 16326 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 |
|---|
| 16327 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 |
|---|
| 16328 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 |
|---|
| 16329 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 |
|---|
| 16330 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 16331 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 16332 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 16333 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 16334 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 |
|---|
| 16335 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf |
|---|
| 16336 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 |
|---|
| 16337 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 |
|---|
| 16338 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 |
|---|
| 16339 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 |
|---|
| 16340 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 |
|---|
| 16341 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 |
|---|
| 16342 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 |
|---|
| 16343 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 |
|---|
| 16344 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 |
|---|
| 16345 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 |
|---|
| 16346 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 |
|---|
| 16347 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 |
|---|
| 16348 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 |
|---|
| 16349 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 |
|---|
| 16350 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 |
|---|
| 16351 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 |
|---|
| 16352 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 |
|---|
| 16353 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 |
|---|
| 16354 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 |
|---|
| 16355 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 |
|---|
| 16356 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3 |
|---|
| 16357 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0 |
|---|
| 16358 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc |
|---|
| 16359 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2 |
|---|
| 16360 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000 |
|---|
| 16361 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13 |
|---|
| 16362 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000 |
|---|
| 16363 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15 |
|---|
| 16364 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000 |
|---|
| 16365 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16 |
|---|
| 16366 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000 |
|---|
| 16367 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19 |
|---|
| 16368 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000 |
|---|
| 16369 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a |
|---|
| 16370 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000 |
|---|
| 16371 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c |
|---|
| 16372 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000 |
|---|
| 16373 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d |
|---|
| 16374 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000 |
|---|
| 16375 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f |
|---|
| 16376 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf |
|---|
| 16377 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 |
|---|
| 16378 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 |
|---|
| 16379 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 |
|---|
| 16380 | #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff |
|---|
| 16381 | #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 |
|---|
| 16382 | #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 |
|---|
| 16383 | #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 |
|---|
| 16384 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 16385 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 16386 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 16387 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 16388 | #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 16389 | #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 16390 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 |
|---|
| 16391 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 |
|---|
| 16392 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 |
|---|
| 16393 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 |
|---|
| 16394 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 |
|---|
| 16395 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf |
|---|
| 16396 | #define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff |
|---|
| 16397 | #define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 |
|---|
| 16398 | #define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff |
|---|
| 16399 | #define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 |
|---|
| 16400 | #define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff |
|---|
| 16401 | #define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 |
|---|
| 16402 | #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 |
|---|
| 16403 | #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 |
|---|
| 16404 | #define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 |
|---|
| 16405 | #define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 |
|---|
| 16406 | #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 |
|---|
| 16407 | #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a |
|---|
| 16408 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 16409 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 16410 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 16411 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 16412 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 |
|---|
| 16413 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 |
|---|
| 16414 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400 |
|---|
| 16415 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa |
|---|
| 16416 | #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 16417 | #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 16418 | #define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 |
|---|
| 16419 | #define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc |
|---|
| 16420 | #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 |
|---|
| 16421 | #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe |
|---|
| 16422 | #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 |
|---|
| 16423 | #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 |
|---|
| 16424 | #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 |
|---|
| 16425 | #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 |
|---|
| 16426 | #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 |
|---|
| 16427 | #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 |
|---|
| 16428 | #define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 |
|---|
| 16429 | #define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 |
|---|
| 16430 | #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff |
|---|
| 16431 | #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 |
|---|
| 16432 | #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 |
|---|
| 16433 | #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 |
|---|
| 16434 | #define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 |
|---|
| 16435 | #define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c |
|---|
| 16436 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 |
|---|
| 16437 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 |
|---|
| 16438 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 |
|---|
| 16439 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc |
|---|
| 16440 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 |
|---|
| 16441 | #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 |
|---|
| 16442 | #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff |
|---|
| 16443 | #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 |
|---|
| 16444 | #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff |
|---|
| 16445 | #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 |
|---|
| 16446 | #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff |
|---|
| 16447 | #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 |
|---|
| 16448 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 |
|---|
| 16449 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 |
|---|
| 16450 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 |
|---|
| 16451 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 |
|---|
| 16452 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 |
|---|
| 16453 | #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc |
|---|
| 16454 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 |
|---|
| 16455 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 |
|---|
| 16456 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 |
|---|
| 16457 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 |
|---|
| 16458 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 |
|---|
| 16459 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 |
|---|
| 16460 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 |
|---|
| 16461 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc |
|---|
| 16462 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 |
|---|
| 16463 | #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 |
|---|
| 16464 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff |
|---|
| 16465 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 |
|---|
| 16466 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 |
|---|
| 16467 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc |
|---|
| 16468 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 |
|---|
| 16469 | #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 |
|---|
| 16470 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff |
|---|
| 16471 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 |
|---|
| 16472 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 |
|---|
| 16473 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc |
|---|
| 16474 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 |
|---|
| 16475 | #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 |
|---|
| 16476 | #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 |
|---|
| 16477 | #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 |
|---|
| 16478 | #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 |
|---|
| 16479 | #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 |
|---|
| 16480 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff |
|---|
| 16481 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 |
|---|
| 16482 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 |
|---|
| 16483 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 |
|---|
| 16484 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 |
|---|
| 16485 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 |
|---|
| 16486 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 |
|---|
| 16487 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa |
|---|
| 16488 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 |
|---|
| 16489 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb |
|---|
| 16490 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 |
|---|
| 16491 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc |
|---|
| 16492 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 |
|---|
| 16493 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf |
|---|
| 16494 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 |
|---|
| 16495 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 |
|---|
| 16496 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 |
|---|
| 16497 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 |
|---|
| 16498 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 |
|---|
| 16499 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 |
|---|
| 16500 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 |
|---|
| 16501 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a |
|---|
| 16502 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 |
|---|
| 16503 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b |
|---|
| 16504 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000 |
|---|
| 16505 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c |
|---|
| 16506 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000 |
|---|
| 16507 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d |
|---|
| 16508 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000 |
|---|
| 16509 | #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f |
|---|
| 16510 | #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff |
|---|
| 16511 | #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 |
|---|
| 16512 | #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 |
|---|
| 16513 | #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 |
|---|
| 16514 | #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff |
|---|
| 16515 | #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 |
|---|
| 16516 | #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 |
|---|
| 16517 | #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 |
|---|
| 16518 | #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff |
|---|
| 16519 | #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 |
|---|
| 16520 | #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 |
|---|
| 16521 | #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 |
|---|
| 16522 | #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff |
|---|
| 16523 | #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 |
|---|
| 16524 | #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff |
|---|
| 16525 | #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 |
|---|
| 16526 | #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff |
|---|
| 16527 | #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 |
|---|
| 16528 | #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff |
|---|
| 16529 | #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 |
|---|
| 16530 | #define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff |
|---|
| 16531 | #define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 |
|---|
| 16532 | #define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff |
|---|
| 16533 | #define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 |
|---|
| 16534 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff |
|---|
| 16535 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 |
|---|
| 16536 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000 |
|---|
| 16537 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d |
|---|
| 16538 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000 |
|---|
| 16539 | #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f |
|---|
| 16540 | #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff |
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| 16541 | #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 |
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| 16542 | #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 |
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| 16543 | #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 |
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| 16544 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff |
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| 16545 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 |
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| 16546 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 |
|---|
| 16547 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 |
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| 16548 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 |
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| 16549 | #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e |
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| 16550 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff |
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| 16551 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 |
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| 16552 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 |
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| 16553 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc |
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| 16554 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 |
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| 16555 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 |
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| 16556 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 |
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| 16557 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 |
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| 16558 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 |
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| 16559 | #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f |
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| 16560 | #define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 |
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| 16561 | #define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 |
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| 16562 | #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 |
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| 16563 | #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 |
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| 16564 | #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 |
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| 16565 | #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa |
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| 16566 | #define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 |
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| 16567 | #define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc |
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| 16568 | #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 |
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| 16569 | #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 |
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| 16570 | #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 |
|---|
| 16571 | #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 |
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| 16572 | #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 |
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| 16573 | #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 |
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| 16574 | #define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 |
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| 16575 | #define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 |
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| 16576 | #define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000 |
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| 16577 | #define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19 |
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| 16578 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 |
|---|
| 16579 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 |
|---|
| 16580 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 |
|---|
| 16581 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc |
|---|
| 16582 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 |
|---|
| 16583 | #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 |
|---|
| 16584 | #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff |
|---|
| 16585 | #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 |
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| 16586 | #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 |
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| 16587 | #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 |
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| 16588 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 |
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| 16589 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 |
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| 16590 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 |
|---|
| 16591 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 |
|---|
| 16592 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 |
|---|
| 16593 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 |
|---|
| 16594 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 |
|---|
| 16595 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc |
|---|
| 16596 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 |
|---|
| 16597 | #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 |
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| 16598 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 |
|---|
| 16599 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 |
|---|
| 16600 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 |
|---|
| 16601 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 |
|---|
| 16602 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 |
|---|
| 16603 | #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc |
|---|
| 16604 | #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff |
|---|
| 16605 | #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 |
|---|
| 16606 | #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 |
|---|
| 16607 | #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 |
|---|
| 16608 | #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff |
|---|
| 16609 | #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 |
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| 16610 | #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 |
|---|
| 16611 | #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 |
|---|
| 16612 | #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff |
|---|
| 16613 | #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 |
|---|
| 16614 | #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 |
|---|
| 16615 | #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 |
|---|
| 16616 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff |
|---|
| 16617 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 |
|---|
| 16618 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 |
|---|
| 16619 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc |
|---|
| 16620 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 |
|---|
| 16621 | #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 |
|---|
| 16622 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff |
|---|
| 16623 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 |
|---|
| 16624 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 |
|---|
| 16625 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 |
|---|
| 16626 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 |
|---|
| 16627 | #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f |
|---|
| 16628 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff |
|---|
| 16629 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 |
|---|
| 16630 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 |
|---|
| 16631 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc |
|---|
| 16632 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000 |
|---|
| 16633 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16 |
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| 16634 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000 |
|---|
| 16635 | #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18 |
|---|
| 16636 | #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff |
|---|
| 16637 | #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 |
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| 16638 | #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 |
|---|
| 16639 | #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 |
|---|
| 16640 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff |
|---|
| 16641 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 |
|---|
| 16642 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 |
|---|
| 16643 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 |
|---|
| 16644 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 |
|---|
| 16645 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 |
|---|
| 16646 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 |
|---|
| 16647 | #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 |
|---|
| 16648 | #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff |
|---|
| 16649 | #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 |
|---|
| 16650 | #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff |
|---|
| 16651 | #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 |
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| 16652 | |
|---|
| 16653 | #endif /* DCE_10_0_SH_MASK_H */ |
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| 16654 | |
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