| 1 | /* |
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| 2 | * DCE_10_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef DCE_10_0_SH_MASK_H |
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| 25 | #define DCE_10_0_SH_MASK_H |
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| 26 | |
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| 27 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 |
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| 28 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 |
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| 29 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 |
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| 30 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 |
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| 31 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff |
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| 32 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 |
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| 33 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 34 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 35 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 36 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 37 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 38 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 39 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 40 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 41 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 |
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| 42 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 |
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| 43 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 |
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| 44 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 |
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| 45 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff |
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| 46 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 |
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| 47 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 48 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 49 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 50 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 51 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 52 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 53 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 54 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 55 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 |
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| 56 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 |
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| 57 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 |
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| 58 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 |
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| 59 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff |
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| 60 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 |
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| 61 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 62 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 63 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 64 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 65 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 66 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 67 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 68 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 69 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 |
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| 70 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 |
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| 71 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 |
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| 72 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 |
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| 73 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff |
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| 74 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 |
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| 75 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 76 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 77 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 78 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 79 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 80 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 81 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 82 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 83 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 |
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| 84 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 |
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| 85 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 |
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| 86 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 |
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| 87 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff |
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| 88 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 |
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| 89 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 90 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 91 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 92 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 93 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 94 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 95 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 96 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 97 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 |
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| 98 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 |
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| 99 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 |
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| 100 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 |
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| 101 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff |
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| 102 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 |
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| 103 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 |
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| 104 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 |
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| 105 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 |
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| 106 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c |
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| 107 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 |
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| 108 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d |
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| 109 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 |
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| 110 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e |
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| 111 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 |
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| 112 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 |
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| 113 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff |
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| 114 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 |
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| 115 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff |
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| 116 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 |
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| 117 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 |
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| 118 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 |
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| 119 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 |
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| 120 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 |
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| 121 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 |
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| 122 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 |
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| 123 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 |
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| 124 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 |
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| 125 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff |
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| 126 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 127 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
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| 128 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
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| 129 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 130 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 |
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| 131 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff |
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| 132 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 |
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| 133 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff |
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| 134 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 |
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| 135 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff |
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| 136 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 |
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| 137 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff |
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| 138 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 |
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| 139 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff |
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| 140 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 |
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| 141 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff |
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| 142 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 |
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| 143 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 |
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| 144 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 |
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| 145 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 |
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| 146 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 |
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| 147 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 |
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| 148 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 |
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| 149 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 |
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| 150 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 |
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| 151 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 |
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| 152 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 |
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| 153 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 154 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 155 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 156 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 157 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 158 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 159 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 160 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 161 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 162 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 163 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 |
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| 164 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 |
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| 165 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 |
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| 166 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 |
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| 167 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 |
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| 168 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 |
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| 169 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 |
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| 170 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 |
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| 171 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
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| 172 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
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| 173 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
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| 174 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
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| 175 | #define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 |
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| 176 | #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 |
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| 177 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 |
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| 178 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 |
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| 179 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 |
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| 180 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f |
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| 181 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf |
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| 182 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 |
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| 183 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 |
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| 184 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 |
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| 185 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 |
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| 186 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 |
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| 187 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 188 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 189 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff |
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| 190 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 |
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| 191 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 |
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| 192 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 |
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| 193 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 194 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 195 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff |
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| 196 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 |
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| 197 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 |
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| 198 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 |
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| 199 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 200 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 201 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff |
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| 202 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 |
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| 203 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 |
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| 204 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 |
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| 205 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 206 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 207 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff |
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| 208 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 |
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| 209 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 |
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| 210 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 |
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| 211 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 212 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 213 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff |
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| 214 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 |
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| 215 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 |
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| 216 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 |
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| 217 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 218 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 219 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff |
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| 220 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 |
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| 221 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 |
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| 222 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 |
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| 223 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 224 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 225 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff |
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| 226 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 |
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| 227 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 |
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| 228 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 |
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| 229 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 |
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| 230 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c |
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| 231 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 |
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| 232 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d |
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| 233 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 |
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| 234 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e |
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| 235 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 |
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| 236 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f |
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| 237 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 |
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| 238 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 |
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| 239 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 |
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| 240 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 |
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| 241 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 |
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| 242 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 |
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| 243 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 |
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| 244 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 |
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| 245 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 |
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| 246 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 |
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| 247 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 |
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| 248 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 |
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| 249 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 |
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| 250 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 |
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| 251 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 |
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| 252 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 |
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| 253 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 |
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| 254 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 |
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| 255 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 |
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| 256 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 |
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| 257 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 |
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| 258 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa |
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| 259 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 |
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| 260 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 |
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| 261 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 |
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| 262 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 |
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| 263 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 |
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| 264 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f |
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| 265 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 |
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| 266 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 |
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| 267 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 |
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| 268 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 |
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| 269 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 |
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| 270 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc |
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| 271 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 |
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| 272 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 |
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| 273 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 |
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| 274 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 |
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| 275 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 |
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| 276 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 |
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| 277 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 |
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| 278 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 |
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| 279 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 |
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| 280 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c |
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| 281 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 |
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| 282 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d |
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| 283 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 |
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| 284 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e |
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| 285 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 286 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 287 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff |
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| 288 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 |
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| 289 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff |
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| 290 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 |
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| 291 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 |
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| 292 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 |
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| 293 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff |
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| 294 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 |
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| 295 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 |
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| 296 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 |
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| 297 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff |
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| 298 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 |
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| 299 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff |
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| 300 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 |
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| 301 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff |
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| 302 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 |
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| 303 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 |
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| 304 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 |
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| 305 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 306 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 307 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff |
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| 308 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 |
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| 309 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff |
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| 310 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 |
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| 311 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 312 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 313 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 314 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 315 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 316 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 317 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 318 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 319 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 320 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 321 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
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| 322 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
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| 323 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
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| 324 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
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| 325 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
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| 326 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
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| 327 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
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| 328 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
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| 329 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
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| 330 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
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| 331 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff |
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| 332 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 |
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| 333 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff |
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| 334 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 |
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| 335 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff |
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| 336 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 |
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| 337 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff |
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| 338 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 |
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| 339 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff |
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| 340 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 |
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| 341 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff |
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| 342 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 |
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| 343 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff |
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| 344 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 |
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| 345 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff |
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| 346 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 |
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| 347 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff |
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| 348 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 |
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| 349 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff |
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| 350 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 |
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| 351 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff |
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| 352 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 |
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| 353 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff |
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| 354 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 |
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| 355 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff |
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| 356 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 |
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| 357 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff |
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| 358 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 |
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| 359 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff |
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| 360 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 |
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| 361 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff |
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| 362 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 |
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| 363 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff |
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| 364 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 |
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| 365 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff |
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| 366 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 |
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| 367 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff |
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| 368 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 |
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| 369 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff |
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| 370 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 |
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| 371 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff |
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| 372 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 |
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| 373 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff |
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| 374 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 |
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| 375 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff |
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| 376 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 |
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| 377 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff |
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| 378 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 |
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| 379 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff |
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| 380 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 |
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| 381 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff |
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| 382 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 |
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| 383 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff |
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| 384 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 |
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| 385 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff |
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| 386 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 |
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| 387 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff |
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| 388 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 |
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| 389 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff |
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| 390 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 |
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| 391 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 |
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| 392 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa |
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| 393 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 |
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| 394 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 |
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| 395 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 |
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| 396 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f |
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| 397 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff |
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| 398 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 399 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 |
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| 400 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
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| 401 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 402 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 |
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| 403 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 |
|---|
| 404 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 |
|---|
| 405 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 |
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| 406 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 |
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| 407 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 |
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| 408 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc |
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| 409 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 |
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| 410 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 |
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| 411 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 |
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| 412 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f |
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| 413 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff |
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| 414 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 |
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| 415 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 |
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| 416 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 |
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| 417 | #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf |
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| 418 | #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 |
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| 419 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 |
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| 420 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 |
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| 421 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 |
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| 422 | #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 |
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| 423 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 |
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| 424 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 |
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| 425 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 |
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| 426 | #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 |
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| 427 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 |
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| 428 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 |
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| 429 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 |
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| 430 | #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 |
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| 431 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 |
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| 432 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 |
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| 433 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 |
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| 434 | #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb |
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| 435 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 |
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| 436 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc |
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| 437 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 |
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| 438 | #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe |
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| 439 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 |
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| 440 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf |
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| 441 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 |
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| 442 | #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 |
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| 443 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 |
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| 444 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 |
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| 445 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 |
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| 446 | #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 |
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| 447 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 |
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| 448 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 |
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| 449 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 |
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| 450 | #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 |
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| 451 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 |
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| 452 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 |
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| 453 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 |
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| 454 | #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a |
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| 455 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 |
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| 456 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b |
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| 457 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 |
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| 458 | #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d |
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| 459 | #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 |
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| 460 | #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 |
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| 461 | #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc |
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| 462 | #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 |
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| 463 | #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 |
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| 464 | #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 |
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| 465 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 |
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| 466 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 |
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| 467 | #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 |
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| 468 | #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 |
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| 469 | #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 |
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| 470 | #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa |
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| 471 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 |
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| 472 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc |
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| 473 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 |
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| 474 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe |
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| 475 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 |
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| 476 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 |
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| 477 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 |
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| 478 | #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 |
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| 479 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK 0x80000 |
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| 480 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT 0x13 |
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| 481 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK 0x100000 |
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| 482 | #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT 0x14 |
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| 483 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 |
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| 484 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 |
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| 485 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 |
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| 486 | #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 |
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| 487 | #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 |
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| 488 | #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 |
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| 489 | #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc |
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| 490 | #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 |
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| 491 | #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 |
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| 492 | #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 |
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| 493 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 |
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| 494 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 |
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| 495 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 |
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| 496 | #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 |
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| 497 | #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 |
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| 498 | #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa |
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| 499 | #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 |
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| 500 | #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc |
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| 501 | #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 |
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| 502 | #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe |
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| 503 | #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 |
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| 504 | #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 |
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| 505 | #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 |
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| 506 | #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 |
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| 507 | #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 |
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| 508 | #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 |
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| 509 | #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 |
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| 510 | #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 |
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| 511 | #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK 0x1000000 |
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| 512 | #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT 0x18 |
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| 513 | #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff |
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| 514 | #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 |
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| 515 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff |
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| 516 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 |
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| 517 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 |
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| 518 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 |
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| 519 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff |
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| 520 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 |
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| 521 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 |
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| 522 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 |
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| 523 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 |
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| 524 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 |
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| 525 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 |
|---|
| 526 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 |
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| 527 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 |
|---|
| 528 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 |
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| 529 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff |
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| 530 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 |
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| 531 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 |
|---|
| 532 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 |
|---|
| 533 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 |
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| 534 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 |
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| 535 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 |
|---|
| 536 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 |
|---|
| 537 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 |
|---|
| 538 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 |
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| 539 | #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff |
|---|
| 540 | #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 |
|---|
| 541 | #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 |
|---|
| 542 | #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 |
|---|
| 543 | #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff |
|---|
| 544 | #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 |
|---|
| 545 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff |
|---|
| 546 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 |
|---|
| 547 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff |
|---|
| 548 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 |
|---|
| 549 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 |
|---|
| 550 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 |
|---|
| 551 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 |
|---|
| 552 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 |
|---|
| 553 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 |
|---|
| 554 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 |
|---|
| 555 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 |
|---|
| 556 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 |
|---|
| 557 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 |
|---|
| 558 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc |
|---|
| 559 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 |
|---|
| 560 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf |
|---|
| 561 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 |
|---|
| 562 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
|---|
| 563 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 |
|---|
| 564 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
|---|
| 565 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 |
|---|
| 566 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
|---|
| 567 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 |
|---|
| 568 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
|---|
| 569 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 |
|---|
| 570 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
|---|
| 571 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 |
|---|
| 572 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 |
|---|
| 573 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 |
|---|
| 574 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
|---|
| 575 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff |
|---|
| 576 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 |
|---|
| 577 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 |
|---|
| 578 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 |
|---|
| 579 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff |
|---|
| 580 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 |
|---|
| 581 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 |
|---|
| 582 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 |
|---|
| 583 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 |
|---|
| 584 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 |
|---|
| 585 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff |
|---|
| 586 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 |
|---|
| 587 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 |
|---|
| 588 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 |
|---|
| 589 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 |
|---|
| 590 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 |
|---|
| 591 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 |
|---|
| 592 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 |
|---|
| 593 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e |
|---|
| 594 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 |
|---|
| 595 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff |
|---|
| 596 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 |
|---|
| 597 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 598 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 |
|---|
| 599 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f |
|---|
| 600 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 601 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 |
|---|
| 602 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 |
|---|
| 603 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 |
|---|
| 604 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 |
|---|
| 605 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 |
|---|
| 606 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 |
|---|
| 607 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 |
|---|
| 608 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa |
|---|
| 609 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 |
|---|
| 610 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb |
|---|
| 611 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
|---|
| 612 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
|---|
| 613 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
|---|
| 614 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
|---|
| 615 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 |
|---|
| 616 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
|---|
| 617 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 |
|---|
| 618 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 |
|---|
| 619 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 |
|---|
| 620 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f |
|---|
| 621 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 |
|---|
| 622 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
|---|
| 623 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f |
|---|
| 624 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 625 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 |
|---|
| 626 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 |
|---|
| 627 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 |
|---|
| 628 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 |
|---|
| 629 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 |
|---|
| 630 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 |
|---|
| 631 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 |
|---|
| 632 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa |
|---|
| 633 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 |
|---|
| 634 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb |
|---|
| 635 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
|---|
| 636 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
|---|
| 637 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
|---|
| 638 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
|---|
| 639 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 |
|---|
| 640 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
|---|
| 641 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 |
|---|
| 642 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 |
|---|
| 643 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 |
|---|
| 644 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f |
|---|
| 645 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 |
|---|
| 646 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
|---|
| 647 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 |
|---|
| 648 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
|---|
| 649 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 |
|---|
| 650 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
|---|
| 651 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 |
|---|
| 652 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
|---|
| 653 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 |
|---|
| 654 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
|---|
| 655 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 |
|---|
| 656 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
|---|
| 657 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f |
|---|
| 658 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 659 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 |
|---|
| 660 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
|---|
| 661 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 |
|---|
| 662 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
|---|
| 663 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 |
|---|
| 664 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
|---|
| 665 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 |
|---|
| 666 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
|---|
| 667 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 |
|---|
| 668 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
|---|
| 669 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 |
|---|
| 670 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
|---|
| 671 | #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff |
|---|
| 672 | #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 |
|---|
| 673 | #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 |
|---|
| 674 | #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 |
|---|
| 675 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 |
|---|
| 676 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 |
|---|
| 677 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 |
|---|
| 678 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 |
|---|
| 679 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 |
|---|
| 680 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc |
|---|
| 681 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 |
|---|
| 682 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd |
|---|
| 683 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 |
|---|
| 684 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe |
|---|
| 685 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 |
|---|
| 686 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
|---|
| 687 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 |
|---|
| 688 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 |
|---|
| 689 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 |
|---|
| 690 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 |
|---|
| 691 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 |
|---|
| 692 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d |
|---|
| 693 | #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 |
|---|
| 694 | #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e |
|---|
| 695 | #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 |
|---|
| 696 | #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f |
|---|
| 697 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 |
|---|
| 698 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 |
|---|
| 699 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 |
|---|
| 700 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 |
|---|
| 701 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 |
|---|
| 702 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 |
|---|
| 703 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 |
|---|
| 704 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 |
|---|
| 705 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 |
|---|
| 706 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
|---|
| 707 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 |
|---|
| 708 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
|---|
| 709 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 |
|---|
| 710 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
|---|
| 711 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 |
|---|
| 712 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
|---|
| 713 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 |
|---|
| 714 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 |
|---|
| 715 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff |
|---|
| 716 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
|---|
| 717 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 |
|---|
| 718 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
|---|
| 719 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff |
|---|
| 720 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 |
|---|
| 721 | #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 |
|---|
| 722 | #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 |
|---|
| 723 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 |
|---|
| 724 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 |
|---|
| 725 | #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 |
|---|
| 726 | #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 |
|---|
| 727 | #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 |
|---|
| 728 | #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 |
|---|
| 729 | #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 |
|---|
| 730 | #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 |
|---|
| 731 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 |
|---|
| 732 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
|---|
| 733 | #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 |
|---|
| 734 | #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 |
|---|
| 735 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 |
|---|
| 736 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 |
|---|
| 737 | #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 |
|---|
| 738 | #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 |
|---|
| 739 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff |
|---|
| 740 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 |
|---|
| 741 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 742 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 |
|---|
| 743 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff |
|---|
| 744 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 |
|---|
| 745 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff |
|---|
| 746 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 |
|---|
| 747 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff |
|---|
| 748 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 |
|---|
| 749 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff |
|---|
| 750 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 |
|---|
| 751 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 |
|---|
| 752 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
|---|
| 753 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e |
|---|
| 754 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 |
|---|
| 755 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 |
|---|
| 756 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 |
|---|
| 757 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 |
|---|
| 758 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
|---|
| 759 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 |
|---|
| 760 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
|---|
| 761 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 |
|---|
| 762 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
|---|
| 763 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 |
|---|
| 764 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
|---|
| 765 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 |
|---|
| 766 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 |
|---|
| 767 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 |
|---|
| 768 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
|---|
| 769 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 |
|---|
| 770 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 |
|---|
| 771 | #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 |
|---|
| 772 | #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 |
|---|
| 773 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 |
|---|
| 774 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
|---|
| 775 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff |
|---|
| 776 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
|---|
| 777 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 |
|---|
| 778 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
|---|
| 779 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 |
|---|
| 780 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 |
|---|
| 781 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 |
|---|
| 782 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
|---|
| 783 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 |
|---|
| 784 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
|---|
| 785 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 |
|---|
| 786 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 |
|---|
| 787 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 |
|---|
| 788 | #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
|---|
| 789 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 |
|---|
| 790 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 |
|---|
| 791 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 |
|---|
| 792 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 |
|---|
| 793 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 |
|---|
| 794 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 |
|---|
| 795 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 |
|---|
| 796 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
|---|
| 797 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 |
|---|
| 798 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
|---|
| 799 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff |
|---|
| 800 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
|---|
| 801 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 |
|---|
| 802 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
|---|
| 803 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff |
|---|
| 804 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
|---|
| 805 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 |
|---|
| 806 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 |
|---|
| 807 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 |
|---|
| 808 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 |
|---|
| 809 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 |
|---|
| 810 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc |
|---|
| 811 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 |
|---|
| 812 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 |
|---|
| 813 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 |
|---|
| 814 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c |
|---|
| 815 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 |
|---|
| 816 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 |
|---|
| 817 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 |
|---|
| 818 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
|---|
| 819 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 |
|---|
| 820 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 |
|---|
| 821 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 |
|---|
| 822 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 |
|---|
| 823 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 |
|---|
| 824 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
|---|
| 825 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 |
|---|
| 826 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
|---|
| 827 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 |
|---|
| 828 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
|---|
| 829 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 |
|---|
| 830 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
|---|
| 831 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 |
|---|
| 832 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 |
|---|
| 833 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 |
|---|
| 834 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 |
|---|
| 835 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 |
|---|
| 836 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a |
|---|
| 837 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 |
|---|
| 838 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b |
|---|
| 839 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 |
|---|
| 840 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
|---|
| 841 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 |
|---|
| 842 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
|---|
| 843 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 |
|---|
| 844 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
|---|
| 845 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 |
|---|
| 846 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
|---|
| 847 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 |
|---|
| 848 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 849 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 |
|---|
| 850 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 |
|---|
| 851 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 |
|---|
| 852 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 |
|---|
| 853 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 |
|---|
| 854 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
|---|
| 855 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 |
|---|
| 856 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 |
|---|
| 857 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 |
|---|
| 858 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 |
|---|
| 859 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 |
|---|
| 860 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 |
|---|
| 861 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 |
|---|
| 862 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
|---|
| 863 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 |
|---|
| 864 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
|---|
| 865 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf |
|---|
| 866 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 |
|---|
| 867 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 |
|---|
| 868 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 |
|---|
| 869 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 |
|---|
| 870 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 |
|---|
| 871 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 |
|---|
| 872 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc |
|---|
| 873 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 |
|---|
| 874 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
|---|
| 875 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff |
|---|
| 876 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 |
|---|
| 877 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 |
|---|
| 878 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 |
|---|
| 879 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 |
|---|
| 880 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 |
|---|
| 881 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 |
|---|
| 882 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 |
|---|
| 883 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 |
|---|
| 884 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 |
|---|
| 885 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 |
|---|
| 886 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 |
|---|
| 887 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 |
|---|
| 888 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 |
|---|
| 889 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 |
|---|
| 890 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 |
|---|
| 891 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff |
|---|
| 892 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 |
|---|
| 893 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 |
|---|
| 894 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 |
|---|
| 895 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 |
|---|
| 896 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 |
|---|
| 897 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 |
|---|
| 898 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 |
|---|
| 899 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 |
|---|
| 900 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 |
|---|
| 901 | #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 |
|---|
| 902 | #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 |
|---|
| 903 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff |
|---|
| 904 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 |
|---|
| 905 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 |
|---|
| 906 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 |
|---|
| 907 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 |
|---|
| 908 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 |
|---|
| 909 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 |
|---|
| 910 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 |
|---|
| 911 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff |
|---|
| 912 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 |
|---|
| 913 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 |
|---|
| 914 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa |
|---|
| 915 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 |
|---|
| 916 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 |
|---|
| 917 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 |
|---|
| 918 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 |
|---|
| 919 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 |
|---|
| 920 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 |
|---|
| 921 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 |
|---|
| 922 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 |
|---|
| 923 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff |
|---|
| 924 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
|---|
| 925 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 |
|---|
| 926 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
|---|
| 927 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 |
|---|
| 928 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
|---|
| 929 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 |
|---|
| 930 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
|---|
| 931 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 |
|---|
| 932 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
|---|
| 933 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 |
|---|
| 934 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
|---|
| 935 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff |
|---|
| 936 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 |
|---|
| 937 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 |
|---|
| 938 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa |
|---|
| 939 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 |
|---|
| 940 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 |
|---|
| 941 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 |
|---|
| 942 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
|---|
| 943 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 |
|---|
| 944 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
|---|
| 945 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 |
|---|
| 946 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
|---|
| 947 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff |
|---|
| 948 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
|---|
| 949 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 |
|---|
| 950 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
|---|
| 951 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 |
|---|
| 952 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
|---|
| 953 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 |
|---|
| 954 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
|---|
| 955 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 |
|---|
| 956 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
|---|
| 957 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 |
|---|
| 958 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
|---|
| 959 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 |
|---|
| 960 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
|---|
| 961 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 |
|---|
| 962 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
|---|
| 963 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff |
|---|
| 964 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
|---|
| 965 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 |
|---|
| 966 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
|---|
| 967 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 |
|---|
| 968 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
|---|
| 969 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 |
|---|
| 970 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
|---|
| 971 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 |
|---|
| 972 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
|---|
| 973 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 |
|---|
| 974 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
|---|
| 975 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff |
|---|
| 976 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
|---|
| 977 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 |
|---|
| 978 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
|---|
| 979 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 |
|---|
| 980 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
|---|
| 981 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 |
|---|
| 982 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
|---|
| 983 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 |
|---|
| 984 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
|---|
| 985 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 |
|---|
| 986 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
|---|
| 987 | #define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 |
|---|
| 988 | #define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 |
|---|
| 989 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 |
|---|
| 990 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 |
|---|
| 991 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 |
|---|
| 992 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 |
|---|
| 993 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 |
|---|
| 994 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc |
|---|
| 995 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 |
|---|
| 996 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 |
|---|
| 997 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 |
|---|
| 998 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 |
|---|
| 999 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 |
|---|
| 1000 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 |
|---|
| 1001 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff |
|---|
| 1002 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 |
|---|
| 1003 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 |
|---|
| 1004 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 |
|---|
| 1005 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff |
|---|
| 1006 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
|---|
| 1007 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 |
|---|
| 1008 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
|---|
| 1009 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff |
|---|
| 1010 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 |
|---|
| 1011 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 |
|---|
| 1012 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 |
|---|
| 1013 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff |
|---|
| 1014 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
|---|
| 1015 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 |
|---|
| 1016 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
|---|
| 1017 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff |
|---|
| 1018 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
|---|
| 1019 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 |
|---|
| 1020 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
|---|
| 1021 | #define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff |
|---|
| 1022 | #define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
|---|
| 1023 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff |
|---|
| 1024 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 |
|---|
| 1025 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 |
|---|
| 1026 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 |
|---|
| 1027 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff |
|---|
| 1028 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
|---|
| 1029 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 |
|---|
| 1030 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
|---|
| 1031 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff |
|---|
| 1032 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 |
|---|
| 1033 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 |
|---|
| 1034 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 |
|---|
| 1035 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff |
|---|
| 1036 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
|---|
| 1037 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 |
|---|
| 1038 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
|---|
| 1039 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff |
|---|
| 1040 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
|---|
| 1041 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 |
|---|
| 1042 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
|---|
| 1043 | #define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff |
|---|
| 1044 | #define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
|---|
| 1045 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 |
|---|
| 1046 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 |
|---|
| 1047 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 |
|---|
| 1048 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 |
|---|
| 1049 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 |
|---|
| 1050 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 |
|---|
| 1051 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 |
|---|
| 1052 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 |
|---|
| 1053 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 |
|---|
| 1054 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 |
|---|
| 1055 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 |
|---|
| 1056 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 |
|---|
| 1057 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 |
|---|
| 1058 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc |
|---|
| 1059 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 |
|---|
| 1060 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd |
|---|
| 1061 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 |
|---|
| 1062 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe |
|---|
| 1063 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 |
|---|
| 1064 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 |
|---|
| 1065 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 |
|---|
| 1066 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c |
|---|
| 1067 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff |
|---|
| 1068 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 |
|---|
| 1069 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000 |
|---|
| 1070 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 |
|---|
| 1071 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff |
|---|
| 1072 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 |
|---|
| 1073 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000 |
|---|
| 1074 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 |
|---|
| 1075 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 |
|---|
| 1076 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 |
|---|
| 1077 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 |
|---|
| 1078 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 |
|---|
| 1079 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 |
|---|
| 1080 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 |
|---|
| 1081 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 |
|---|
| 1082 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 |
|---|
| 1083 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 |
|---|
| 1084 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 |
|---|
| 1085 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 |
|---|
| 1086 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d |
|---|
| 1087 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 |
|---|
| 1088 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 |
|---|
| 1089 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 |
|---|
| 1090 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 |
|---|
| 1091 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 |
|---|
| 1092 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 |
|---|
| 1093 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 |
|---|
| 1094 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 |
|---|
| 1095 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 |
|---|
| 1096 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 |
|---|
| 1097 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 |
|---|
| 1098 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 |
|---|
| 1099 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 |
|---|
| 1100 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 |
|---|
| 1101 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 |
|---|
| 1102 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 |
|---|
| 1103 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 |
|---|
| 1104 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 |
|---|
| 1105 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 |
|---|
| 1106 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 |
|---|
| 1107 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff |
|---|
| 1108 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
|---|
| 1109 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 |
|---|
| 1110 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
|---|
| 1111 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 |
|---|
| 1112 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 |
|---|
| 1113 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 |
|---|
| 1114 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 |
|---|
| 1115 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 |
|---|
| 1116 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a |
|---|
| 1117 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 |
|---|
| 1118 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b |
|---|
| 1119 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 |
|---|
| 1120 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c |
|---|
| 1121 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 |
|---|
| 1122 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 |
|---|
| 1123 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 |
|---|
| 1124 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 |
|---|
| 1125 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 |
|---|
| 1126 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
|---|
| 1127 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 |
|---|
| 1128 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
|---|
| 1129 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 |
|---|
| 1130 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
|---|
| 1131 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 |
|---|
| 1132 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
|---|
| 1133 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 |
|---|
| 1134 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
|---|
| 1135 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff |
|---|
| 1136 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
|---|
| 1137 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 |
|---|
| 1138 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
|---|
| 1139 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 |
|---|
| 1140 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
|---|
| 1141 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 |
|---|
| 1142 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
|---|
| 1143 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 |
|---|
| 1144 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
|---|
| 1145 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 |
|---|
| 1146 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
|---|
| 1147 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 |
|---|
| 1148 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
|---|
| 1149 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 |
|---|
| 1150 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 |
|---|
| 1151 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff |
|---|
| 1152 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 |
|---|
| 1153 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 |
|---|
| 1154 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 |
|---|
| 1155 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff |
|---|
| 1156 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 |
|---|
| 1157 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 |
|---|
| 1158 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 |
|---|
| 1159 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 |
|---|
| 1160 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
|---|
| 1161 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1162 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1163 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1164 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1165 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1166 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1167 | #define DAC_ENABLE__DAC_ENABLE_MASK 0x1 |
|---|
| 1168 | #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 |
|---|
| 1169 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 |
|---|
| 1170 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 |
|---|
| 1171 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc |
|---|
| 1172 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 |
|---|
| 1173 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 |
|---|
| 1174 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 |
|---|
| 1175 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 |
|---|
| 1176 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 |
|---|
| 1177 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 |
|---|
| 1178 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 |
|---|
| 1179 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 |
|---|
| 1180 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 |
|---|
| 1181 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 |
|---|
| 1182 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 |
|---|
| 1183 | #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 |
|---|
| 1184 | #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 |
|---|
| 1185 | #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 |
|---|
| 1186 | #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 |
|---|
| 1187 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 |
|---|
| 1188 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 |
|---|
| 1189 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 |
|---|
| 1190 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 |
|---|
| 1191 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff |
|---|
| 1192 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
|---|
| 1193 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 |
|---|
| 1194 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa |
|---|
| 1195 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 |
|---|
| 1196 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 |
|---|
| 1197 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f |
|---|
| 1198 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 |
|---|
| 1199 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff |
|---|
| 1200 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 |
|---|
| 1201 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 |
|---|
| 1202 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa |
|---|
| 1203 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 |
|---|
| 1204 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 |
|---|
| 1205 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f |
|---|
| 1206 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 |
|---|
| 1207 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 |
|---|
| 1208 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 |
|---|
| 1209 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 |
|---|
| 1210 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 |
|---|
| 1211 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 |
|---|
| 1212 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 |
|---|
| 1213 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 |
|---|
| 1214 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 |
|---|
| 1215 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 |
|---|
| 1216 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 |
|---|
| 1217 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 |
|---|
| 1218 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 |
|---|
| 1219 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 |
|---|
| 1220 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 |
|---|
| 1221 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff |
|---|
| 1222 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 |
|---|
| 1223 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 |
|---|
| 1224 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 |
|---|
| 1225 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff |
|---|
| 1226 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 |
|---|
| 1227 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 |
|---|
| 1228 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 |
|---|
| 1229 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 |
|---|
| 1230 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 |
|---|
| 1231 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 |
|---|
| 1232 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 |
|---|
| 1233 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 |
|---|
| 1234 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 |
|---|
| 1235 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 |
|---|
| 1236 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 |
|---|
| 1237 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 |
|---|
| 1238 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 |
|---|
| 1239 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 |
|---|
| 1240 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 |
|---|
| 1241 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 |
|---|
| 1242 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 |
|---|
| 1243 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 |
|---|
| 1244 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 |
|---|
| 1245 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 |
|---|
| 1246 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 |
|---|
| 1247 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 |
|---|
| 1248 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 |
|---|
| 1249 | #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff |
|---|
| 1250 | #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 |
|---|
| 1251 | #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 |
|---|
| 1252 | #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 |
|---|
| 1253 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 |
|---|
| 1254 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 |
|---|
| 1255 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 |
|---|
| 1256 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 |
|---|
| 1257 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 |
|---|
| 1258 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 |
|---|
| 1259 | #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 |
|---|
| 1260 | #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 |
|---|
| 1261 | #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 |
|---|
| 1262 | #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 |
|---|
| 1263 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 |
|---|
| 1264 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 |
|---|
| 1265 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 |
|---|
| 1266 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 |
|---|
| 1267 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 |
|---|
| 1268 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 |
|---|
| 1269 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 |
|---|
| 1270 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 |
|---|
| 1271 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 |
|---|
| 1272 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 |
|---|
| 1273 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 |
|---|
| 1274 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 |
|---|
| 1275 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 |
|---|
| 1276 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 |
|---|
| 1277 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 |
|---|
| 1278 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 |
|---|
| 1279 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 |
|---|
| 1280 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 |
|---|
| 1281 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 |
|---|
| 1282 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 |
|---|
| 1283 | #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 |
|---|
| 1284 | #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 |
|---|
| 1285 | #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 |
|---|
| 1286 | #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 |
|---|
| 1287 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff |
|---|
| 1288 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 |
|---|
| 1289 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
|---|
| 1290 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
|---|
| 1291 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
|---|
| 1292 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
|---|
| 1293 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
|---|
| 1294 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
|---|
| 1295 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 |
|---|
| 1296 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
|---|
| 1297 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
|---|
| 1298 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
|---|
| 1299 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 |
|---|
| 1300 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d |
|---|
| 1301 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
|---|
| 1302 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
|---|
| 1303 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
|---|
| 1304 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
|---|
| 1305 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1306 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1307 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1308 | #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1309 | #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1310 | #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1311 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff |
|---|
| 1312 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
|---|
| 1313 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 |
|---|
| 1314 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
|---|
| 1315 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 |
|---|
| 1316 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
|---|
| 1317 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 |
|---|
| 1318 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe |
|---|
| 1319 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 |
|---|
| 1320 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf |
|---|
| 1321 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 |
|---|
| 1322 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 |
|---|
| 1323 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 |
|---|
| 1324 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 |
|---|
| 1325 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 |
|---|
| 1326 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 |
|---|
| 1327 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 |
|---|
| 1328 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 |
|---|
| 1329 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 |
|---|
| 1330 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 |
|---|
| 1331 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 |
|---|
| 1332 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 |
|---|
| 1333 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 |
|---|
| 1334 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a |
|---|
| 1335 | #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 |
|---|
| 1336 | #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b |
|---|
| 1337 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 |
|---|
| 1338 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
|---|
| 1339 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 |
|---|
| 1340 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
|---|
| 1341 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 |
|---|
| 1342 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
|---|
| 1343 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 |
|---|
| 1344 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
|---|
| 1345 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 |
|---|
| 1346 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
|---|
| 1347 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 |
|---|
| 1348 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
|---|
| 1349 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 |
|---|
| 1350 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
|---|
| 1351 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 |
|---|
| 1352 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
|---|
| 1353 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 |
|---|
| 1354 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
|---|
| 1355 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 |
|---|
| 1356 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
|---|
| 1357 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 |
|---|
| 1358 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
|---|
| 1359 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 |
|---|
| 1360 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
|---|
| 1361 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 |
|---|
| 1362 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
|---|
| 1363 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 |
|---|
| 1364 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
|---|
| 1365 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 |
|---|
| 1366 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
|---|
| 1367 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 |
|---|
| 1368 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
|---|
| 1369 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 |
|---|
| 1370 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
|---|
| 1371 | #define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 |
|---|
| 1372 | #define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
|---|
| 1373 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc |
|---|
| 1374 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 |
|---|
| 1375 | #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 |
|---|
| 1376 | #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
|---|
| 1377 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 |
|---|
| 1378 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
|---|
| 1379 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 |
|---|
| 1380 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
|---|
| 1381 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 |
|---|
| 1382 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
|---|
| 1383 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 |
|---|
| 1384 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
|---|
| 1385 | #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 |
|---|
| 1386 | #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
|---|
| 1387 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 |
|---|
| 1388 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
|---|
| 1389 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 |
|---|
| 1390 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
|---|
| 1391 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 |
|---|
| 1392 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
|---|
| 1393 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 |
|---|
| 1394 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
|---|
| 1395 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 |
|---|
| 1396 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
|---|
| 1397 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 |
|---|
| 1398 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
|---|
| 1399 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 |
|---|
| 1400 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
|---|
| 1401 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 |
|---|
| 1402 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
|---|
| 1403 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 |
|---|
| 1404 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
|---|
| 1405 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 |
|---|
| 1406 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
|---|
| 1407 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 |
|---|
| 1408 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
|---|
| 1409 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 |
|---|
| 1410 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
|---|
| 1411 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 |
|---|
| 1412 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
|---|
| 1413 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 |
|---|
| 1414 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
|---|
| 1415 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 |
|---|
| 1416 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
|---|
| 1417 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 |
|---|
| 1418 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
|---|
| 1419 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 |
|---|
| 1420 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
|---|
| 1421 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff |
|---|
| 1422 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
|---|
| 1423 | #define PERFMON_HI__PERFMON_HI_MASK 0xffff |
|---|
| 1424 | #define PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
|---|
| 1425 | #define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 |
|---|
| 1426 | #define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
|---|
| 1427 | #define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff |
|---|
| 1428 | #define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
|---|
| 1429 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 1430 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 1431 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1432 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1433 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 1434 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1435 | #define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 |
|---|
| 1436 | #define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 |
|---|
| 1437 | #define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 |
|---|
| 1438 | #define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 |
|---|
| 1439 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf |
|---|
| 1440 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 |
|---|
| 1441 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 |
|---|
| 1442 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 |
|---|
| 1443 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 |
|---|
| 1444 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 |
|---|
| 1445 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff |
|---|
| 1446 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 |
|---|
| 1447 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 |
|---|
| 1448 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 |
|---|
| 1449 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff |
|---|
| 1450 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 |
|---|
| 1451 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 |
|---|
| 1452 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 |
|---|
| 1453 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff |
|---|
| 1454 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 |
|---|
| 1455 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff |
|---|
| 1456 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 |
|---|
| 1457 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff |
|---|
| 1458 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 |
|---|
| 1459 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff |
|---|
| 1460 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 |
|---|
| 1461 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff |
|---|
| 1462 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 |
|---|
| 1463 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 |
|---|
| 1464 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 |
|---|
| 1465 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 |
|---|
| 1466 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 |
|---|
| 1467 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 |
|---|
| 1468 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 |
|---|
| 1469 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 |
|---|
| 1470 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 |
|---|
| 1471 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 |
|---|
| 1472 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 |
|---|
| 1473 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 |
|---|
| 1474 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 |
|---|
| 1475 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff |
|---|
| 1476 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 |
|---|
| 1477 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 |
|---|
| 1478 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 |
|---|
| 1479 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 |
|---|
| 1480 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 |
|---|
| 1481 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 |
|---|
| 1482 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 |
|---|
| 1483 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 |
|---|
| 1484 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 |
|---|
| 1485 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 |
|---|
| 1486 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 |
|---|
| 1487 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 |
|---|
| 1488 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 |
|---|
| 1489 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 |
|---|
| 1490 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 |
|---|
| 1491 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 |
|---|
| 1492 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 |
|---|
| 1493 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 |
|---|
| 1494 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 |
|---|
| 1495 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 |
|---|
| 1496 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 |
|---|
| 1497 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 |
|---|
| 1498 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 |
|---|
| 1499 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 |
|---|
| 1500 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 |
|---|
| 1501 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 |
|---|
| 1502 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 |
|---|
| 1503 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 |
|---|
| 1504 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 |
|---|
| 1505 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 |
|---|
| 1506 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 |
|---|
| 1507 | #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 |
|---|
| 1508 | #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 |
|---|
| 1509 | #define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 |
|---|
| 1510 | #define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 |
|---|
| 1511 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 |
|---|
| 1512 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 |
|---|
| 1513 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 |
|---|
| 1514 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 |
|---|
| 1515 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 |
|---|
| 1516 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 |
|---|
| 1517 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 |
|---|
| 1518 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 |
|---|
| 1519 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 |
|---|
| 1520 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 |
|---|
| 1521 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 |
|---|
| 1522 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 |
|---|
| 1523 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 |
|---|
| 1524 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 |
|---|
| 1525 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 |
|---|
| 1526 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 |
|---|
| 1527 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 |
|---|
| 1528 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 |
|---|
| 1529 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 |
|---|
| 1530 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 |
|---|
| 1531 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 |
|---|
| 1532 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 |
|---|
| 1533 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 |
|---|
| 1534 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 |
|---|
| 1535 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 |
|---|
| 1536 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 |
|---|
| 1537 | #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 |
|---|
| 1538 | #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 |
|---|
| 1539 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 |
|---|
| 1540 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 |
|---|
| 1541 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 |
|---|
| 1542 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 |
|---|
| 1543 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 |
|---|
| 1544 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 |
|---|
| 1545 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 |
|---|
| 1546 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 |
|---|
| 1547 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 |
|---|
| 1548 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 |
|---|
| 1549 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 |
|---|
| 1550 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 |
|---|
| 1551 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 |
|---|
| 1552 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 |
|---|
| 1553 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 |
|---|
| 1554 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 |
|---|
| 1555 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 |
|---|
| 1556 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 |
|---|
| 1557 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 |
|---|
| 1558 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a |
|---|
| 1559 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 |
|---|
| 1560 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b |
|---|
| 1561 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 |
|---|
| 1562 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c |
|---|
| 1563 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 |
|---|
| 1564 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d |
|---|
| 1565 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 |
|---|
| 1566 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e |
|---|
| 1567 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1568 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1569 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1570 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1571 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 |
|---|
| 1572 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc |
|---|
| 1573 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1574 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1575 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1576 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1577 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 |
|---|
| 1578 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc |
|---|
| 1579 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1580 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1581 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1582 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1583 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf |
|---|
| 1584 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 |
|---|
| 1585 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 |
|---|
| 1586 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
|---|
| 1587 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff |
|---|
| 1588 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 |
|---|
| 1589 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1590 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1591 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 |
|---|
| 1592 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 |
|---|
| 1593 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1594 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1595 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 |
|---|
| 1596 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 |
|---|
| 1597 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 |
|---|
| 1598 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 |
|---|
| 1599 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 |
|---|
| 1600 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 |
|---|
| 1601 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f |
|---|
| 1602 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 |
|---|
| 1603 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 |
|---|
| 1604 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 |
|---|
| 1605 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 |
|---|
| 1606 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 |
|---|
| 1607 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 |
|---|
| 1608 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 |
|---|
| 1609 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
|---|
| 1610 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
|---|
| 1611 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 |
|---|
| 1612 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 |
|---|
| 1613 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff |
|---|
| 1614 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 |
|---|
| 1615 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
|---|
| 1616 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
|---|
| 1617 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff |
|---|
| 1618 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 |
|---|
| 1619 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 |
|---|
| 1620 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 |
|---|
| 1621 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 |
|---|
| 1622 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 |
|---|
| 1623 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 |
|---|
| 1624 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 |
|---|
| 1625 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 |
|---|
| 1626 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c |
|---|
| 1627 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 |
|---|
| 1628 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d |
|---|
| 1629 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 |
|---|
| 1630 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e |
|---|
| 1631 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 |
|---|
| 1632 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f |
|---|
| 1633 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 |
|---|
| 1634 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 |
|---|
| 1635 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 |
|---|
| 1636 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 |
|---|
| 1637 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 |
|---|
| 1638 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 |
|---|
| 1639 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 |
|---|
| 1640 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 |
|---|
| 1641 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 |
|---|
| 1642 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 |
|---|
| 1643 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 |
|---|
| 1644 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 |
|---|
| 1645 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 |
|---|
| 1646 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 |
|---|
| 1647 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 |
|---|
| 1648 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 |
|---|
| 1649 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 |
|---|
| 1650 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 |
|---|
| 1651 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 |
|---|
| 1652 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 |
|---|
| 1653 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 |
|---|
| 1654 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb |
|---|
| 1655 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 |
|---|
| 1656 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 |
|---|
| 1657 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 |
|---|
| 1658 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 |
|---|
| 1659 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1660 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1661 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 |
|---|
| 1662 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 |
|---|
| 1663 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 |
|---|
| 1664 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 |
|---|
| 1665 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 |
|---|
| 1666 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1667 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 |
|---|
| 1668 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1669 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1670 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1671 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1672 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1673 | #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff |
|---|
| 1674 | #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 |
|---|
| 1675 | #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff |
|---|
| 1676 | #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 |
|---|
| 1677 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1678 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1679 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 |
|---|
| 1680 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 |
|---|
| 1681 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 |
|---|
| 1682 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 |
|---|
| 1683 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 |
|---|
| 1684 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1685 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 |
|---|
| 1686 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1687 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1688 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1689 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1690 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1691 | #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff |
|---|
| 1692 | #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 |
|---|
| 1693 | #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff |
|---|
| 1694 | #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 |
|---|
| 1695 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1696 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1697 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 |
|---|
| 1698 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 |
|---|
| 1699 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 |
|---|
| 1700 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 |
|---|
| 1701 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 |
|---|
| 1702 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1703 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 |
|---|
| 1704 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1705 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1706 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1707 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1708 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1709 | #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff |
|---|
| 1710 | #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 |
|---|
| 1711 | #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff |
|---|
| 1712 | #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 |
|---|
| 1713 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1714 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1715 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 |
|---|
| 1716 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 |
|---|
| 1717 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 |
|---|
| 1718 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 |
|---|
| 1719 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 |
|---|
| 1720 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1721 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 |
|---|
| 1722 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1723 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1724 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1725 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1726 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1727 | #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff |
|---|
| 1728 | #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 |
|---|
| 1729 | #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff |
|---|
| 1730 | #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 |
|---|
| 1731 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1732 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1733 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 |
|---|
| 1734 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 |
|---|
| 1735 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 |
|---|
| 1736 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 |
|---|
| 1737 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 |
|---|
| 1738 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1739 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 |
|---|
| 1740 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1741 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1742 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1743 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1744 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1745 | #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff |
|---|
| 1746 | #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 |
|---|
| 1747 | #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff |
|---|
| 1748 | #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 |
|---|
| 1749 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 |
|---|
| 1750 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 |
|---|
| 1751 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 |
|---|
| 1752 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 |
|---|
| 1753 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 |
|---|
| 1754 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 |
|---|
| 1755 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 |
|---|
| 1756 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 |
|---|
| 1757 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 |
|---|
| 1758 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 |
|---|
| 1759 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 |
|---|
| 1760 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe |
|---|
| 1761 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
|---|
| 1762 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
|---|
| 1763 | #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff |
|---|
| 1764 | #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 |
|---|
| 1765 | #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff |
|---|
| 1766 | #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 |
|---|
| 1767 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 |
|---|
| 1768 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 |
|---|
| 1769 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 |
|---|
| 1770 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 |
|---|
| 1771 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 |
|---|
| 1772 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 |
|---|
| 1773 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 |
|---|
| 1774 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 |
|---|
| 1775 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 |
|---|
| 1776 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 |
|---|
| 1777 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 |
|---|
| 1778 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 |
|---|
| 1779 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 |
|---|
| 1780 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc |
|---|
| 1781 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 |
|---|
| 1782 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd |
|---|
| 1783 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 |
|---|
| 1784 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe |
|---|
| 1785 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 |
|---|
| 1786 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf |
|---|
| 1787 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 |
|---|
| 1788 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 |
|---|
| 1789 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 |
|---|
| 1790 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 |
|---|
| 1791 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 |
|---|
| 1792 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 |
|---|
| 1793 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 |
|---|
| 1794 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 |
|---|
| 1795 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 |
|---|
| 1796 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 |
|---|
| 1797 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 |
|---|
| 1798 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 |
|---|
| 1799 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1800 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1801 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 |
|---|
| 1802 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1803 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1804 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1805 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1806 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1807 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 |
|---|
| 1808 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1809 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1810 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1811 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1812 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1813 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 |
|---|
| 1814 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1815 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1816 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1817 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1818 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1819 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 |
|---|
| 1820 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1821 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1822 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1823 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1824 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1825 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 |
|---|
| 1826 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1827 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1828 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1829 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 |
|---|
| 1830 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 |
|---|
| 1831 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 |
|---|
| 1832 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 |
|---|
| 1833 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 |
|---|
| 1834 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 |
|---|
| 1835 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 |
|---|
| 1836 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 |
|---|
| 1837 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 |
|---|
| 1838 | #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 |
|---|
| 1839 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 |
|---|
| 1840 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 |
|---|
| 1841 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 |
|---|
| 1842 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 |
|---|
| 1843 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 |
|---|
| 1844 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 |
|---|
| 1845 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1846 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1847 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 |
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| 1848 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 |
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| 1849 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 |
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| 1850 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 |
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| 1851 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 |
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| 1852 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 |
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| 1853 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 |
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| 1854 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 |
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| 1855 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1856 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1857 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 |
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| 1858 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 |
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| 1859 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 |
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| 1860 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 |
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| 1861 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 |
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| 1862 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 |
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| 1863 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 |
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| 1864 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c |
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| 1865 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 |
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| 1866 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 |
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| 1867 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 |
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| 1868 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 |
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| 1869 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 |
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| 1870 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 |
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| 1871 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 |
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| 1872 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 |
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| 1873 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 |
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| 1874 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 |
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| 1875 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 |
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| 1876 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 |
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| 1877 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 |
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| 1878 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 |
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| 1879 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 |
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| 1880 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc |
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| 1881 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 |
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| 1882 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 |
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| 1883 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 |
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| 1884 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 |
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| 1885 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 |
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| 1886 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 |
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| 1887 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 |
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| 1888 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c |
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| 1889 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff |
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| 1890 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 |
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| 1891 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff |
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| 1892 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 |
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| 1893 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff |
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| 1894 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 |
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| 1895 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff |
|---|
| 1896 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 |
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| 1897 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff |
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| 1898 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 |
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| 1899 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 1900 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 1901 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff |
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| 1902 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 1903 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff |
|---|
| 1904 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 |
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| 1905 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 |
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| 1906 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc |
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| 1907 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 |
|---|
| 1908 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 |
|---|
| 1909 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 |
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| 1910 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c |
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| 1911 | #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1912 | #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1913 | #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1914 | #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1915 | #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1916 | #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1917 | #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1918 | #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1919 | #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1920 | #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1921 | #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1922 | #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1923 | #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1924 | #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1925 | #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1926 | #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1927 | #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1928 | #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1929 | #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1930 | #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1931 | #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1932 | #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1933 | #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1934 | #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1935 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1936 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1937 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1938 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1939 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1940 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1941 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1942 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1943 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1944 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1945 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1946 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1947 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1948 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1949 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1950 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1951 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1952 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1953 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1954 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1955 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1956 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1957 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1958 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1959 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1960 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1961 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1962 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1963 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1964 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1965 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1966 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1967 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1968 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1969 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
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| 1970 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1971 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1972 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1973 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1974 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1975 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1976 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1977 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1978 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1979 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1980 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1981 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1982 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1983 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1984 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1985 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1986 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1987 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1988 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1989 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1990 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1991 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1992 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1993 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1994 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 1995 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1996 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1997 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 1998 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
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| 1999 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2000 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2001 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2002 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2003 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2004 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2005 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2006 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2007 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2008 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2009 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2010 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2011 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2012 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2013 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2014 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2015 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2016 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2017 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff |
|---|
| 2018 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
|---|
| 2019 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f |
|---|
| 2020 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 |
|---|
| 2021 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 |
|---|
| 2022 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 |
|---|
| 2023 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 |
|---|
| 2024 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf |
|---|
| 2025 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 |
|---|
| 2026 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 |
|---|
| 2027 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 |
|---|
| 2028 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 |
|---|
| 2029 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 |
|---|
| 2030 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 |
|---|
| 2031 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 |
|---|
| 2032 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 |
|---|
| 2033 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 |
|---|
| 2034 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 |
|---|
| 2035 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 |
|---|
| 2036 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 |
|---|
| 2037 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 |
|---|
| 2038 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 |
|---|
| 2039 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff |
|---|
| 2040 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 |
|---|
| 2041 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff |
|---|
| 2042 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 |
|---|
| 2043 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff |
|---|
| 2044 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 |
|---|
| 2045 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff |
|---|
| 2046 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 |
|---|
| 2047 | #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff |
|---|
| 2048 | #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 |
|---|
| 2049 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f |
|---|
| 2050 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 |
|---|
| 2051 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 |
|---|
| 2052 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 |
|---|
| 2053 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 |
|---|
| 2054 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc |
|---|
| 2055 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 |
|---|
| 2056 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf |
|---|
| 2057 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 |
|---|
| 2058 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 |
|---|
| 2059 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 |
|---|
| 2060 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c |
|---|
| 2061 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f |
|---|
| 2062 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 |
|---|
| 2063 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 |
|---|
| 2064 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 |
|---|
| 2065 | #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 |
|---|
| 2066 | #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 |
|---|
| 2067 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff |
|---|
| 2068 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 |
|---|
| 2069 | #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 |
|---|
| 2070 | #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
|---|
| 2071 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 |
|---|
| 2072 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
|---|
| 2073 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 |
|---|
| 2074 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
|---|
| 2075 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 |
|---|
| 2076 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc |
|---|
| 2077 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 |
|---|
| 2078 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
|---|
| 2079 | #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 |
|---|
| 2080 | #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
|---|
| 2081 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 |
|---|
| 2082 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
|---|
| 2083 | #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 |
|---|
| 2084 | #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 |
|---|
| 2085 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 |
|---|
| 2086 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 |
|---|
| 2087 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 |
|---|
| 2088 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 |
|---|
| 2089 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 |
|---|
| 2090 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 |
|---|
| 2091 | #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 |
|---|
| 2092 | #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb |
|---|
| 2093 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 |
|---|
| 2094 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc |
|---|
| 2095 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 |
|---|
| 2096 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 |
|---|
| 2097 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 |
|---|
| 2098 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 |
|---|
| 2099 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 |
|---|
| 2100 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d |
|---|
| 2101 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff |
|---|
| 2102 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 |
|---|
| 2103 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00 |
|---|
| 2104 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 |
|---|
| 2105 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 |
|---|
| 2106 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 |
|---|
| 2107 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 |
|---|
| 2108 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 |
|---|
| 2109 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 |
|---|
| 2110 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 |
|---|
| 2111 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 |
|---|
| 2112 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 |
|---|
| 2113 | #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 |
|---|
| 2114 | #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c |
|---|
| 2115 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff |
|---|
| 2116 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 |
|---|
| 2117 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff |
|---|
| 2118 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 |
|---|
| 2119 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 |
|---|
| 2120 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 |
|---|
| 2121 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2122 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2123 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2124 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2125 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2126 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2127 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2128 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2129 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2130 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2131 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2132 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2133 | #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2134 | #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2135 | #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
|---|
| 2136 | #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
|---|
| 2137 | #define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf |
|---|
| 2138 | #define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 |
|---|
| 2139 | #define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 |
|---|
| 2140 | #define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 |
|---|
| 2141 | #define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 |
|---|
| 2142 | #define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 |
|---|
| 2143 | #define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 |
|---|
| 2144 | #define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc |
|---|
| 2145 | #define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 |
|---|
| 2146 | #define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 |
|---|
| 2147 | #define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 |
|---|
| 2148 | #define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 |
|---|
| 2149 | #define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 |
|---|
| 2150 | #define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 |
|---|
| 2151 | #define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 |
|---|
| 2152 | #define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c |
|---|
| 2153 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 |
|---|
| 2154 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 2155 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 |
|---|
| 2156 | #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 |
|---|
| 2157 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2158 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2159 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2160 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2161 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2162 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2163 | #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff |
|---|
| 2164 | #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 |
|---|
| 2165 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 |
|---|
| 2166 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 |
|---|
| 2167 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 |
|---|
| 2168 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 |
|---|
| 2169 | #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff |
|---|
| 2170 | #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 |
|---|
| 2171 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 |
|---|
| 2172 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 |
|---|
| 2173 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 |
|---|
| 2174 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 |
|---|
| 2175 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 |
|---|
| 2176 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
|---|
| 2177 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 |
|---|
| 2178 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c |
|---|
| 2179 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 |
|---|
| 2180 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 |
|---|
| 2181 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 |
|---|
| 2182 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 |
|---|
| 2183 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 |
|---|
| 2184 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 |
|---|
| 2185 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 |
|---|
| 2186 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 |
|---|
| 2187 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 |
|---|
| 2188 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 |
|---|
| 2189 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 |
|---|
| 2190 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 |
|---|
| 2191 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 |
|---|
| 2192 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 |
|---|
| 2193 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 |
|---|
| 2194 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 |
|---|
| 2195 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2196 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2197 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2198 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2199 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2200 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2201 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2202 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2203 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2204 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2205 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2206 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2207 | #define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2208 | #define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2209 | #define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
|---|
| 2210 | #define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
|---|
| 2211 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 |
|---|
| 2212 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 |
|---|
| 2213 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 |
|---|
| 2214 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 |
|---|
| 2215 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 |
|---|
| 2216 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 |
|---|
| 2217 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 |
|---|
| 2218 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 |
|---|
| 2219 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 |
|---|
| 2220 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb |
|---|
| 2221 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 |
|---|
| 2222 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc |
|---|
| 2223 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 |
|---|
| 2224 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 |
|---|
| 2225 | #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 |
|---|
| 2226 | #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 |
|---|
| 2227 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 |
|---|
| 2228 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 |
|---|
| 2229 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 |
|---|
| 2230 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 |
|---|
| 2231 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 |
|---|
| 2232 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc |
|---|
| 2233 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 |
|---|
| 2234 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 |
|---|
| 2235 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 |
|---|
| 2236 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 |
|---|
| 2237 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 |
|---|
| 2238 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e |
|---|
| 2239 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 |
|---|
| 2240 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f |
|---|
| 2241 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff |
|---|
| 2242 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 |
|---|
| 2243 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 |
|---|
| 2244 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 |
|---|
| 2245 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2246 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2247 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2248 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2249 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2250 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2251 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff |
|---|
| 2252 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 |
|---|
| 2253 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff |
|---|
| 2254 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 |
|---|
| 2255 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff |
|---|
| 2256 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 |
|---|
| 2257 | #define MCIF_VMID__MCIF_WR_VMID_MASK 0xf |
|---|
| 2258 | #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 |
|---|
| 2259 | #define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 |
|---|
| 2260 | #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 |
|---|
| 2261 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 |
|---|
| 2262 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 |
|---|
| 2263 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 |
|---|
| 2264 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 |
|---|
| 2265 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 |
|---|
| 2266 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 |
|---|
| 2267 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 |
|---|
| 2268 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 |
|---|
| 2269 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 |
|---|
| 2270 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 |
|---|
| 2271 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e |
|---|
| 2272 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 |
|---|
| 2273 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK 0x100 |
|---|
| 2274 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT 0x8 |
|---|
| 2275 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK 0x1e00 |
|---|
| 2276 | #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT 0x9 |
|---|
| 2277 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 |
|---|
| 2278 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 |
|---|
| 2279 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 |
|---|
| 2280 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 |
|---|
| 2281 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 |
|---|
| 2282 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 |
|---|
| 2283 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 |
|---|
| 2284 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc |
|---|
| 2285 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 |
|---|
| 2286 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 |
|---|
| 2287 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 |
|---|
| 2288 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 |
|---|
| 2289 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 |
|---|
| 2290 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 |
|---|
| 2291 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 |
|---|
| 2292 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c |
|---|
| 2293 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff |
|---|
| 2294 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 |
|---|
| 2295 | #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK 0xfff00000 |
|---|
| 2296 | #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT 0x14 |
|---|
| 2297 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff |
|---|
| 2298 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 |
|---|
| 2299 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 |
|---|
| 2300 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c |
|---|
| 2301 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 |
|---|
| 2302 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d |
|---|
| 2303 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 |
|---|
| 2304 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e |
|---|
| 2305 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 |
|---|
| 2306 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f |
|---|
| 2307 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 |
|---|
| 2308 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 |
|---|
| 2309 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 |
|---|
| 2310 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 |
|---|
| 2311 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 |
|---|
| 2312 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 |
|---|
| 2313 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 |
|---|
| 2314 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 |
|---|
| 2315 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 |
|---|
| 2316 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 2317 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 |
|---|
| 2318 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 |
|---|
| 2319 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 |
|---|
| 2320 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 |
|---|
| 2321 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 |
|---|
| 2322 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 |
|---|
| 2323 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 |
|---|
| 2324 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 |
|---|
| 2325 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 |
|---|
| 2326 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 |
|---|
| 2327 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 |
|---|
| 2328 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa |
|---|
| 2329 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 |
|---|
| 2330 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb |
|---|
| 2331 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 |
|---|
| 2332 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc |
|---|
| 2333 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 |
|---|
| 2334 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd |
|---|
| 2335 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 |
|---|
| 2336 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe |
|---|
| 2337 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x7 |
|---|
| 2338 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 |
|---|
| 2339 | #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK 0x8 |
|---|
| 2340 | #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT 0x3 |
|---|
| 2341 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 |
|---|
| 2342 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 |
|---|
| 2343 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 |
|---|
| 2344 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 |
|---|
| 2345 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 |
|---|
| 2346 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 |
|---|
| 2347 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 |
|---|
| 2348 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 |
|---|
| 2349 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc |
|---|
| 2350 | #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 |
|---|
| 2351 | #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 |
|---|
| 2352 | #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 2353 | #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 |
|---|
| 2354 | #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 |
|---|
| 2355 | #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 |
|---|
| 2356 | #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 |
|---|
| 2357 | #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 |
|---|
| 2358 | #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 |
|---|
| 2359 | #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 |
|---|
| 2360 | #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb |
|---|
| 2361 | #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 2362 | #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 2363 | #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 |
|---|
| 2364 | #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe |
|---|
| 2365 | #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000 |
|---|
| 2366 | #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10 |
|---|
| 2367 | #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000 |
|---|
| 2368 | #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12 |
|---|
| 2369 | #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000 |
|---|
| 2370 | #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14 |
|---|
| 2371 | #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 |
|---|
| 2372 | #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 |
|---|
| 2373 | #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 |
|---|
| 2374 | #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 |
|---|
| 2375 | #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 |
|---|
| 2376 | #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a |
|---|
| 2377 | #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 |
|---|
| 2378 | #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c |
|---|
| 2379 | #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 |
|---|
| 2380 | #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 |
|---|
| 2381 | #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc |
|---|
| 2382 | #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 |
|---|
| 2383 | #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 |
|---|
| 2384 | #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 |
|---|
| 2385 | #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 |
|---|
| 2386 | #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 |
|---|
| 2387 | #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 |
|---|
| 2388 | #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 |
|---|
| 2389 | #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 |
|---|
| 2390 | #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 |
|---|
| 2391 | #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 |
|---|
| 2392 | #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa |
|---|
| 2393 | #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 |
|---|
| 2394 | #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc |
|---|
| 2395 | #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 |
|---|
| 2396 | #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe |
|---|
| 2397 | #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 |
|---|
| 2398 | #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf |
|---|
| 2399 | #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 |
|---|
| 2400 | #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 |
|---|
| 2401 | #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 |
|---|
| 2402 | #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 |
|---|
| 2403 | #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 |
|---|
| 2404 | #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 |
|---|
| 2405 | #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 |
|---|
| 2406 | #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 |
|---|
| 2407 | #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 |
|---|
| 2408 | #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 |
|---|
| 2409 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f |
|---|
| 2410 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 |
|---|
| 2411 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 |
|---|
| 2412 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 |
|---|
| 2413 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 |
|---|
| 2414 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 |
|---|
| 2415 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 |
|---|
| 2416 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 |
|---|
| 2417 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 |
|---|
| 2418 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 |
|---|
| 2419 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 |
|---|
| 2420 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 |
|---|
| 2421 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 |
|---|
| 2422 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb |
|---|
| 2423 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 |
|---|
| 2424 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd |
|---|
| 2425 | #define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 |
|---|
| 2426 | #define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe |
|---|
| 2427 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 |
|---|
| 2428 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf |
|---|
| 2429 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 |
|---|
| 2430 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 |
|---|
| 2431 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 |
|---|
| 2432 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 |
|---|
| 2433 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 |
|---|
| 2434 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 |
|---|
| 2435 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 |
|---|
| 2436 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 |
|---|
| 2437 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 |
|---|
| 2438 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 |
|---|
| 2439 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 |
|---|
| 2440 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 |
|---|
| 2441 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 |
|---|
| 2442 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 |
|---|
| 2443 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 |
|---|
| 2444 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 |
|---|
| 2445 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 |
|---|
| 2446 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 |
|---|
| 2447 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000 |
|---|
| 2448 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19 |
|---|
| 2449 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000 |
|---|
| 2450 | #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a |
|---|
| 2451 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 |
|---|
| 2452 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b |
|---|
| 2453 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2454 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2455 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2456 | #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2457 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 |
|---|
| 2458 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2459 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 |
|---|
| 2460 | #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 |
|---|
| 2461 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 |
|---|
| 2462 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 |
|---|
| 2463 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 |
|---|
| 2464 | #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 |
|---|
| 2465 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 |
|---|
| 2466 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 |
|---|
| 2467 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 |
|---|
| 2468 | #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 |
|---|
| 2469 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 |
|---|
| 2470 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 |
|---|
| 2471 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 |
|---|
| 2472 | #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb |
|---|
| 2473 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 |
|---|
| 2474 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc |
|---|
| 2475 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2476 | #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2477 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 |
|---|
| 2478 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2479 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 |
|---|
| 2480 | #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 |
|---|
| 2481 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 |
|---|
| 2482 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 |
|---|
| 2483 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 |
|---|
| 2484 | #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 |
|---|
| 2485 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 |
|---|
| 2486 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 |
|---|
| 2487 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 |
|---|
| 2488 | #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 |
|---|
| 2489 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 |
|---|
| 2490 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 |
|---|
| 2491 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 |
|---|
| 2492 | #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 |
|---|
| 2493 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 |
|---|
| 2494 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a |
|---|
| 2495 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 |
|---|
| 2496 | #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c |
|---|
| 2497 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 |
|---|
| 2498 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d |
|---|
| 2499 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 |
|---|
| 2500 | #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e |
|---|
| 2501 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2502 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2503 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2504 | #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2505 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 |
|---|
| 2506 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2507 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 |
|---|
| 2508 | #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 |
|---|
| 2509 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 |
|---|
| 2510 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 |
|---|
| 2511 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 |
|---|
| 2512 | #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 |
|---|
| 2513 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 |
|---|
| 2514 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 |
|---|
| 2515 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 |
|---|
| 2516 | #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa |
|---|
| 2517 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 |
|---|
| 2518 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb |
|---|
| 2519 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2520 | #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2521 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 |
|---|
| 2522 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2523 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 |
|---|
| 2524 | #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf |
|---|
| 2525 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 |
|---|
| 2526 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 |
|---|
| 2527 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 |
|---|
| 2528 | #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 |
|---|
| 2529 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 |
|---|
| 2530 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 |
|---|
| 2531 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 |
|---|
| 2532 | #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 |
|---|
| 2533 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 |
|---|
| 2534 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 |
|---|
| 2535 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 |
|---|
| 2536 | #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 |
|---|
| 2537 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 |
|---|
| 2538 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 |
|---|
| 2539 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 |
|---|
| 2540 | #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a |
|---|
| 2541 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 |
|---|
| 2542 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b |
|---|
| 2543 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 |
|---|
| 2544 | #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d |
|---|
| 2545 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 |
|---|
| 2546 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e |
|---|
| 2547 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 |
|---|
| 2548 | #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f |
|---|
| 2549 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 |
|---|
| 2550 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 |
|---|
| 2551 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 |
|---|
| 2552 | #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 |
|---|
| 2553 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 |
|---|
| 2554 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 |
|---|
| 2555 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 |
|---|
| 2556 | #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 |
|---|
| 2557 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 |
|---|
| 2558 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 |
|---|
| 2559 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 |
|---|
| 2560 | #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 |
|---|
| 2561 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 |
|---|
| 2562 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 |
|---|
| 2563 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 |
|---|
| 2564 | #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa |
|---|
| 2565 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 |
|---|
| 2566 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb |
|---|
| 2567 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 |
|---|
| 2568 | #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd |
|---|
| 2569 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 |
|---|
| 2570 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe |
|---|
| 2571 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 |
|---|
| 2572 | #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf |
|---|
| 2573 | #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 |
|---|
| 2574 | #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 |
|---|
| 2575 | #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 |
|---|
| 2576 | #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 |
|---|
| 2577 | #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 |
|---|
| 2578 | #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 |
|---|
| 2579 | #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 |
|---|
| 2580 | #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 |
|---|
| 2581 | #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 |
|---|
| 2582 | #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 |
|---|
| 2583 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 |
|---|
| 2584 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 |
|---|
| 2585 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 |
|---|
| 2586 | #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b |
|---|
| 2587 | #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 |
|---|
| 2588 | #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d |
|---|
| 2589 | #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 |
|---|
| 2590 | #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 |
|---|
| 2591 | #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 |
|---|
| 2592 | #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 |
|---|
| 2593 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 |
|---|
| 2594 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 |
|---|
| 2595 | #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 |
|---|
| 2596 | #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 |
|---|
| 2597 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 |
|---|
| 2598 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 |
|---|
| 2599 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 |
|---|
| 2600 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 |
|---|
| 2601 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 |
|---|
| 2602 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 |
|---|
| 2603 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 |
|---|
| 2604 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 |
|---|
| 2605 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 |
|---|
| 2606 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 |
|---|
| 2607 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 |
|---|
| 2608 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 |
|---|
| 2609 | #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 |
|---|
| 2610 | #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa |
|---|
| 2611 | #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 |
|---|
| 2612 | #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb |
|---|
| 2613 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 |
|---|
| 2614 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc |
|---|
| 2615 | #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 |
|---|
| 2616 | #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 |
|---|
| 2617 | #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 |
|---|
| 2618 | #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 |
|---|
| 2619 | #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 |
|---|
| 2620 | #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 |
|---|
| 2621 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 2622 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 2623 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 2624 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 2625 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 2626 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 2627 | #define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 |
|---|
| 2628 | #define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 |
|---|
| 2629 | #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 |
|---|
| 2630 | #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 |
|---|
| 2631 | #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 |
|---|
| 2632 | #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 |
|---|
| 2633 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2634 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2635 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2636 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2637 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2638 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2639 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2640 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2641 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2642 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2643 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2644 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2645 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2646 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2647 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2648 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2649 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2650 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2651 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2652 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2653 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
|---|
| 2654 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
|---|
| 2655 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
|---|
| 2656 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
|---|
| 2657 | #define DC_GENERICA__GENERICA_EN_MASK 0x1 |
|---|
| 2658 | #define DC_GENERICA__GENERICA_EN__SHIFT 0x0 |
|---|
| 2659 | #define DC_GENERICA__GENERICA_SEL_MASK 0xf80 |
|---|
| 2660 | #define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 |
|---|
| 2661 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
|---|
| 2662 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
|---|
| 2663 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
|---|
| 2664 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
|---|
| 2665 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
|---|
| 2666 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
|---|
| 2667 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
|---|
| 2668 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
|---|
| 2669 | #define DC_GENERICB__GENERICB_EN_MASK 0x1 |
|---|
| 2670 | #define DC_GENERICB__GENERICB_EN__SHIFT 0x0 |
|---|
| 2671 | #define DC_GENERICB__GENERICB_SEL_MASK 0xf00 |
|---|
| 2672 | #define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 |
|---|
| 2673 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
|---|
| 2674 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
|---|
| 2675 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
|---|
| 2676 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
|---|
| 2677 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
|---|
| 2678 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
|---|
| 2679 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
|---|
| 2680 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
|---|
| 2681 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf |
|---|
| 2682 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 |
|---|
| 2683 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 |
|---|
| 2684 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 |
|---|
| 2685 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 |
|---|
| 2686 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 |
|---|
| 2687 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 |
|---|
| 2688 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 |
|---|
| 2689 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 |
|---|
| 2690 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 |
|---|
| 2691 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 |
|---|
| 2692 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 |
|---|
| 2693 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 |
|---|
| 2694 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 |
|---|
| 2695 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 |
|---|
| 2696 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 |
|---|
| 2697 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 |
|---|
| 2698 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f |
|---|
| 2699 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2700 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2701 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2702 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2703 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2704 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2705 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2706 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2707 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2708 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2709 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2710 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2711 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2712 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2713 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2714 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2715 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2716 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2717 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2718 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2719 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2720 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2721 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2722 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2723 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2724 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2725 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2726 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2727 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2728 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2729 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2730 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2731 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2732 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2733 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2734 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2735 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2736 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2737 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2738 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2739 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2740 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2741 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2742 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2743 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2744 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2745 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2746 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2747 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2748 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2749 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2750 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2751 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2752 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2753 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2754 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2755 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2756 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2757 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2758 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2759 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2760 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2761 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2762 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2763 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2764 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2765 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2766 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2767 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2768 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2769 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2770 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2771 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2772 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2773 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2774 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2775 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2776 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2777 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2778 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2779 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2780 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2781 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2782 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2783 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2784 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2785 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2786 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2787 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2788 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2789 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2790 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2791 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2792 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2793 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2794 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2795 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2796 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2797 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2798 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2799 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2800 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2801 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2802 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2803 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2804 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2805 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2806 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2807 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2808 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2809 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2810 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2811 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2812 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2813 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2814 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2815 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2816 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2817 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2818 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2819 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2820 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2821 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2822 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2823 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2824 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2825 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2826 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2827 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2828 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2829 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2830 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2831 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2832 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2833 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2834 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2835 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2836 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2837 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2838 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2839 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2840 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2841 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2842 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2843 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2844 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2845 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2846 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2847 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2848 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2849 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2850 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2851 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2852 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2853 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2854 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2855 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2856 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2857 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2858 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2859 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2860 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2861 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2862 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2863 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2864 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2865 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2866 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2867 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
|---|
| 2868 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
|---|
| 2869 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
|---|
| 2870 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
|---|
| 2871 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
|---|
| 2872 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
|---|
| 2873 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
|---|
| 2874 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
|---|
| 2875 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
|---|
| 2876 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
|---|
| 2877 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
|---|
| 2878 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
|---|
| 2879 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
|---|
| 2880 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
|---|
| 2881 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
|---|
| 2882 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
|---|
| 2883 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 |
|---|
| 2884 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
|---|
| 2885 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
|---|
| 2886 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
|---|
| 2887 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
|---|
| 2888 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
|---|
| 2889 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
|---|
| 2890 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
|---|
| 2891 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
|---|
| 2892 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
|---|
| 2893 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 |
|---|
| 2894 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
|---|
| 2895 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 |
|---|
| 2896 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 |
|---|
| 2897 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 |
|---|
| 2898 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 |
|---|
| 2899 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 |
|---|
| 2900 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 |
|---|
| 2901 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 |
|---|
| 2902 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa |
|---|
| 2903 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 |
|---|
| 2904 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 |
|---|
| 2905 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 |
|---|
| 2906 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 |
|---|
| 2907 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 |
|---|
| 2908 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 |
|---|
| 2909 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 |
|---|
| 2910 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c |
|---|
| 2911 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 |
|---|
| 2912 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e |
|---|
| 2913 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 |
|---|
| 2914 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 |
|---|
| 2915 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 |
|---|
| 2916 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 |
|---|
| 2917 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 |
|---|
| 2918 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 |
|---|
| 2919 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 |
|---|
| 2920 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa |
|---|
| 2921 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 |
|---|
| 2922 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 |
|---|
| 2923 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 |
|---|
| 2924 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 |
|---|
| 2925 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 |
|---|
| 2926 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 |
|---|
| 2927 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 |
|---|
| 2928 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c |
|---|
| 2929 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 |
|---|
| 2930 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e |
|---|
| 2931 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 |
|---|
| 2932 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 |
|---|
| 2933 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 |
|---|
| 2934 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 |
|---|
| 2935 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 |
|---|
| 2936 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 |
|---|
| 2937 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 |
|---|
| 2938 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa |
|---|
| 2939 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 |
|---|
| 2940 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 |
|---|
| 2941 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 |
|---|
| 2942 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 |
|---|
| 2943 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 |
|---|
| 2944 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 |
|---|
| 2945 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 |
|---|
| 2946 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c |
|---|
| 2947 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 |
|---|
| 2948 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e |
|---|
| 2949 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 |
|---|
| 2950 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 |
|---|
| 2951 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 |
|---|
| 2952 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 |
|---|
| 2953 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 |
|---|
| 2954 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 |
|---|
| 2955 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 |
|---|
| 2956 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa |
|---|
| 2957 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 |
|---|
| 2958 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 |
|---|
| 2959 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 |
|---|
| 2960 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 |
|---|
| 2961 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 |
|---|
| 2962 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 |
|---|
| 2963 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 |
|---|
| 2964 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c |
|---|
| 2965 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 |
|---|
| 2966 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e |
|---|
| 2967 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 |
|---|
| 2968 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 |
|---|
| 2969 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 |
|---|
| 2970 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 |
|---|
| 2971 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 |
|---|
| 2972 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 |
|---|
| 2973 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 |
|---|
| 2974 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa |
|---|
| 2975 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 |
|---|
| 2976 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 |
|---|
| 2977 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 |
|---|
| 2978 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 |
|---|
| 2979 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 |
|---|
| 2980 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 |
|---|
| 2981 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 |
|---|
| 2982 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c |
|---|
| 2983 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 |
|---|
| 2984 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e |
|---|
| 2985 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 |
|---|
| 2986 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 |
|---|
| 2987 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 |
|---|
| 2988 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 |
|---|
| 2989 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 |
|---|
| 2990 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 |
|---|
| 2991 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 |
|---|
| 2992 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa |
|---|
| 2993 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 |
|---|
| 2994 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 |
|---|
| 2995 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 |
|---|
| 2996 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 |
|---|
| 2997 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 |
|---|
| 2998 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 |
|---|
| 2999 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 |
|---|
| 3000 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c |
|---|
| 3001 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 |
|---|
| 3002 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e |
|---|
| 3003 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff |
|---|
| 3004 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 |
|---|
| 3005 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 |
|---|
| 3006 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 |
|---|
| 3007 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 |
|---|
| 3008 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 |
|---|
| 3009 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 |
|---|
| 3010 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 |
|---|
| 3011 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 |
|---|
| 3012 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa |
|---|
| 3013 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 |
|---|
| 3014 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 |
|---|
| 3015 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 |
|---|
| 3016 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 |
|---|
| 3017 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 |
|---|
| 3018 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 |
|---|
| 3019 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
|---|
| 3020 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
|---|
| 3021 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 |
|---|
| 3022 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 |
|---|
| 3023 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 |
|---|
| 3024 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 |
|---|
| 3025 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 |
|---|
| 3026 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 |
|---|
| 3027 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 |
|---|
| 3028 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa |
|---|
| 3029 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 |
|---|
| 3030 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 |
|---|
| 3031 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 |
|---|
| 3032 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 |
|---|
| 3033 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 |
|---|
| 3034 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 |
|---|
| 3035 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
|---|
| 3036 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
|---|
| 3037 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3038 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3039 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3040 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3041 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3042 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3043 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3044 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3045 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 |
|---|
| 3046 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf |
|---|
| 3047 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff |
|---|
| 3048 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 |
|---|
| 3049 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 |
|---|
| 3050 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 |
|---|
| 3051 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3052 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3053 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3054 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3055 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3056 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3057 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3058 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3059 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff |
|---|
| 3060 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 |
|---|
| 3061 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 |
|---|
| 3062 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 |
|---|
| 3063 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf |
|---|
| 3064 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
|---|
| 3065 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 |
|---|
| 3066 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 |
|---|
| 3067 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 |
|---|
| 3068 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 |
|---|
| 3069 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 |
|---|
| 3070 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc |
|---|
| 3071 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff |
|---|
| 3072 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 |
|---|
| 3073 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 |
|---|
| 3074 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 |
|---|
| 3075 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf |
|---|
| 3076 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 |
|---|
| 3077 | #define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 |
|---|
| 3078 | #define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 |
|---|
| 3079 | #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 |
|---|
| 3080 | #define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 |
|---|
| 3081 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 |
|---|
| 3082 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc |
|---|
| 3083 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 |
|---|
| 3084 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa |
|---|
| 3085 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 |
|---|
| 3086 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd |
|---|
| 3087 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 |
|---|
| 3088 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe |
|---|
| 3089 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 |
|---|
| 3090 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 |
|---|
| 3091 | #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 |
|---|
| 3092 | #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 |
|---|
| 3093 | #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 |
|---|
| 3094 | #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 |
|---|
| 3095 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 |
|---|
| 3096 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 |
|---|
| 3097 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 |
|---|
| 3098 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 |
|---|
| 3099 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 |
|---|
| 3100 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 |
|---|
| 3101 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 |
|---|
| 3102 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 |
|---|
| 3103 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 |
|---|
| 3104 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 |
|---|
| 3105 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 |
|---|
| 3106 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 |
|---|
| 3107 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 |
|---|
| 3108 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 |
|---|
| 3109 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 |
|---|
| 3110 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa |
|---|
| 3111 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 |
|---|
| 3112 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 |
|---|
| 3113 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 |
|---|
| 3114 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 |
|---|
| 3115 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 |
|---|
| 3116 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 |
|---|
| 3117 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 |
|---|
| 3118 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 |
|---|
| 3119 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 |
|---|
| 3120 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 |
|---|
| 3121 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 |
|---|
| 3122 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a |
|---|
| 3123 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 |
|---|
| 3124 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 |
|---|
| 3125 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 |
|---|
| 3126 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 |
|---|
| 3127 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 |
|---|
| 3128 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 |
|---|
| 3129 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 |
|---|
| 3130 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 |
|---|
| 3131 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 |
|---|
| 3132 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 |
|---|
| 3133 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 |
|---|
| 3134 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 |
|---|
| 3135 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff |
|---|
| 3136 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 |
|---|
| 3137 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 |
|---|
| 3138 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 |
|---|
| 3139 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff |
|---|
| 3140 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 |
|---|
| 3141 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 |
|---|
| 3142 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 |
|---|
| 3143 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 |
|---|
| 3144 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 |
|---|
| 3145 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 |
|---|
| 3146 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 |
|---|
| 3147 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff |
|---|
| 3148 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 |
|---|
| 3149 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 |
|---|
| 3150 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 |
|---|
| 3151 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 |
|---|
| 3152 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 |
|---|
| 3153 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 |
|---|
| 3154 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 |
|---|
| 3155 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff |
|---|
| 3156 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 |
|---|
| 3157 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 |
|---|
| 3158 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e |
|---|
| 3159 | #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 |
|---|
| 3160 | #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f |
|---|
| 3161 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff |
|---|
| 3162 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 |
|---|
| 3163 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 |
|---|
| 3164 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c |
|---|
| 3165 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 |
|---|
| 3166 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e |
|---|
| 3167 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 |
|---|
| 3168 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f |
|---|
| 3169 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff |
|---|
| 3170 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 |
|---|
| 3171 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 |
|---|
| 3172 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 |
|---|
| 3173 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 |
|---|
| 3174 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 |
|---|
| 3175 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 |
|---|
| 3176 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 |
|---|
| 3177 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 |
|---|
| 3178 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 |
|---|
| 3179 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 |
|---|
| 3180 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 |
|---|
| 3181 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
|---|
| 3182 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
|---|
| 3183 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
|---|
| 3184 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
|---|
| 3185 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 |
|---|
| 3186 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
|---|
| 3187 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 |
|---|
| 3188 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
|---|
| 3189 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 |
|---|
| 3190 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 |
|---|
| 3191 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
|---|
| 3192 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
|---|
| 3193 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
|---|
| 3194 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
|---|
| 3195 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 |
|---|
| 3196 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 |
|---|
| 3197 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 |
|---|
| 3198 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
|---|
| 3199 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 |
|---|
| 3200 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
|---|
| 3201 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 |
|---|
| 3202 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 |
|---|
| 3203 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
|---|
| 3204 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
|---|
| 3205 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
|---|
| 3206 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
|---|
| 3207 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 |
|---|
| 3208 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 |
|---|
| 3209 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 |
|---|
| 3210 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3211 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3212 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3213 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3214 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3215 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 |
|---|
| 3216 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3217 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3218 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3219 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3220 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3221 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 |
|---|
| 3222 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 |
|---|
| 3223 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 |
|---|
| 3224 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 |
|---|
| 3225 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
|---|
| 3226 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
|---|
| 3227 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 |
|---|
| 3228 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 |
|---|
| 3229 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 |
|---|
| 3230 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 |
|---|
| 3231 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 |
|---|
| 3232 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 |
|---|
| 3233 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 |
|---|
| 3234 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc |
|---|
| 3235 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 |
|---|
| 3236 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 |
|---|
| 3237 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 |
|---|
| 3238 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 |
|---|
| 3239 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 |
|---|
| 3240 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 |
|---|
| 3241 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 |
|---|
| 3242 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 |
|---|
| 3243 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 |
|---|
| 3244 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 |
|---|
| 3245 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 |
|---|
| 3246 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc |
|---|
| 3247 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 |
|---|
| 3248 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 |
|---|
| 3249 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 |
|---|
| 3250 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 |
|---|
| 3251 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff |
|---|
| 3252 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 |
|---|
| 3253 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f |
|---|
| 3254 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 |
|---|
| 3255 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 |
|---|
| 3256 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 |
|---|
| 3257 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 |
|---|
| 3258 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb |
|---|
| 3259 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 |
|---|
| 3260 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe |
|---|
| 3261 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 |
|---|
| 3262 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 |
|---|
| 3263 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 |
|---|
| 3264 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 |
|---|
| 3265 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 |
|---|
| 3266 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 |
|---|
| 3267 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f |
|---|
| 3268 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 |
|---|
| 3269 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 |
|---|
| 3270 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 |
|---|
| 3271 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK 0x100 |
|---|
| 3272 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT 0x8 |
|---|
| 3273 | #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff |
|---|
| 3274 | #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 |
|---|
| 3275 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 |
|---|
| 3276 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 |
|---|
| 3277 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 |
|---|
| 3278 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 |
|---|
| 3279 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 |
|---|
| 3280 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 |
|---|
| 3281 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 |
|---|
| 3282 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc |
|---|
| 3283 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 |
|---|
| 3284 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 |
|---|
| 3285 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 |
|---|
| 3286 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 |
|---|
| 3287 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 |
|---|
| 3288 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 |
|---|
| 3289 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 |
|---|
| 3290 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c |
|---|
| 3291 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 |
|---|
| 3292 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f |
|---|
| 3293 | #define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 |
|---|
| 3294 | #define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 |
|---|
| 3295 | #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 |
|---|
| 3296 | #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 |
|---|
| 3297 | #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 |
|---|
| 3298 | #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 |
|---|
| 3299 | #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 |
|---|
| 3300 | #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc |
|---|
| 3301 | #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 |
|---|
| 3302 | #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 |
|---|
| 3303 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 |
|---|
| 3304 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 |
|---|
| 3305 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 |
|---|
| 3306 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 |
|---|
| 3307 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 |
|---|
| 3308 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 |
|---|
| 3309 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 |
|---|
| 3310 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 |
|---|
| 3311 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 |
|---|
| 3312 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 |
|---|
| 3313 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 |
|---|
| 3314 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 |
|---|
| 3315 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 |
|---|
| 3316 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 |
|---|
| 3317 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 |
|---|
| 3318 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 |
|---|
| 3319 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 |
|---|
| 3320 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 |
|---|
| 3321 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 |
|---|
| 3322 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 |
|---|
| 3323 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 |
|---|
| 3324 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa |
|---|
| 3325 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 |
|---|
| 3326 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb |
|---|
| 3327 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 |
|---|
| 3328 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc |
|---|
| 3329 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 |
|---|
| 3330 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd |
|---|
| 3331 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 |
|---|
| 3332 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 |
|---|
| 3333 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 |
|---|
| 3334 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 |
|---|
| 3335 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 |
|---|
| 3336 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 |
|---|
| 3337 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 |
|---|
| 3338 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 |
|---|
| 3339 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc |
|---|
| 3340 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 |
|---|
| 3341 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 |
|---|
| 3342 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 |
|---|
| 3343 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 |
|---|
| 3344 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 |
|---|
| 3345 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff |
|---|
| 3346 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 |
|---|
| 3347 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 |
|---|
| 3348 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
|---|
| 3349 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff |
|---|
| 3350 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 |
|---|
| 3351 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 |
|---|
| 3352 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 |
|---|
| 3353 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc |
|---|
| 3354 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 |
|---|
| 3355 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 |
|---|
| 3356 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 |
|---|
| 3357 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 |
|---|
| 3358 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 |
|---|
| 3359 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 |
|---|
| 3360 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 |
|---|
| 3361 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 |
|---|
| 3362 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa |
|---|
| 3363 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 |
|---|
| 3364 | #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc |
|---|
| 3365 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 |
|---|
| 3366 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd |
|---|
| 3367 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 |
|---|
| 3368 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe |
|---|
| 3369 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 |
|---|
| 3370 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf |
|---|
| 3371 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 |
|---|
| 3372 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 |
|---|
| 3373 | #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 |
|---|
| 3374 | #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 |
|---|
| 3375 | #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 |
|---|
| 3376 | #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 |
|---|
| 3377 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 |
|---|
| 3378 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 |
|---|
| 3379 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 |
|---|
| 3380 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 |
|---|
| 3381 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 |
|---|
| 3382 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 |
|---|
| 3383 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 |
|---|
| 3384 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 |
|---|
| 3385 | #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 |
|---|
| 3386 | #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 |
|---|
| 3387 | #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 |
|---|
| 3388 | #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 |
|---|
| 3389 | #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 |
|---|
| 3390 | #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 |
|---|
| 3391 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 |
|---|
| 3392 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a |
|---|
| 3393 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 |
|---|
| 3394 | #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b |
|---|
| 3395 | #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff |
|---|
| 3396 | #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 |
|---|
| 3397 | #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff |
|---|
| 3398 | #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 |
|---|
| 3399 | #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff |
|---|
| 3400 | #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 |
|---|
| 3401 | #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff |
|---|
| 3402 | #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 |
|---|
| 3403 | #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff |
|---|
| 3404 | #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 |
|---|
| 3405 | #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff |
|---|
| 3406 | #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 |
|---|
| 3407 | #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff |
|---|
| 3408 | #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 |
|---|
| 3409 | #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff |
|---|
| 3410 | #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 |
|---|
| 3411 | #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff |
|---|
| 3412 | #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 |
|---|
| 3413 | #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff |
|---|
| 3414 | #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 |
|---|
| 3415 | #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff |
|---|
| 3416 | #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 |
|---|
| 3417 | #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff |
|---|
| 3418 | #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 |
|---|
| 3419 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff |
|---|
| 3420 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 |
|---|
| 3421 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff |
|---|
| 3422 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 |
|---|
| 3423 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff |
|---|
| 3424 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 |
|---|
| 3425 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff |
|---|
| 3426 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 |
|---|
| 3427 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff |
|---|
| 3428 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 |
|---|
| 3429 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff |
|---|
| 3430 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 |
|---|
| 3431 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff |
|---|
| 3432 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 |
|---|
| 3433 | #define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff |
|---|
| 3434 | #define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 |
|---|
| 3435 | #define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff |
|---|
| 3436 | #define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 |
|---|
| 3437 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff |
|---|
| 3438 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 |
|---|
| 3439 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 |
|---|
| 3440 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 |
|---|
| 3441 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 |
|---|
| 3442 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 |
|---|
| 3443 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 |
|---|
| 3444 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 |
|---|
| 3445 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 |
|---|
| 3446 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 |
|---|
| 3447 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 |
|---|
| 3448 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 |
|---|
| 3449 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 |
|---|
| 3450 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 |
|---|
| 3451 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 |
|---|
| 3452 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 |
|---|
| 3453 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 |
|---|
| 3454 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 |
|---|
| 3455 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 |
|---|
| 3456 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa |
|---|
| 3457 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 |
|---|
| 3458 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc |
|---|
| 3459 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 |
|---|
| 3460 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd |
|---|
| 3461 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 |
|---|
| 3462 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe |
|---|
| 3463 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 |
|---|
| 3464 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 |
|---|
| 3465 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 |
|---|
| 3466 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 |
|---|
| 3467 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 |
|---|
| 3468 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 |
|---|
| 3469 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 |
|---|
| 3470 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 |
|---|
| 3471 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 |
|---|
| 3472 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 |
|---|
| 3473 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 |
|---|
| 3474 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 |
|---|
| 3475 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 |
|---|
| 3476 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 |
|---|
| 3477 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 |
|---|
| 3478 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 |
|---|
| 3479 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 |
|---|
| 3480 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a |
|---|
| 3481 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 |
|---|
| 3482 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 |
|---|
| 3483 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 |
|---|
| 3484 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 |
|---|
| 3485 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 |
|---|
| 3486 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 |
|---|
| 3487 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 |
|---|
| 3488 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 |
|---|
| 3489 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 |
|---|
| 3490 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 |
|---|
| 3491 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 |
|---|
| 3492 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 |
|---|
| 3493 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 |
|---|
| 3494 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 |
|---|
| 3495 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 |
|---|
| 3496 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 |
|---|
| 3497 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 |
|---|
| 3498 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 |
|---|
| 3499 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 |
|---|
| 3500 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 |
|---|
| 3501 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 |
|---|
| 3502 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 |
|---|
| 3503 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 |
|---|
| 3504 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 |
|---|
| 3505 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 |
|---|
| 3506 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 |
|---|
| 3507 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 |
|---|
| 3508 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 |
|---|
| 3509 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 |
|---|
| 3510 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 |
|---|
| 3511 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 |
|---|
| 3512 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 |
|---|
| 3513 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 |
|---|
| 3514 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 |
|---|
| 3515 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 |
|---|
| 3516 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 |
|---|
| 3517 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 |
|---|
| 3518 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 |
|---|
| 3519 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 |
|---|
| 3520 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 |
|---|
| 3521 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 |
|---|
| 3522 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 |
|---|
| 3523 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff |
|---|
| 3524 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 |
|---|
| 3525 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 |
|---|
| 3526 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 |
|---|
| 3527 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 |
|---|
| 3528 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d |
|---|
| 3529 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 |
|---|
| 3530 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e |
|---|
| 3531 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff |
|---|
| 3532 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 |
|---|
| 3533 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 |
|---|
| 3534 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 |
|---|
| 3535 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 |
|---|
| 3536 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d |
|---|
| 3537 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 |
|---|
| 3538 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e |
|---|
| 3539 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff |
|---|
| 3540 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 |
|---|
| 3541 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 |
|---|
| 3542 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 |
|---|
| 3543 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 |
|---|
| 3544 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d |
|---|
| 3545 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 |
|---|
| 3546 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e |
|---|
| 3547 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff |
|---|
| 3548 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 |
|---|
| 3549 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 |
|---|
| 3550 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 |
|---|
| 3551 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 |
|---|
| 3552 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d |
|---|
| 3553 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 |
|---|
| 3554 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e |
|---|
| 3555 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 |
|---|
| 3556 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 |
|---|
| 3557 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 |
|---|
| 3558 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 |
|---|
| 3559 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 |
|---|
| 3560 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 |
|---|
| 3561 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 |
|---|
| 3562 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 |
|---|
| 3563 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 |
|---|
| 3564 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc |
|---|
| 3565 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 |
|---|
| 3566 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe |
|---|
| 3567 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 |
|---|
| 3568 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 |
|---|
| 3569 | #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 |
|---|
| 3570 | #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 |
|---|
| 3571 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 |
|---|
| 3572 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 |
|---|
| 3573 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 |
|---|
| 3574 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 |
|---|
| 3575 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 |
|---|
| 3576 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c |
|---|
| 3577 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 |
|---|
| 3578 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 |
|---|
| 3579 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 |
|---|
| 3580 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 |
|---|
| 3581 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 |
|---|
| 3582 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 |
|---|
| 3583 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 |
|---|
| 3584 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 |
|---|
| 3585 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 |
|---|
| 3586 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 |
|---|
| 3587 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 |
|---|
| 3588 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 |
|---|
| 3589 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 |
|---|
| 3590 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 |
|---|
| 3591 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 |
|---|
| 3592 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 |
|---|
| 3593 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 |
|---|
| 3594 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 |
|---|
| 3595 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 |
|---|
| 3596 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 |
|---|
| 3597 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 |
|---|
| 3598 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc |
|---|
| 3599 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 |
|---|
| 3600 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe |
|---|
| 3601 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 |
|---|
| 3602 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 |
|---|
| 3603 | #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 |
|---|
| 3604 | #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 |
|---|
| 3605 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 |
|---|
| 3606 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 |
|---|
| 3607 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 |
|---|
| 3608 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 |
|---|
| 3609 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 |
|---|
| 3610 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c |
|---|
| 3611 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 |
|---|
| 3612 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 |
|---|
| 3613 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 |
|---|
| 3614 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 |
|---|
| 3615 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 |
|---|
| 3616 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 |
|---|
| 3617 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 |
|---|
| 3618 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 |
|---|
| 3619 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 |
|---|
| 3620 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 |
|---|
| 3621 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 |
|---|
| 3622 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 |
|---|
| 3623 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 |
|---|
| 3624 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 |
|---|
| 3625 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 |
|---|
| 3626 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 |
|---|
| 3627 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 |
|---|
| 3628 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 |
|---|
| 3629 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 |
|---|
| 3630 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 |
|---|
| 3631 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 |
|---|
| 3632 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc |
|---|
| 3633 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 |
|---|
| 3634 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe |
|---|
| 3635 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 |
|---|
| 3636 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 |
|---|
| 3637 | #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 |
|---|
| 3638 | #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 |
|---|
| 3639 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 |
|---|
| 3640 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 |
|---|
| 3641 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 |
|---|
| 3642 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 |
|---|
| 3643 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 |
|---|
| 3644 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c |
|---|
| 3645 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 |
|---|
| 3646 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 |
|---|
| 3647 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 |
|---|
| 3648 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 |
|---|
| 3649 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 |
|---|
| 3650 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 |
|---|
| 3651 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 |
|---|
| 3652 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 |
|---|
| 3653 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 |
|---|
| 3654 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 |
|---|
| 3655 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 |
|---|
| 3656 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 |
|---|
| 3657 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 |
|---|
| 3658 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 |
|---|
| 3659 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 |
|---|
| 3660 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 |
|---|
| 3661 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 |
|---|
| 3662 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 |
|---|
| 3663 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 |
|---|
| 3664 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 |
|---|
| 3665 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 |
|---|
| 3666 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc |
|---|
| 3667 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 |
|---|
| 3668 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe |
|---|
| 3669 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 |
|---|
| 3670 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 |
|---|
| 3671 | #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 |
|---|
| 3672 | #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 |
|---|
| 3673 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 |
|---|
| 3674 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 |
|---|
| 3675 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 |
|---|
| 3676 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 |
|---|
| 3677 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 |
|---|
| 3678 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c |
|---|
| 3679 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 |
|---|
| 3680 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 |
|---|
| 3681 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 |
|---|
| 3682 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 |
|---|
| 3683 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 |
|---|
| 3684 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 |
|---|
| 3685 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 |
|---|
| 3686 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 |
|---|
| 3687 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 |
|---|
| 3688 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 |
|---|
| 3689 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 |
|---|
| 3690 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 |
|---|
| 3691 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 |
|---|
| 3692 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 |
|---|
| 3693 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 |
|---|
| 3694 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 |
|---|
| 3695 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 |
|---|
| 3696 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 |
|---|
| 3697 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 |
|---|
| 3698 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 |
|---|
| 3699 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 |
|---|
| 3700 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc |
|---|
| 3701 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 |
|---|
| 3702 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe |
|---|
| 3703 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 |
|---|
| 3704 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 |
|---|
| 3705 | #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 |
|---|
| 3706 | #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 |
|---|
| 3707 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 |
|---|
| 3708 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 |
|---|
| 3709 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 |
|---|
| 3710 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 |
|---|
| 3711 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 |
|---|
| 3712 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c |
|---|
| 3713 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 |
|---|
| 3714 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 |
|---|
| 3715 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 |
|---|
| 3716 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 |
|---|
| 3717 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 |
|---|
| 3718 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 |
|---|
| 3719 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 |
|---|
| 3720 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 |
|---|
| 3721 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 |
|---|
| 3722 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 |
|---|
| 3723 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 |
|---|
| 3724 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 |
|---|
| 3725 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 |
|---|
| 3726 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 |
|---|
| 3727 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 |
|---|
| 3728 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 |
|---|
| 3729 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 |
|---|
| 3730 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 |
|---|
| 3731 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 |
|---|
| 3732 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 |
|---|
| 3733 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 |
|---|
| 3734 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc |
|---|
| 3735 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 |
|---|
| 3736 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe |
|---|
| 3737 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 |
|---|
| 3738 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 |
|---|
| 3739 | #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 |
|---|
| 3740 | #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 |
|---|
| 3741 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 |
|---|
| 3742 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 |
|---|
| 3743 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 |
|---|
| 3744 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 |
|---|
| 3745 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 |
|---|
| 3746 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c |
|---|
| 3747 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 |
|---|
| 3748 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 |
|---|
| 3749 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 |
|---|
| 3750 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 |
|---|
| 3751 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 |
|---|
| 3752 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 |
|---|
| 3753 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 |
|---|
| 3754 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 |
|---|
| 3755 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 |
|---|
| 3756 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 |
|---|
| 3757 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 |
|---|
| 3758 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 |
|---|
| 3759 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 |
|---|
| 3760 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 |
|---|
| 3761 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 |
|---|
| 3762 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 |
|---|
| 3763 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 |
|---|
| 3764 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 |
|---|
| 3765 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 |
|---|
| 3766 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc |
|---|
| 3767 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 |
|---|
| 3768 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe |
|---|
| 3769 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 |
|---|
| 3770 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 |
|---|
| 3771 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 |
|---|
| 3772 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 |
|---|
| 3773 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 |
|---|
| 3774 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 |
|---|
| 3775 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 |
|---|
| 3776 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 |
|---|
| 3777 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 |
|---|
| 3778 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c |
|---|
| 3779 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 |
|---|
| 3780 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 |
|---|
| 3781 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 |
|---|
| 3782 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 |
|---|
| 3783 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 |
|---|
| 3784 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 |
|---|
| 3785 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 |
|---|
| 3786 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 |
|---|
| 3787 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 |
|---|
| 3788 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 |
|---|
| 3789 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 |
|---|
| 3790 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 |
|---|
| 3791 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 |
|---|
| 3792 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 |
|---|
| 3793 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 |
|---|
| 3794 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 |
|---|
| 3795 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 |
|---|
| 3796 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 |
|---|
| 3797 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 |
|---|
| 3798 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 |
|---|
| 3799 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 |
|---|
| 3800 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc |
|---|
| 3801 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 |
|---|
| 3802 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe |
|---|
| 3803 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 |
|---|
| 3804 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 |
|---|
| 3805 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 |
|---|
| 3806 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c |
|---|
| 3807 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 |
|---|
| 3808 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 |
|---|
| 3809 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 |
|---|
| 3810 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 |
|---|
| 3811 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 |
|---|
| 3812 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 |
|---|
| 3813 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 |
|---|
| 3814 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 |
|---|
| 3815 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 |
|---|
| 3816 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 |
|---|
| 3817 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 |
|---|
| 3818 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 |
|---|
| 3819 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 |
|---|
| 3820 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 |
|---|
| 3821 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 |
|---|
| 3822 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 |
|---|
| 3823 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 |
|---|
| 3824 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 |
|---|
| 3825 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 |
|---|
| 3826 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 |
|---|
| 3827 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 |
|---|
| 3828 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 |
|---|
| 3829 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 |
|---|
| 3830 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 |
|---|
| 3831 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 |
|---|
| 3832 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa |
|---|
| 3833 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 |
|---|
| 3834 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb |
|---|
| 3835 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 |
|---|
| 3836 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 |
|---|
| 3837 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 |
|---|
| 3838 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 |
|---|
| 3839 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 |
|---|
| 3840 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 |
|---|
| 3841 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 |
|---|
| 3842 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 |
|---|
| 3843 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 |
|---|
| 3844 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 |
|---|
| 3845 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 |
|---|
| 3846 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 |
|---|
| 3847 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 |
|---|
| 3848 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a |
|---|
| 3849 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 |
|---|
| 3850 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b |
|---|
| 3851 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 |
|---|
| 3852 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 |
|---|
| 3853 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 |
|---|
| 3854 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 |
|---|
| 3855 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 |
|---|
| 3856 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 |
|---|
| 3857 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 |
|---|
| 3858 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 |
|---|
| 3859 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 |
|---|
| 3860 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 |
|---|
| 3861 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 |
|---|
| 3862 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 |
|---|
| 3863 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 |
|---|
| 3864 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 |
|---|
| 3865 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 |
|---|
| 3866 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 |
|---|
| 3867 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 |
|---|
| 3868 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 |
|---|
| 3869 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 |
|---|
| 3870 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 |
|---|
| 3871 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 |
|---|
| 3872 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 |
|---|
| 3873 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 |
|---|
| 3874 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 |
|---|
| 3875 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 |
|---|
| 3876 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 |
|---|
| 3877 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 |
|---|
| 3878 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 |
|---|
| 3879 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 |
|---|
| 3880 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 |
|---|
| 3881 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8 |
|---|
| 3882 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 |
|---|
| 3883 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 |
|---|
| 3884 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 |
|---|
| 3885 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 |
|---|
| 3886 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 |
|---|
| 3887 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 |
|---|
| 3888 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 |
|---|
| 3889 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 |
|---|
| 3890 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 |
|---|
| 3891 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 |
|---|
| 3892 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa |
|---|
| 3893 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 |
|---|
| 3894 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 |
|---|
| 3895 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 |
|---|
| 3896 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 |
|---|
| 3897 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 |
|---|
| 3898 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 |
|---|
| 3899 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 |
|---|
| 3900 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 |
|---|
| 3901 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 |
|---|
| 3902 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 |
|---|
| 3903 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 |
|---|
| 3904 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 |
|---|
| 3905 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 |
|---|
| 3906 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 |
|---|
| 3907 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 |
|---|
| 3908 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 |
|---|
| 3909 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 |
|---|
| 3910 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a |
|---|
| 3911 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 |
|---|
| 3912 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c |
|---|
| 3913 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 |
|---|
| 3914 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d |
|---|
| 3915 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 |
|---|
| 3916 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e |
|---|
| 3917 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 |
|---|
| 3918 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 |
|---|
| 3919 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 |
|---|
| 3920 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 |
|---|
| 3921 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 |
|---|
| 3922 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 |
|---|
| 3923 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 |
|---|
| 3924 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 |
|---|
| 3925 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 |
|---|
| 3926 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a |
|---|
| 3927 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 |
|---|
| 3928 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c |
|---|
| 3929 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 |
|---|
| 3930 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 |
|---|
| 3931 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 |
|---|
| 3932 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 |
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| 3933 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 |
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| 3934 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 |
|---|
| 3935 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 |
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| 3936 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 |
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| 3937 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 |
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| 3938 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 |
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| 3939 | #define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 |
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| 3940 | #define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 |
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| 3941 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 |
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| 3942 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 |
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| 3943 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 |
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| 3944 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 |
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| 3945 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 |
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| 3946 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 |
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| 3947 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 |
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| 3948 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 |
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| 3949 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 |
|---|
| 3950 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a |
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| 3951 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 |
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| 3952 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c |
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| 3953 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 |
|---|
| 3954 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 |
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| 3955 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 |
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| 3956 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 |
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| 3957 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 |
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| 3958 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 |
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| 3959 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 |
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| 3960 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 |
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| 3961 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 |
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| 3962 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a |
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| 3963 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 |
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| 3964 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c |
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| 3965 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 |
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| 3966 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 |
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| 3967 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 |
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| 3968 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 |
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| 3969 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 |
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| 3970 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 |
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| 3971 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 |
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| 3972 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 |
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| 3973 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 |
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| 3974 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc |
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| 3975 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 |
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| 3976 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe |
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| 3977 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 |
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| 3978 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 |
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| 3979 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 |
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| 3980 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 |
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| 3981 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 |
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| 3982 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 |
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| 3983 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 |
|---|
| 3984 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 |
|---|
| 3985 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 |
|---|
| 3986 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 |
|---|
| 3987 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 |
|---|
| 3988 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a |
|---|
| 3989 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 |
|---|
| 3990 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c |
|---|
| 3991 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 |
|---|
| 3992 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d |
|---|
| 3993 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 |
|---|
| 3994 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e |
|---|
| 3995 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 |
|---|
| 3996 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 |
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| 3997 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 |
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| 3998 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 |
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| 3999 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 |
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| 4000 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 |
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| 4001 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 |
|---|
| 4002 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 |
|---|
| 4003 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 |
|---|
| 4004 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f |
|---|
| 4005 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 |
|---|
| 4006 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 |
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| 4007 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 |
|---|
| 4008 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 |
|---|
| 4009 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 |
|---|
| 4010 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 |
|---|
| 4011 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 |
|---|
| 4012 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 |
|---|
| 4013 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 |
|---|
| 4014 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 |
|---|
| 4015 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 |
|---|
| 4016 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f |
|---|
| 4017 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 |
|---|
| 4018 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 |
|---|
| 4019 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 |
|---|
| 4020 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 |
|---|
| 4021 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 |
|---|
| 4022 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 |
|---|
| 4023 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 |
|---|
| 4024 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 |
|---|
| 4025 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 |
|---|
| 4026 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f |
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| 4027 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf |
|---|
| 4028 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 |
|---|
| 4029 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 |
|---|
| 4030 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 |
|---|
| 4031 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 |
|---|
| 4032 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 |
|---|
| 4033 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 |
|---|
| 4034 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc |
|---|
| 4035 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 |
|---|
| 4036 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 |
|---|
| 4037 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 |
|---|
| 4038 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c |
|---|
| 4039 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf |
|---|
| 4040 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 |
|---|
| 4041 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 |
|---|
| 4042 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 |
|---|
| 4043 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 |
|---|
| 4044 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 |
|---|
| 4045 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 |
|---|
| 4046 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc |
|---|
| 4047 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 |
|---|
| 4048 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 |
|---|
| 4049 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 |
|---|
| 4050 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 |
|---|
| 4051 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 |
|---|
| 4052 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e |
|---|
| 4053 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 |
|---|
| 4054 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 |
|---|
| 4055 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 |
|---|
| 4056 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 |
|---|
| 4057 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 |
|---|
| 4058 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 |
|---|
| 4059 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 |
|---|
| 4060 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 |
|---|
| 4061 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 |
|---|
| 4062 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 |
|---|
| 4063 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 |
|---|
| 4064 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 |
|---|
| 4065 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 |
|---|
| 4066 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 |
|---|
| 4067 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 |
|---|
| 4068 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 |
|---|
| 4069 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 |
|---|
| 4070 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc |
|---|
| 4071 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 |
|---|
| 4072 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd |
|---|
| 4073 | #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 |
|---|
| 4074 | #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe |
|---|
| 4075 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 |
|---|
| 4076 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 |
|---|
| 4077 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 |
|---|
| 4078 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 |
|---|
| 4079 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 |
|---|
| 4080 | #define |
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