1 | /* |
2 | * DCE_8_0 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef DCE_8_0_D_H |
25 | #define DCE_8_0_D_H |
26 | |
27 | #define mmPIPE0_PG_CONFIG 0x1760 |
28 | #define mmPIPE0_PG_ENABLE 0x1761 |
29 | #define mmPIPE0_PG_STATUS 0x1762 |
30 | #define mmPIPE1_PG_CONFIG 0x1764 |
31 | #define mmPIPE1_PG_ENABLE 0x1765 |
32 | #define mmPIPE1_PG_STATUS 0x1766 |
33 | #define mmPIPE2_PG_CONFIG 0x1768 |
34 | #define mmPIPE2_PG_ENABLE 0x1769 |
35 | #define mmPIPE2_PG_STATUS 0x176a |
36 | #define mmPIPE3_PG_CONFIG 0x176c |
37 | #define mmPIPE3_PG_ENABLE 0x176d |
38 | #define mmPIPE3_PG_STATUS 0x176e |
39 | #define mmPIPE4_PG_CONFIG 0x1770 |
40 | #define mmPIPE4_PG_ENABLE 0x1771 |
41 | #define mmPIPE4_PG_STATUS 0x1772 |
42 | #define mmPIPE5_PG_CONFIG 0x1774 |
43 | #define mmPIPE5_PG_ENABLE 0x1775 |
44 | #define mmPIPE5_PG_STATUS 0x1776 |
45 | #define mmDC_IP_REQUEST_CNTL 0x1778 |
46 | #define mmDC_PGFSM_CONFIG_REG 0x177c |
47 | #define mmDC_PGFSM_WRITE_REG 0x177d |
48 | #define mmDC_PGCNTL_STATUS_REG 0x177e |
49 | #define mmDCPG_TEST_DEBUG_INDEX 0x1779 |
50 | #define mmDCPG_TEST_DEBUG_DATA 0x177b |
51 | #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 |
52 | #define mmBL1_PWM_USER_LEVEL 0x1629 |
53 | #define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a |
54 | #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b |
55 | #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c |
56 | #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d |
57 | #define mmBL1_PWM_ABM_CNTL 0x162e |
58 | #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f |
59 | #define mmBL1_PWM_GRP2_REG_LOCK 0x1630 |
60 | #define mmDC_ABM1_CNTL 0x1638 |
61 | #define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 |
62 | #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a |
63 | #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b |
64 | #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c |
65 | #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d |
66 | #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e |
67 | #define mmDC_ABM1_ACE_THRES_12 0x163f |
68 | #define mmDC_ABM1_ACE_THRES_34 0x1640 |
69 | #define mmDC_ABM1_ACE_CNTL_MISC 0x1641 |
70 | #define mmDC_ABM1_DEBUG_MISC 0x1649 |
71 | #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a |
72 | #define mmDC_ABM1_HG_MISC_CTRL 0x164b |
73 | #define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c |
74 | #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d |
75 | #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e |
76 | #define mmDC_ABM1_LS_PIXEL_COUNT 0x164f |
77 | #define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 |
78 | #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 |
79 | #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 |
80 | #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 |
81 | #define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 |
82 | #define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 |
83 | #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 |
84 | #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 |
85 | #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 |
86 | #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 |
87 | #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a |
88 | #define mmDC_ABM1_HG_RESULT_1 0x165b |
89 | #define mmDC_ABM1_HG_RESULT_2 0x165c |
90 | #define mmDC_ABM1_HG_RESULT_3 0x165d |
91 | #define mmDC_ABM1_HG_RESULT_4 0x165e |
92 | #define mmDC_ABM1_HG_RESULT_5 0x165f |
93 | #define mmDC_ABM1_HG_RESULT_6 0x1660 |
94 | #define mmDC_ABM1_HG_RESULT_7 0x1661 |
95 | #define mmDC_ABM1_HG_RESULT_8 0x1662 |
96 | #define mmDC_ABM1_HG_RESULT_9 0x1663 |
97 | #define mmDC_ABM1_HG_RESULT_10 0x1664 |
98 | #define mmDC_ABM1_HG_RESULT_11 0x1665 |
99 | #define mmDC_ABM1_HG_RESULT_12 0x1666 |
100 | #define mmDC_ABM1_HG_RESULT_13 0x1667 |
101 | #define mmDC_ABM1_HG_RESULT_14 0x1668 |
102 | #define mmDC_ABM1_HG_RESULT_15 0x1669 |
103 | #define mmDC_ABM1_HG_RESULT_16 0x166a |
104 | #define mmDC_ABM1_HG_RESULT_17 0x166b |
105 | #define mmDC_ABM1_HG_RESULT_18 0x166c |
106 | #define mmDC_ABM1_HG_RESULT_19 0x166d |
107 | #define mmDC_ABM1_HG_RESULT_20 0x166e |
108 | #define mmDC_ABM1_HG_RESULT_21 0x166f |
109 | #define mmDC_ABM1_HG_RESULT_22 0x1670 |
110 | #define mmDC_ABM1_HG_RESULT_23 0x1671 |
111 | #define mmDC_ABM1_HG_RESULT_24 0x1672 |
112 | #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b |
113 | #define mmDC_ABM1_BL_MASTER_LOCK 0x169c |
114 | #define mmABM_TEST_DEBUG_INDEX 0x169e |
115 | #define mmABM_TEST_DEBUG_DATA 0x169f |
116 | #define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c |
117 | #define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c |
118 | #define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c |
119 | #define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c |
120 | #define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c |
121 | #define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c |
122 | #define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c |
123 | #define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d |
124 | #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d |
125 | #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d |
126 | #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d |
127 | #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d |
128 | #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d |
129 | #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d |
130 | #define mmDCFE_DBG_SEL 0x1b7e |
131 | #define mmCRTC0_DCFE_DBG_SEL 0x1b7e |
132 | #define mmCRTC1_DCFE_DBG_SEL 0x1e7e |
133 | #define mmCRTC2_DCFE_DBG_SEL 0x417e |
134 | #define mmCRTC3_DCFE_DBG_SEL 0x447e |
135 | #define mmCRTC4_DCFE_DBG_SEL 0x477e |
136 | #define mmCRTC5_DCFE_DBG_SEL 0x4a7e |
137 | #define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f |
138 | #define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f |
139 | #define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f |
140 | #define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f |
141 | #define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f |
142 | #define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f |
143 | #define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f |
144 | #define mmCRTC_H_TOTAL 0x1b80 |
145 | #define mmCRTC0_CRTC_H_TOTAL 0x1b80 |
146 | #define mmCRTC1_CRTC_H_TOTAL 0x1e80 |
147 | #define mmCRTC2_CRTC_H_TOTAL 0x4180 |
148 | #define mmCRTC3_CRTC_H_TOTAL 0x4480 |
149 | #define mmCRTC4_CRTC_H_TOTAL 0x4780 |
150 | #define mmCRTC5_CRTC_H_TOTAL 0x4a80 |
151 | #define mmCRTC_H_BLANK_START_END 0x1b81 |
152 | #define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 |
153 | #define mmCRTC1_CRTC_H_BLANK_START_END 0x1e81 |
154 | #define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 |
155 | #define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 |
156 | #define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 |
157 | #define mmCRTC5_CRTC_H_BLANK_START_END 0x4a81 |
158 | #define mmCRTC_H_SYNC_A 0x1b82 |
159 | #define mmCRTC0_CRTC_H_SYNC_A 0x1b82 |
160 | #define mmCRTC1_CRTC_H_SYNC_A 0x1e82 |
161 | #define mmCRTC2_CRTC_H_SYNC_A 0x4182 |
162 | #define mmCRTC3_CRTC_H_SYNC_A 0x4482 |
163 | #define mmCRTC4_CRTC_H_SYNC_A 0x4782 |
164 | #define mmCRTC5_CRTC_H_SYNC_A 0x4a82 |
165 | #define mmCRTC_H_SYNC_A_CNTL 0x1b83 |
166 | #define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 |
167 | #define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83 |
168 | #define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 |
169 | #define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 |
170 | #define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 |
171 | #define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83 |
172 | #define mmCRTC_H_SYNC_B 0x1b84 |
173 | #define mmCRTC0_CRTC_H_SYNC_B 0x1b84 |
174 | #define mmCRTC1_CRTC_H_SYNC_B 0x1e84 |
175 | #define mmCRTC2_CRTC_H_SYNC_B 0x4184 |
176 | #define mmCRTC3_CRTC_H_SYNC_B 0x4484 |
177 | #define mmCRTC4_CRTC_H_SYNC_B 0x4784 |
178 | #define mmCRTC5_CRTC_H_SYNC_B 0x4a84 |
179 | #define mmCRTC_H_SYNC_B_CNTL 0x1b85 |
180 | #define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 |
181 | #define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85 |
182 | #define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 |
183 | #define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 |
184 | #define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 |
185 | #define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85 |
186 | #define mmCRTC_VBI_END 0x1b86 |
187 | #define mmCRTC0_CRTC_VBI_END 0x1b86 |
188 | #define mmCRTC1_CRTC_VBI_END 0x1e86 |
189 | #define mmCRTC2_CRTC_VBI_END 0x4186 |
190 | #define mmCRTC3_CRTC_VBI_END 0x4486 |
191 | #define mmCRTC4_CRTC_VBI_END 0x4786 |
192 | #define mmCRTC5_CRTC_VBI_END 0x4a86 |
193 | #define mmCRTC_V_TOTAL 0x1b87 |
194 | #define mmCRTC0_CRTC_V_TOTAL 0x1b87 |
195 | #define mmCRTC1_CRTC_V_TOTAL 0x1e87 |
196 | #define mmCRTC2_CRTC_V_TOTAL 0x4187 |
197 | #define mmCRTC3_CRTC_V_TOTAL 0x4487 |
198 | #define mmCRTC4_CRTC_V_TOTAL 0x4787 |
199 | #define mmCRTC5_CRTC_V_TOTAL 0x4a87 |
200 | #define mmCRTC_V_TOTAL_MIN 0x1b88 |
201 | #define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 |
202 | #define mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88 |
203 | #define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 |
204 | #define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 |
205 | #define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 |
206 | #define mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88 |
207 | #define mmCRTC_V_TOTAL_MAX 0x1b89 |
208 | #define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 |
209 | #define mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89 |
210 | #define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 |
211 | #define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 |
212 | #define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 |
213 | #define mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89 |
214 | #define mmCRTC_V_TOTAL_CONTROL 0x1b8a |
215 | #define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a |
216 | #define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a |
217 | #define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a |
218 | #define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a |
219 | #define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a |
220 | #define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a |
221 | #define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b |
222 | #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b |
223 | #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b |
224 | #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b |
225 | #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b |
226 | #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b |
227 | #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b |
228 | #define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c |
229 | #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c |
230 | #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c |
231 | #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c |
232 | #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c |
233 | #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c |
234 | #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c |
235 | #define mmCRTC_V_BLANK_START_END 0x1b8d |
236 | #define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d |
237 | #define mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d |
238 | #define mmCRTC2_CRTC_V_BLANK_START_END 0x418d |
239 | #define mmCRTC3_CRTC_V_BLANK_START_END 0x448d |
240 | #define mmCRTC4_CRTC_V_BLANK_START_END 0x478d |
241 | #define mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d |
242 | #define mmCRTC_V_SYNC_A 0x1b8e |
243 | #define mmCRTC0_CRTC_V_SYNC_A 0x1b8e |
244 | #define mmCRTC1_CRTC_V_SYNC_A 0x1e8e |
245 | #define mmCRTC2_CRTC_V_SYNC_A 0x418e |
246 | #define mmCRTC3_CRTC_V_SYNC_A 0x448e |
247 | #define mmCRTC4_CRTC_V_SYNC_A 0x478e |
248 | #define mmCRTC5_CRTC_V_SYNC_A 0x4a8e |
249 | #define mmCRTC_V_SYNC_A_CNTL 0x1b8f |
250 | #define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f |
251 | #define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f |
252 | #define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f |
253 | #define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f |
254 | #define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f |
255 | #define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f |
256 | #define mmCRTC_V_SYNC_B 0x1b90 |
257 | #define mmCRTC0_CRTC_V_SYNC_B 0x1b90 |
258 | #define mmCRTC1_CRTC_V_SYNC_B 0x1e90 |
259 | #define mmCRTC2_CRTC_V_SYNC_B 0x4190 |
260 | #define mmCRTC3_CRTC_V_SYNC_B 0x4490 |
261 | #define mmCRTC4_CRTC_V_SYNC_B 0x4790 |
262 | #define mmCRTC5_CRTC_V_SYNC_B 0x4a90 |
263 | #define mmCRTC_V_SYNC_B_CNTL 0x1b91 |
264 | #define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 |
265 | #define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91 |
266 | #define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 |
267 | #define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 |
268 | #define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 |
269 | #define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91 |
270 | #define mmCRTC_DTMTEST_CNTL 0x1b92 |
271 | #define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 |
272 | #define mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92 |
273 | #define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 |
274 | #define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 |
275 | #define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 |
276 | #define mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92 |
277 | #define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 |
278 | #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 |
279 | #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93 |
280 | #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 |
281 | #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 |
282 | #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 |
283 | #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93 |
284 | #define mmCRTC_TRIGA_CNTL 0x1b94 |
285 | #define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 |
286 | #define mmCRTC1_CRTC_TRIGA_CNTL 0x1e94 |
287 | #define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 |
288 | #define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 |
289 | #define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 |
290 | #define mmCRTC5_CRTC_TRIGA_CNTL 0x4a94 |
291 | #define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 |
292 | #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 |
293 | #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95 |
294 | #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 |
295 | #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 |
296 | #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 |
297 | #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95 |
298 | #define mmCRTC_TRIGB_CNTL 0x1b96 |
299 | #define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 |
300 | #define mmCRTC1_CRTC_TRIGB_CNTL 0x1e96 |
301 | #define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 |
302 | #define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 |
303 | #define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 |
304 | #define mmCRTC5_CRTC_TRIGB_CNTL 0x4a96 |
305 | #define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 |
306 | #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 |
307 | #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97 |
308 | #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 |
309 | #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 |
310 | #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 |
311 | #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97 |
312 | #define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 |
313 | #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 |
314 | #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98 |
315 | #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 |
316 | #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 |
317 | #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 |
318 | #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98 |
319 | #define mmCRTC_FLOW_CONTROL 0x1b99 |
320 | #define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 |
321 | #define mmCRTC1_CRTC_FLOW_CONTROL 0x1e99 |
322 | #define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 |
323 | #define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 |
324 | #define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 |
325 | #define mmCRTC5_CRTC_FLOW_CONTROL 0x4a99 |
326 | #define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b |
327 | #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b |
328 | #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b |
329 | #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b |
330 | #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b |
331 | #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b |
332 | #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b |
333 | #define mmCRTC_CONTROL 0x1b9c |
334 | #define mmCRTC0_CRTC_CONTROL 0x1b9c |
335 | #define mmCRTC1_CRTC_CONTROL 0x1e9c |
336 | #define mmCRTC2_CRTC_CONTROL 0x419c |
337 | #define mmCRTC3_CRTC_CONTROL 0x449c |
338 | #define mmCRTC4_CRTC_CONTROL 0x479c |
339 | #define mmCRTC5_CRTC_CONTROL 0x4a9c |
340 | #define mmCRTC_BLANK_CONTROL 0x1b9d |
341 | #define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d |
342 | #define mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d |
343 | #define mmCRTC2_CRTC_BLANK_CONTROL 0x419d |
344 | #define mmCRTC3_CRTC_BLANK_CONTROL 0x449d |
345 | #define mmCRTC4_CRTC_BLANK_CONTROL 0x479d |
346 | #define mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d |
347 | #define mmCRTC_INTERLACE_CONTROL 0x1b9e |
348 | #define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e |
349 | #define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e |
350 | #define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e |
351 | #define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e |
352 | #define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e |
353 | #define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e |
354 | #define mmCRTC_INTERLACE_STATUS 0x1b9f |
355 | #define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f |
356 | #define mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f |
357 | #define mmCRTC2_CRTC_INTERLACE_STATUS 0x419f |
358 | #define mmCRTC3_CRTC_INTERLACE_STATUS 0x449f |
359 | #define mmCRTC4_CRTC_INTERLACE_STATUS 0x479f |
360 | #define mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f |
361 | #define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 |
362 | #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 |
363 | #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0 |
364 | #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0 |
365 | #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0 |
366 | #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0 |
367 | #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0 |
368 | #define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 |
369 | #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 |
370 | #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1 |
371 | #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1 |
372 | #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1 |
373 | #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1 |
374 | #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1 |
375 | #define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 |
376 | #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 |
377 | #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2 |
378 | #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2 |
379 | #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2 |
380 | #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2 |
381 | #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2 |
382 | #define mmCRTC_STATUS 0x1ba3 |
383 | #define mmCRTC0_CRTC_STATUS 0x1ba3 |
384 | #define mmCRTC1_CRTC_STATUS 0x1ea3 |
385 | #define mmCRTC2_CRTC_STATUS 0x41a3 |
386 | #define mmCRTC3_CRTC_STATUS 0x44a3 |
387 | #define mmCRTC4_CRTC_STATUS 0x47a3 |
388 | #define mmCRTC5_CRTC_STATUS 0x4aa3 |
389 | #define mmCRTC_STATUS_POSITION 0x1ba4 |
390 | #define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 |
391 | #define mmCRTC1_CRTC_STATUS_POSITION 0x1ea4 |
392 | #define mmCRTC2_CRTC_STATUS_POSITION 0x41a4 |
393 | #define mmCRTC3_CRTC_STATUS_POSITION 0x44a4 |
394 | #define mmCRTC4_CRTC_STATUS_POSITION 0x47a4 |
395 | #define mmCRTC5_CRTC_STATUS_POSITION 0x4aa4 |
396 | #define mmCRTC_NOM_VERT_POSITION 0x1ba5 |
397 | #define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 |
398 | #define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5 |
399 | #define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5 |
400 | #define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5 |
401 | #define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5 |
402 | #define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5 |
403 | #define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 |
404 | #define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 |
405 | #define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6 |
406 | #define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6 |
407 | #define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6 |
408 | #define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6 |
409 | #define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6 |
410 | #define mmCRTC_STATUS_VF_COUNT 0x1ba7 |
411 | #define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 |
412 | #define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7 |
413 | #define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7 |
414 | #define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7 |
415 | #define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7 |
416 | #define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7 |
417 | #define mmCRTC_STATUS_HV_COUNT 0x1ba8 |
418 | #define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 |
419 | #define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8 |
420 | #define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8 |
421 | #define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8 |
422 | #define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8 |
423 | #define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8 |
424 | #define mmCRTC_COUNT_CONTROL 0x1ba9 |
425 | #define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 |
426 | #define mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9 |
427 | #define mmCRTC2_CRTC_COUNT_CONTROL 0x41a9 |
428 | #define mmCRTC3_CRTC_COUNT_CONTROL 0x44a9 |
429 | #define mmCRTC4_CRTC_COUNT_CONTROL 0x47a9 |
430 | #define mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9 |
431 | #define mmCRTC_COUNT_RESET 0x1baa |
432 | #define mmCRTC0_CRTC_COUNT_RESET 0x1baa |
433 | #define mmCRTC1_CRTC_COUNT_RESET 0x1eaa |
434 | #define mmCRTC2_CRTC_COUNT_RESET 0x41aa |
435 | #define mmCRTC3_CRTC_COUNT_RESET 0x44aa |
436 | #define mmCRTC4_CRTC_COUNT_RESET 0x47aa |
437 | #define mmCRTC5_CRTC_COUNT_RESET 0x4aaa |
438 | #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab |
439 | #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab |
440 | #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab |
441 | #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab |
442 | #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab |
443 | #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab |
444 | #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab |
445 | #define mmCRTC_VERT_SYNC_CONTROL 0x1bac |
446 | #define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac |
447 | #define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac |
448 | #define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac |
449 | #define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac |
450 | #define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac |
451 | #define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac |
452 | #define mmCRTC_STEREO_STATUS 0x1bad |
453 | #define mmCRTC0_CRTC_STEREO_STATUS 0x1bad |
454 | #define mmCRTC1_CRTC_STEREO_STATUS 0x1ead |
455 | #define mmCRTC2_CRTC_STEREO_STATUS 0x41ad |
456 | #define mmCRTC3_CRTC_STEREO_STATUS 0x44ad |
457 | #define mmCRTC4_CRTC_STEREO_STATUS 0x47ad |
458 | #define mmCRTC5_CRTC_STEREO_STATUS 0x4aad |
459 | #define mmCRTC_STEREO_CONTROL 0x1bae |
460 | #define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae |
461 | #define mmCRTC1_CRTC_STEREO_CONTROL 0x1eae |
462 | #define mmCRTC2_CRTC_STEREO_CONTROL 0x41ae |
463 | #define mmCRTC3_CRTC_STEREO_CONTROL 0x44ae |
464 | #define mmCRTC4_CRTC_STEREO_CONTROL 0x47ae |
465 | #define mmCRTC5_CRTC_STEREO_CONTROL 0x4aae |
466 | #define mmCRTC_SNAPSHOT_STATUS 0x1baf |
467 | #define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf |
468 | #define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf |
469 | #define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af |
470 | #define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af |
471 | #define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af |
472 | #define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf |
473 | #define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 |
474 | #define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 |
475 | #define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0 |
476 | #define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0 |
477 | #define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0 |
478 | #define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0 |
479 | #define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0 |
480 | #define mmCRTC_SNAPSHOT_POSITION 0x1bb1 |
481 | #define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 |
482 | #define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1 |
483 | #define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1 |
484 | #define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1 |
485 | #define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1 |
486 | #define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1 |
487 | #define mmCRTC_SNAPSHOT_FRAME 0x1bb2 |
488 | #define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 |
489 | #define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2 |
490 | #define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2 |
491 | #define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2 |
492 | #define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2 |
493 | #define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2 |
494 | #define mmCRTC_START_LINE_CONTROL 0x1bb3 |
495 | #define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 |
496 | #define mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3 |
497 | #define mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3 |
498 | #define mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3 |
499 | #define mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3 |
500 | #define mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3 |
501 | #define mmCRTC_INTERRUPT_CONTROL 0x1bb4 |
502 | #define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 |
503 | #define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4 |
504 | #define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4 |
505 | #define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4 |
506 | #define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4 |
507 | #define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4 |
508 | #define mmCRTC_UPDATE_LOCK 0x1bb5 |
509 | #define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 |
510 | #define mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5 |
511 | #define mmCRTC2_CRTC_UPDATE_LOCK 0x41b5 |
512 | #define mmCRTC3_CRTC_UPDATE_LOCK 0x44b5 |
513 | #define mmCRTC4_CRTC_UPDATE_LOCK 0x47b5 |
514 | #define mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5 |
515 | #define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 |
516 | #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 |
517 | #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6 |
518 | #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 |
519 | #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6 |
520 | #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 |
521 | #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6 |
522 | #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 |
523 | #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 |
524 | #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7 |
525 | #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 |
526 | #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7 |
527 | #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 |
528 | #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7 |
529 | #define mmCRTC_TEST_PATTERN_CONTROL 0x1bba |
530 | #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba |
531 | #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba |
532 | #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba |
533 | #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba |
534 | #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba |
535 | #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba |
536 | #define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb |
537 | #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb |
538 | #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb |
539 | #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb |
540 | #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb |
541 | #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb |
542 | #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb |
543 | #define mmCRTC_TEST_PATTERN_COLOR 0x1bbc |
544 | #define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc |
545 | #define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc |
546 | #define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc |
547 | #define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc |
548 | #define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc |
549 | #define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc |
550 | #define mmMASTER_UPDATE_LOCK 0x1bbd |
551 | #define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd |
552 | #define mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd |
553 | #define mmCRTC2_MASTER_UPDATE_LOCK 0x41bd |
554 | #define mmCRTC3_MASTER_UPDATE_LOCK 0x44bd |
555 | #define mmCRTC4_MASTER_UPDATE_LOCK 0x47bd |
556 | #define mmCRTC5_MASTER_UPDATE_LOCK 0x4abd |
557 | #define mmMASTER_UPDATE_MODE 0x1bbe |
558 | #define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe |
559 | #define mmCRTC1_MASTER_UPDATE_MODE 0x1ebe |
560 | #define mmCRTC2_MASTER_UPDATE_MODE 0x41be |
561 | #define mmCRTC3_MASTER_UPDATE_MODE 0x44be |
562 | #define mmCRTC4_MASTER_UPDATE_MODE 0x47be |
563 | #define mmCRTC5_MASTER_UPDATE_MODE 0x4abe |
564 | #define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf |
565 | #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf |
566 | #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf |
567 | #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf |
568 | #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf |
569 | #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf |
570 | #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf |
571 | #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 |
572 | #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 |
573 | #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0 |
574 | #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 |
575 | #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0 |
576 | #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 |
577 | #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0 |
578 | #define mmCRTC_MVP_STATUS 0x1bc1 |
579 | #define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 |
580 | #define mmCRTC1_CRTC_MVP_STATUS 0x1ec1 |
581 | #define mmCRTC2_CRTC_MVP_STATUS 0x41c1 |
582 | #define mmCRTC3_CRTC_MVP_STATUS 0x44c1 |
583 | #define mmCRTC4_CRTC_MVP_STATUS 0x47c1 |
584 | #define mmCRTC5_CRTC_MVP_STATUS 0x4ac1 |
585 | #define mmCRTC_MASTER_EN 0x1bc2 |
586 | #define mmCRTC0_CRTC_MASTER_EN 0x1bc2 |
587 | #define mmCRTC1_CRTC_MASTER_EN 0x1ec2 |
588 | #define mmCRTC2_CRTC_MASTER_EN 0x41c2 |
589 | #define mmCRTC3_CRTC_MASTER_EN 0x44c2 |
590 | #define mmCRTC4_CRTC_MASTER_EN 0x47c2 |
591 | #define mmCRTC5_CRTC_MASTER_EN 0x4ac2 |
592 | #define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 |
593 | #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 |
594 | #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3 |
595 | #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 |
596 | #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3 |
597 | #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 |
598 | #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3 |
599 | #define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 |
600 | #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 |
601 | #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4 |
602 | #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4 |
603 | #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4 |
604 | #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4 |
605 | #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4 |
606 | #define mmCRTC_OVERSCAN_COLOR 0x1bc8 |
607 | #define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 |
608 | #define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8 |
609 | #define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8 |
610 | #define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8 |
611 | #define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8 |
612 | #define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8 |
613 | #define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 |
614 | #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 |
615 | #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9 |
616 | #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9 |
617 | #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9 |
618 | #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9 |
619 | #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9 |
620 | #define mmCRTC_BLANK_DATA_COLOR 0x1bca |
621 | #define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca |
622 | #define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca |
623 | #define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca |
624 | #define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca |
625 | #define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca |
626 | #define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca |
627 | #define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb |
628 | #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb |
629 | #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb |
630 | #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb |
631 | #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb |
632 | #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb |
633 | #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb |
634 | #define mmCRTC_BLACK_COLOR 0x1bcc |
635 | #define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc |
636 | #define mmCRTC1_CRTC_BLACK_COLOR 0x1ecc |
637 | #define mmCRTC2_CRTC_BLACK_COLOR 0x41cc |
638 | #define mmCRTC3_CRTC_BLACK_COLOR 0x44cc |
639 | #define mmCRTC4_CRTC_BLACK_COLOR 0x47cc |
640 | #define mmCRTC5_CRTC_BLACK_COLOR 0x4acc |
641 | #define mmCRTC_BLACK_COLOR_EXT 0x1bcd |
642 | #define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd |
643 | #define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd |
644 | #define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd |
645 | #define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd |
646 | #define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd |
647 | #define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd |
648 | #define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce |
649 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce |
650 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece |
651 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce |
652 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce |
653 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce |
654 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace |
655 | #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf |
656 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf |
657 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf |
658 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf |
659 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf |
660 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf |
661 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf |
662 | #define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 |
663 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 |
664 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0 |
665 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 |
666 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0 |
667 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 |
668 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0 |
669 | #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 |
670 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 |
671 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1 |
672 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 |
673 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1 |
674 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 |
675 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1 |
676 | #define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 |
677 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 |
678 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2 |
679 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 |
680 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2 |
681 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 |
682 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2 |
683 | #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 |
684 | #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 |
685 | #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3 |
686 | #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 |
687 | #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3 |
688 | #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 |
689 | #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3 |
690 | #define mmCRTC_CRC_CNTL 0x1bd4 |
691 | #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 |
692 | #define mmCRTC1_CRTC_CRC_CNTL 0x1ed4 |
693 | #define mmCRTC2_CRTC_CRC_CNTL 0x41d4 |
694 | #define mmCRTC3_CRTC_CRC_CNTL 0x44d4 |
695 | #define mmCRTC4_CRTC_CRC_CNTL 0x47d4 |
696 | #define mmCRTC5_CRTC_CRC_CNTL 0x4ad4 |
697 | #define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 |
698 | #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 |
699 | #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5 |
700 | #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 |
701 | #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5 |
702 | #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 |
703 | #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5 |
704 | #define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 |
705 | #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 |
706 | #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6 |
707 | #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 |
708 | #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6 |
709 | #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 |
710 | #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6 |
711 | #define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 |
712 | #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 |
713 | #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7 |
714 | #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 |
715 | #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7 |
716 | #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 |
717 | #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7 |
718 | #define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 |
719 | #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 |
720 | #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8 |
721 | #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 |
722 | #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8 |
723 | #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 |
724 | #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8 |
725 | #define mmCRTC_CRC0_DATA_RG 0x1bd9 |
726 | #define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 |
727 | #define mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9 |
728 | #define mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9 |
729 | #define mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9 |
730 | #define mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9 |
731 | #define mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9 |
732 | #define mmCRTC_CRC0_DATA_B 0x1bda |
733 | #define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda |
734 | #define mmCRTC1_CRTC_CRC0_DATA_B 0x1eda |
735 | #define mmCRTC2_CRTC_CRC0_DATA_B 0x41da |
736 | #define mmCRTC3_CRTC_CRC0_DATA_B 0x44da |
737 | #define mmCRTC4_CRTC_CRC0_DATA_B 0x47da |
738 | #define mmCRTC5_CRTC_CRC0_DATA_B 0x4ada |
739 | #define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb |
740 | #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb |
741 | #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb |
742 | #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db |
743 | #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db |
744 | #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db |
745 | #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb |
746 | #define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc |
747 | #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc |
748 | #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc |
749 | #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc |
750 | #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc |
751 | #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc |
752 | #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc |
753 | #define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd |
754 | #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd |
755 | #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd |
756 | #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd |
757 | #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd |
758 | #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd |
759 | #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add |
760 | #define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde |
761 | #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde |
762 | #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede |
763 | #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de |
764 | #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de |
765 | #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de |
766 | #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade |
767 | #define mmCRTC_CRC1_DATA_RG 0x1bdf |
768 | #define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf |
769 | #define mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf |
770 | #define mmCRTC2_CRTC_CRC1_DATA_RG 0x41df |
771 | #define mmCRTC3_CRTC_CRC1_DATA_RG 0x44df |
772 | #define mmCRTC4_CRTC_CRC1_DATA_RG 0x47df |
773 | #define mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf |
774 | #define mmCRTC_CRC1_DATA_B 0x1be0 |
775 | #define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 |
776 | #define mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0 |
777 | #define mmCRTC2_CRTC_CRC1_DATA_B 0x41e0 |
778 | #define mmCRTC3_CRTC_CRC1_DATA_B 0x44e0 |
779 | #define mmCRTC4_CRTC_CRC1_DATA_B 0x47e0 |
780 | #define mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0 |
781 | #define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 |
782 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 |
783 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1 |
784 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 |
785 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1 |
786 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 |
787 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1 |
788 | #define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 |
789 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 |
790 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2 |
791 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 |
792 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2 |
793 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 |
794 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2 |
795 | #define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 |
796 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 |
797 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3 |
798 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 |
799 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3 |
800 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 |
801 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3 |
802 | #define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 |
803 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 |
804 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4 |
805 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 |
806 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4 |
807 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 |
808 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4 |
809 | #define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 |
810 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 |
811 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5 |
812 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 |
813 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5 |
814 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 |
815 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5 |
816 | #define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 |
817 | #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 |
818 | #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6 |
819 | #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 |
820 | #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6 |
821 | #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 |
822 | #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6 |
823 | #define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 |
824 | #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 |
825 | #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7 |
826 | #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7 |
827 | #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7 |
828 | #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7 |
829 | #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7 |
830 | #define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 |
831 | #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 |
832 | #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78 |
833 | #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 |
834 | #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 |
835 | #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 |
836 | #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78 |
837 | #define mmCRTC_GSL_VSYNC_GAP 0x1b79 |
838 | #define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 |
839 | #define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79 |
840 | #define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 |
841 | #define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 |
842 | #define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 |
843 | #define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79 |
844 | #define mmCRTC_GSL_WINDOW 0x1b7a |
845 | #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a |
846 | #define mmCRTC1_CRTC_GSL_WINDOW 0x1e7a |
847 | #define mmCRTC2_CRTC_GSL_WINDOW 0x417a |
848 | #define mmCRTC3_CRTC_GSL_WINDOW 0x447a |
849 | #define mmCRTC4_CRTC_GSL_WINDOW 0x477a |
850 | #define mmCRTC5_CRTC_GSL_WINDOW 0x4a7a |
851 | #define mmCRTC_GSL_CONTROL 0x1b7b |
852 | #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b |
853 | #define mmCRTC1_CRTC_GSL_CONTROL 0x1e7b |
854 | #define mmCRTC2_CRTC_GSL_CONTROL 0x417b |
855 | #define mmCRTC3_CRTC_GSL_CONTROL 0x447b |
856 | #define mmCRTC4_CRTC_GSL_CONTROL 0x477b |
857 | #define mmCRTC5_CRTC_GSL_CONTROL 0x4a7b |
858 | #define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 |
859 | #define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 |
860 | #define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6 |
861 | #define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6 |
862 | #define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6 |
863 | #define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6 |
864 | #define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6 |
865 | #define mmCRTC_TEST_DEBUG_DATA 0x1bc7 |
866 | #define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 |
867 | #define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7 |
868 | #define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7 |
869 | #define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7 |
870 | #define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7 |
871 | #define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7 |
872 | #define mmDAC_ENABLE 0x19e4 |
873 | #define mmDAC_SOURCE_SELECT 0x19e5 |
874 | #define mmDAC_CRC_EN 0x19e6 |
875 | #define mmDAC_CRC_CONTROL 0x19e7 |
876 | #define mmDAC_CRC_SIG_RGB_MASK 0x19e8 |
877 | #define mmDAC_CRC_SIG_CONTROL_MASK 0x19e9 |
878 | #define mmDAC_CRC_SIG_RGB 0x19ea |
879 | #define mmDAC_CRC_SIG_CONTROL 0x19eb |
880 | #define mmDAC_SYNC_TRISTATE_CONTROL 0x19ec |
881 | #define mmDAC_STEREOSYNC_SELECT 0x19ed |
882 | #define mmDAC_AUTODETECT_CONTROL 0x19ee |
883 | #define mmDAC_AUTODETECT_CONTROL2 0x19ef |
884 | #define mmDAC_AUTODETECT_CONTROL3 0x19f0 |
885 | #define mmDAC_AUTODETECT_STATUS 0x19f1 |
886 | #define mmDAC_AUTODETECT_INT_CONTROL 0x19f2 |
887 | #define mmDAC_FORCE_OUTPUT_CNTL 0x19f3 |
888 | #define mmDAC_FORCE_DATA 0x19f4 |
889 | #define mmDAC_POWERDOWN 0x19f5 |
890 | #define mmDAC_CONTROL 0x19f6 |
891 | #define mmDAC_COMPARATOR_ENABLE 0x19f7 |
892 | #define mmDAC_COMPARATOR_OUTPUT 0x19f8 |
893 | #define mmDAC_PWR_CNTL 0x19f9 |
894 | #define mmDAC_DFT_CONFIG 0x19fa |
895 | #define mmDAC_FIFO_STATUS 0x19fb |
896 | #define mmPERFCOUNTER_CNTL 0x170 |
897 | #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 |
898 | #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870 |
899 | #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24 |
900 | #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24 |
901 | #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124 |
902 | #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424 |
903 | #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724 |
904 | #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24 |
905 | #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40 |
906 | #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14 |
907 | #define mmPERFCOUNTER_STATE 0x171 |
908 | #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 |
909 | #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871 |
910 | #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25 |
911 | #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25 |
912 | #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125 |
913 | #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425 |
914 | #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725 |
915 | #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25 |
916 | #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41 |
917 | #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15 |
918 | #define mmPERFMON_CNTL 0x173 |
919 | #define mmDC_PERFMON0_PERFMON_CNTL 0x173 |
920 | #define mmDC_PERFMON1_PERFMON_CNTL 0x1873 |
921 | #define mmDC_PERFMON2_PERFMON_CNTL 0x1b27 |
922 | #define mmDC_PERFMON3_PERFMON_CNTL 0x1e27 |
923 | #define mmDC_PERFMON4_PERFMON_CNTL 0x4127 |
924 | #define mmDC_PERFMON5_PERFMON_CNTL 0x4427 |
925 | #define mmDC_PERFMON6_PERFMON_CNTL 0x4727 |
926 | #define mmDC_PERFMON7_PERFMON_CNTL 0x4a27 |
927 | #define mmDC_PERFMON8_PERFMON_CNTL 0x4c43 |
928 | #define mmDC_PERFMON9_PERFMON_CNTL 0x4d17 |
929 | #define mmPERFMON_CVALUE_INT_MISC 0x172 |
930 | #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 |
931 | #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872 |
932 | #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26 |
933 | #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26 |
934 | #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126 |
935 | #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426 |
936 | #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726 |
937 | #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26 |
938 | #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42 |
939 | #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16 |
940 | #define mmPERFMON_CVALUE_LOW 0x174 |
941 | #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 |
942 | #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874 |
943 | #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28 |
944 | #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28 |
945 | #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128 |
946 | #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428 |
947 | #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728 |
948 | #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28 |
949 | #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44 |
950 | #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18 |
951 | #define mmPERFMON_HI 0x175 |
952 | #define mmDC_PERFMON0_PERFMON_HI 0x175 |
953 | #define mmDC_PERFMON1_PERFMON_HI 0x1875 |
954 | #define mmDC_PERFMON2_PERFMON_HI 0x1b29 |
955 | #define mmDC_PERFMON3_PERFMON_HI 0x1e29 |
956 | #define mmDC_PERFMON4_PERFMON_HI 0x4129 |
957 | #define mmDC_PERFMON5_PERFMON_HI 0x4429 |
958 | #define mmDC_PERFMON6_PERFMON_HI 0x4729 |
959 | #define mmDC_PERFMON7_PERFMON_HI 0x4a29 |
960 | #define mmDC_PERFMON8_PERFMON_HI 0x4c45 |
961 | #define mmDC_PERFMON9_PERFMON_HI 0x4d19 |
962 | #define mmPERFMON_LOW 0x176 |
963 | #define mmDC_PERFMON0_PERFMON_LOW 0x176 |
964 | #define mmDC_PERFMON1_PERFMON_LOW 0x1876 |
965 | #define mmDC_PERFMON2_PERFMON_LOW 0x1b2a |
966 | #define mmDC_PERFMON3_PERFMON_LOW 0x1e2a |
967 | #define mmDC_PERFMON4_PERFMON_LOW 0x412a |
968 | #define mmDC_PERFMON5_PERFMON_LOW 0x442a |
969 | #define mmDC_PERFMON6_PERFMON_LOW 0x472a |
970 | #define mmDC_PERFMON7_PERFMON_LOW 0x4a2a |
971 | #define mmDC_PERFMON8_PERFMON_LOW 0x4c46 |
972 | #define mmDC_PERFMON9_PERFMON_LOW 0x4d1a |
973 | #define mmPERFMON_TEST_DEBUG_INDEX 0x177 |
974 | #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 |
975 | #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877 |
976 | #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b |
977 | #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b |
978 | #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b |
979 | #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b |
980 | #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b |
981 | #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b |
982 | #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47 |
983 | #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b |
984 | #define mmPERFMON_TEST_DEBUG_DATA 0x178 |
985 | #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 |
986 | #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878 |
987 | #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c |
988 | #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c |
989 | #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c |
990 | #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c |
991 | #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c |
992 | #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c |
993 | #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48 |
994 | #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c |
995 | #define mmVGA25_PPLL_REF_DIV 0xd8 |
996 | #define mmVGA28_PPLL_REF_DIV 0xd9 |
997 | #define mmVGA41_PPLL_REF_DIV 0xda |
998 | #define mmVGA25_PPLL_FB_DIV 0xdc |
999 | #define mmVGA28_PPLL_FB_DIV 0xdd |
1000 | #define mmVGA41_PPLL_FB_DIV 0xde |
1001 | #define mmVGA25_PPLL_POST_DIV 0xe0 |
1002 | #define mmVGA28_PPLL_POST_DIV 0xe1 |
1003 | #define mmVGA41_PPLL_POST_DIV 0xe2 |
1004 | #define mmVGA25_PPLL_ANALOG 0xe4 |
1005 | #define mmVGA28_PPLL_ANALOG 0xe5 |
1006 | #define mmVGA41_PPLL_ANALOG 0xe6 |
1007 | #define mmDPREFCLK_CNTL 0x118 |
1008 | #define mmSCANIN_SOFT_RESET 0x11e |
1009 | #define mmDCCG_GTC_CNTL 0x120 |
1010 | #define mmDCCG_GTC_DTO_INCR 0x121 |
1011 | #define mmDCCG_GTC_DTO_MODULO 0x122 |
1012 | #define mmDCCG_GTC_CURRENT 0x123 |
1013 | #define mmDCCG_DS_DTO_INCR 0x113 |
1014 | #define mmDCCG_DS_DTO_MODULO 0x114 |
1015 | #define mmDCCG_DS_CNTL 0x115 |
1016 | #define mmDCCG_DS_HW_CAL_INTERVAL 0x116 |
1017 | #define mmDCCG_DS_DEBUG_CNTL 0x112 |
1018 | #define mmDMCU_SMU_INTERRUPT_CNTL 0x12c |
1019 | #define mmSMU_CONTROL 0x12d |
1020 | #define mmSMU_INTERRUPT_CONTROL 0x12e |
1021 | #define mmDAC_CLK_ENABLE 0x128 |
1022 | #define mmDVO_CLK_ENABLE 0x129 |
1023 | #define mmDCCG_GATE_DISABLE_CNTL 0x134 |
1024 | #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 |
1025 | #define mmSCLK_CGTT_BLK_CTRL_REG 0x136 |
1026 | #define mmDCCG_CAC_STATUS 0x137 |
1027 | #define mmPIXCLK1_RESYNC_CNTL 0x138 |
1028 | #define mmPIXCLK2_RESYNC_CNTL 0x139 |
1029 | #define mmPIXCLK0_RESYNC_CNTL 0x13a |
1030 | #define mmMICROSECOND_TIME_BASE_DIV 0x13b |
1031 | #define mmDCCG_DISP_CNTL_REG 0x13f |
1032 | #define mmDISPPLL_BG_CNTL 0x13c |
1033 | #define mmDIG_SOFT_RESET 0x13d |
1034 | #define mmMILLISECOND_TIME_BASE_DIV 0x130 |
1035 | #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 |
1036 | #define mmLIGHT_SLEEP_CNTL 0x132 |
1037 | #define mmDCCG_PERFMON_CNTL 0x133 |
1038 | #define mmCRTC0_PIXEL_RATE_CNTL 0x140 |
1039 | #define mmDP_DTO0_PHASE 0x141 |
1040 | #define mmDP_DTO0_MODULO 0x142 |
1041 | #define mmCRTC1_PIXEL_RATE_CNTL 0x144 |
1042 | #define mmDP_DTO1_PHASE 0x145 |
1043 | #define mmDP_DTO1_MODULO 0x146 |
1044 | #define mmCRTC2_PIXEL_RATE_CNTL 0x148 |
1045 | #define mmDP_DTO2_PHASE 0x149 |
1046 | #define mmDP_DTO2_MODULO 0x14a |
1047 | #define mmCRTC3_PIXEL_RATE_CNTL 0x14c |
1048 | #define mmDP_DTO3_PHASE 0x14d |
1049 | #define mmDP_DTO3_MODULO 0x14e |
1050 | #define mmCRTC4_PIXEL_RATE_CNTL 0x150 |
1051 | #define mmDP_DTO4_PHASE 0x151 |
1052 | #define mmDP_DTO4_MODULO 0x152 |
1053 | #define mmCRTC5_PIXEL_RATE_CNTL 0x154 |
1054 | #define mmDP_DTO5_PHASE 0x155 |
1055 | #define mmDP_DTO5_MODULO 0x156 |
1056 | #define mmDCFE0_SOFT_RESET 0x158 |
1057 | #define mmDCFE1_SOFT_RESET 0x159 |
1058 | #define mmDCFE2_SOFT_RESET 0x15a |
1059 | #define mmDCFE3_SOFT_RESET 0x15b |
1060 | #define mmDCFE4_SOFT_RESET 0x15c |
1061 | #define mmDCFE5_SOFT_RESET 0x15d |
1062 | #define mmDCI_SOFT_RESET 0x15e |
1063 | #define mmDCCG_SOFT_RESET 0x15f |
1064 | #define mmSYMCLKA_CLOCK_ENABLE 0x160 |
1065 | #define mmSYMCLKB_CLOCK_ENABLE 0x161 |
1066 | #define mmSYMCLKC_CLOCK_ENABLE 0x162 |
1067 | #define mmSYMCLKD_CLOCK_ENABLE 0x163 |
1068 | #define mmSYMCLKE_CLOCK_ENABLE 0x164 |
1069 | #define mmSYMCLKF_CLOCK_ENABLE 0x165 |
1070 | #define mmSYMCLKG_CLOCK_ENABLE 0x117 |
1071 | #define mmUNIPHY_SOFT_RESET 0x166 |
1072 | #define mmDCO_SOFT_RESET 0x167 |
1073 | #define mmDVOACLKD_CNTL 0x168 |
1074 | #define mmDVOACLKC_MVP_CNTL 0x169 |
1075 | #define mmDVOACLKC_CNTL 0x16a |
1076 | #define mmDCCG_AUDIO_DTO_SOURCE 0x16b |
1077 | #define mmDCCG_AUDIO_DTO0_PHASE 0x16c |
1078 | #define mmDCCG_AUDIO_DTO0_MODULE 0x16d |
1079 | #define mmDCCG_AUDIO_DTO1_PHASE 0x16e |
1080 | #define mmDCCG_AUDIO_DTO1_MODULE 0x16f |
1081 | #define mmDCCG_TEST_DEBUG_INDEX 0x17c |
1082 | #define mmDCCG_TEST_DEBUG_DATA 0x17d |
1083 | #define mmDCCG_TEST_CLK_SEL 0x17e |
1084 | #define mmPLL_REF_DIV 0x1700 |
1085 | #define mmDCCG_PLL0_PLL_REF_DIV 0x1700 |
1086 | #define mmDCCG_PLL1_PLL_REF_DIV 0x1714 |
1087 | #define mmDCCG_PLL2_PLL_REF_DIV 0x1728 |
1088 | #define mmDCCG_PLL3_PLL_REF_DIV 0x173c |
1089 | #define mmPLL_FB_DIV 0x1701 |
1090 | #define mmDCCG_PLL0_PLL_FB_DIV 0x1701 |
1091 | #define mmDCCG_PLL1_PLL_FB_DIV 0x1715 |
1092 | #define mmDCCG_PLL2_PLL_FB_DIV 0x1729 |
1093 | #define mmDCCG_PLL3_PLL_FB_DIV 0x173d |
1094 | #define mmPLL_POST_DIV 0x1702 |
1095 | #define mmDCCG_PLL0_PLL_POST_DIV 0x1702 |
1096 | #define mmDCCG_PLL1_PLL_POST_DIV 0x1716 |
1097 | #define mmDCCG_PLL2_PLL_POST_DIV 0x172a |
1098 | #define mmDCCG_PLL3_PLL_POST_DIV 0x173e |
1099 | #define mmPLL_SS_AMOUNT_DSFRAC 0x1703 |
1100 | #define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 |
1101 | #define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717 |
1102 | #define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b |
1103 | #define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f |
1104 | #define mmPLL_SS_CNTL 0x1704 |
1105 | #define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 |
1106 | #define mmDCCG_PLL1_PLL_SS_CNTL 0x1718 |
1107 | #define mmDCCG_PLL2_PLL_SS_CNTL 0x172c |
1108 | #define mmDCCG_PLL3_PLL_SS_CNTL 0x1740 |
1109 | #define mmPLL_DS_CNTL 0x1705 |
1110 | #define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 |
1111 | #define mmDCCG_PLL1_PLL_DS_CNTL 0x1719 |
1112 | #define mmDCCG_PLL2_PLL_DS_CNTL 0x172d |
1113 | #define mmDCCG_PLL3_PLL_DS_CNTL 0x1741 |
1114 | #define mmPLL_IDCLK_CNTL 0x1706 |
1115 | #define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 |
1116 | #define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a |
1117 | #define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e |
1118 | #define mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742 |
1119 | #define mmPLL_CNTL 0x1707 |
1120 | #define mmDCCG_PLL0_PLL_CNTL 0x1707 |
1121 | #define mmDCCG_PLL1_PLL_CNTL 0x171b |
1122 | #define mmDCCG_PLL2_PLL_CNTL 0x172f |
1123 | #define mmDCCG_PLL3_PLL_CNTL 0x1743 |
1124 | #define mmPLL_ANALOG 0x1708 |
1125 | #define mmDCCG_PLL0_PLL_ANALOG 0x1708 |
1126 | #define mmDCCG_PLL1_PLL_ANALOG 0x171c |
1127 | #define mmDCCG_PLL2_PLL_ANALOG 0x1730 |
1128 | #define mmDCCG_PLL3_PLL_ANALOG 0x1744 |
1129 | #define mmPLL_ANALOG_CNTL 0x1711 |
1130 | #define mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711 |
1131 | #define mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725 |
1132 | #define mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739 |
1133 | #define mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d |
1134 | #define mmPLL_VREG_CNTL 0x1709 |
1135 | #define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 |
1136 | #define mmDCCG_PLL1_PLL_VREG_CNTL 0x171d |
1137 | #define mmDCCG_PLL2_PLL_VREG_CNTL 0x1731 |
1138 | #define mmDCCG_PLL3_PLL_VREG_CNTL 0x1745 |
1139 | #define mmPLL_XOR_LOCK 0x1710 |
1140 | #define mmDCCG_PLL0_PLL_XOR_LOCK 0x1710 |
1141 | #define mmDCCG_PLL1_PLL_XOR_LOCK 0x1724 |
1142 | #define mmDCCG_PLL2_PLL_XOR_LOCK 0x1738 |
1143 | #define mmDCCG_PLL3_PLL_XOR_LOCK 0x174c |
1144 | #define mmPLL_UNLOCK_DETECT_CNTL 0x170a |
1145 | #define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a |
1146 | #define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e |
1147 | #define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732 |
1148 | #define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746 |
1149 | #define mmPLL_DEBUG_CNTL 0x170b |
1150 | #define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b |
1151 | #define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f |
1152 | #define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733 |
1153 | #define mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747 |
1154 | #define mmPLL_UPDATE_LOCK 0x170c |
1155 | #define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c |
1156 | #define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720 |
1157 | #define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734 |
1158 | #define mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748 |
1159 | #define mmPLL_UPDATE_CNTL 0x170d |
1160 | #define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d |
1161 | #define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721 |
1162 | #define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735 |
1163 | #define mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749 |
1164 | #define mmPLL_DISPCLK_DTO_CNTL 0x170e |
1165 | #define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e |
1166 | #define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722 |
1167 | #define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736 |
1168 | #define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a |
1169 | #define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f |
1170 | #define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f |
1171 | #define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723 |
1172 | #define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737 |
1173 | #define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b |
1174 | #define mmDENTIST_DISPCLK_CNTL 0x124 |
1175 | #define mmDCDEBUG_BUS_CLK1_SEL 0x1860 |
1176 | #define mmDCDEBUG_BUS_CLK2_SEL 0x1861 |
1177 | #define mmDCDEBUG_BUS_CLK3_SEL 0x1862 |
1178 | #define mmDCDEBUG_BUS_CLK4_SEL 0x1863 |
1179 | #define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a |
1180 | #define mmDCDEBUG_OUT_CNTL 0x186b |
1181 | #define mmDCDEBUG_OUT_DATA 0x186e |
1182 | #define mmDMIF_ADDR_CONFIG 0x2f5 |
1183 | #define mmDMIF_CONTROL 0x2f6 |
1184 | #define mmDMIF_STATUS 0x2f7 |
1185 | #define mmDMIF_HW_DEBUG 0x2f8 |
1186 | #define mmDMIF_ARBITRATION_CONTROL 0x2f9 |
1187 | #define mmPIPE0_ARBITRATION_CONTROL3 0x2fa |
1188 | #define mmPIPE1_ARBITRATION_CONTROL3 0x2fb |
1189 | #define mmPIPE2_ARBITRATION_CONTROL3 0x2fc |
1190 | #define mmPIPE3_ARBITRATION_CONTROL3 0x2fd |
1191 | #define mmPIPE4_ARBITRATION_CONTROL3 0x2fe |
1192 | #define mmPIPE5_ARBITRATION_CONTROL3 0x2ff |
1193 | #define mmDMIF_TEST_DEBUG_INDEX 0x312 |
1194 | #define mmDMIF_TEST_DEBUG_DATA 0x313 |
1195 | #define ixDMIF_DEBUG02_CORE0 0x2 |
1196 | #define ixDMIF_DEBUG02_CORE1 0xa |
1197 | #define mmDMIF_ADDR_CALC 0x300 |
1198 | #define mmDMIF_STATUS2 0x301 |
1199 | #define mmPIPE0_MAX_REQUESTS 0x302 |
1200 | #define mmPIPE1_MAX_REQUESTS 0x303 |
1201 | #define mmPIPE2_MAX_REQUESTS 0x304 |
1202 | #define mmPIPE3_MAX_REQUESTS 0x305 |
1203 | #define mmPIPE4_MAX_REQUESTS 0x306 |
1204 | #define mmPIPE5_MAX_REQUESTS 0x307 |
1205 | #define mmLOW_POWER_TILING_CONTROL 0x325 |
1206 | #define mmMCIF_CONTROL 0x314 |
1207 | #define mmMCIF_WRITE_COMBINE_CONTROL 0x315 |
1208 | #define mmMCIF_TEST_DEBUG_INDEX 0x316 |
1209 | #define mmMCIF_TEST_DEBUG_DATA 0x317 |
1210 | #define ixIDDCCIF02_DBG_DCCIF_C 0x9 |
1211 | #define ixIDDCCIF04_DBG_DCCIF_E 0xb |
1212 | #define ixIDDCCIF05_DBG_DCCIF_F 0xc |
1213 | #define mmMCIF_VMID 0x318 |
1214 | #define mmMCIF_MEM_CONTROL 0x319 |
1215 | #define mmCC_DC_PIPE_DIS 0x177f |
1216 | #define mmMC_DC_INTERFACE_NACK_STATUS 0x31c |
1217 | #define mmDC_RBBMIF_RDWR_CNTL1 0x31a |
1218 | #define mmDC_RBBMIF_RDWR_CNTL2 0x31d |
1219 | #define mmDC_RBBMIF_RDWR_CNTL3 0x311 |
1220 | #define mmDCI_MEM_PWR_STATE 0x31b |
1221 | #define mmDCI_MEM_PWR_STATE2 0x322 |
1222 | #define mmDCI_CLK_CNTL 0x31e |
1223 | #define mmDCCG_VPCLK_CNTL 0x31f |
1224 | #define mmDCI_MEM_PWR_CNTL 0x326 |
1225 | #define mmDC_XDMA_INTERFACE_CNTL 0x327 |
1226 | #define mmDCI_TEST_DEBUG_INDEX 0x320 |
1227 | #define mmDCI_TEST_DEBUG_DATA 0x321 |
1228 | #define mmDCI_DEBUG_CONFIG 0x323 |
1229 | #define mmPIPE0_DMIF_BUFFER_CONTROL 0x328 |
1230 | #define mmPIPE1_DMIF_BUFFER_CONTROL 0x330 |
1231 | #define mmPIPE2_DMIF_BUFFER_CONTROL 0x338 |
1232 | #define mmPIPE3_DMIF_BUFFER_CONTROL 0x340 |
1233 | #define mmPIPE4_DMIF_BUFFER_CONTROL 0x348 |
1234 | #define mmPIPE5_DMIF_BUFFER_CONTROL 0x350 |
1235 | #define mmMCIF_BUFMGR_SW_CONTROL 0x358 |
1236 | #define mmMCIF_BUFMGR_STATUS 0x35a |
1237 | #define mmMCIF_BUF_PITCH 0x35b |
1238 | #define mmMCIF_BUF_1_ADDR_Y_LOW 0x35c |
1239 | #define mmMCIF_BUF_2_ADDR_Y_LOW 0x360 |
1240 | #define mmMCIF_BUF_3_ADDR_Y_LOW 0x364 |
1241 | #define mmMCIF_BUF_4_ADDR_Y_LOW 0x368 |
1242 | #define mmMCIF_BUF_1_ADDR_UP 0x35d |
1243 | #define mmMCIF_BUF_2_ADDR_UP 0x361 |
1244 | #define mmMCIF_BUF_3_ADDR_UP 0x365 |
1245 | #define mmMCIF_BUF_4_ADDR_UP 0x369 |
1246 | #define mmMCIF_BUF_1_ADDR_C_LOW 0x35e |
1247 | #define mmMCIF_BUF_2_ADDR_C_LOW 0x362 |
1248 | #define mmMCIF_BUF_3_ADDR_C_LOW 0x366 |
1249 | #define mmMCIF_BUF_4_ADDR_C_LOW 0x36a |
1250 | #define mmMCIF_BUF_1_STATUS 0x35f |
1251 | #define mmMCIF_BUF_2_STATUS 0x363 |
1252 | #define mmMCIF_BUF_3_STATUS 0x367 |
1253 | #define mmMCIF_BUF_4_STATUS 0x36b |
1254 | #define mmMCIF_SI_ARBITRATION_CONTROL 0x36c |
1255 | #define mmMCIF_URGENCY_WATERMARK 0x36d |
1256 | #define mmDC_GENERICA 0x1900 |
1257 | #define mmDC_GENERICB 0x1901 |
1258 | #define mmDC_PAD_EXTERN_SIG 0x1902 |
1259 | #define mmDC_REF_CLK_CNTL 0x1903 |
1260 | #define mmDC_GPIO_DEBUG 0x1904 |
1261 | #define mmDCO_MEM_POWER_STATE 0x1906 |
1262 | #define mmDCO_MEM_POWER_STATE_2 0x193a |
1263 | #define mmDCO_LIGHT_SLEEP_DIS 0x1907 |
1264 | #define mmUNIPHY_IMPCAL_LINKA 0x1908 |
1265 | #define mmUNIPHY_IMPCAL_LINKB 0x1909 |
1266 | #define mmUNIPHY_IMPCAL_PERIOD 0x190a |
1267 | #define mmAUXP_IMPCAL 0x190b |
1268 | #define mmAUXN_IMPCAL 0x190c |
1269 | #define mmDCIO_IMPCAL_CNTL_AB 0x190d |
1270 | #define mmUNIPHY_IMPCAL_PSW_AB 0x190e |
1271 | #define mmUNIPHY_IMPCAL_LINKC 0x190f |
1272 | #define mmUNIPHY_IMPCAL_LINKD 0x1910 |
1273 | #define mmDCIO_IMPCAL_CNTL_CD 0x1911 |
1274 | #define mmUNIPHY_IMPCAL_PSW_CD 0x1912 |
1275 | #define mmUNIPHY_IMPCAL_LINKE 0x1913 |
1276 | #define mmUNIPHY_IMPCAL_LINKF 0x1914 |
1277 | #define mmDCIO_IMPCAL_CNTL_EF 0x1915 |
1278 | #define mmUNIPHY_IMPCAL_PSW_EF 0x1916 |
1279 | #define mmDC_PINSTRAPS 0x1917 |
1280 | #define mmDC_DVODATA_CONFIG 0x1905 |
1281 | #define mmLVTMA_PWRSEQ_CNTL 0x1919 |
1282 | #define mmLVTMA_PWRSEQ_STATE 0x191a |
1283 | #define mmLVTMA_PWRSEQ_REF_DIV 0x191b |
1284 | #define mmLVTMA_PWRSEQ_DELAY1 0x191c |
1285 | #define mmLVTMA_PWRSEQ_DELAY2 0x191d |
1286 | #define mmBL_PWM_CNTL 0x191e |
1287 | #define mmBL_PWM_CNTL2 0x191f |
1288 | #define mmBL_PWM_PERIOD_CNTL 0x1920 |
1289 | #define mmBL_PWM_GRP1_REG_LOCK 0x1921 |
1290 | #define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 |
1291 | #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 |
1292 | #define mmDCIO_GSL0_CNTL 0x1924 |
1293 | #define mmDCIO_GSL1_CNTL 0x1925 |
1294 | #define mmDCIO_GSL2_CNTL 0x1926 |
1295 | #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 |
1296 | #define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 |
1297 | #define mmDC_GPU_TIMER_READ 0x1929 |
1298 | #define mmDC_GPU_TIMER_READ_CNTL 0x192a |
1299 | #define mmDCO_CLK_CNTL 0x192b |
1300 | #define mmDCO_CLK_RAMP_CNTL 0x192c |
1301 | #define mmDCIO_DEBUG 0x192e |
1302 | #define mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937 |
1303 | #define mmDCIO_TEST_DEBUG_INDEX 0x192f |
1304 | #define mmDCIO_TEST_DEBUG_DATA 0x1930 |
1305 | #define ixDCIO_DEBUG1 0x1 |
1306 | #define ixDCIO_DEBUG2 0x2 |
1307 | #define ixDCIO_DEBUG3 0x3 |
1308 | #define ixDCIO_DEBUG4 0x4 |
1309 | #define ixDCIO_DEBUG5 0x5 |
1310 | #define ixDCIO_DEBUG6 0x6 |
1311 | #define ixDCIO_DEBUG7 0x7 |
1312 | #define ixDCIO_DEBUG8 0x8 |
1313 | #define ixDCIO_DEBUG9 0x9 |
1314 | #define ixDCIO_DEBUGA 0xa |
1315 | #define ixDCIO_DEBUGB 0xb |
1316 | #define ixDCIO_DEBUGC 0xc |
1317 | #define ixDCIO_DEBUGD 0xd |
1318 | #define ixDCIO_DEBUGE 0xe |
1319 | #define ixDCIO_DEBUGF 0xf |
1320 | #define ixDCIO_DEBUG10 0x10 |
1321 | #define ixDCIO_DEBUG11 0x11 |
1322 | #define ixDCIO_DEBUG12 0x12 |
1323 | #define ixDCIO_DEBUG13 0x13 |
1324 | #define ixDCIO_DEBUG14 0x14 |
1325 | #define ixDCIO_DEBUG15 0x15 |
1326 | #define ixDCIO_DEBUG_ID 0x0 |
1327 | #define mmDC_GPIO_GENERIC_MASK 0x1944 |
1328 | #define mmDC_GPIO_GENERIC_A 0x1945 |
1329 | #define mmDC_GPIO_GENERIC_EN 0x1946 |
1330 | #define mmDC_GPIO_GENERIC_Y 0x1947 |
1331 | #define mmDC_GPIO_DVODATA_MASK 0x1948 |
1332 | #define mmDC_GPIO_DVODATA_A 0x1949 |
1333 | #define mmDC_GPIO_DVODATA_EN 0x194a |
1334 | #define mmDC_GPIO_DVODATA_Y 0x194b |
1335 | #define mmDC_GPIO_DDC1_MASK 0x194c |
1336 | #define mmDC_GPIO_DDC1_A 0x194d |
1337 | #define mmDC_GPIO_DDC1_EN 0x194e |
1338 | #define mmDC_GPIO_DDC1_Y 0x194f |
1339 | #define mmDC_GPIO_DDC2_MASK 0x1950 |
1340 | #define mmDC_GPIO_DDC2_A 0x1951 |
1341 | #define mmDC_GPIO_DDC2_EN 0x1952 |
1342 | #define mmDC_GPIO_DDC2_Y 0x1953 |
1343 | #define mmDC_GPIO_DDC3_MASK 0x1954 |
1344 | #define mmDC_GPIO_DDC3_A 0x1955 |
1345 | #define mmDC_GPIO_DDC3_EN 0x1956 |
1346 | #define mmDC_GPIO_DDC3_Y 0x1957 |
1347 | #define mmDC_GPIO_DDC4_MASK 0x1958 |
1348 | #define mmDC_GPIO_DDC4_A 0x1959 |
1349 | #define mmDC_GPIO_DDC4_EN 0x195a |
1350 | #define mmDC_GPIO_DDC4_Y 0x195b |
1351 | #define mmDC_GPIO_DDC5_MASK 0x195c |
1352 | #define mmDC_GPIO_DDC5_A 0x195d |
1353 | #define mmDC_GPIO_DDC5_EN 0x195e |
1354 | #define mmDC_GPIO_DDC5_Y 0x195f |
1355 | #define mmDC_GPIO_DDC6_MASK 0x1960 |
1356 | #define mmDC_GPIO_DDC6_A 0x1961 |
1357 | #define mmDC_GPIO_DDC6_EN 0x1962 |
1358 | #define mmDC_GPIO_DDC6_Y 0x1963 |
1359 | #define mmDC_GPIO_DDCVGA_MASK 0x1970 |
1360 | #define mmDC_GPIO_DDCVGA_A 0x1971 |
1361 | #define mmDC_GPIO_DDCVGA_EN 0x1972 |
1362 | #define mmDC_GPIO_DDCVGA_Y 0x1973 |
1363 | #define mmDC_GPIO_SYNCA_MASK 0x1964 |
1364 | #define mmDC_GPIO_SYNCA_A 0x1965 |
1365 | #define mmDC_GPIO_SYNCA_EN 0x1966 |
1366 | #define mmDC_GPIO_SYNCA_Y 0x1967 |
1367 | #define mmDC_GPIO_GENLK_MASK 0x1968 |
1368 | #define mmDC_GPIO_GENLK_A 0x1969 |
1369 | #define mmDC_GPIO_GENLK_EN 0x196a |
1370 | #define mmDC_GPIO_GENLK_Y 0x196b |
1371 | #define mmDC_GPIO_HPD_MASK 0x196c |
1372 | #define mmDC_GPIO_HPD_A 0x196d |
1373 | #define mmDC_GPIO_HPD_EN 0x196e |
1374 | #define mmDC_GPIO_HPD_Y 0x196f |
1375 | #define mmDC_GPIO_PWRSEQ_MASK 0x1940 |
1376 | #define mmDC_GPIO_PWRSEQ_A 0x1941 |
1377 | #define mmDC_GPIO_PWRSEQ_EN 0x1942 |
1378 | #define mmDC_GPIO_PWRSEQ_Y 0x1943 |
1379 | #define mmDC_GPIO_PAD_STRENGTH_1 0x1978 |
1380 | #define mmDC_GPIO_PAD_STRENGTH_2 0x1979 |
1381 | #define mmPHY_AUX_CNTL 0x197f |
1382 | #define mmDC_GPIO_I2CPAD_MASK 0x1974 |
1383 | #define mmDC_GPIO_I2CPAD_A 0x1975 |
1384 | #define mmDC_GPIO_I2CPAD_EN 0x1976 |
1385 | #define mmDC_GPIO_I2CPAD_Y 0x1977 |
1386 | #define mmDC_GPIO_I2CPAD_STRENGTH 0x197a |
1387 | #define mmDVO_STRENGTH_CONTROL 0x197b |
1388 | #define mmDVO_VREF_CONTROL 0x197c |
1389 | #define mmDVO_SKEW_ADJUST 0x197d |
1390 | #define mmUNIPHYAB_TPG_CONTROL 0x1931 |
1391 | #define mmUNIPHYAB_TPG_SEED 0x1932 |
1392 | #define mmUNIPHYCD_TPG_CONTROL 0x1933 |
1393 | #define mmUNIPHYCD_TPG_SEED 0x1934 |
1394 | #define mmUNIPHYEF_TPG_CONTROL 0x1935 |
1395 | #define mmUNIPHYEF_TPG_SEED 0x1936 |
1396 | #define mmUNIPHYGH_TPG_CONTROL 0x1938 |
1397 | #define mmUNIPHYGH_TPG_SEED 0x1939 |
1398 | #define mmDC_GPIO_I2S_SPDIF_MASK 0x193c |
1399 | #define mmDC_GPIO_I2S_SPDIF_A 0x193d |
1400 | #define mmDC_GPIO_I2S_SPDIF_EN 0x193e |
1401 | #define mmDC_GPIO_I2S_SPDIF_Y 0x193f |
1402 | #define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b |
1403 | #define mmDAC_MACRO_CNTL_RESERVED0 0x19fc |
1404 | #define mmDAC_MACRO_CNTL_RESERVED1 0x19fd |
1405 | #define mmDAC_MACRO_CNTL_RESERVED2 0x19fe |
1406 | #define mmDAC_MACRO_CNTL_RESERVED3 0x19ff |
1407 | #define mmUNIPHY_TX_CONTROL1 0x1980 |
1408 | #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 |
1409 | #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 |
1410 | #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0 |
1411 | #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0 |
1412 | #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0 |
1413 | #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0 |
1414 | #define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0 |
1415 | #define mmUNIPHY_TX_CONTROL2 0x1981 |
1416 | #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 |
1417 | #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 |
1418 | #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1 |
1419 | #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1 |
1420 | #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1 |
1421 | #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1 |
1422 | #define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1 |
1423 | #define mmUNIPHY_TX_CONTROL3 0x1982 |
1424 | #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 |
1425 | #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 |
1426 | #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2 |
1427 | #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2 |
1428 | #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2 |
1429 | #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2 |
1430 | #define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2 |
1431 | #define mmUNIPHY_TX_CONTROL4 0x1983 |
1432 | #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 |
1433 | #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 |
1434 | #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3 |
1435 | #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3 |
1436 | #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3 |
1437 | #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3 |
1438 | #define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3 |
1439 | #define mmUNIPHY_POWER_CONTROL 0x1984 |
1440 | #define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 |
1441 | #define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 |
1442 | #define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4 |
1443 | #define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4 |
1444 | #define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4 |
1445 | #define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4 |
1446 | #define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4 |
1447 | #define mmUNIPHY_PLL_FBDIV 0x1985 |
1448 | #define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 |
1449 | #define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 |
1450 | #define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5 |
1451 | #define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5 |
1452 | #define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5 |
1453 | #define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5 |
1454 | #define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5 |
1455 | #define mmUNIPHY_PLL_CONTROL1 0x1986 |
1456 | #define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 |
1457 | #define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 |
1458 | #define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6 |
1459 | #define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6 |
1460 | #define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6 |
1461 | #define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6 |
1462 | #define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6 |
1463 | #define mmUNIPHY_PLL_CONTROL2 0x1987 |
1464 | #define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 |
1465 | #define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 |
1466 | #define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7 |
1467 | #define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7 |
1468 | #define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7 |
1469 | #define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7 |
1470 | #define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7 |
1471 | #define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 |
1472 | #define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 |
1473 | #define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 |
1474 | #define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8 |
1475 | #define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8 |
1476 | #define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8 |
1477 | #define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8 |
1478 | #define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8 |
1479 | #define mmUNIPHY_PLL_SS_CNTL 0x1989 |
1480 | #define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 |
1481 | #define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 |
1482 | #define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9 |
1483 | #define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9 |
1484 | #define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9 |
1485 | #define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9 |
1486 | #define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9 |
1487 | #define mmUNIPHY_DATA_SYNCHRONIZATION 0x198a |
1488 | #define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a |
1489 | #define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a |
1490 | #define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa |
1491 | #define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba |
1492 | #define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca |
1493 | #define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da |
1494 | #define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa |
1495 | #define mmUNIPHY_REG_TEST_OUTPUT 0x198b |
1496 | #define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b |
1497 | #define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b |
1498 | #define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab |
1499 | #define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb |
1500 | #define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb |
1501 | #define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db |
1502 | #define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb |
1503 | #define mmUNIPHY_ANG_BIST_CNTL 0x198c |
1504 | #define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c |
1505 | #define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c |
1506 | #define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac |
1507 | #define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc |
1508 | #define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc |
1509 | #define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc |
1510 | #define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc |
1511 | #define mmUNIPHY_LINK_CNTL 0x198d |
1512 | #define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d |
1513 | #define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d |
1514 | #define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad |
1515 | #define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd |
1516 | #define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd |
1517 | #define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd |
1518 | #define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd |
1519 | #define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e |
1520 | #define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e |
1521 | #define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e |
1522 | #define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae |
1523 | #define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be |
1524 | #define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce |
1525 | #define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de |
1526 | #define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe |
1527 | #define mmUNIPHY_REG_TEST_OUTPUT2 0x198f |
1528 | #define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f |
1529 | #define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f |
1530 | #define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af |
1531 | #define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf |
1532 | #define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf |
1533 | #define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df |
1534 | #define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff |
1535 | #define mmGRPH_ENABLE 0x1a00 |
1536 | #define mmDCP0_GRPH_ENABLE 0x1a00 |
1537 | #define mmDCP1_GRPH_ENABLE 0x1d00 |
1538 | #define mmDCP2_GRPH_ENABLE 0x4000 |
1539 | #define mmDCP3_GRPH_ENABLE 0x4300 |
1540 | #define mmDCP4_GRPH_ENABLE 0x4600 |
1541 | #define mmDCP5_GRPH_ENABLE 0x4900 |
1542 | #define mmGRPH_CONTROL 0x1a01 |
1543 | #define mmDCP0_GRPH_CONTROL 0x1a01 |
1544 | #define mmDCP1_GRPH_CONTROL 0x1d01 |
1545 | #define mmDCP2_GRPH_CONTROL 0x4001 |
1546 | #define mmDCP3_GRPH_CONTROL 0x4301 |
1547 | #define mmDCP4_GRPH_CONTROL 0x4601 |
1548 | #define mmDCP5_GRPH_CONTROL 0x4901 |
1549 | #define mmGRPH_LUT_10BIT_BYPASS 0x1a02 |
1550 | #define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 |
1551 | #define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02 |
1552 | #define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 |
1553 | #define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 |
1554 | #define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 |
1555 | #define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 |
1556 | #define mmGRPH_SWAP_CNTL 0x1a03 |
1557 | #define mmDCP0_GRPH_SWAP_CNTL 0x1a03 |
1558 | #define mmDCP1_GRPH_SWAP_CNTL 0x1d03 |
1559 | #define mmDCP2_GRPH_SWAP_CNTL 0x4003 |
1560 | #define mmDCP3_GRPH_SWAP_CNTL 0x4303 |
1561 | #define mmDCP4_GRPH_SWAP_CNTL 0x4603 |
1562 | #define mmDCP5_GRPH_SWAP_CNTL 0x4903 |
1563 | #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 |
1564 | #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 |
1565 | #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04 |
1566 | #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 |
1567 | #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 |
1568 | #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 |
1569 | #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 |
1570 | #define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 |
1571 | #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 |
1572 | #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05 |
1573 | #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 |
1574 | #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 |
1575 | #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 |
1576 | #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 |
1577 | #define mmGRPH_PITCH 0x1a06 |
1578 | #define mmDCP0_GRPH_PITCH 0x1a06 |
1579 | #define mmDCP1_GRPH_PITCH 0x1d06 |
1580 | #define mmDCP2_GRPH_PITCH 0x4006 |
1581 | #define mmDCP3_GRPH_PITCH 0x4306 |
1582 | #define mmDCP4_GRPH_PITCH 0x4606 |
1583 | #define mmDCP5_GRPH_PITCH 0x4906 |
1584 | #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 |
1585 | #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 |
1586 | #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07 |
1587 | #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 |
1588 | #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 |
1589 | #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 |
1590 | #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 |
1591 | #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 |
1592 | #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 |
1593 | #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08 |
1594 | #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 |
1595 | #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 |
1596 | #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 |
1597 | #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 |
1598 | #define mmGRPH_SURFACE_OFFSET_X 0x1a09 |
1599 | #define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 |
1600 | #define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09 |
1601 | #define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 |
1602 | #define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 |
1603 | #define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 |
1604 | #define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 |
1605 | #define mmGRPH_SURFACE_OFFSET_Y 0x1a0a |
1606 | #define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a |
1607 | #define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a |
1608 | #define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a |
1609 | #define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a |
1610 | #define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a |
1611 | #define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a |
1612 | #define mmGRPH_X_START 0x1a0b |
1613 | #define mmDCP0_GRPH_X_START 0x1a0b |
1614 | #define mmDCP1_GRPH_X_START 0x1d0b |
1615 | #define mmDCP2_GRPH_X_START 0x400b |
1616 | #define mmDCP3_GRPH_X_START 0x430b |
1617 | #define mmDCP4_GRPH_X_START 0x460b |
1618 | #define mmDCP5_GRPH_X_START 0x490b |
1619 | #define mmGRPH_Y_START 0x1a0c |
1620 | #define mmDCP0_GRPH_Y_START 0x1a0c |
1621 | #define mmDCP1_GRPH_Y_START 0x1d0c |
1622 | #define mmDCP2_GRPH_Y_START 0x400c |
1623 | #define mmDCP3_GRPH_Y_START 0x430c |
1624 | #define mmDCP4_GRPH_Y_START 0x460c |
1625 | #define mmDCP5_GRPH_Y_START 0x490c |
1626 | #define mmGRPH_X_END 0x1a0d |
1627 | #define mmDCP0_GRPH_X_END 0x1a0d |
1628 | #define mmDCP1_GRPH_X_END 0x1d0d |
1629 | #define mmDCP2_GRPH_X_END 0x400d |
1630 | #define mmDCP3_GRPH_X_END 0x430d |
1631 | #define mmDCP4_GRPH_X_END 0x460d |
1632 | #define mmDCP5_GRPH_X_END 0x490d |
1633 | #define mmGRPH_Y_END 0x1a0e |
1634 | #define mmDCP0_GRPH_Y_END 0x1a0e |
1635 | #define mmDCP1_GRPH_Y_END 0x1d0e |
1636 | #define mmDCP2_GRPH_Y_END 0x400e |
1637 | #define mmDCP3_GRPH_Y_END 0x430e |
1638 | #define mmDCP4_GRPH_Y_END 0x460e |
1639 | #define mmDCP5_GRPH_Y_END 0x490e |
1640 | #define mmINPUT_GAMMA_CONTROL 0x1a10 |
1641 | #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 |
1642 | #define mmDCP1_INPUT_GAMMA_CONTROL 0x1d10 |
1643 | #define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 |
1644 | #define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 |
1645 | #define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 |
1646 | #define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 |
1647 | #define mmGRPH_UPDATE 0x1a11 |
1648 | #define mmDCP0_GRPH_UPDATE 0x1a11 |
1649 | #define mmDCP1_GRPH_UPDATE 0x1d11 |
1650 | #define mmDCP2_GRPH_UPDATE 0x4011 |
1651 | #define mmDCP3_GRPH_UPDATE 0x4311 |
1652 | #define mmDCP4_GRPH_UPDATE 0x4611 |
1653 | #define mmDCP5_GRPH_UPDATE 0x4911 |
1654 | #define mmGRPH_FLIP_CONTROL 0x1a12 |
1655 | #define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 |
1656 | #define mmDCP1_GRPH_FLIP_CONTROL 0x1d12 |
1657 | #define mmDCP2_GRPH_FLIP_CONTROL 0x4012 |
1658 | #define mmDCP3_GRPH_FLIP_CONTROL 0x4312 |
1659 | #define mmDCP4_GRPH_FLIP_CONTROL 0x4612 |
1660 | #define mmDCP5_GRPH_FLIP_CONTROL 0x4912 |
1661 | #define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 |
1662 | #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 |
1663 | #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13 |
1664 | #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 |
1665 | #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 |
1666 | #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 |
1667 | #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 |
1668 | #define mmGRPH_DFQ_CONTROL 0x1a14 |
1669 | #define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 |
1670 | #define mmDCP1_GRPH_DFQ_CONTROL 0x1d14 |
1671 | #define mmDCP2_GRPH_DFQ_CONTROL 0x4014 |
1672 | #define mmDCP3_GRPH_DFQ_CONTROL 0x4314 |
1673 | #define mmDCP4_GRPH_DFQ_CONTROL 0x4614 |
1674 | #define mmDCP5_GRPH_DFQ_CONTROL 0x4914 |
1675 | #define mmGRPH_DFQ_STATUS 0x1a15 |
1676 | #define mmDCP0_GRPH_DFQ_STATUS 0x1a15 |
1677 | #define mmDCP1_GRPH_DFQ_STATUS 0x1d15 |
1678 | #define mmDCP2_GRPH_DFQ_STATUS 0x4015 |
1679 | #define mmDCP3_GRPH_DFQ_STATUS 0x4315 |
1680 | #define mmDCP4_GRPH_DFQ_STATUS 0x4615 |
1681 | #define mmDCP5_GRPH_DFQ_STATUS 0x4915 |
1682 | #define mmGRPH_INTERRUPT_STATUS 0x1a16 |
1683 | #define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 |
1684 | #define mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16 |
1685 | #define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 |
1686 | #define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 |
1687 | #define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 |
1688 | #define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 |
1689 | #define mmGRPH_INTERRUPT_CONTROL 0x1a17 |
1690 | #define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 |
1691 | #define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17 |
1692 | #define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 |
1693 | #define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 |
1694 | #define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 |
1695 | #define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 |
1696 | #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 |
1697 | #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 |
1698 | #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18 |
1699 | #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 |
1700 | #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 |
1701 | #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 |
1702 | #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 |
1703 | #define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 |
1704 | #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 |
1705 | #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19 |
1706 | #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 |
1707 | #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 |
1708 | #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 |
1709 | #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 |
1710 | #define mmGRPH_COMPRESS_PITCH 0x1a1a |
1711 | #define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a |
1712 | #define mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a |
1713 | #define mmDCP2_GRPH_COMPRESS_PITCH 0x401a |
1714 | #define mmDCP3_GRPH_COMPRESS_PITCH 0x431a |
1715 | #define mmDCP4_GRPH_COMPRESS_PITCH 0x461a |
1716 | #define mmDCP5_GRPH_COMPRESS_PITCH 0x491a |
1717 | #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b |
1718 | #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b |
1719 | #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b |
1720 | #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b |
1721 | #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b |
1722 | #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b |
1723 | #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b |
1724 | #define mmOVL_ENABLE 0x1a1c |
1725 | #define mmDCP0_OVL_ENABLE 0x1a1c |
1726 | #define mmDCP1_OVL_ENABLE 0x1d1c |
1727 | #define mmDCP2_OVL_ENABLE 0x401c |
1728 | #define mmDCP3_OVL_ENABLE 0x431c |
1729 | #define mmDCP4_OVL_ENABLE 0x461c |
1730 | #define mmDCP5_OVL_ENABLE 0x491c |
1731 | #define mmOVL_CONTROL1 0x1a1d |
1732 | #define mmDCP0_OVL_CONTROL1 0x1a1d |
1733 | #define mmDCP1_OVL_CONTROL1 0x1d1d |
1734 | #define mmDCP2_OVL_CONTROL1 0x401d |
1735 | #define mmDCP3_OVL_CONTROL1 0x431d |
1736 | #define mmDCP4_OVL_CONTROL1 0x461d |
1737 | #define mmDCP5_OVL_CONTROL1 0x491d |
1738 | #define mmOVL_CONTROL2 0x1a1e |
1739 | #define mmDCP0_OVL_CONTROL2 0x1a1e |
1740 | #define mmDCP1_OVL_CONTROL2 0x1d1e |
1741 | #define mmDCP2_OVL_CONTROL2 0x401e |
1742 | #define mmDCP3_OVL_CONTROL2 0x431e |
1743 | #define mmDCP4_OVL_CONTROL2 0x461e |
1744 | #define mmDCP5_OVL_CONTROL2 0x491e |
1745 | #define mmOVL_SWAP_CNTL 0x1a1f |
1746 | #define mmDCP0_OVL_SWAP_CNTL 0x1a1f |
1747 | #define mmDCP1_OVL_SWAP_CNTL 0x1d1f |
1748 | #define mmDCP2_OVL_SWAP_CNTL 0x401f |
1749 | #define mmDCP3_OVL_SWAP_CNTL 0x431f |
1750 | #define mmDCP4_OVL_SWAP_CNTL 0x461f |
1751 | #define mmDCP5_OVL_SWAP_CNTL 0x491f |
1752 | #define mmOVL_SURFACE_ADDRESS 0x1a20 |
1753 | #define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 |
1754 | #define mmDCP1_OVL_SURFACE_ADDRESS 0x1d20 |
1755 | #define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 |
1756 | #define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 |
1757 | #define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 |
1758 | #define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 |
1759 | #define mmOVL_PITCH 0x1a21 |
1760 | #define mmDCP0_OVL_PITCH 0x1a21 |
1761 | #define mmDCP1_OVL_PITCH 0x1d21 |
1762 | #define mmDCP2_OVL_PITCH 0x4021 |
1763 | #define mmDCP3_OVL_PITCH 0x4321 |
1764 | #define mmDCP4_OVL_PITCH 0x4621 |
1765 | #define mmDCP5_OVL_PITCH 0x4921 |
1766 | #define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 |
1767 | #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 |
1768 | #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22 |
1769 | #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 |
1770 | #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 |
1771 | #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 |
1772 | #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 |
1773 | #define mmOVL_SURFACE_OFFSET_X 0x1a23 |
1774 | #define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 |
1775 | #define mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23 |
1776 | #define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 |
1777 | #define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 |
1778 | #define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 |
1779 | #define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 |
1780 | #define mmOVL_SURFACE_OFFSET_Y 0x1a24 |
1781 | #define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 |
1782 | #define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24 |
1783 | #define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 |
1784 | #define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 |
1785 | #define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 |
1786 | #define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 |
1787 | #define mmOVL_START 0x1a25 |
1788 | #define mmDCP0_OVL_START 0x1a25 |
1789 | #define mmDCP1_OVL_START 0x1d25 |
1790 | #define mmDCP2_OVL_START 0x4025 |
1791 | #define mmDCP3_OVL_START 0x4325 |
1792 | #define mmDCP4_OVL_START 0x4625 |
1793 | #define mmDCP5_OVL_START 0x4925 |
1794 | #define mmOVL_END 0x1a26 |
1795 | #define mmDCP0_OVL_END 0x1a26 |
1796 | #define mmDCP1_OVL_END 0x1d26 |
1797 | #define mmDCP2_OVL_END 0x4026 |
1798 | #define mmDCP3_OVL_END 0x4326 |
1799 | #define mmDCP4_OVL_END 0x4626 |
1800 | #define mmDCP5_OVL_END 0x4926 |
1801 | #define mmOVL_UPDATE 0x1a27 |
1802 | #define mmDCP0_OVL_UPDATE 0x1a27 |
1803 | #define mmDCP1_OVL_UPDATE 0x1d27 |
1804 | #define mmDCP2_OVL_UPDATE 0x4027 |
1805 | #define mmDCP3_OVL_UPDATE 0x4327 |
1806 | #define mmDCP4_OVL_UPDATE 0x4627 |
1807 | #define mmDCP5_OVL_UPDATE 0x4927 |
1808 | #define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 |
1809 | #define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 |
1810 | #define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28 |
1811 | #define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 |
1812 | #define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 |
1813 | #define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 |
1814 | #define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 |
1815 | #define mmOVL_DFQ_CONTROL 0x1a29 |
1816 | #define mmDCP0_OVL_DFQ_CONTROL 0x1a29 |
1817 | #define mmDCP1_OVL_DFQ_CONTROL 0x1d29 |
1818 | #define mmDCP2_OVL_DFQ_CONTROL 0x4029 |
1819 | #define mmDCP3_OVL_DFQ_CONTROL 0x4329 |
1820 | #define mmDCP4_OVL_DFQ_CONTROL 0x4629 |
1821 | #define mmDCP5_OVL_DFQ_CONTROL 0x4929 |
1822 | #define mmOVL_DFQ_STATUS 0x1a2a |
1823 | #define mmDCP0_OVL_DFQ_STATUS 0x1a2a |
1824 | #define mmDCP1_OVL_DFQ_STATUS 0x1d2a |
1825 | #define mmDCP2_OVL_DFQ_STATUS 0x402a |
1826 | #define mmDCP3_OVL_DFQ_STATUS 0x432a |
1827 | #define mmDCP4_OVL_DFQ_STATUS 0x462a |
1828 | #define mmDCP5_OVL_DFQ_STATUS 0x492a |
1829 | #define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b |
1830 | #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b |
1831 | #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b |
1832 | #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b |
1833 | #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b |
1834 | #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b |
1835 | #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b |
1836 | #define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c |
1837 | #define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c |
1838 | #define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c |
1839 | #define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c |
1840 | #define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c |
1841 | #define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c |
1842 | #define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c |
1843 | #define mmPRESCALE_GRPH_CONTROL 0x1a2d |
1844 | #define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d |
1845 | #define mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d |
1846 | #define mmDCP2_PRESCALE_GRPH_CONTROL 0x402d |
1847 | #define mmDCP3_PRESCALE_GRPH_CONTROL 0x432d |
1848 | #define mmDCP4_PRESCALE_GRPH_CONTROL 0x462d |
1849 | #define mmDCP5_PRESCALE_GRPH_CONTROL 0x492d |
1850 | #define mmPRESCALE_VALUES_GRPH_R 0x1a2e |
1851 | #define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e |
1852 | #define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e |
1853 | #define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e |
1854 | #define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e |
1855 | #define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e |
1856 | #define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e |
1857 | #define mmPRESCALE_VALUES_GRPH_G 0x1a2f |
1858 | #define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f |
1859 | #define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f |
1860 | #define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f |
1861 | #define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f |
1862 | #define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f |
1863 | #define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f |
1864 | #define mmPRESCALE_VALUES_GRPH_B 0x1a30 |
1865 | #define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 |
1866 | #define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30 |
1867 | #define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 |
1868 | #define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 |
1869 | #define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 |
1870 | #define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 |
1871 | #define mmPRESCALE_OVL_CONTROL 0x1a31 |
1872 | #define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 |
1873 | #define mmDCP1_PRESCALE_OVL_CONTROL 0x1d31 |
1874 | #define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 |
1875 | #define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 |
1876 | #define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 |
1877 | #define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 |
1878 | #define mmPRESCALE_VALUES_OVL_CB 0x1a32 |
1879 | #define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 |
1880 | #define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32 |
1881 | #define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 |
1882 | #define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 |
1883 | #define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 |
1884 | #define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 |
1885 | #define mmPRESCALE_VALUES_OVL_Y 0x1a33 |
1886 | #define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 |
1887 | #define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33 |
1888 | #define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 |
1889 | #define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 |
1890 | #define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 |
1891 | #define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 |
1892 | #define mmPRESCALE_VALUES_OVL_CR 0x1a34 |
1893 | #define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 |
1894 | #define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34 |
1895 | #define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 |
1896 | #define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 |
1897 | #define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 |
1898 | #define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 |
1899 | #define mmINPUT_CSC_CONTROL 0x1a35 |
1900 | #define mmDCP0_INPUT_CSC_CONTROL 0x1a35 |
1901 | #define mmDCP1_INPUT_CSC_CONTROL 0x1d35 |
1902 | #define mmDCP2_INPUT_CSC_CONTROL 0x4035 |
1903 | #define mmDCP3_INPUT_CSC_CONTROL 0x4335 |
1904 | #define mmDCP4_INPUT_CSC_CONTROL 0x4635 |
1905 | #define mmDCP5_INPUT_CSC_CONTROL 0x4935 |
1906 | #define mmINPUT_CSC_C11_C12 0x1a36 |
1907 | #define mmDCP0_INPUT_CSC_C11_C12 0x1a36 |
1908 | #define mmDCP1_INPUT_CSC_C11_C12 0x1d36 |
1909 | #define mmDCP2_INPUT_CSC_C11_C12 0x4036 |
1910 | #define mmDCP3_INPUT_CSC_C11_C12 0x4336 |
1911 | #define mmDCP4_INPUT_CSC_C11_C12 0x4636 |
1912 | #define mmDCP5_INPUT_CSC_C11_C12 0x4936 |
1913 | #define mmINPUT_CSC_C13_C14 0x1a37 |
1914 | #define mmDCP0_INPUT_CSC_C13_C14 0x1a37 |
1915 | #define mmDCP1_INPUT_CSC_C13_C14 0x1d37 |
1916 | #define mmDCP2_INPUT_CSC_C13_C14 0x4037 |
1917 | #define mmDCP3_INPUT_CSC_C13_C14 0x4337 |
1918 | #define mmDCP4_INPUT_CSC_C13_C14 0x4637 |
1919 | #define mmDCP5_INPUT_CSC_C13_C14 0x4937 |
1920 | #define mmINPUT_CSC_C21_C22 0x1a38 |
1921 | #define mmDCP0_INPUT_CSC_C21_C22 0x1a38 |
1922 | #define mmDCP1_INPUT_CSC_C21_C22 0x1d38 |
1923 | #define mmDCP2_INPUT_CSC_C21_C22 0x4038 |
1924 | #define mmDCP3_INPUT_CSC_C21_C22 0x4338 |
1925 | #define mmDCP4_INPUT_CSC_C21_C22 0x4638 |
1926 | #define mmDCP5_INPUT_CSC_C21_C22 0x4938 |
1927 | #define mmINPUT_CSC_C23_C24 0x1a39 |
1928 | #define mmDCP0_INPUT_CSC_C23_C24 0x1a39 |
1929 | #define mmDCP1_INPUT_CSC_C23_C24 0x1d39 |
1930 | #define mmDCP2_INPUT_CSC_C23_C24 0x4039 |
1931 | #define mmDCP3_INPUT_CSC_C23_C24 0x4339 |
1932 | #define mmDCP4_INPUT_CSC_C23_C24 0x4639 |
1933 | #define mmDCP5_INPUT_CSC_C23_C24 0x4939 |
1934 | #define mmINPUT_CSC_C31_C32 0x1a3a |
1935 | #define mmDCP0_INPUT_CSC_C31_C32 0x1a3a |
1936 | #define mmDCP1_INPUT_CSC_C31_C32 0x1d3a |
1937 | #define mmDCP2_INPUT_CSC_C31_C32 0x403a |
1938 | #define mmDCP3_INPUT_CSC_C31_C32 0x433a |
1939 | #define mmDCP4_INPUT_CSC_C31_C32 0x463a |
1940 | #define mmDCP5_INPUT_CSC_C31_C32 0x493a |
1941 | #define mmINPUT_CSC_C33_C34 0x1a3b |
1942 | #define mmDCP0_INPUT_CSC_C33_C34 0x1a3b |
1943 | #define mmDCP1_INPUT_CSC_C33_C34 0x1d3b |
1944 | #define mmDCP2_INPUT_CSC_C33_C34 0x403b |
1945 | #define mmDCP3_INPUT_CSC_C33_C34 0x433b |
1946 | #define mmDCP4_INPUT_CSC_C33_C34 0x463b |
1947 | #define mmDCP5_INPUT_CSC_C33_C34 0x493b |
1948 | #define mmOUTPUT_CSC_CONTROL 0x1a3c |
1949 | #define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c |
1950 | #define mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c |
1951 | #define mmDCP2_OUTPUT_CSC_CONTROL 0x403c |
1952 | #define mmDCP3_OUTPUT_CSC_CONTROL 0x433c |
1953 | #define mmDCP4_OUTPUT_CSC_CONTROL 0x463c |
1954 | #define mmDCP5_OUTPUT_CSC_CONTROL 0x493c |
1955 | #define mmOUTPUT_CSC_C11_C12 0x1a3d |
1956 | #define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d |
1957 | #define mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d |
1958 | #define mmDCP2_OUTPUT_CSC_C11_C12 0x403d |
1959 | #define mmDCP3_OUTPUT_CSC_C11_C12 0x433d |
1960 | #define mmDCP4_OUTPUT_CSC_C11_C12 0x463d |
1961 | #define mmDCP5_OUTPUT_CSC_C11_C12 0x493d |
1962 | #define mmOUTPUT_CSC_C13_C14 0x1a3e |
1963 | #define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e |
1964 | #define mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e |
1965 | #define mmDCP2_OUTPUT_CSC_C13_C14 0x403e |
1966 | #define mmDCP3_OUTPUT_CSC_C13_C14 0x433e |
1967 | #define mmDCP4_OUTPUT_CSC_C13_C14 0x463e |
1968 | #define mmDCP5_OUTPUT_CSC_C13_C14 0x493e |
1969 | #define mmOUTPUT_CSC_C21_C22 0x1a3f |
1970 | #define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f |
1971 | #define mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f |
1972 | #define mmDCP2_OUTPUT_CSC_C21_C22 0x403f |
1973 | #define mmDCP3_OUTPUT_CSC_C21_C22 0x433f |
1974 | #define mmDCP4_OUTPUT_CSC_C21_C22 0x463f |
1975 | #define mmDCP5_OUTPUT_CSC_C21_C22 0x493f |
1976 | #define mmOUTPUT_CSC_C23_C24 0x1a40 |
1977 | #define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 |
1978 | #define mmDCP1_OUTPUT_CSC_C23_C24 0x1d40 |
1979 | #define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 |
1980 | #define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 |
1981 | #define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 |
1982 | #define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 |
1983 | #define mmOUTPUT_CSC_C31_C32 0x1a41 |
1984 | #define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 |
1985 | #define mmDCP1_OUTPUT_CSC_C31_C32 0x1d41 |
1986 | #define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 |
1987 | #define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 |
1988 | #define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 |
1989 | #define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 |
1990 | #define mmOUTPUT_CSC_C33_C34 0x1a42 |
1991 | #define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 |
1992 | #define mmDCP1_OUTPUT_CSC_C33_C34 0x1d42 |
1993 | #define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 |
1994 | #define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 |
1995 | #define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 |
1996 | #define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 |
1997 | #define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 |
1998 | #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 |
1999 | #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43 |
2000 | #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 |
2001 | #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 |
2002 | #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 |
2003 | #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 |
2004 | #define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 |
2005 | #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 |
2006 | #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44 |
2007 | #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 |
2008 | #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 |
2009 | #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 |
2010 | #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 |
2011 | #define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 |
2012 | #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 |
2013 | #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45 |
2014 | #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 |
2015 | #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 |
2016 | #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 |
2017 | #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 |
2018 | #define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 |
2019 | #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 |
2020 | #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46 |
2021 | #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 |
2022 | #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 |
2023 | #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 |
2024 | #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 |
2025 | #define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 |
2026 | #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 |
2027 | #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47 |
2028 | #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 |
2029 | #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 |
2030 | #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 |
2031 | #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 |
2032 | #define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 |
2033 | #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 |
2034 | #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48 |
2035 | #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 |
2036 | #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 |
2037 | #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 |
2038 | #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 |
2039 | #define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 |
2040 | #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 |
2041 | #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49 |
2042 | #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 |
2043 | #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 |
2044 | #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 |
2045 | #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 |
2046 | #define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a |
2047 | #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a |
2048 | #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a |
2049 | #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a |
2050 | #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a |
2051 | #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a |
2052 | #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a |
2053 | #define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b |
2054 | #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b |
2055 | #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b |
2056 | #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b |
2057 | #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b |
2058 | #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b |
2059 | #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b |
2060 | #define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c |
2061 | #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c |
2062 | #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c |
2063 | #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c |
2064 | #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c |
2065 | #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c |
2066 | #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c |
2067 | #define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d |
2068 | #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d |
2069 | #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d |
2070 | #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d |
2071 | #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d |
2072 | #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d |
2073 | #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d |
2074 | #define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e |
2075 | #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e |
2076 | #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e |
2077 | #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e |
2078 | #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e |
2079 | #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e |
2080 | #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e |
2081 | #define mmDENORM_CONTROL 0x1a50 |
2082 | #define mmDCP0_DENORM_CONTROL 0x1a50 |
2083 | #define mmDCP1_DENORM_CONTROL 0x1d50 |
2084 | #define mmDCP2_DENORM_CONTROL 0x4050 |
2085 | #define mmDCP3_DENORM_CONTROL 0x4350 |
2086 | #define mmDCP4_DENORM_CONTROL 0x4650 |
2087 | #define mmDCP5_DENORM_CONTROL 0x4950 |
2088 | #define mmOUT_ROUND_CONTROL 0x1a51 |
2089 | #define mmDCP0_OUT_ROUND_CONTROL 0x1a51 |
2090 | #define mmDCP1_OUT_ROUND_CONTROL 0x1d51 |
2091 | #define mmDCP2_OUT_ROUND_CONTROL 0x4051 |
2092 | #define mmDCP3_OUT_ROUND_CONTROL 0x4351 |
2093 | #define mmDCP4_OUT_ROUND_CONTROL 0x4651 |
2094 | #define mmDCP5_OUT_ROUND_CONTROL 0x4951 |
2095 | #define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 |
2096 | #define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 |
2097 | #define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52 |
2098 | #define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052 |
2099 | #define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352 |
2100 | #define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652 |
2101 | #define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952 |
2102 | #define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c |
2103 | #define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c |
2104 | #define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c |
2105 | #define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c |
2106 | #define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c |
2107 | #define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c |
2108 | #define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c |
2109 | #define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d |
2110 | #define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d |
2111 | #define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d |
2112 | #define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d |
2113 | #define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d |
2114 | #define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d |
2115 | #define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d |
2116 | #define mmKEY_CONTROL 0x1a53 |
2117 | #define mmDCP0_KEY_CONTROL 0x1a53 |
2118 | #define mmDCP1_KEY_CONTROL 0x1d53 |
2119 | #define mmDCP2_KEY_CONTROL 0x4053 |
2120 | #define mmDCP3_KEY_CONTROL 0x4353 |
2121 | #define mmDCP4_KEY_CONTROL 0x4653 |
2122 | #define mmDCP5_KEY_CONTROL 0x4953 |
2123 | #define mmKEY_RANGE_ALPHA 0x1a54 |
2124 | #define mmDCP0_KEY_RANGE_ALPHA 0x1a54 |
2125 | #define mmDCP1_KEY_RANGE_ALPHA 0x1d54 |
2126 | #define mmDCP2_KEY_RANGE_ALPHA 0x4054 |
2127 | #define mmDCP3_KEY_RANGE_ALPHA 0x4354 |
2128 | #define mmDCP4_KEY_RANGE_ALPHA 0x4654 |
2129 | #define mmDCP5_KEY_RANGE_ALPHA 0x4954 |
2130 | #define mmKEY_RANGE_RED 0x1a55 |
2131 | #define mmDCP0_KEY_RANGE_RED 0x1a55 |
2132 | #define mmDCP1_KEY_RANGE_RED 0x1d55 |
2133 | #define mmDCP2_KEY_RANGE_RED 0x4055 |
2134 | #define mmDCP3_KEY_RANGE_RED 0x4355 |
2135 | #define mmDCP4_KEY_RANGE_RED 0x4655 |
2136 | #define mmDCP5_KEY_RANGE_RED 0x4955 |
2137 | #define mmKEY_RANGE_GREEN 0x1a56 |
2138 | #define mmDCP0_KEY_RANGE_GREEN 0x1a56 |
2139 | #define mmDCP1_KEY_RANGE_GREEN 0x1d56 |
2140 | #define mmDCP2_KEY_RANGE_GREEN 0x4056 |
2141 | #define mmDCP3_KEY_RANGE_GREEN 0x4356 |
2142 | #define mmDCP4_KEY_RANGE_GREEN 0x4656 |
2143 | #define mmDCP5_KEY_RANGE_GREEN 0x4956 |
2144 | #define mmKEY_RANGE_BLUE 0x1a57 |
2145 | #define mmDCP0_KEY_RANGE_BLUE 0x1a57 |
2146 | #define mmDCP1_KEY_RANGE_BLUE 0x1d57 |
2147 | #define mmDCP2_KEY_RANGE_BLUE 0x4057 |
2148 | #define mmDCP3_KEY_RANGE_BLUE 0x4357 |
2149 | #define mmDCP4_KEY_RANGE_BLUE 0x4657 |
2150 | #define mmDCP5_KEY_RANGE_BLUE 0x4957 |
2151 | #define mmDEGAMMA_CONTROL 0x1a58 |
2152 | #define mmDCP0_DEGAMMA_CONTROL 0x1a58 |
2153 | #define mmDCP1_DEGAMMA_CONTROL 0x1d58 |
2154 | #define mmDCP2_DEGAMMA_CONTROL 0x4058 |
2155 | #define mmDCP3_DEGAMMA_CONTROL 0x4358 |
2156 | #define mmDCP4_DEGAMMA_CONTROL 0x4658 |
2157 | #define mmDCP5_DEGAMMA_CONTROL 0x4958 |
2158 | #define mmGAMUT_REMAP_CONTROL 0x1a59 |
2159 | #define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 |
2160 | #define mmDCP1_GAMUT_REMAP_CONTROL 0x1d59 |
2161 | #define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 |
2162 | #define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 |
2163 | #define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 |
2164 | #define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 |
2165 | #define mmGAMUT_REMAP_C11_C12 0x1a5a |
2166 | #define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a |
2167 | #define mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a |
2168 | #define mmDCP2_GAMUT_REMAP_C11_C12 0x405a |
2169 | #define mmDCP3_GAMUT_REMAP_C11_C12 0x435a |
2170 | #define mmDCP4_GAMUT_REMAP_C11_C12 0x465a |
2171 | #define mmDCP5_GAMUT_REMAP_C11_C12 0x495a |
2172 | #define mmGAMUT_REMAP_C13_C14 0x1a5b |
2173 | #define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b |
2174 | #define mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b |
2175 | #define mmDCP2_GAMUT_REMAP_C13_C14 0x405b |
2176 | #define mmDCP3_GAMUT_REMAP_C13_C14 0x435b |
2177 | #define mmDCP4_GAMUT_REMAP_C13_C14 0x465b |
2178 | #define mmDCP5_GAMUT_REMAP_C13_C14 0x495b |
2179 | #define mmGAMUT_REMAP_C21_C22 0x1a5c |
2180 | #define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c |
2181 | #define mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c |
2182 | #define mmDCP2_GAMUT_REMAP_C21_C22 0x405c |
2183 | #define mmDCP3_GAMUT_REMAP_C21_C22 0x435c |
2184 | #define mmDCP4_GAMUT_REMAP_C21_C22 0x465c |
2185 | #define mmDCP5_GAMUT_REMAP_C21_C22 0x495c |
2186 | #define mmGAMUT_REMAP_C23_C24 0x1a5d |
2187 | #define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d |
2188 | #define mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d |
2189 | #define mmDCP2_GAMUT_REMAP_C23_C24 0x405d |
2190 | #define mmDCP3_GAMUT_REMAP_C23_C24 0x435d |
2191 | #define mmDCP4_GAMUT_REMAP_C23_C24 0x465d |
2192 | #define mmDCP5_GAMUT_REMAP_C23_C24 0x495d |
2193 | #define mmGAMUT_REMAP_C31_C32 0x1a5e |
2194 | #define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e |
2195 | #define mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e |
2196 | #define mmDCP2_GAMUT_REMAP_C31_C32 0x405e |
2197 | #define mmDCP3_GAMUT_REMAP_C31_C32 0x435e |
2198 | #define mmDCP4_GAMUT_REMAP_C31_C32 0x465e |
2199 | #define mmDCP5_GAMUT_REMAP_C31_C32 0x495e |
2200 | #define mmGAMUT_REMAP_C33_C34 0x1a5f |
2201 | #define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f |
2202 | #define mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f |
2203 | #define mmDCP2_GAMUT_REMAP_C33_C34 0x405f |
2204 | #define mmDCP3_GAMUT_REMAP_C33_C34 0x435f |
2205 | #define mmDCP4_GAMUT_REMAP_C33_C34 0x465f |
2206 | #define mmDCP5_GAMUT_REMAP_C33_C34 0x495f |
2207 | #define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 |
2208 | #define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 |
2209 | #define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60 |
2210 | #define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 |
2211 | #define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 |
2212 | #define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 |
2213 | #define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 |
2214 | #define mmDCP_RANDOM_SEEDS 0x1a61 |
2215 | #define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 |
2216 | #define mmDCP1_DCP_RANDOM_SEEDS 0x1d61 |
2217 | #define mmDCP2_DCP_RANDOM_SEEDS 0x4061 |
2218 | #define mmDCP3_DCP_RANDOM_SEEDS 0x4361 |
2219 | #define mmDCP4_DCP_RANDOM_SEEDS 0x4661 |
2220 | #define mmDCP5_DCP_RANDOM_SEEDS 0x4961 |
2221 | #define mmDCP_FP_CONVERTED_FIELD 0x1a65 |
2222 | #define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 |
2223 | #define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65 |
2224 | #define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 |
2225 | #define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 |
2226 | #define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 |
2227 | #define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 |
2228 | #define mmCUR_CONTROL 0x1a66 |
2229 | #define mmDCP0_CUR_CONTROL 0x1a66 |
2230 | #define mmDCP1_CUR_CONTROL 0x1d66 |
2231 | #define mmDCP2_CUR_CONTROL 0x4066 |
2232 | #define mmDCP3_CUR_CONTROL 0x4366 |
2233 | #define mmDCP4_CUR_CONTROL 0x4666 |
2234 | #define mmDCP5_CUR_CONTROL 0x4966 |
2235 | #define mmCUR_SURFACE_ADDRESS 0x1a67 |
2236 | #define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 |
2237 | #define mmDCP1_CUR_SURFACE_ADDRESS 0x1d67 |
2238 | #define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 |
2239 | #define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 |
2240 | #define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 |
2241 | #define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 |
2242 | #define mmCUR_SIZE 0x1a68 |
2243 | #define mmDCP0_CUR_SIZE 0x1a68 |
2244 | #define mmDCP1_CUR_SIZE 0x1d68 |
2245 | #define mmDCP2_CUR_SIZE 0x4068 |
2246 | #define mmDCP3_CUR_SIZE 0x4368 |
2247 | #define mmDCP4_CUR_SIZE 0x4668 |
2248 | #define mmDCP5_CUR_SIZE 0x4968 |
2249 | #define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 |
2250 | #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 |
2251 | #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69 |
2252 | #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 |
2253 | #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 |
2254 | #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 |
2255 | #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 |
2256 | #define mmCUR_POSITION 0x1a6a |
2257 | #define mmDCP0_CUR_POSITION 0x1a6a |
2258 | #define mmDCP1_CUR_POSITION 0x1d6a |
2259 | #define mmDCP2_CUR_POSITION 0x406a |
2260 | #define mmDCP3_CUR_POSITION 0x436a |
2261 | #define mmDCP4_CUR_POSITION 0x466a |
2262 | #define mmDCP5_CUR_POSITION 0x496a |
2263 | #define mmCUR_HOT_SPOT 0x1a6b |
2264 | #define mmDCP0_CUR_HOT_SPOT 0x1a6b |
2265 | #define mmDCP1_CUR_HOT_SPOT 0x1d6b |
2266 | #define mmDCP2_CUR_HOT_SPOT 0x406b |
2267 | #define mmDCP3_CUR_HOT_SPOT 0x436b |
2268 | #define mmDCP4_CUR_HOT_SPOT 0x466b |
2269 | #define mmDCP5_CUR_HOT_SPOT 0x496b |
2270 | #define mmCUR_COLOR1 0x1a6c |
2271 | #define mmDCP0_CUR_COLOR1 0x1a6c |
2272 | #define mmDCP1_CUR_COLOR1 0x1d6c |
2273 | #define mmDCP2_CUR_COLOR1 0x406c |
2274 | #define mmDCP3_CUR_COLOR1 0x436c |
2275 | #define mmDCP4_CUR_COLOR1 0x466c |
2276 | #define mmDCP5_CUR_COLOR1 0x496c |
2277 | #define mmCUR_COLOR2 0x1a6d |
2278 | #define mmDCP0_CUR_COLOR2 0x1a6d |
2279 | #define mmDCP1_CUR_COLOR2 0x1d6d |
2280 | #define mmDCP2_CUR_COLOR2 0x406d |
2281 | #define mmDCP3_CUR_COLOR2 0x436d |
2282 | #define mmDCP4_CUR_COLOR2 0x466d |
2283 | #define mmDCP5_CUR_COLOR2 0x496d |
2284 | #define mmCUR_UPDATE 0x1a6e |
2285 | #define mmDCP0_CUR_UPDATE 0x1a6e |
2286 | #define mmDCP1_CUR_UPDATE 0x1d6e |
2287 | #define mmDCP2_CUR_UPDATE 0x406e |
2288 | #define mmDCP3_CUR_UPDATE 0x436e |
2289 | #define mmDCP4_CUR_UPDATE 0x466e |
2290 | #define mmDCP5_CUR_UPDATE 0x496e |
2291 | #define mmCUR2_CONTROL 0x1a6f |
2292 | #define mmDCP0_CUR2_CONTROL 0x1a6f |
2293 | #define mmDCP1_CUR2_CONTROL 0x1d6f |
2294 | #define mmDCP2_CUR2_CONTROL 0x406f |
2295 | #define mmDCP3_CUR2_CONTROL 0x436f |
2296 | #define mmDCP4_CUR2_CONTROL 0x466f |
2297 | #define mmDCP5_CUR2_CONTROL 0x496f |
2298 | #define mmCUR2_SURFACE_ADDRESS 0x1a70 |
2299 | #define mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70 |
2300 | #define mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70 |
2301 | #define mmDCP2_CUR2_SURFACE_ADDRESS 0x4070 |
2302 | #define mmDCP3_CUR2_SURFACE_ADDRESS 0x4370 |
2303 | #define mmDCP4_CUR2_SURFACE_ADDRESS 0x4670 |
2304 | #define mmDCP5_CUR2_SURFACE_ADDRESS 0x4970 |
2305 | #define mmCUR2_SIZE 0x1a71 |
2306 | #define mmDCP0_CUR2_SIZE 0x1a71 |
2307 | #define mmDCP1_CUR2_SIZE 0x1d71 |
2308 | #define mmDCP2_CUR2_SIZE 0x4071 |
2309 | #define mmDCP3_CUR2_SIZE 0x4371 |
2310 | #define mmDCP4_CUR2_SIZE 0x4671 |
2311 | #define mmDCP5_CUR2_SIZE 0x4971 |
2312 | #define mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72 |
2313 | #define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72 |
2314 | #define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72 |
2315 | #define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072 |
2316 | #define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372 |
2317 | #define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672 |
2318 | #define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972 |
2319 | #define mmCUR2_POSITION 0x1a73 |
2320 | #define mmDCP0_CUR2_POSITION 0x1a73 |
2321 | #define mmDCP1_CUR2_POSITION 0x1d73 |
2322 | #define mmDCP2_CUR2_POSITION 0x4073 |
2323 | #define mmDCP3_CUR2_POSITION 0x4373 |
2324 | #define mmDCP4_CUR2_POSITION 0x4673 |
2325 | #define mmDCP5_CUR2_POSITION 0x4973 |
2326 | #define mmCUR2_HOT_SPOT 0x1a74 |
2327 | #define mmDCP0_CUR2_HOT_SPOT 0x1a74 |
2328 | #define mmDCP1_CUR2_HOT_SPOT 0x1d74 |
2329 | #define mmDCP2_CUR2_HOT_SPOT 0x4074 |
2330 | #define mmDCP3_CUR2_HOT_SPOT 0x4374 |
2331 | #define mmDCP4_CUR2_HOT_SPOT 0x4674 |
2332 | #define mmDCP5_CUR2_HOT_SPOT 0x4974 |
2333 | #define mmCUR2_COLOR1 0x1a75 |
2334 | #define mmDCP0_CUR2_COLOR1 0x1a75 |
2335 | #define mmDCP1_CUR2_COLOR1 0x1d75 |
2336 | #define mmDCP2_CUR2_COLOR1 0x4075 |
2337 | #define mmDCP3_CUR2_COLOR1 0x4375 |
2338 | #define mmDCP4_CUR2_COLOR1 0x4675 |
2339 | #define mmDCP5_CUR2_COLOR1 0x4975 |
2340 | #define mmCUR2_COLOR2 0x1a76 |
2341 | #define mmDCP0_CUR2_COLOR2 0x1a76 |
2342 | #define mmDCP1_CUR2_COLOR2 0x1d76 |
2343 | #define mmDCP2_CUR2_COLOR2 0x4076 |
2344 | #define mmDCP3_CUR2_COLOR2 0x4376 |
2345 | #define mmDCP4_CUR2_COLOR2 0x4676 |
2346 | #define mmDCP5_CUR2_COLOR2 0x4976 |
2347 | #define mmCUR2_UPDATE 0x1a77 |
2348 | #define mmDCP0_CUR2_UPDATE 0x1a77 |
2349 | #define mmDCP1_CUR2_UPDATE 0x1d77 |
2350 | #define mmDCP2_CUR2_UPDATE 0x4077 |
2351 | #define mmDCP3_CUR2_UPDATE 0x4377 |
2352 | #define mmDCP4_CUR2_UPDATE 0x4677 |
2353 | #define mmDCP5_CUR2_UPDATE 0x4977 |
2354 | #define mmCUR_REQUEST_FILTER_CNTL 0x1a99 |
2355 | #define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 |
2356 | #define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99 |
2357 | #define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 |
2358 | #define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 |
2359 | #define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 |
2360 | #define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 |
2361 | #define mmCUR_STEREO_CONTROL 0x1a9a |
2362 | #define mmDCP0_CUR_STEREO_CONTROL 0x1a9a |
2363 | #define mmDCP1_CUR_STEREO_CONTROL 0x1d9a |
2364 | #define mmDCP2_CUR_STEREO_CONTROL 0x409a |
2365 | #define mmDCP3_CUR_STEREO_CONTROL 0x439a |
2366 | #define mmDCP4_CUR_STEREO_CONTROL 0x469a |
2367 | #define mmDCP5_CUR_STEREO_CONTROL 0x499a |
2368 | #define mmCUR2_STEREO_CONTROL 0x1a9b |
2369 | #define mmDCP0_CUR2_STEREO_CONTROL 0x1a9b |
2370 | #define mmDCP1_CUR2_STEREO_CONTROL 0x1d9b |
2371 | #define mmDCP2_CUR2_STEREO_CONTROL 0x409b |
2372 | #define mmDCP3_CUR2_STEREO_CONTROL 0x439b |
2373 | #define mmDCP4_CUR2_STEREO_CONTROL 0x469b |
2374 | #define mmDCP5_CUR2_STEREO_CONTROL 0x499b |
2375 | #define mmDC_LUT_RW_MODE 0x1a78 |
2376 | #define mmDCP0_DC_LUT_RW_MODE 0x1a78 |
2377 | #define mmDCP1_DC_LUT_RW_MODE 0x1d78 |
2378 | #define mmDCP2_DC_LUT_RW_MODE 0x4078 |
2379 | #define mmDCP3_DC_LUT_RW_MODE 0x4378 |
2380 | #define mmDCP4_DC_LUT_RW_MODE 0x4678 |
2381 | #define mmDCP5_DC_LUT_RW_MODE 0x4978 |
2382 | #define mmDC_LUT_RW_INDEX 0x1a79 |
2383 | #define mmDCP0_DC_LUT_RW_INDEX 0x1a79 |
2384 | #define mmDCP1_DC_LUT_RW_INDEX 0x1d79 |
2385 | #define mmDCP2_DC_LUT_RW_INDEX 0x4079 |
2386 | #define mmDCP3_DC_LUT_RW_INDEX 0x4379 |
2387 | #define mmDCP4_DC_LUT_RW_INDEX 0x4679 |
2388 | #define mmDCP5_DC_LUT_RW_INDEX 0x4979 |
2389 | #define mmDC_LUT_SEQ_COLOR 0x1a7a |
2390 | #define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a |
2391 | #define mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a |
2392 | #define mmDCP2_DC_LUT_SEQ_COLOR 0x407a |
2393 | #define mmDCP3_DC_LUT_SEQ_COLOR 0x437a |
2394 | #define mmDCP4_DC_LUT_SEQ_COLOR 0x467a |
2395 | #define mmDCP5_DC_LUT_SEQ_COLOR 0x497a |
2396 | #define mmDC_LUT_PWL_DATA 0x1a7b |
2397 | #define mmDCP0_DC_LUT_PWL_DATA 0x1a7b |
2398 | #define mmDCP1_DC_LUT_PWL_DATA 0x1d7b |
2399 | #define mmDCP2_DC_LUT_PWL_DATA 0x407b |
2400 | #define mmDCP3_DC_LUT_PWL_DATA 0x437b |
2401 | #define mmDCP4_DC_LUT_PWL_DATA 0x467b |
2402 | #define mmDCP5_DC_LUT_PWL_DATA 0x497b |
2403 | #define mmDC_LUT_30_COLOR 0x1a7c |
2404 | #define mmDCP0_DC_LUT_30_COLOR 0x1a7c |
2405 | #define mmDCP1_DC_LUT_30_COLOR 0x1d7c |
2406 | #define mmDCP2_DC_LUT_30_COLOR 0x407c |
2407 | #define mmDCP3_DC_LUT_30_COLOR 0x437c |
2408 | #define mmDCP4_DC_LUT_30_COLOR 0x467c |
2409 | #define mmDCP5_DC_LUT_30_COLOR 0x497c |
2410 | #define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d |
2411 | #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d |
2412 | #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d |
2413 | #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d |
2414 | #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d |
2415 | #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d |
2416 | #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d |
2417 | #define mmDC_LUT_WRITE_EN_MASK 0x1a7e |
2418 | #define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e |
2419 | #define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e |
2420 | #define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e |
2421 | #define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e |
2422 | #define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e |
2423 | #define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e |
2424 | #define mmDC_LUT_AUTOFILL 0x1a7f |
2425 | #define mmDCP0_DC_LUT_AUTOFILL 0x1a7f |
2426 | #define mmDCP1_DC_LUT_AUTOFILL 0x1d7f |
2427 | #define mmDCP2_DC_LUT_AUTOFILL 0x407f |
2428 | #define mmDCP3_DC_LUT_AUTOFILL 0x437f |
2429 | #define mmDCP4_DC_LUT_AUTOFILL 0x467f |
2430 | #define mmDCP5_DC_LUT_AUTOFILL 0x497f |
2431 | #define mmDC_LUT_CONTROL 0x1a80 |
2432 | #define mmDCP0_DC_LUT_CONTROL 0x1a80 |
2433 | #define mmDCP1_DC_LUT_CONTROL 0x1d80 |
2434 | #define mmDCP2_DC_LUT_CONTROL 0x4080 |
2435 | #define mmDCP3_DC_LUT_CONTROL 0x4380 |
2436 | #define mmDCP4_DC_LUT_CONTROL 0x4680 |
2437 | #define mmDCP5_DC_LUT_CONTROL 0x4980 |
2438 | #define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 |
2439 | #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 |
2440 | #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81 |
2441 | #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 |
2442 | #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 |
2443 | #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 |
2444 | #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 |
2445 | #define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 |
2446 | #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 |
2447 | #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82 |
2448 | #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 |
2449 | #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 |
2450 | #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 |
2451 | #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 |
2452 | #define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 |
2453 | #define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 |
2454 | #define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83 |
2455 | #define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 |
2456 | #define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 |
2457 | #define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 |
2458 | #define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 |
2459 | #define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 |
2460 | #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 |
2461 | #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84 |
2462 | #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 |
2463 | #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 |
2464 | #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 |
2465 | #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 |
2466 | #define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 |
2467 | #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 |
2468 | #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85 |
2469 | #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 |
2470 | #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 |
2471 | #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 |
2472 | #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 |
2473 | #define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 |
2474 | #define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 |
2475 | #define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86 |
2476 | #define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 |
2477 | #define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 |
2478 | #define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 |
2479 | #define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 |
2480 | #define mmDCP_CRC_CONTROL 0x1a87 |
2481 | #define mmDCP0_DCP_CRC_CONTROL 0x1a87 |
2482 | #define mmDCP1_DCP_CRC_CONTROL 0x1d87 |
2483 | #define mmDCP2_DCP_CRC_CONTROL 0x4087 |
2484 | #define mmDCP3_DCP_CRC_CONTROL 0x4387 |
2485 | #define mmDCP4_DCP_CRC_CONTROL 0x4687 |
2486 | #define mmDCP5_DCP_CRC_CONTROL 0x4987 |
2487 | #define mmDCP_CRC_MASK 0x1a88 |
2488 | #define mmDCP0_DCP_CRC_MASK 0x1a88 |
2489 | #define mmDCP1_DCP_CRC_MASK 0x1d88 |
2490 | #define mmDCP2_DCP_CRC_MASK 0x4088 |
2491 | #define mmDCP3_DCP_CRC_MASK 0x4388 |
2492 | #define mmDCP4_DCP_CRC_MASK 0x4688 |
2493 | #define mmDCP5_DCP_CRC_MASK 0x4988 |
2494 | #define mmDCP_CRC_CURRENT 0x1a89 |
2495 | #define mmDCP0_DCP_CRC_CURRENT 0x1a89 |
2496 | #define mmDCP1_DCP_CRC_CURRENT 0x1d89 |
2497 | #define mmDCP2_DCP_CRC_CURRENT 0x4089 |
2498 | #define mmDCP3_DCP_CRC_CURRENT 0x4389 |
2499 | #define mmDCP4_DCP_CRC_CURRENT 0x4689 |
2500 | #define mmDCP5_DCP_CRC_CURRENT 0x4989 |
2501 | #define mmDCP_CRC_LAST 0x1a8b |
2502 | #define mmDCP0_DCP_CRC_LAST 0x1a8b |
2503 | #define mmDCP1_DCP_CRC_LAST 0x1d8b |
2504 | #define mmDCP2_DCP_CRC_LAST 0x408b |
2505 | #define mmDCP3_DCP_CRC_LAST 0x438b |
2506 | #define mmDCP4_DCP_CRC_LAST 0x468b |
2507 | #define mmDCP5_DCP_CRC_LAST 0x498b |
2508 | #define mmDCP_DEBUG 0x1a8d |
2509 | #define mmDCP0_DCP_DEBUG 0x1a8d |
2510 | #define mmDCP1_DCP_DEBUG 0x1d8d |
2511 | #define mmDCP2_DCP_DEBUG 0x408d |
2512 | #define mmDCP3_DCP_DEBUG 0x438d |
2513 | #define mmDCP4_DCP_DEBUG 0x468d |
2514 | #define mmDCP5_DCP_DEBUG 0x498d |
2515 | #define mmGRPH_FLIP_RATE_CNTL 0x1a8e |
2516 | #define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e |
2517 | #define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e |
2518 | #define mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e |
2519 | #define mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e |
2520 | #define mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e |
2521 | #define mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e |
2522 | #define mmDCP_GSL_CONTROL 0x1a90 |
2523 | #define mmDCP0_DCP_GSL_CONTROL 0x1a90 |
2524 | #define mmDCP1_DCP_GSL_CONTROL 0x1d90 |
2525 | #define mmDCP2_DCP_GSL_CONTROL 0x4090 |
2526 | #define mmDCP3_DCP_GSL_CONTROL 0x4390 |
2527 | #define mmDCP4_DCP_GSL_CONTROL 0x4690 |
2528 | #define mmDCP5_DCP_GSL_CONTROL 0x4990 |
2529 | #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 |
2530 | #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 |
2531 | #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91 |
2532 | #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 |
2533 | #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 |
2534 | #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 |
2535 | #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 |
2536 | #define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 |
2537 | #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 |
2538 | #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92 |
2539 | #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 |
2540 | #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 |
2541 | #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 |
2542 | #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 |
2543 | #define mmOVL_STEREOSYNC_FLIP 0x1a93 |
2544 | #define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 |
2545 | #define mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93 |
2546 | #define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 |
2547 | #define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 |
2548 | #define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 |
2549 | #define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 |
2550 | #define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 |
2551 | #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 |
2552 | #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94 |
2553 | #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 |
2554 | #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 |
2555 | #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 |
2556 | #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 |
2557 | #define mmDCP_TEST_DEBUG_INDEX 0x1a95 |
2558 | #define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 |
2559 | #define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95 |
2560 | #define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 |
2561 | #define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 |
2562 | #define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 |
2563 | #define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 |
2564 | #define mmDCP_TEST_DEBUG_DATA 0x1a96 |
2565 | #define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 |
2566 | #define mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96 |
2567 | #define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 |
2568 | #define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 |
2569 | #define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 |
2570 | #define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 |
2571 | #define mmGRPH_STEREOSYNC_FLIP 0x1a97 |
2572 | #define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 |
2573 | #define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97 |
2574 | #define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 |
2575 | #define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 |
2576 | #define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 |
2577 | #define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 |
2578 | #define mmDCP_DEBUG2 0x1a98 |
2579 | #define mmDCP0_DCP_DEBUG2 0x1a98 |
2580 | #define mmDCP1_DCP_DEBUG2 0x1d98 |
2581 | #define mmDCP2_DCP_DEBUG2 0x4098 |
2582 | #define mmDCP3_DCP_DEBUG2 0x4398 |
2583 | #define mmDCP4_DCP_DEBUG2 0x4698 |
2584 | #define mmDCP5_DCP_DEBUG2 0x4998 |
2585 | #define mmHW_ROTATION 0x1a9e |
2586 | #define mmDCP0_HW_ROTATION 0x1a9e |
2587 | #define mmDCP1_HW_ROTATION 0x1d9e |
2588 | #define mmDCP2_HW_ROTATION 0x409e |
2589 | #define mmDCP3_HW_ROTATION 0x439e |
2590 | #define mmDCP4_HW_ROTATION 0x469e |
2591 | #define mmDCP5_HW_ROTATION 0x499e |
2592 | #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f |
2593 | #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f |
2594 | #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f |
2595 | #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f |
2596 | #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f |
2597 | #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f |
2598 | #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f |
2599 | #define mmREGAMMA_CONTROL 0x1aa0 |
2600 | #define mmDCP0_REGAMMA_CONTROL 0x1aa0 |
2601 | #define mmDCP1_REGAMMA_CONTROL 0x1da0 |
2602 | #define mmDCP2_REGAMMA_CONTROL 0x40a0 |
2603 | #define mmDCP3_REGAMMA_CONTROL 0x43a0 |
2604 | #define mmDCP4_REGAMMA_CONTROL 0x46a0 |
2605 | #define mmDCP5_REGAMMA_CONTROL 0x49a0 |
2606 | #define mmREGAMMA_LUT_INDEX 0x1aa1 |
2607 | #define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 |
2608 | #define mmDCP1_REGAMMA_LUT_INDEX 0x1da1 |
2609 | #define mmDCP2_REGAMMA_LUT_INDEX 0x40a1 |
2610 | #define mmDCP3_REGAMMA_LUT_INDEX 0x43a1 |
2611 | #define mmDCP4_REGAMMA_LUT_INDEX 0x46a1 |
2612 | #define mmDCP5_REGAMMA_LUT_INDEX 0x49a1 |
2613 | #define mmREGAMMA_LUT_DATA 0x1aa2 |
2614 | #define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 |
2615 | #define mmDCP1_REGAMMA_LUT_DATA 0x1da2 |
2616 | #define mmDCP2_REGAMMA_LUT_DATA 0x40a2 |
2617 | #define mmDCP3_REGAMMA_LUT_DATA 0x43a2 |
2618 | #define mmDCP4_REGAMMA_LUT_DATA 0x46a2 |
2619 | #define mmDCP5_REGAMMA_LUT_DATA 0x49a2 |
2620 | #define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 |
2621 | #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 |
2622 | #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3 |
2623 | #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 |
2624 | #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3 |
2625 | #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3 |
2626 | #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3 |
2627 | #define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 |
2628 | #define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 |
2629 | #define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4 |
2630 | #define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4 |
2631 | #define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4 |
2632 | #define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4 |
2633 | #define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4 |
2634 | #define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 |
2635 | #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 |
2636 | #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5 |
2637 | #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 |
2638 | #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5 |
2639 | #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5 |
2640 | #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5 |
2641 | #define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 |
2642 | #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 |
2643 | #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6 |
2644 | #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6 |
2645 | #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6 |
2646 | #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6 |
2647 | #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6 |
2648 | #define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 |
2649 | #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 |
2650 | #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7 |
2651 | #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7 |
2652 | #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7 |
2653 | #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7 |
2654 | #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7 |
2655 | #define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 |
2656 | #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 |
2657 | #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8 |
2658 | #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8 |
2659 | #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8 |
2660 | #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8 |
2661 | #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8 |
2662 | #define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 |
2663 | #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 |
2664 | #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9 |
2665 | #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9 |
2666 | #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9 |
2667 | #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9 |
2668 | #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9 |
2669 | #define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa |
2670 | #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa |
2671 | #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa |
2672 | #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa |
2673 | #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa |
2674 | #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa |
2675 | #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa |
2676 | #define mmREGAMMA_CNTLA_REGION_6_7 0x1aab |
2677 | #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab |
2678 | #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab |
2679 | #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab |
2680 | #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab |
2681 | #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab |
2682 | #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab |
2683 | #define mmREGAMMA_CNTLA_REGION_8_9 0x1aac |
2684 | #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac |
2685 | #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac |
2686 | #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac |
2687 | #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac |
2688 | #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac |
2689 | #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac |
2690 | #define mmREGAMMA_CNTLA_REGION_10_11 0x1aad |
2691 | #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad |
2692 | #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad |
2693 | #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad |
2694 | #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad |
2695 | #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad |
2696 | #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad |
2697 | #define mmREGAMMA_CNTLA_REGION_12_13 0x1aae |
2698 | #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae |
2699 | #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae |
2700 | #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae |
2701 | #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae |
2702 | #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae |
2703 | #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae |
2704 | #define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf |
2705 | #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf |
2706 | #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf |
2707 | #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af |
2708 | #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af |
2709 | #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af |
2710 | #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af |
2711 | #define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 |
2712 | #define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 |
2713 | #define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0 |
2714 | #define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0 |
2715 | #define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0 |
2716 | #define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0 |
2717 | #define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0 |
2718 | #define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 |
2719 | #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 |
2720 | #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1 |
2721 | #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 |
2722 | #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1 |
2723 | #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1 |
2724 | #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1 |
2725 | #define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 |
2726 | #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 |
2727 | #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2 |
2728 | #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2 |
2729 | #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2 |
2730 | #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2 |
2731 | #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2 |
2732 | #define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 |
2733 | #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 |
2734 | #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3 |
2735 | #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3 |
2736 | #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3 |
2737 | #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3 |
2738 | #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3 |
2739 | #define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 |
2740 | #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 |
2741 | #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4 |
2742 | #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4 |
2743 | #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4 |
2744 | #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4 |
2745 | #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4 |
2746 | #define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 |
2747 | #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 |
2748 | #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5 |
2749 | #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5 |
2750 | #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5 |
2751 | #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5 |
2752 | #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5 |
2753 | #define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 |
2754 | #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 |
2755 | #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6 |
2756 | #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6 |
2757 | #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6 |
2758 | #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6 |
2759 | #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6 |
2760 | #define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 |
2761 | #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 |
2762 | #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7 |
2763 | #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7 |
2764 | #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7 |
2765 | #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7 |
2766 | #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7 |
2767 | #define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 |
2768 | #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 |
2769 | #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8 |
2770 | #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8 |
2771 | #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8 |
2772 | #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8 |
2773 | #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8 |
2774 | #define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 |
2775 | #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 |
2776 | #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9 |
2777 | #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9 |
2778 | #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9 |
2779 | #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9 |
2780 | #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9 |
2781 | #define mmREGAMMA_CNTLB_REGION_12_13 0x1aba |
2782 | #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba |
2783 | #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba |
2784 | #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba |
2785 | #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba |
2786 | #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba |
2787 | #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba |
2788 | #define mmREGAMMA_CNTLB_REGION_14_15 0x1abb |
2789 | #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb |
2790 | #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb |
2791 | #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb |
2792 | #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb |
2793 | #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb |
2794 | #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb |
2795 | #define mmALPHA_CONTROL 0x1abc |
2796 | #define mmDCP0_ALPHA_CONTROL 0x1abc |
2797 | #define mmDCP1_ALPHA_CONTROL 0x1dbc |
2798 | #define mmDCP2_ALPHA_CONTROL 0x40bc |
2799 | #define mmDCP3_ALPHA_CONTROL 0x43bc |
2800 | #define mmDCP4_ALPHA_CONTROL 0x46bc |
2801 | #define mmDCP5_ALPHA_CONTROL 0x49bc |
2802 | #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd |
2803 | #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd |
2804 | #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd |
2805 | #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd |
2806 | #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd |
2807 | #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd |
2808 | #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd |
2809 | #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe |
2810 | #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe |
2811 | #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe |
2812 | #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be |
2813 | #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be |
2814 | #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be |
2815 | #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be |
2816 | #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf |
2817 | #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf |
2818 | #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf |
2819 | #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf |
2820 | #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf |
2821 | #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf |
2822 | #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf |
2823 | #define mmDIG_FE_CNTL 0x1c00 |
2824 | #define mmDIG0_DIG_FE_CNTL 0x1c00 |
2825 | #define mmDIG1_DIG_FE_CNTL 0x1f00 |
2826 | #define mmDIG2_DIG_FE_CNTL 0x4200 |
2827 | #define mmDIG3_DIG_FE_CNTL 0x4500 |
2828 | #define mmDIG4_DIG_FE_CNTL 0x4800 |
2829 | #define mmDIG5_DIG_FE_CNTL 0x4b00 |
2830 | #define mmDIG6_DIG_FE_CNTL 0x4e00 |
2831 | #define mmDIG_OUTPUT_CRC_CNTL 0x1c01 |
2832 | #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01 |
2833 | #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01 |
2834 | #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 |
2835 | #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 |
2836 | #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 |
2837 | #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01 |
2838 | #define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01 |
2839 | #define mmDIG_OUTPUT_CRC_RESULT 0x1c02 |
2840 | #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02 |
2841 | #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02 |
2842 | #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 |
2843 | #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 |
2844 | #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 |
2845 | #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02 |
2846 | #define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02 |
2847 | #define mmDIG_CLOCK_PATTERN 0x1c03 |
2848 | #define mmDIG0_DIG_CLOCK_PATTERN 0x1c03 |
2849 | #define mmDIG1_DIG_CLOCK_PATTERN 0x1f03 |
2850 | #define mmDIG2_DIG_CLOCK_PATTERN 0x4203 |
2851 | #define mmDIG3_DIG_CLOCK_PATTERN 0x4503 |
2852 | #define mmDIG4_DIG_CLOCK_PATTERN 0x4803 |
2853 | #define mmDIG5_DIG_CLOCK_PATTERN 0x4b03 |
2854 | #define mmDIG6_DIG_CLOCK_PATTERN 0x4e03 |
2855 | #define mmDIG_TEST_PATTERN 0x1c04 |
2856 | #define mmDIG0_DIG_TEST_PATTERN 0x1c04 |
2857 | #define mmDIG1_DIG_TEST_PATTERN 0x1f04 |
2858 | #define mmDIG2_DIG_TEST_PATTERN 0x4204 |
2859 | #define mmDIG3_DIG_TEST_PATTERN 0x4504 |
2860 | #define mmDIG4_DIG_TEST_PATTERN 0x4804 |
2861 | #define mmDIG5_DIG_TEST_PATTERN 0x4b04 |
2862 | #define mmDIG6_DIG_TEST_PATTERN 0x4e04 |
2863 | #define mmDIG_RANDOM_PATTERN_SEED 0x1c05 |
2864 | #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05 |
2865 | #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05 |
2866 | #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 |
2867 | #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 |
2868 | #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 |
2869 | #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05 |
2870 | #define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05 |
2871 | #define mmDIG_FIFO_STATUS 0x1c0a |
2872 | #define mmDIG0_DIG_FIFO_STATUS 0x1c0a |
2873 | #define mmDIG1_DIG_FIFO_STATUS 0x1f0a |
2874 | #define mmDIG2_DIG_FIFO_STATUS 0x420a |
2875 | #define mmDIG3_DIG_FIFO_STATUS 0x450a |
2876 | #define mmDIG4_DIG_FIFO_STATUS 0x480a |
2877 | #define mmDIG5_DIG_FIFO_STATUS 0x4b0a |
2878 | #define mmDIG6_DIG_FIFO_STATUS 0x4e0a |
2879 | #define mmDIG_DISPCLK_SWITCH_CNTL 0x1c08 |
2880 | #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08 |
2881 | #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08 |
2882 | #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 |
2883 | #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 |
2884 | #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 |
2885 | #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08 |
2886 | #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08 |
2887 | #define mmDIG_DISPCLK_SWITCH_STATUS 0x1c09 |
2888 | #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09 |
2889 | #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09 |
2890 | #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 |
2891 | #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 |
2892 | #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 |
2893 | #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09 |
2894 | #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09 |
2895 | #define mmHDMI_CONTROL 0x1c0c |
2896 | #define mmDIG0_HDMI_CONTROL 0x1c0c |
2897 | #define mmDIG1_HDMI_CONTROL 0x1f0c |
2898 | #define mmDIG2_HDMI_CONTROL 0x420c |
2899 | #define mmDIG3_HDMI_CONTROL 0x450c |
2900 | #define mmDIG4_HDMI_CONTROL 0x480c |
2901 | #define mmDIG5_HDMI_CONTROL 0x4b0c |
2902 | #define mmDIG6_HDMI_CONTROL 0x4e0c |
2903 | #define mmHDMI_STATUS 0x1c0d |
2904 | #define mmDIG0_HDMI_STATUS 0x1c0d |
2905 | #define mmDIG1_HDMI_STATUS 0x1f0d |
2906 | #define mmDIG2_HDMI_STATUS 0x420d |
2907 | #define mmDIG3_HDMI_STATUS 0x450d |
2908 | #define mmDIG4_HDMI_STATUS 0x480d |
2909 | #define mmDIG5_HDMI_STATUS 0x4b0d |
2910 | #define mmDIG6_HDMI_STATUS 0x4e0d |
2911 | #define mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e |
2912 | #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e |
2913 | #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e |
2914 | #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e |
2915 | #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e |
2916 | #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e |
2917 | #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e |
2918 | #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e |
2919 | #define mmHDMI_ACR_PACKET_CONTROL 0x1c0f |
2920 | #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f |
2921 | #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f |
2922 | #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f |
2923 | #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f |
2924 | #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f |
2925 | #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f |
2926 | #define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f |
2927 | #define mmHDMI_VBI_PACKET_CONTROL 0x1c10 |
2928 | #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10 |
2929 | #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10 |
2930 | #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 |
2931 | #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 |
2932 | #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 |
2933 | #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10 |
2934 | #define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10 |
2935 | #define mmHDMI_INFOFRAME_CONTROL0 0x1c11 |
2936 | #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11 |
2937 | #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11 |
2938 | #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 |
2939 | #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 |
2940 | #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 |
2941 | #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11 |
2942 | #define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11 |
2943 | #define mmHDMI_INFOFRAME_CONTROL1 0x1c12 |
2944 | #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12 |
2945 | #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12 |
2946 | #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 |
2947 | #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 |
2948 | #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 |
2949 | #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12 |
2950 | #define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12 |
2951 | #define mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13 |
2952 | #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13 |
2953 | #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13 |
2954 | #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 |
2955 | #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 |
2956 | #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 |
2957 | #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13 |
2958 | #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13 |
2959 | #define mmAFMT_INTERRUPT_STATUS 0x1c14 |
2960 | #define mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14 |
2961 | #define mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14 |
2962 | #define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 |
2963 | #define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 |
2964 | #define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 |
2965 | #define mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14 |
2966 | #define mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14 |
2967 | #define mmHDMI_GC 0x1c16 |
2968 | #define mmDIG0_HDMI_GC 0x1c16 |
2969 | #define mmDIG1_HDMI_GC 0x1f16 |
2970 | #define mmDIG2_HDMI_GC 0x4216 |
2971 | #define mmDIG3_HDMI_GC 0x4516 |
2972 | #define mmDIG4_HDMI_GC 0x4816 |
2973 | #define mmDIG5_HDMI_GC 0x4b16 |
2974 | #define mmDIG6_HDMI_GC 0x4e16 |
2975 | #define mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17 |
2976 | #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17 |
2977 | #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17 |
2978 | #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 |
2979 | #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 |
2980 | #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 |
2981 | #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17 |
2982 | #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17 |
2983 | #define mmAFMT_ISRC1_0 0x1c18 |
2984 | #define mmDIG0_AFMT_ISRC1_0 0x1c18 |
2985 | #define mmDIG1_AFMT_ISRC1_0 0x1f18 |
2986 | #define mmDIG2_AFMT_ISRC1_0 0x4218 |
2987 | #define mmDIG3_AFMT_ISRC1_0 0x4518 |
2988 | #define mmDIG4_AFMT_ISRC1_0 0x4818 |
2989 | #define mmDIG5_AFMT_ISRC1_0 0x4b18 |
2990 | #define mmDIG6_AFMT_ISRC1_0 0x4e18 |
2991 | #define mmAFMT_ISRC1_1 0x1c19 |
2992 | #define mmDIG0_AFMT_ISRC1_1 0x1c19 |
2993 | #define mmDIG1_AFMT_ISRC1_1 0x1f19 |
2994 | #define mmDIG2_AFMT_ISRC1_1 0x4219 |
2995 | #define mmDIG3_AFMT_ISRC1_1 0x4519 |
2996 | #define mmDIG4_AFMT_ISRC1_1 0x4819 |
2997 | #define mmDIG5_AFMT_ISRC1_1 0x4b19 |
2998 | #define mmDIG6_AFMT_ISRC1_1 0x4e19 |
2999 | #define mmAFMT_ISRC1_2 0x1c1a |
3000 | #define mmDIG0_AFMT_ISRC1_2 0x1c1a |
3001 | #define mmDIG1_AFMT_ISRC1_2 0x1f1a |
3002 | #define mmDIG2_AFMT_ISRC1_2 0x421a |
3003 | #define mmDIG3_AFMT_ISRC1_2 0x451a |
3004 | #define mmDIG4_AFMT_ISRC1_2 0x481a |
3005 | #define mmDIG5_AFMT_ISRC1_2 0x4b1a |
3006 | #define mmDIG6_AFMT_ISRC1_2 0x4e1a |
3007 | #define mmAFMT_ISRC1_3 0x1c1b |
3008 | #define mmDIG0_AFMT_ISRC1_3 0x1c1b |
3009 | #define mmDIG1_AFMT_ISRC1_3 0x1f1b |
3010 | #define mmDIG2_AFMT_ISRC1_3 0x421b |
3011 | #define mmDIG3_AFMT_ISRC1_3 0x451b |
3012 | #define mmDIG4_AFMT_ISRC1_3 0x481b |
3013 | #define mmDIG5_AFMT_ISRC1_3 0x4b1b |
3014 | #define mmDIG6_AFMT_ISRC1_3 0x4e1b |
3015 | #define mmAFMT_ISRC1_4 0x1c1c |
3016 | #define mmDIG0_AFMT_ISRC1_4 0x1c1c |
3017 | #define mmDIG1_AFMT_ISRC1_4 0x1f1c |
3018 | #define mmDIG2_AFMT_ISRC1_4 0x421c |
3019 | #define mmDIG3_AFMT_ISRC1_4 0x451c |
3020 | #define mmDIG4_AFMT_ISRC1_4 0x481c |
3021 | #define mmDIG5_AFMT_ISRC1_4 0x4b1c |
3022 | #define mmDIG6_AFMT_ISRC1_4 0x4e1c |
3023 | #define mmAFMT_ISRC2_0 0x1c1d |
3024 | #define mmDIG0_AFMT_ISRC2_0 0x1c1d |
3025 | #define mmDIG1_AFMT_ISRC2_0 0x1f1d |
3026 | #define mmDIG2_AFMT_ISRC2_0 0x421d |
3027 | #define mmDIG3_AFMT_ISRC2_0 0x451d |
3028 | #define mmDIG4_AFMT_ISRC2_0 0x481d |
3029 | #define mmDIG5_AFMT_ISRC2_0 0x4b1d |
3030 | #define mmDIG6_AFMT_ISRC2_0 0x4e1d |
3031 | #define mmAFMT_ISRC2_1 0x1c1e |
3032 | #define mmDIG0_AFMT_ISRC2_1 0x1c1e |
3033 | #define mmDIG1_AFMT_ISRC2_1 0x1f1e |
3034 | #define mmDIG2_AFMT_ISRC2_1 0x421e |
3035 | #define mmDIG3_AFMT_ISRC2_1 0x451e |
3036 | #define mmDIG4_AFMT_ISRC2_1 0x481e |
3037 | #define mmDIG5_AFMT_ISRC2_1 0x4b1e |
3038 | #define mmDIG6_AFMT_ISRC2_1 0x4e1e |
3039 | #define mmAFMT_ISRC2_2 0x1c1f |
3040 | #define mmDIG0_AFMT_ISRC2_2 0x1c1f |
3041 | #define mmDIG1_AFMT_ISRC2_2 0x1f1f |
3042 | #define mmDIG2_AFMT_ISRC2_2 0x421f |
3043 | #define mmDIG3_AFMT_ISRC2_2 0x451f |
3044 | #define mmDIG4_AFMT_ISRC2_2 0x481f |
3045 | #define mmDIG5_AFMT_ISRC2_2 0x4b1f |
3046 | #define mmDIG6_AFMT_ISRC2_2 0x4e1f |
3047 | #define mmAFMT_ISRC2_3 0x1c20 |
3048 | #define mmDIG0_AFMT_ISRC2_3 0x1c20 |
3049 | #define mmDIG1_AFMT_ISRC2_3 0x1f20 |
3050 | #define mmDIG2_AFMT_ISRC2_3 0x4220 |
3051 | #define mmDIG3_AFMT_ISRC2_3 0x4520 |
3052 | #define mmDIG4_AFMT_ISRC2_3 0x4820 |
3053 | #define mmDIG5_AFMT_ISRC2_3 0x4b20 |
3054 | #define mmDIG6_AFMT_ISRC2_3 0x4e20 |
3055 | #define mmAFMT_AVI_INFO0 0x1c21 |
3056 | #define mmDIG0_AFMT_AVI_INFO0 0x1c21 |
3057 | #define mmDIG1_AFMT_AVI_INFO0 0x1f21 |
3058 | #define mmDIG2_AFMT_AVI_INFO0 0x4221 |
3059 | #define mmDIG3_AFMT_AVI_INFO0 0x4521 |
3060 | #define mmDIG4_AFMT_AVI_INFO0 0x4821 |
3061 | #define mmDIG5_AFMT_AVI_INFO0 0x4b21 |
3062 | #define mmDIG6_AFMT_AVI_INFO0 0x4e21 |
3063 | #define mmAFMT_AVI_INFO1 0x1c22 |
3064 | #define mmDIG0_AFMT_AVI_INFO1 0x1c22 |
3065 | #define mmDIG1_AFMT_AVI_INFO1 0x1f22 |
3066 | #define mmDIG2_AFMT_AVI_INFO1 0x4222 |
3067 | #define mmDIG3_AFMT_AVI_INFO1 0x4522 |
3068 | #define mmDIG4_AFMT_AVI_INFO1 0x4822 |
3069 | #define mmDIG5_AFMT_AVI_INFO1 0x4b22 |
3070 | #define mmDIG6_AFMT_AVI_INFO1 0x4e22 |
3071 | #define mmAFMT_AVI_INFO2 0x1c23 |
3072 | #define mmDIG0_AFMT_AVI_INFO2 0x1c23 |
3073 | #define mmDIG1_AFMT_AVI_INFO2 0x1f23 |
3074 | #define mmDIG2_AFMT_AVI_INFO2 0x4223 |
3075 | #define mmDIG3_AFMT_AVI_INFO2 0x4523 |
3076 | #define mmDIG4_AFMT_AVI_INFO2 0x4823 |
3077 | #define mmDIG5_AFMT_AVI_INFO2 0x4b23 |
3078 | #define mmDIG6_AFMT_AVI_INFO2 0x4e23 |
3079 | #define mmAFMT_AVI_INFO3 0x1c24 |
3080 | #define mmDIG0_AFMT_AVI_INFO3 0x1c24 |
3081 | #define mmDIG1_AFMT_AVI_INFO3 0x1f24 |
3082 | #define mmDIG2_AFMT_AVI_INFO3 0x4224 |
3083 | #define mmDIG3_AFMT_AVI_INFO3 0x4524 |
3084 | #define mmDIG4_AFMT_AVI_INFO3 0x4824 |
3085 | #define mmDIG5_AFMT_AVI_INFO3 0x4b24 |
3086 | #define mmDIG6_AFMT_AVI_INFO3 0x4e24 |
3087 | #define mmAFMT_MPEG_INFO0 0x1c25 |
3088 | #define mmDIG0_AFMT_MPEG_INFO0 0x1c25 |
3089 | #define mmDIG1_AFMT_MPEG_INFO0 0x1f25 |
3090 | #define mmDIG2_AFMT_MPEG_INFO0 0x4225 |
3091 | #define mmDIG3_AFMT_MPEG_INFO0 0x4525 |
3092 | #define mmDIG4_AFMT_MPEG_INFO0 0x4825 |
3093 | #define mmDIG5_AFMT_MPEG_INFO0 0x4b25 |
3094 | #define mmDIG6_AFMT_MPEG_INFO0 0x4e25 |
3095 | #define mmAFMT_MPEG_INFO1 0x1c26 |
3096 | #define mmDIG0_AFMT_MPEG_INFO1 0x1c26 |
3097 | #define mmDIG1_AFMT_MPEG_INFO1 0x1f26 |
3098 | #define mmDIG2_AFMT_MPEG_INFO1 0x4226 |
3099 | #define mmDIG3_AFMT_MPEG_INFO1 0x4526 |
3100 | #define mmDIG4_AFMT_MPEG_INFO1 0x4826 |
3101 | #define mmDIG5_AFMT_MPEG_INFO1 0x4b26 |
3102 | #define mmDIG6_AFMT_MPEG_INFO1 0x4e26 |
3103 | #define mmAFMT_GENERIC_HDR 0x1c27 |
3104 | #define mmDIG0_AFMT_GENERIC_HDR 0x1c27 |
3105 | #define mmDIG1_AFMT_GENERIC_HDR 0x1f27 |
3106 | #define mmDIG2_AFMT_GENERIC_HDR 0x4227 |
3107 | #define mmDIG3_AFMT_GENERIC_HDR 0x4527 |
3108 | #define mmDIG4_AFMT_GENERIC_HDR 0x4827 |
3109 | #define mmDIG5_AFMT_GENERIC_HDR 0x4b27 |
3110 | #define mmDIG6_AFMT_GENERIC_HDR 0x4e27 |
3111 | #define mmAFMT_GENERIC_0 0x1c28 |
3112 | #define mmDIG0_AFMT_GENERIC_0 0x1c28 |
3113 | #define mmDIG1_AFMT_GENERIC_0 0x1f28 |
3114 | #define mmDIG2_AFMT_GENERIC_0 0x4228 |
3115 | #define mmDIG3_AFMT_GENERIC_0 0x4528 |
3116 | #define mmDIG4_AFMT_GENERIC_0 0x4828 |
3117 | #define mmDIG5_AFMT_GENERIC_0 0x4b28 |
3118 | #define mmDIG6_AFMT_GENERIC_0 0x4e28 |
3119 | #define mmAFMT_GENERIC_1 0x1c29 |
3120 | #define mmDIG0_AFMT_GENERIC_1 0x1c29 |
3121 | #define mmDIG1_AFMT_GENERIC_1 0x1f29 |
3122 | #define mmDIG2_AFMT_GENERIC_1 0x4229 |
3123 | #define mmDIG3_AFMT_GENERIC_1 0x4529 |
3124 | #define mmDIG4_AFMT_GENERIC_1 0x4829 |
3125 | #define mmDIG5_AFMT_GENERIC_1 0x4b29 |
3126 | #define mmDIG6_AFMT_GENERIC_1 0x4e29 |
3127 | #define mmAFMT_GENERIC_2 0x1c2a |
3128 | #define mmDIG0_AFMT_GENERIC_2 0x1c2a |
3129 | #define mmDIG1_AFMT_GENERIC_2 0x1f2a |
3130 | #define mmDIG2_AFMT_GENERIC_2 0x422a |
3131 | #define mmDIG3_AFMT_GENERIC_2 0x452a |
3132 | #define mmDIG4_AFMT_GENERIC_2 0x482a |
3133 | #define mmDIG5_AFMT_GENERIC_2 0x4b2a |
3134 | #define mmDIG6_AFMT_GENERIC_2 0x4e2a |
3135 | #define mmAFMT_GENERIC_3 0x1c2b |
3136 | #define mmDIG0_AFMT_GENERIC_3 0x1c2b |
3137 | #define mmDIG1_AFMT_GENERIC_3 0x1f2b |
3138 | #define mmDIG2_AFMT_GENERIC_3 0x422b |
3139 | #define mmDIG3_AFMT_GENERIC_3 0x452b |
3140 | #define mmDIG4_AFMT_GENERIC_3 0x482b |
3141 | #define mmDIG5_AFMT_GENERIC_3 0x4b2b |
3142 | #define mmDIG6_AFMT_GENERIC_3 0x4e2b |
3143 | #define mmAFMT_GENERIC_4 0x1c2c |
3144 | #define mmDIG0_AFMT_GENERIC_4 0x1c2c |
3145 | #define mmDIG1_AFMT_GENERIC_4 0x1f2c |
3146 | #define mmDIG2_AFMT_GENERIC_4 0x422c |
3147 | #define mmDIG3_AFMT_GENERIC_4 0x452c |
3148 | #define mmDIG4_AFMT_GENERIC_4 0x482c |
3149 | #define mmDIG5_AFMT_GENERIC_4 0x4b2c |
3150 | #define mmDIG6_AFMT_GENERIC_4 0x4e2c |
3151 | #define mmAFMT_GENERIC_5 0x1c2d |
3152 | #define mmDIG0_AFMT_GENERIC_5 0x1c2d |
3153 | #define mmDIG1_AFMT_GENERIC_5 0x1f2d |
3154 | #define mmDIG2_AFMT_GENERIC_5 0x422d |
3155 | #define mmDIG3_AFMT_GENERIC_5 0x452d |
3156 | #define mmDIG4_AFMT_GENERIC_5 0x482d |
3157 | #define mmDIG5_AFMT_GENERIC_5 0x4b2d |
3158 | #define mmDIG6_AFMT_GENERIC_5 0x4e2d |
3159 | #define mmAFMT_GENERIC_6 0x1c2e |
3160 | #define mmDIG0_AFMT_GENERIC_6 0x1c2e |
3161 | #define mmDIG1_AFMT_GENERIC_6 0x1f2e |
3162 | #define mmDIG2_AFMT_GENERIC_6 0x422e |
3163 | #define mmDIG3_AFMT_GENERIC_6 0x452e |
3164 | #define mmDIG4_AFMT_GENERIC_6 0x482e |
3165 | #define mmDIG5_AFMT_GENERIC_6 0x4b2e |
3166 | #define mmDIG6_AFMT_GENERIC_6 0x4e2e |
3167 | #define mmAFMT_GENERIC_7 0x1c2f |
3168 | #define mmDIG0_AFMT_GENERIC_7 0x1c2f |
3169 | #define mmDIG1_AFMT_GENERIC_7 0x1f2f |
3170 | #define mmDIG2_AFMT_GENERIC_7 0x422f |
3171 | #define mmDIG3_AFMT_GENERIC_7 0x452f |
3172 | #define mmDIG4_AFMT_GENERIC_7 0x482f |
3173 | #define mmDIG5_AFMT_GENERIC_7 0x4b2f |
3174 | #define mmDIG6_AFMT_GENERIC_7 0x4e2f |
3175 | #define mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30 |
3176 | #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30 |
3177 | #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30 |
3178 | #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 |
3179 | #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 |
3180 | #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 |
3181 | #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30 |
3182 | #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30 |
3183 | #define mmHDMI_ACR_32_0 0x1c37 |
3184 | #define mmDIG0_HDMI_ACR_32_0 0x1c37 |
3185 | #define mmDIG1_HDMI_ACR_32_0 0x1f37 |
3186 | #define mmDIG2_HDMI_ACR_32_0 0x4237 |
3187 | #define mmDIG3_HDMI_ACR_32_0 0x4537 |
3188 | #define mmDIG4_HDMI_ACR_32_0 0x4837 |
3189 | #define mmDIG5_HDMI_ACR_32_0 0x4b37 |
3190 | #define mmDIG6_HDMI_ACR_32_0 0x4e37 |
3191 | #define mmHDMI_ACR_32_1 0x1c38 |
3192 | #define mmDIG0_HDMI_ACR_32_1 0x1c38 |
3193 | #define mmDIG1_HDMI_ACR_32_1 0x1f38 |
3194 | #define mmDIG2_HDMI_ACR_32_1 0x4238 |
3195 | #define mmDIG3_HDMI_ACR_32_1 0x4538 |
3196 | #define mmDIG4_HDMI_ACR_32_1 0x4838 |
3197 | #define mmDIG5_HDMI_ACR_32_1 0x4b38 |
3198 | #define mmDIG6_HDMI_ACR_32_1 0x4e38 |
3199 | #define mmHDMI_ACR_44_0 0x1c39 |
3200 | #define mmDIG0_HDMI_ACR_44_0 0x1c39 |
3201 | #define mmDIG1_HDMI_ACR_44_0 0x1f39 |
3202 | #define mmDIG2_HDMI_ACR_44_0 0x4239 |
3203 | #define mmDIG3_HDMI_ACR_44_0 0x4539 |
3204 | #define mmDIG4_HDMI_ACR_44_0 0x4839 |
3205 | #define mmDIG5_HDMI_ACR_44_0 0x4b39 |
3206 | #define mmDIG6_HDMI_ACR_44_0 0x4e39 |
3207 | #define mmHDMI_ACR_44_1 0x1c3a |
3208 | #define mmDIG0_HDMI_ACR_44_1 0x1c3a |
3209 | #define mmDIG1_HDMI_ACR_44_1 0x1f3a |
3210 | #define mmDIG2_HDMI_ACR_44_1 0x423a |
3211 | #define mmDIG3_HDMI_ACR_44_1 0x453a |
3212 | #define mmDIG4_HDMI_ACR_44_1 0x483a |
3213 | #define mmDIG5_HDMI_ACR_44_1 0x4b3a |
3214 | #define mmDIG6_HDMI_ACR_44_1 0x4e3a |
3215 | #define mmHDMI_ACR_48_0 0x1c3b |
3216 | #define mmDIG0_HDMI_ACR_48_0 0x1c3b |
3217 | #define mmDIG1_HDMI_ACR_48_0 0x1f3b |
3218 | #define mmDIG2_HDMI_ACR_48_0 0x423b |
3219 | #define mmDIG3_HDMI_ACR_48_0 0x453b |
3220 | #define mmDIG4_HDMI_ACR_48_0 0x483b |
3221 | #define mmDIG5_HDMI_ACR_48_0 0x4b3b |
3222 | #define mmDIG6_HDMI_ACR_48_0 0x4e3b |
3223 | #define mmHDMI_ACR_48_1 0x1c3c |
3224 | #define mmDIG0_HDMI_ACR_48_1 0x1c3c |
3225 | #define mmDIG1_HDMI_ACR_48_1 0x1f3c |
3226 | #define mmDIG2_HDMI_ACR_48_1 0x423c |
3227 | #define mmDIG3_HDMI_ACR_48_1 0x453c |
3228 | #define mmDIG4_HDMI_ACR_48_1 0x483c |
3229 | #define mmDIG5_HDMI_ACR_48_1 0x4b3c |
3230 | #define mmDIG6_HDMI_ACR_48_1 0x4e3c |
3231 | #define mmHDMI_ACR_STATUS_0 0x1c3d |
3232 | #define mmDIG0_HDMI_ACR_STATUS_0 0x1c3d |
3233 | #define mmDIG1_HDMI_ACR_STATUS_0 0x1f3d |
3234 | #define mmDIG2_HDMI_ACR_STATUS_0 0x423d |
3235 | #define mmDIG3_HDMI_ACR_STATUS_0 0x453d |
3236 | #define mmDIG4_HDMI_ACR_STATUS_0 0x483d |
3237 | #define mmDIG5_HDMI_ACR_STATUS_0 0x4b3d |
3238 | #define mmDIG6_HDMI_ACR_STATUS_0 0x4e3d |
3239 | #define mmHDMI_ACR_STATUS_1 0x1c3e |
3240 | #define mmDIG0_HDMI_ACR_STATUS_1 0x1c3e |
3241 | #define mmDIG1_HDMI_ACR_STATUS_1 0x1f3e |
3242 | #define mmDIG2_HDMI_ACR_STATUS_1 0x423e |
3243 | #define mmDIG3_HDMI_ACR_STATUS_1 0x453e |
3244 | #define mmDIG4_HDMI_ACR_STATUS_1 0x483e |
3245 | #define mmDIG5_HDMI_ACR_STATUS_1 0x4b3e |
3246 | #define mmDIG6_HDMI_ACR_STATUS_1 0x4e3e |
3247 | #define mmAFMT_AUDIO_INFO0 0x1c3f |
3248 | #define mmDIG0_AFMT_AUDIO_INFO0 0x1c3f |
3249 | #define mmDIG1_AFMT_AUDIO_INFO0 0x1f3f |
3250 | #define mmDIG2_AFMT_AUDIO_INFO0 0x423f |
3251 | #define mmDIG3_AFMT_AUDIO_INFO0 0x453f |
3252 | #define mmDIG4_AFMT_AUDIO_INFO0 0x483f |
3253 | #define mmDIG5_AFMT_AUDIO_INFO0 0x4b3f |
3254 | #define mmDIG6_AFMT_AUDIO_INFO0 0x4e3f |
3255 | #define mmAFMT_AUDIO_INFO1 0x1c40 |
3256 | #define mmDIG0_AFMT_AUDIO_INFO1 0x1c40 |
3257 | #define mmDIG1_AFMT_AUDIO_INFO1 0x1f40 |
3258 | #define mmDIG2_AFMT_AUDIO_INFO1 0x4240 |
3259 | #define mmDIG3_AFMT_AUDIO_INFO1 0x4540 |
3260 | #define mmDIG4_AFMT_AUDIO_INFO1 0x4840 |
3261 | #define mmDIG5_AFMT_AUDIO_INFO1 0x4b40 |
3262 | #define mmDIG6_AFMT_AUDIO_INFO1 0x4e40 |
3263 | #define mmAFMT_60958_0 0x1c41 |
3264 | #define mmDIG0_AFMT_60958_0 0x1c41 |
3265 | #define mmDIG1_AFMT_60958_0 0x1f41 |
3266 | #define mmDIG2_AFMT_60958_0 0x4241 |
3267 | #define mmDIG3_AFMT_60958_0 0x4541 |
3268 | #define mmDIG4_AFMT_60958_0 0x4841 |
3269 | #define mmDIG5_AFMT_60958_0 0x4b41 |
3270 | #define mmDIG6_AFMT_60958_0 0x4e41 |
3271 | #define mmAFMT_60958_1 0x1c42 |
3272 | #define mmDIG0_AFMT_60958_1 0x1c42 |
3273 | #define mmDIG1_AFMT_60958_1 0x1f42 |
3274 | #define mmDIG2_AFMT_60958_1 0x4242 |
3275 | #define mmDIG3_AFMT_60958_1 0x4542 |
3276 | #define mmDIG4_AFMT_60958_1 0x4842 |
3277 | #define mmDIG5_AFMT_60958_1 0x4b42 |
3278 | #define mmDIG6_AFMT_60958_1 0x4e42 |
3279 | #define mmAFMT_AUDIO_CRC_CONTROL 0x1c43 |
3280 | #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43 |
3281 | #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43 |
3282 | #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 |
3283 | #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 |
3284 | #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 |
3285 | #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43 |
3286 | #define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43 |
3287 | #define mmAFMT_RAMP_CONTROL0 0x1c44 |
3288 | #define mmDIG0_AFMT_RAMP_CONTROL0 0x1c44 |
3289 | #define mmDIG1_AFMT_RAMP_CONTROL0 0x1f44 |
3290 | #define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 |
3291 | #define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 |
3292 | #define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 |
3293 | #define mmDIG5_AFMT_RAMP_CONTROL0 0x4b44 |
3294 | #define mmDIG6_AFMT_RAMP_CONTROL0 0x4e44 |
3295 | #define mmAFMT_RAMP_CONTROL1 0x1c45 |
3296 | #define mmDIG0_AFMT_RAMP_CONTROL1 0x1c45 |
3297 | #define mmDIG1_AFMT_RAMP_CONTROL1 0x1f45 |
3298 | #define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 |
3299 | #define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 |
3300 | #define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 |
3301 | #define mmDIG5_AFMT_RAMP_CONTROL1 0x4b45 |
3302 | #define mmDIG6_AFMT_RAMP_CONTROL1 0x4e45 |
3303 | #define mmAFMT_RAMP_CONTROL2 0x1c46 |
3304 | #define mmDIG0_AFMT_RAMP_CONTROL2 0x1c46 |
3305 | #define mmDIG1_AFMT_RAMP_CONTROL2 0x1f46 |
3306 | #define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 |
3307 | #define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 |
3308 | #define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 |
3309 | #define mmDIG5_AFMT_RAMP_CONTROL2 0x4b46 |
3310 | #define mmDIG6_AFMT_RAMP_CONTROL2 0x4e46 |
3311 | #define mmAFMT_RAMP_CONTROL3 0x1c47 |
3312 | #define mmDIG0_AFMT_RAMP_CONTROL3 0x1c47 |
3313 | #define mmDIG1_AFMT_RAMP_CONTROL3 0x1f47 |
3314 | #define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 |
3315 | #define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 |
3316 | #define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 |
3317 | #define mmDIG5_AFMT_RAMP_CONTROL3 0x4b47 |
3318 | #define mmDIG6_AFMT_RAMP_CONTROL3 0x4e47 |
3319 | #define mmAFMT_60958_2 0x1c48 |
3320 | #define mmDIG0_AFMT_60958_2 0x1c48 |
3321 | #define mmDIG1_AFMT_60958_2 0x1f48 |
3322 | #define mmDIG2_AFMT_60958_2 0x4248 |
3323 | #define mmDIG3_AFMT_60958_2 0x4548 |
3324 | #define mmDIG4_AFMT_60958_2 0x4848 |
3325 | #define mmDIG5_AFMT_60958_2 0x4b48 |
3326 | #define mmDIG6_AFMT_60958_2 0x4e48 |
3327 | #define mmAFMT_AUDIO_CRC_RESULT 0x1c49 |
3328 | #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49 |
3329 | #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49 |
3330 | #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 |
3331 | #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 |
3332 | #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 |
3333 | #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49 |
3334 | #define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49 |
3335 | #define mmAFMT_STATUS 0x1c4a |
3336 | #define mmDIG0_AFMT_STATUS 0x1c4a |
3337 | #define mmDIG1_AFMT_STATUS 0x1f4a |
3338 | #define mmDIG2_AFMT_STATUS 0x424a |
3339 | #define mmDIG3_AFMT_STATUS 0x454a |
3340 | #define mmDIG4_AFMT_STATUS 0x484a |
3341 | #define mmDIG5_AFMT_STATUS 0x4b4a |
3342 | #define mmDIG6_AFMT_STATUS 0x4e4a |
3343 | #define mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b |
3344 | #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b |
3345 | #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b |
3346 | #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b |
3347 | #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b |
3348 | #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b |
3349 | #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b |
3350 | #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b |
3351 | #define mmAFMT_VBI_PACKET_CONTROL 0x1c4c |
3352 | #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c |
3353 | #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c |
3354 | #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c |
3355 | #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c |
3356 | #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c |
3357 | #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c |
3358 | #define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c |
3359 | #define mmAFMT_INFOFRAME_CONTROL0 0x1c4d |
3360 | #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d |
3361 | #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d |
3362 | #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d |
3363 | #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d |
3364 | #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d |
3365 | #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d |
3366 | #define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d |
3367 | #define mmAFMT_AUDIO_SRC_CONTROL 0x1c4f |
3368 | #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f |
3369 | #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f |
3370 | #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f |
3371 | #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f |
3372 | #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f |
3373 | #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f |
3374 | #define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f |
3375 | #define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52 |
3376 | #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52 |
3377 | #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52 |
3378 | #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 |
3379 | #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 |
3380 | #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 |
3381 | #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52 |
3382 | #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52 |
3383 | #define mmDIG_BE_CNTL 0x1c50 |
3384 | #define mmDIG0_DIG_BE_CNTL 0x1c50 |
3385 | #define mmDIG1_DIG_BE_CNTL 0x1f50 |
3386 | #define mmDIG2_DIG_BE_CNTL 0x4250 |
3387 | #define mmDIG3_DIG_BE_CNTL 0x4550 |
3388 | #define mmDIG4_DIG_BE_CNTL 0x4850 |
3389 | #define mmDIG5_DIG_BE_CNTL 0x4b50 |
3390 | #define mmDIG6_DIG_BE_CNTL 0x4e50 |
3391 | #define mmDIG_BE_EN_CNTL 0x1c51 |
3392 | #define mmDIG0_DIG_BE_EN_CNTL 0x1c51 |
3393 | #define mmDIG1_DIG_BE_EN_CNTL 0x1f51 |
3394 | #define mmDIG2_DIG_BE_EN_CNTL 0x4251 |
3395 | #define mmDIG3_DIG_BE_EN_CNTL 0x4551 |
3396 | #define mmDIG4_DIG_BE_EN_CNTL 0x4851 |
3397 | #define mmDIG5_DIG_BE_EN_CNTL 0x4b51 |
3398 | #define mmDIG6_DIG_BE_EN_CNTL 0x4e51 |
3399 | #define mmTMDS_CNTL 0x1c7c |
3400 | #define mmDIG0_TMDS_CNTL 0x1c7c |
3401 | #define mmDIG1_TMDS_CNTL 0x1f7c |
3402 | #define mmDIG2_TMDS_CNTL 0x427c |
3403 | #define mmDIG3_TMDS_CNTL 0x457c |
3404 | #define mmDIG4_TMDS_CNTL 0x487c |
3405 | #define mmDIG5_TMDS_CNTL 0x4b7c |
3406 | #define mmDIG6_TMDS_CNTL 0x4e7c |
3407 | #define mmTMDS_CONTROL_CHAR 0x1c7d |
3408 | #define mmDIG0_TMDS_CONTROL_CHAR 0x1c7d |
3409 | #define mmDIG1_TMDS_CONTROL_CHAR 0x1f7d |
3410 | #define mmDIG2_TMDS_CONTROL_CHAR 0x427d |
3411 | #define mmDIG3_TMDS_CONTROL_CHAR 0x457d |
3412 | #define mmDIG4_TMDS_CONTROL_CHAR 0x487d |
3413 | #define mmDIG5_TMDS_CONTROL_CHAR 0x4b7d |
3414 | #define mmDIG6_TMDS_CONTROL_CHAR 0x4e7d |
3415 | #define mmTMDS_CONTROL0_FEEDBACK 0x1c7e |
3416 | #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e |
3417 | #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e |
3418 | #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e |
3419 | #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e |
3420 | #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e |
3421 | #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e |
3422 | #define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e |
3423 | #define mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f |
3424 | #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f |
3425 | #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f |
3426 | #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f |
3427 | #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f |
3428 | #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f |
3429 | #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f |
3430 | #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f |
3431 | #define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 |
3432 | #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 |
3433 | #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80 |
3434 | #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 |
3435 | #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 |
3436 | #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 |
3437 | #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80 |
3438 | #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80 |
3439 | #define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 |
3440 | #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 |
3441 | #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81 |
3442 | #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 |
3443 | #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 |
3444 | #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 |
3445 | #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81 |
3446 | #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81 |
3447 | #define mmTMDS_DEBUG 0x1c82 |
3448 | #define mmDIG0_TMDS_DEBUG 0x1c82 |
3449 | #define mmDIG1_TMDS_DEBUG 0x1f82 |
3450 | #define mmDIG2_TMDS_DEBUG 0x4282 |
3451 | #define mmDIG3_TMDS_DEBUG 0x4582 |
3452 | #define mmDIG4_TMDS_DEBUG 0x4882 |
3453 | #define mmDIG5_TMDS_DEBUG 0x4b82 |
3454 | #define mmDIG6_TMDS_DEBUG 0x4e82 |
3455 | #define mmTMDS_CTL_BITS 0x1c83 |
3456 | #define mmDIG0_TMDS_CTL_BITS 0x1c83 |
3457 | #define mmDIG1_TMDS_CTL_BITS 0x1f83 |
3458 | #define mmDIG2_TMDS_CTL_BITS 0x4283 |
3459 | #define mmDIG3_TMDS_CTL_BITS 0x4583 |
3460 | #define mmDIG4_TMDS_CTL_BITS 0x4883 |
3461 | #define mmDIG5_TMDS_CTL_BITS 0x4b83 |
3462 | #define mmDIG6_TMDS_CTL_BITS 0x4e83 |
3463 | #define mmTMDS_DCBALANCER_CONTROL 0x1c84 |
3464 | #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 |
3465 | #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 |
3466 | #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 |
3467 | #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 |
3468 | #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 |
3469 | #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 |
3470 | #define mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84 |
3471 | #define mmTMDS_CTL0_1_GEN_CNTL 0x1c86 |
3472 | #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 |
3473 | #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86 |
3474 | #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 |
3475 | #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 |
3476 | #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 |
3477 | #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86 |
3478 | #define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86 |
3479 | #define mmTMDS_CTL2_3_GEN_CNTL 0x1c87 |
3480 | #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87 |
3481 | #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87 |
3482 | #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 |
3483 | #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 |
3484 | #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 |
3485 | #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87 |
3486 | #define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87 |
3487 | #define mmLVDS_DATA_CNTL 0x1c8c |
3488 | #define mmDIG0_LVDS_DATA_CNTL 0x1c8c |
3489 | #define mmDIG1_LVDS_DATA_CNTL 0x1f8c |
3490 | #define mmDIG2_LVDS_DATA_CNTL 0x428c |
3491 | #define mmDIG3_LVDS_DATA_CNTL 0x458c |
3492 | #define mmDIG4_LVDS_DATA_CNTL 0x488c |
3493 | #define mmDIG5_LVDS_DATA_CNTL 0x4b8c |
3494 | #define mmDIG6_LVDS_DATA_CNTL 0x4e8c |
3495 | #define mmDIG_LANE_ENABLE 0x1c8d |
3496 | #define mmDIG0_DIG_LANE_ENABLE 0x1c8d |
3497 | #define mmDIG1_DIG_LANE_ENABLE 0x1f8d |
3498 | #define mmDIG2_DIG_LANE_ENABLE 0x428d |
3499 | #define mmDIG3_DIG_LANE_ENABLE 0x458d |
3500 | #define mmDIG4_DIG_LANE_ENABLE 0x488d |
3501 | #define mmDIG5_DIG_LANE_ENABLE 0x4b8d |
3502 | #define mmDIG6_DIG_LANE_ENABLE 0x4e8d |
3503 | #define mmDOUT_SCRATCH0 0x1844 |
3504 | #define mmDOUT_SCRATCH1 0x1845 |
3505 | #define mmDOUT_SCRATCH2 0x1846 |
3506 | #define mmDOUT_SCRATCH3 0x1847 |
3507 | #define mmDOUT_SCRATCH4 0x1848 |
3508 | #define mmDOUT_SCRATCH5 0x1849 |
3509 | #define mmDOUT_SCRATCH6 0x184a |
3510 | #define mmDOUT_SCRATCH7 0x184b |
3511 | #define mmDOUT_DCE_VCE_CONTROL 0x18ff |
3512 | #define mmDC_HPD1_INT_STATUS 0x1807 |
3513 | #define mmDC_HPD1_INT_CONTROL 0x1808 |
3514 | #define mmDC_HPD1_CONTROL 0x1809 |
3515 | #define mmDC_HPD2_INT_STATUS 0x180a |
3516 | #define mmDC_HPD2_INT_CONTROL 0x180b |
3517 | #define mmDC_HPD2_CONTROL 0x180c |
3518 | #define mmDC_HPD3_INT_STATUS 0x180d |
3519 | #define mmDC_HPD3_INT_CONTROL 0x180e |
3520 | #define mmDC_HPD3_CONTROL 0x180f |
3521 | #define mmDC_HPD4_INT_STATUS 0x1810 |
3522 | #define mmDC_HPD4_INT_CONTROL 0x1811 |
3523 | #define mmDC_HPD4_CONTROL 0x1812 |
3524 | #define mmDC_HPD5_INT_STATUS 0x1813 |
3525 | #define mmDC_HPD5_INT_CONTROL 0x1814 |
3526 | #define mmDC_HPD5_CONTROL 0x1815 |
3527 | #define mmDC_HPD6_INT_STATUS 0x1816 |
3528 | #define mmDC_HPD6_INT_CONTROL 0x1817 |
3529 | #define mmDC_HPD6_CONTROL 0x1818 |
3530 | #define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 |
3531 | #define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 |
3532 | #define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 |
3533 | #define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 |
3534 | #define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 |
3535 | #define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 |
3536 | #define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc |
3537 | #define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd |
3538 | #define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be |
3539 | #define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc |
3540 | #define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd |
3541 | #define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe |
3542 | #define mmDC_I2C_CONTROL 0x1819 |
3543 | #define mmDC_I2C_ARBITRATION 0x181a |
3544 | #define mmDC_I2C_INTERRUPT_CONTROL 0x181b |
3545 | #define mmDC_I2C_SW_STATUS 0x181c |
3546 | #define mmDC_I2C_DDC1_HW_STATUS 0x181d |
3547 | #define mmDC_I2C_DDC2_HW_STATUS 0x181e |
3548 | #define mmDC_I2C_DDC3_HW_STATUS 0x181f |
3549 | #define mmDC_I2C_DDC4_HW_STATUS 0x1820 |
3550 | #define mmDC_I2C_DDC5_HW_STATUS 0x1821 |
3551 | #define mmDC_I2C_DDC6_HW_STATUS 0x1822 |
3552 | #define mmDC_I2C_DDC1_SPEED 0x1823 |
3553 | #define mmDC_I2C_DDC1_SETUP 0x1824 |
3554 | #define mmDC_I2C_DDC2_SPEED 0x1825 |
3555 | #define mmDC_I2C_DDC2_SETUP 0x1826 |
3556 | #define mmDC_I2C_DDC3_SPEED 0x1827 |
3557 | #define mmDC_I2C_DDC3_SETUP 0x1828 |
3558 | #define mmDC_I2C_DDC4_SPEED 0x1829 |
3559 | #define mmDC_I2C_DDC4_SETUP 0x182a |
3560 | #define mmDC_I2C_DDC5_SPEED 0x182b |
3561 | #define mmDC_I2C_DDC5_SETUP 0x182c |
3562 | #define mmDC_I2C_DDC6_SPEED 0x182d |
3563 | #define mmDC_I2C_DDC6_SETUP 0x182e |
3564 | #define mmDC_I2C_TRANSACTION0 0x182f |
3565 | #define mmDC_I2C_TRANSACTION1 0x1830 |
3566 | #define mmDC_I2C_TRANSACTION2 0x1831 |
3567 | #define mmDC_I2C_TRANSACTION3 0x1832 |
3568 | #define mmDC_I2C_DATA 0x1833 |
3569 | #define mmGENERIC_I2C_CONTROL 0x1834 |
3570 | #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 |
3571 | #define mmGENERIC_I2C_STATUS 0x1836 |
3572 | #define mmGENERIC_I2C_SPEED 0x1837 |
3573 | #define mmGENERIC_I2C_SETUP 0x1838 |
3574 | #define mmGENERIC_I2C_TRANSACTION 0x1839 |
3575 | #define mmGENERIC_I2C_DATA 0x183a |
3576 | #define mmGENERIC_I2C_PIN_SELECTION 0x183b |
3577 | #define mmGENERIC_I2C_PIN_DEBUG 0x183c |
3578 | #define mmDISP_INTERRUPT_STATUS 0x183d |
3579 | #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e |
3580 | #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f |
3581 | #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 |
3582 | #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 |
3583 | #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 |
3584 | #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0 |
3585 | #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1 |
3586 | #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2 |
3587 | #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3 |
3588 | #define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 |
3589 | #define mmDISP_TIMER_CONTROL 0x1842 |
3590 | #define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 |
3591 | #define mmDC_I2C_DDCVGA_SPEED 0x1856 |
3592 | #define mmDC_I2C_DDCVGA_SETUP 0x1857 |
3593 | #define mmDC_I2C_EDID_DETECT_CTRL 0x186f |
3594 | #define mmDISPOUT_STEREOSYNC_SEL 0x18bf |
3595 | #define mmDOUT_TEST_DEBUG_INDEX 0x184d |
3596 | #define mmDOUT_TEST_DEBUG_DATA 0x184e |
3597 | #define ixDP_AUX1_DEBUG_A 0x10 |
3598 | #define ixDP_AUX1_DEBUG_B 0x11 |
3599 | #define ixDP_AUX1_DEBUG_C 0x12 |
3600 | #define ixDP_AUX1_DEBUG_D 0x13 |
3601 | #define ixDP_AUX1_DEBUG_E 0x14 |
3602 | #define ixDP_AUX1_DEBUG_F 0x15 |
3603 | #define ixDP_AUX1_DEBUG_G 0x16 |
3604 | #define ixDP_AUX1_DEBUG_H 0x17 |
3605 | #define ixDP_AUX1_DEBUG_I 0x18 |
3606 | #define ixDP_AUX1_DEBUG_J 0x19 |
3607 | #define ixDP_AUX1_DEBUG_K 0x1a |
3608 | #define ixDP_AUX1_DEBUG_L 0x1b |
3609 | #define ixDP_AUX1_DEBUG_M 0x1c |
3610 | #define ixDP_AUX1_DEBUG_N 0x1d |
3611 | #define ixDP_AUX1_DEBUG_O 0x1e |
3612 | #define ixDP_AUX1_DEBUG_P 0x1f |
3613 | #define ixDP_AUX1_DEBUG_Q 0x90 |
3614 | #define ixDP_AUX2_DEBUG_A 0x20 |
3615 | #define ixDP_AUX2_DEBUG_B 0x21 |
3616 | #define ixDP_AUX2_DEBUG_C 0x22 |
3617 | #define ixDP_AUX2_DEBUG_D 0x23 |
3618 | #define ixDP_AUX2_DEBUG_E 0x24 |
3619 | #define ixDP_AUX2_DEBUG_F 0x25 |
3620 | #define ixDP_AUX2_DEBUG_G 0x26 |
3621 | #define ixDP_AUX2_DEBUG_H 0x27 |
3622 | #define ixDP_AUX2_DEBUG_I 0x28 |
3623 | #define ixDP_AUX2_DEBUG_J 0x29 |
3624 | #define ixDP_AUX2_DEBUG_K 0x2a |
3625 | #define ixDP_AUX2_DEBUG_L 0x2b |
3626 | #define ixDP_AUX2_DEBUG_M 0x2c |
3627 | #define ixDP_AUX2_DEBUG_N 0x2d |
3628 | #define ixDP_AUX2_DEBUG_O 0x2e |
3629 | #define ixDP_AUX2_DEBUG_P 0x2f |
3630 | #define ixDP_AUX2_DEBUG_Q 0x91 |
3631 | #define ixDP_AUX3_DEBUG_A 0x30 |
3632 | #define ixDP_AUX3_DEBUG_B 0x31 |
3633 | #define ixDP_AUX3_DEBUG_C 0x32 |
3634 | #define ixDP_AUX3_DEBUG_D 0x33 |
3635 | #define ixDP_AUX3_DEBUG_E 0x34 |
3636 | #define ixDP_AUX3_DEBUG_F 0x35 |
3637 | #define ixDP_AUX3_DEBUG_G 0x36 |
3638 | #define ixDP_AUX3_DEBUG_H 0x37 |
3639 | #define ixDP_AUX3_DEBUG_I 0x38 |
3640 | #define ixDP_AUX3_DEBUG_J 0x39 |
3641 | #define ixDP_AUX3_DEBUG_K 0x3a |
3642 | #define ixDP_AUX3_DEBUG_L 0x3b |
3643 | #define ixDP_AUX3_DEBUG_M 0x3c |
3644 | #define ixDP_AUX3_DEBUG_N 0x3d |
3645 | #define ixDP_AUX3_DEBUG_O 0x3e |
3646 | #define ixDP_AUX3_DEBUG_P 0x3f |
3647 | #define ixDP_AUX3_DEBUG_Q 0x92 |
3648 | #define ixDP_AUX4_DEBUG_A 0x40 |
3649 | #define ixDP_AUX4_DEBUG_B 0x41 |
3650 | #define ixDP_AUX4_DEBUG_C 0x42 |
3651 | #define ixDP_AUX4_DEBUG_D 0x43 |
3652 | #define ixDP_AUX4_DEBUG_E 0x44 |
3653 | #define ixDP_AUX4_DEBUG_F 0x45 |
3654 | #define ixDP_AUX4_DEBUG_G 0x46 |
3655 | #define ixDP_AUX4_DEBUG_H 0x47 |
3656 | #define ixDP_AUX4_DEBUG_I 0x48 |
3657 | #define ixDP_AUX4_DEBUG_J 0x49 |
3658 | #define ixDP_AUX4_DEBUG_K 0x4a |
3659 | #define ixDP_AUX4_DEBUG_L 0x4b |
3660 | #define ixDP_AUX4_DEBUG_M 0x4c |
3661 | #define ixDP_AUX4_DEBUG_N 0x4d |
3662 | #define ixDP_AUX4_DEBUG_O 0x4e |
3663 | #define ixDP_AUX4_DEBUG_P 0x4f |
3664 | #define ixDP_AUX4_DEBUG_Q 0x93 |
3665 | #define ixDP_AUX5_DEBUG_A 0x70 |
3666 | #define ixDP_AUX5_DEBUG_B 0x71 |
3667 | #define ixDP_AUX5_DEBUG_C 0x72 |
3668 | #define ixDP_AUX5_DEBUG_D 0x73 |
3669 | #define ixDP_AUX5_DEBUG_E 0x74 |
3670 | #define ixDP_AUX5_DEBUG_F 0x75 |
3671 | #define ixDP_AUX5_DEBUG_G 0x76 |
3672 | #define ixDP_AUX5_DEBUG_H 0x77 |
3673 | #define ixDP_AUX5_DEBUG_I 0x78 |
3674 | #define ixDP_AUX5_DEBUG_J 0x79 |
3675 | #define ixDP_AUX5_DEBUG_K 0x7a |
3676 | #define ixDP_AUX5_DEBUG_L 0x7b |
3677 | #define ixDP_AUX5_DEBUG_M 0x7c |
3678 | #define ixDP_AUX5_DEBUG_N 0x7d |
3679 | #define ixDP_AUX5_DEBUG_O 0x7f |
3680 | #define ixDP_AUX5_DEBUG_P 0x94 |
3681 | #define ixDP_AUX5_DEBUG_Q 0x95 |
3682 | #define ixDP_AUX6_DEBUG_A 0x80 |
3683 | #define ixDP_AUX6_DEBUG_B 0x81 |
3684 | #define ixDP_AUX6_DEBUG_C 0x82 |
3685 | #define ixDP_AUX6_DEBUG_D 0x83 |
3686 | #define ixDP_AUX6_DEBUG_E 0x84 |
3687 | #define ixDP_AUX6_DEBUG_F 0x85 |
3688 | #define ixDP_AUX6_DEBUG_G 0x86 |
3689 | #define ixDP_AUX6_DEBUG_H 0x87 |
3690 | #define ixDP_AUX6_DEBUG_I 0x88 |
3691 | #define ixDP_AUX6_DEBUG_J 0x89 |
3692 | #define ixDP_AUX6_DEBUG_K 0x8a |
3693 | #define ixDP_AUX6_DEBUG_L 0x8b |
3694 | #define ixDP_AUX6_DEBUG_M 0x8c |
3695 | #define ixDP_AUX6_DEBUG_N 0x8d |
3696 | #define ixDP_AUX6_DEBUG_O 0x8f |
3697 | #define ixDP_AUX6_DEBUG_P 0x96 |
3698 | #define ixDP_AUX6_DEBUG_Q 0x97 |
3699 | #define mmDMCU_CTRL 0x1600 |
3700 | #define mmDMCU_STATUS 0x1601 |
3701 | #define mmDMCU_PC_START_ADDR 0x1602 |
3702 | #define mmDMCU_FW_START_ADDR 0x1603 |
3703 | #define mmDMCU_FW_END_ADDR 0x1604 |
3704 | #define mmDMCU_FW_ISR_START_ADDR 0x1605 |
3705 | #define mmDMCU_FW_CS_HI 0x1606 |
3706 | #define mmDMCU_FW_CS_LO 0x1607 |
3707 | #define mmDMCU_RAM_ACCESS_CTRL 0x1608 |
3708 | #define mmDMCU_ERAM_WR_CTRL 0x1609 |
3709 | #define mmDMCU_ERAM_WR_DATA 0x160a |
3710 | #define mmDMCU_ERAM_RD_CTRL 0x160b |
3711 | #define mmDMCU_ERAM_RD_DATA 0x160c |
3712 | #define mmDMCU_IRAM_WR_CTRL 0x160d |
3713 | #define mmDMCU_IRAM_WR_DATA 0x160e |
3714 | #define mmDMCU_IRAM_RD_CTRL 0x160f |
3715 | #define mmDMCU_IRAM_RD_DATA 0x1610 |
3716 | #define mmDMCU_EVENT_TRIGGER 0x1611 |
3717 | #define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 |
3718 | #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 |
3719 | #define mmDMCU_INTERRUPT_STATUS 0x1614 |
3720 | #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 |
3721 | #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 |
3722 | #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 |
3723 | #define mmDC_DMCU_SCRATCH 0x1618 |
3724 | #define mmDMCU_INT_CNT 0x1619 |
3725 | #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a |
3726 | #define mmDMCU_UC_CLK_GATING_CNTL 0x161b |
3727 | #define mmMASTER_COMM_DATA_REG1 0x161c |
3728 | #define mmMASTER_COMM_DATA_REG2 0x161d |
3729 | #define mmMASTER_COMM_DATA_REG3 0x161e |
3730 | #define mmMASTER_COMM_CMD_REG 0x161f |
3731 | #define mmMASTER_COMM_CNTL_REG 0x1620 |
3732 | #define mmSLAVE_COMM_DATA_REG1 0x1621 |
3733 | #define mmSLAVE_COMM_DATA_REG2 0x1622 |
3734 | #define mmSLAVE_COMM_DATA_REG3 0x1623 |
3735 | #define mmSLAVE_COMM_CMD_REG 0x1624 |
3736 | #define mmSLAVE_COMM_CNTL_REG 0x1625 |
3737 | #define mmDMCU_TEST_DEBUG_INDEX 0x1626 |
3738 | #define mmDMCU_TEST_DEBUG_DATA 0x1627 |
3739 | #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750 |
3740 | #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751 |
3741 | #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752 |
3742 | #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753 |
3743 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754 |
3744 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755 |
3745 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756 |
3746 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757 |
3747 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 |
3748 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759 |
3749 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a |
3750 | #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b |
3751 | #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c |
3752 | #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d |
3753 | #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e |
3754 | #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f |
3755 | #define mmDP_LINK_CNTL 0x1cc0 |
3756 | #define mmDP0_DP_LINK_CNTL 0x1cc0 |
3757 | #define mmDP1_DP_LINK_CNTL 0x1fc0 |
3758 | #define mmDP2_DP_LINK_CNTL 0x42c0 |
3759 | #define mmDP3_DP_LINK_CNTL 0x45c0 |
3760 | #define mmDP4_DP_LINK_CNTL 0x48c0 |
3761 | #define mmDP5_DP_LINK_CNTL 0x4bc0 |
3762 | #define mmDP6_DP_LINK_CNTL 0x4ec0 |
3763 | #define mmDP_PIXEL_FORMAT 0x1cc1 |
3764 | #define mmDP0_DP_PIXEL_FORMAT 0x1cc1 |
3765 | #define mmDP1_DP_PIXEL_FORMAT 0x1fc1 |
3766 | #define mmDP2_DP_PIXEL_FORMAT 0x42c1 |
3767 | #define mmDP3_DP_PIXEL_FORMAT 0x45c1 |
3768 | #define mmDP4_DP_PIXEL_FORMAT 0x48c1 |
3769 | #define mmDP5_DP_PIXEL_FORMAT 0x4bc1 |
3770 | #define mmDP6_DP_PIXEL_FORMAT 0x4ec1 |
3771 | #define mmDP_MSA_COLORIMETRY 0x1cda |
3772 | #define mmDP0_DP_MSA_COLORIMETRY 0x1cda |
3773 | #define mmDP1_DP_MSA_COLORIMETRY 0x1fda |
3774 | #define mmDP2_DP_MSA_COLORIMETRY 0x42da |
3775 | #define mmDP3_DP_MSA_COLORIMETRY 0x45da |
3776 | #define mmDP4_DP_MSA_COLORIMETRY 0x48da |
3777 | #define mmDP5_DP_MSA_COLORIMETRY 0x4bda |
3778 | #define mmDP6_DP_MSA_COLORIMETRY 0x4eda |
3779 | #define mmDP_CONFIG 0x1cc2 |
3780 | #define mmDP0_DP_CONFIG 0x1cc2 |
3781 | #define mmDP1_DP_CONFIG 0x1fc2 |
3782 | #define mmDP2_DP_CONFIG 0x42c2 |
3783 | #define mmDP3_DP_CONFIG 0x45c2 |
3784 | #define mmDP4_DP_CONFIG 0x48c2 |
3785 | #define mmDP5_DP_CONFIG 0x4bc2 |
3786 | #define mmDP6_DP_CONFIG 0x4ec2 |
3787 | #define mmDP_VID_STREAM_CNTL 0x1cc3 |
3788 | #define mmDP0_DP_VID_STREAM_CNTL 0x1cc3 |
3789 | #define mmDP1_DP_VID_STREAM_CNTL 0x1fc3 |
3790 | #define mmDP2_DP_VID_STREAM_CNTL 0x42c3 |
3791 | #define mmDP3_DP_VID_STREAM_CNTL 0x45c3 |
3792 | #define mmDP4_DP_VID_STREAM_CNTL 0x48c3 |
3793 | #define mmDP5_DP_VID_STREAM_CNTL 0x4bc3 |
3794 | #define mmDP6_DP_VID_STREAM_CNTL 0x4ec3 |
3795 | #define mmDP_STEER_FIFO 0x1cc4 |
3796 | #define mmDP0_DP_STEER_FIFO 0x1cc4 |
3797 | #define mmDP1_DP_STEER_FIFO 0x1fc4 |
3798 | #define mmDP2_DP_STEER_FIFO 0x42c4 |
3799 | #define mmDP3_DP_STEER_FIFO 0x45c4 |
3800 | #define mmDP4_DP_STEER_FIFO 0x48c4 |
3801 | #define mmDP5_DP_STEER_FIFO 0x4bc4 |
3802 | #define mmDP6_DP_STEER_FIFO 0x4ec4 |
3803 | #define mmDP_MSA_MISC 0x1cc5 |
3804 | #define mmDP0_DP_MSA_MISC 0x1cc5 |
3805 | #define mmDP1_DP_MSA_MISC 0x1fc5 |
3806 | #define mmDP2_DP_MSA_MISC 0x42c5 |
3807 | #define mmDP3_DP_MSA_MISC 0x45c5 |
3808 | #define mmDP4_DP_MSA_MISC 0x48c5 |
3809 | #define mmDP5_DP_MSA_MISC 0x4bc5 |
3810 | #define mmDP6_DP_MSA_MISC 0x4ec5 |
3811 | #define mmDP_VID_TIMING 0x1cc9 |
3812 | #define mmDP0_DP_VID_TIMING 0x1cc9 |
3813 | #define mmDP1_DP_VID_TIMING 0x1fc9 |
3814 | #define mmDP2_DP_VID_TIMING 0x42c9 |
3815 | #define mmDP3_DP_VID_TIMING 0x45c9 |
3816 | #define mmDP4_DP_VID_TIMING 0x48c9 |
3817 | #define mmDP5_DP_VID_TIMING 0x4bc9 |
3818 | #define mmDP6_DP_VID_TIMING 0x4ec9 |
3819 | #define mmDP_VID_N 0x1cca |
3820 | #define mmDP0_DP_VID_N 0x1cca |
3821 | #define mmDP1_DP_VID_N 0x1fca |
3822 | #define mmDP2_DP_VID_N 0x42ca |
3823 | #define mmDP3_DP_VID_N 0x45ca |
3824 | #define mmDP4_DP_VID_N 0x48ca |
3825 | #define mmDP5_DP_VID_N 0x4bca |
3826 | #define mmDP6_DP_VID_N 0x4eca |
3827 | #define mmDP_VID_M 0x1ccb |
3828 | #define mmDP0_DP_VID_M 0x1ccb |
3829 | #define mmDP1_DP_VID_M 0x1fcb |
3830 | #define mmDP2_DP_VID_M 0x42cb |
3831 | #define mmDP3_DP_VID_M 0x45cb |
3832 | #define mmDP4_DP_VID_M 0x48cb |
3833 | #define mmDP5_DP_VID_M 0x4bcb |
3834 | #define mmDP6_DP_VID_M 0x4ecb |
3835 | #define mmDP_LINK_FRAMING_CNTL 0x1ccc |
3836 | #define mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc |
3837 | #define mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc |
3838 | #define mmDP2_DP_LINK_FRAMING_CNTL 0x42cc |
3839 | #define mmDP3_DP_LINK_FRAMING_CNTL 0x45cc |
3840 | #define mmDP4_DP_LINK_FRAMING_CNTL 0x48cc |
3841 | #define mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc |
3842 | #define mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc |
3843 | #define mmDP_HBR2_EYE_PATTERN 0x1cc8 |
3844 | #define mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8 |
3845 | #define mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8 |
3846 | #define mmDP2_DP_HBR2_EYE_PATTERN 0x42c8 |
3847 | #define mmDP3_DP_HBR2_EYE_PATTERN 0x45c8 |
3848 | #define mmDP4_DP_HBR2_EYE_PATTERN 0x48c8 |
3849 | #define mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8 |
3850 | #define mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8 |
3851 | #define mmDP_VID_MSA_VBID 0x1ccd |
3852 | #define mmDP0_DP_VID_MSA_VBID 0x1ccd |
3853 | #define mmDP1_DP_VID_MSA_VBID 0x1fcd |
3854 | #define mmDP2_DP_VID_MSA_VBID 0x42cd |
3855 | #define mmDP3_DP_VID_MSA_VBID 0x45cd |
3856 | #define mmDP4_DP_VID_MSA_VBID 0x48cd |
3857 | #define mmDP5_DP_VID_MSA_VBID 0x4bcd |
3858 | #define mmDP6_DP_VID_MSA_VBID 0x4ecd |
3859 | #define mmDP_VID_INTERRUPT_CNTL 0x1ccf |
3860 | #define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf |
3861 | #define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf |
3862 | #define mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf |
3863 | #define mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf |
3864 | #define mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf |
3865 | #define mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf |
3866 | #define mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf |
3867 | #define mmDP_DPHY_CNTL 0x1cd0 |
3868 | #define mmDP0_DP_DPHY_CNTL 0x1cd0 |
3869 | #define mmDP1_DP_DPHY_CNTL 0x1fd0 |
3870 | #define mmDP2_DP_DPHY_CNTL 0x42d0 |
3871 | #define mmDP3_DP_DPHY_CNTL 0x45d0 |
3872 | #define mmDP4_DP_DPHY_CNTL 0x48d0 |
3873 | #define mmDP5_DP_DPHY_CNTL 0x4bd0 |
3874 | #define mmDP6_DP_DPHY_CNTL 0x4ed0 |
3875 | #define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 |
3876 | #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 |
3877 | #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1 |
3878 | #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 |
3879 | #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 |
3880 | #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 |
3881 | #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1 |
3882 | #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1 |
3883 | #define mmDP_DPHY_SYM0 0x1cd2 |
3884 | #define mmDP0_DP_DPHY_SYM0 0x1cd2 |
3885 | #define mmDP1_DP_DPHY_SYM0 0x1fd2 |
3886 | #define mmDP2_DP_DPHY_SYM0 0x42d2 |
3887 | #define mmDP3_DP_DPHY_SYM0 0x45d2 |
3888 | #define mmDP4_DP_DPHY_SYM0 0x48d2 |
3889 | #define mmDP5_DP_DPHY_SYM0 0x4bd2 |
3890 | #define mmDP6_DP_DPHY_SYM0 0x4ed2 |
3891 | #define mmDP_DPHY_SYM1 0x1ce0 |
3892 | #define mmDP0_DP_DPHY_SYM1 0x1ce0 |
3893 | #define mmDP1_DP_DPHY_SYM1 0x1fe0 |
3894 | #define mmDP2_DP_DPHY_SYM1 0x42e0 |
3895 | #define mmDP3_DP_DPHY_SYM1 0x45e0 |
3896 | #define mmDP4_DP_DPHY_SYM1 0x48e0 |
3897 | #define mmDP5_DP_DPHY_SYM1 0x4be0 |
3898 | #define mmDP6_DP_DPHY_SYM1 0x4ee0 |
3899 | #define mmDP_DPHY_SYM2 0x1cdf |
3900 | #define mmDP0_DP_DPHY_SYM2 0x1cdf |
3901 | #define mmDP1_DP_DPHY_SYM2 0x1fdf |
3902 | #define mmDP2_DP_DPHY_SYM2 0x42df |
3903 | #define mmDP3_DP_DPHY_SYM2 0x45df |
3904 | #define mmDP4_DP_DPHY_SYM2 0x48df |
3905 | #define mmDP5_DP_DPHY_SYM2 0x4bdf |
3906 | #define mmDP6_DP_DPHY_SYM2 0x4edf |
3907 | #define mmDP_DPHY_8B10B_CNTL 0x1cd3 |
3908 | #define mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3 |
3909 | #define mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3 |
3910 | #define mmDP2_DP_DPHY_8B10B_CNTL 0x42d3 |
3911 | #define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 |
3912 | #define mmDP4_DP_DPHY_8B10B_CNTL 0x48d3 |
3913 | #define mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3 |
3914 | #define mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3 |
3915 | #define mmDP_DPHY_PRBS_CNTL 0x1cd4 |
3916 | #define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 |
3917 | #define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 |
3918 | #define mmDP2_DP_DPHY_PRBS_CNTL 0x42d4 |
3919 | #define mmDP3_DP_DPHY_PRBS_CNTL 0x45d4 |
3920 | #define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 |
3921 | #define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 |
3922 | #define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 |
3923 | #define mmDP_DPHY_SCRAM_CNTL 0x1cd5 |
3924 | #define mmDP0_DP_DPHY_SCRAM_CNTL 0x1cd5 |
3925 | #define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5 |
3926 | #define mmDP2_DP_DPHY_SCRAM_CNTL 0x42d5 |
3927 | #define mmDP3_DP_DPHY_SCRAM_CNTL 0x45d5 |
3928 | #define mmDP4_DP_DPHY_SCRAM_CNTL 0x48d5 |
3929 | #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4bd5 |
3930 | #define mmDP6_DP_DPHY_SCRAM_CNTL 0x4ed5 |
3931 | #define mmDP_DPHY_CRC_EN 0x1cd6 |
3932 | #define mmDP0_DP_DPHY_CRC_EN 0x1cd6 |
3933 | #define mmDP1_DP_DPHY_CRC_EN 0x1fd6 |
3934 | #define mmDP2_DP_DPHY_CRC_EN 0x42d6 |
3935 | #define mmDP3_DP_DPHY_CRC_EN 0x45d6 |
3936 | #define mmDP4_DP_DPHY_CRC_EN 0x48d6 |
3937 | #define mmDP5_DP_DPHY_CRC_EN 0x4bd6 |
3938 | #define mmDP6_DP_DPHY_CRC_EN 0x4ed6 |
3939 | #define mmDP_DPHY_CRC_CNTL 0x1cd7 |
3940 | #define mmDP0_DP_DPHY_CRC_CNTL 0x1cd7 |
3941 | #define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 |
3942 | #define mmDP2_DP_DPHY_CRC_CNTL 0x42d7 |
3943 | #define mmDP3_DP_DPHY_CRC_CNTL 0x45d7 |
3944 | #define mmDP4_DP_DPHY_CRC_CNTL 0x48d7 |
3945 | #define mmDP5_DP_DPHY_CRC_CNTL 0x4bd7 |
3946 | #define mmDP6_DP_DPHY_CRC_CNTL 0x4ed7 |
3947 | #define mmDP_DPHY_CRC_RESULT 0x1cd8 |
3948 | #define mmDP0_DP_DPHY_CRC_RESULT 0x1cd8 |
3949 | #define mmDP1_DP_DPHY_CRC_RESULT 0x1fd8 |
3950 | #define mmDP2_DP_DPHY_CRC_RESULT 0x42d8 |
3951 | #define mmDP3_DP_DPHY_CRC_RESULT 0x45d8 |
3952 | #define mmDP4_DP_DPHY_CRC_RESULT 0x48d8 |
3953 | #define mmDP5_DP_DPHY_CRC_RESULT 0x4bd8 |
3954 | #define mmDP6_DP_DPHY_CRC_RESULT 0x4ed8 |
3955 | #define mmDP_DPHY_CRC_MST_CNTL 0x1cc6 |
3956 | #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6 |
3957 | #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6 |
3958 | #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6 |
3959 | #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6 |
3960 | #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6 |
3961 | #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6 |
3962 | #define mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6 |
3963 | #define mmDP_DPHY_CRC_MST_STATUS 0x1cc7 |
3964 | #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7 |
3965 | #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7 |
3966 | #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7 |
3967 | #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7 |
3968 | #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7 |
3969 | #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7 |
3970 | #define mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7 |
3971 | #define mmDP_DPHY_FAST_TRAINING 0x1cce |
3972 | #define mmDP0_DP_DPHY_FAST_TRAINING 0x1cce |
3973 | #define mmDP1_DP_DPHY_FAST_TRAINING 0x1fce |
3974 | #define mmDP2_DP_DPHY_FAST_TRAINING 0x42ce |
3975 | #define mmDP3_DP_DPHY_FAST_TRAINING 0x45ce |
3976 | #define mmDP4_DP_DPHY_FAST_TRAINING 0x48ce |
3977 | #define mmDP5_DP_DPHY_FAST_TRAINING 0x4bce |
3978 | #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ece |
3979 | #define mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9 |
3980 | #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9 |
3981 | #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9 |
3982 | #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9 |
3983 | #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9 |
3984 | #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9 |
3985 | #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9 |
3986 | #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9 |
3987 | #define mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea |
3988 | #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea |
3989 | #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea |
3990 | #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea |
3991 | #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea |
3992 | #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea |
3993 | #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea |
3994 | #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea |
3995 | #define mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb |
3996 | #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb |
3997 | #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb |
3998 | #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb |
3999 | #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb |
4000 | #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb |
4001 | #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb |
4002 | #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb |
4003 | #define mmDP_SEC_CNTL 0x1ca0 |
4004 | #define mmDP0_DP_SEC_CNTL 0x1ca0 |
4005 | #define mmDP1_DP_SEC_CNTL 0x1fa0 |
4006 | #define mmDP2_DP_SEC_CNTL 0x42a0 |
4007 | #define mmDP3_DP_SEC_CNTL 0x45a0 |
4008 | #define mmDP4_DP_SEC_CNTL 0x48a0 |
4009 | #define mmDP5_DP_SEC_CNTL 0x4ba0 |
4010 | #define mmDP6_DP_SEC_CNTL 0x4ea0 |
4011 | #define mmDP_SEC_CNTL1 0x1cab |
4012 | #define mmDP0_DP_SEC_CNTL1 0x1cab |
4013 | #define mmDP1_DP_SEC_CNTL1 0x1fab |
4014 | #define mmDP2_DP_SEC_CNTL1 0x42ab |
4015 | #define mmDP3_DP_SEC_CNTL1 0x45ab |
4016 | #define mmDP4_DP_SEC_CNTL1 0x48ab |
4017 | #define mmDP5_DP_SEC_CNTL1 0x4bab |
4018 | #define mmDP6_DP_SEC_CNTL1 0x4eab |
4019 | #define mmDP_SEC_FRAMING1 0x1ca1 |
4020 | #define mmDP0_DP_SEC_FRAMING1 0x1ca1 |
4021 | #define mmDP1_DP_SEC_FRAMING1 0x1fa1 |
4022 | #define mmDP2_DP_SEC_FRAMING1 0x42a1 |
4023 | #define mmDP3_DP_SEC_FRAMING1 0x45a1 |
4024 | #define mmDP4_DP_SEC_FRAMING1 0x48a1 |
4025 | #define mmDP5_DP_SEC_FRAMING1 0x4ba1 |
4026 | #define mmDP6_DP_SEC_FRAMING1 0x4ea1 |
4027 | #define mmDP_SEC_FRAMING2 0x1ca2 |
4028 | #define mmDP0_DP_SEC_FRAMING2 0x1ca2 |
4029 | #define mmDP1_DP_SEC_FRAMING2 0x1fa2 |
4030 | #define mmDP2_DP_SEC_FRAMING2 0x42a2 |
4031 | #define mmDP3_DP_SEC_FRAMING2 0x45a2 |
4032 | #define mmDP4_DP_SEC_FRAMING2 0x48a2 |
4033 | #define mmDP5_DP_SEC_FRAMING2 0x4ba2 |
4034 | #define mmDP6_DP_SEC_FRAMING2 0x4ea2 |
4035 | #define mmDP_SEC_FRAMING3 0x1ca3 |
4036 | #define mmDP0_DP_SEC_FRAMING3 0x1ca3 |
4037 | #define mmDP1_DP_SEC_FRAMING3 0x1fa3 |
4038 | #define mmDP2_DP_SEC_FRAMING3 0x42a3 |
4039 | #define mmDP3_DP_SEC_FRAMING3 0x45a3 |
4040 | #define mmDP4_DP_SEC_FRAMING3 0x48a3 |
4041 | #define mmDP5_DP_SEC_FRAMING3 0x4ba3 |
4042 | #define mmDP6_DP_SEC_FRAMING3 0x4ea3 |
4043 | #define mmDP_SEC_FRAMING4 0x1ca4 |
4044 | #define mmDP0_DP_SEC_FRAMING4 0x1ca4 |
4045 | #define mmDP1_DP_SEC_FRAMING4 0x1fa4 |
4046 | #define mmDP2_DP_SEC_FRAMING4 0x42a4 |
4047 | #define mmDP3_DP_SEC_FRAMING4 0x45a4 |
4048 | #define mmDP4_DP_SEC_FRAMING4 0x48a4 |
4049 | #define mmDP5_DP_SEC_FRAMING4 0x4ba4 |
4050 | #define mmDP6_DP_SEC_FRAMING4 0x4ea4 |
4051 | #define mmDP_SEC_AUD_N 0x1ca5 |
4052 | #define mmDP0_DP_SEC_AUD_N 0x1ca5 |
4053 | #define mmDP1_DP_SEC_AUD_N 0x1fa5 |
4054 | #define mmDP2_DP_SEC_AUD_N 0x42a5 |
4055 | #define mmDP3_DP_SEC_AUD_N 0x45a5 |
4056 | #define mmDP4_DP_SEC_AUD_N 0x48a5 |
4057 | #define mmDP5_DP_SEC_AUD_N 0x4ba5 |
4058 | #define mmDP6_DP_SEC_AUD_N 0x4ea5 |
4059 | #define mmDP_SEC_AUD_N_READBACK 0x1ca6 |
4060 | #define mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6 |
4061 | #define mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6 |
4062 | #define mmDP2_DP_SEC_AUD_N_READBACK 0x42a6 |
4063 | #define mmDP3_DP_SEC_AUD_N_READBACK 0x45a6 |
4064 | #define mmDP4_DP_SEC_AUD_N_READBACK 0x48a6 |
4065 | #define mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6 |
4066 | #define mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6 |
4067 | #define mmDP_SEC_AUD_M 0x1ca7 |
4068 | #define mmDP0_DP_SEC_AUD_M 0x1ca7 |
4069 | #define mmDP1_DP_SEC_AUD_M 0x1fa7 |
4070 | #define mmDP2_DP_SEC_AUD_M 0x42a7 |
4071 | #define mmDP3_DP_SEC_AUD_M 0x45a7 |
4072 | #define mmDP4_DP_SEC_AUD_M 0x48a7 |
4073 | #define mmDP5_DP_SEC_AUD_M 0x4ba7 |
4074 | #define mmDP6_DP_SEC_AUD_M 0x4ea7 |
4075 | #define mmDP_SEC_AUD_M_READBACK 0x1ca8 |
4076 | #define mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8 |
4077 | #define mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8 |
4078 | #define mmDP2_DP_SEC_AUD_M_READBACK 0x42a8 |
4079 | #define mmDP3_DP_SEC_AUD_M_READBACK 0x45a8 |
4080 | #define mmDP4_DP_SEC_AUD_M_READBACK 0x48a8 |
4081 | #define mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8 |
4082 | #define mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8 |
4083 | #define mmDP_SEC_TIMESTAMP 0x1ca9 |
4084 | #define mmDP0_DP_SEC_TIMESTAMP 0x1ca9 |
4085 | #define mmDP1_DP_SEC_TIMESTAMP 0x1fa9 |
4086 | #define mmDP2_DP_SEC_TIMESTAMP 0x42a9 |
4087 | #define mmDP3_DP_SEC_TIMESTAMP 0x45a9 |
4088 | #define mmDP4_DP_SEC_TIMESTAMP 0x48a9 |
4089 | #define mmDP5_DP_SEC_TIMESTAMP 0x4ba9 |
4090 | #define mmDP6_DP_SEC_TIMESTAMP 0x4ea9 |
4091 | #define mmDP_SEC_PACKET_CNTL 0x1caa |
4092 | #define mmDP0_DP_SEC_PACKET_CNTL 0x1caa |
4093 | #define mmDP1_DP_SEC_PACKET_CNTL 0x1faa |
4094 | #define mmDP2_DP_SEC_PACKET_CNTL 0x42aa |
4095 | #define mmDP3_DP_SEC_PACKET_CNTL 0x45aa |
4096 | #define mmDP4_DP_SEC_PACKET_CNTL 0x48aa |
4097 | #define mmDP5_DP_SEC_PACKET_CNTL 0x4baa |
4098 | #define mmDP6_DP_SEC_PACKET_CNTL 0x4eaa |
4099 | #define mmDP_MSE_RATE_CNTL 0x1ce1 |
4100 | #define mmDP0_DP_MSE_RATE_CNTL 0x1ce1 |
4101 | #define mmDP1_DP_MSE_RATE_CNTL 0x1fe1 |
4102 | #define mmDP2_DP_MSE_RATE_CNTL 0x42e1 |
4103 | #define mmDP3_DP_MSE_RATE_CNTL 0x45e1 |
4104 | #define mmDP4_DP_MSE_RATE_CNTL 0x48e1 |
4105 | #define mmDP5_DP_MSE_RATE_CNTL 0x4be1 |
4106 | #define mmDP6_DP_MSE_RATE_CNTL 0x4ee1 |
4107 | #define mmDP_MSE_RATE_UPDATE 0x1ce3 |
4108 | #define mmDP0_DP_MSE_RATE_UPDATE 0x1ce3 |
4109 | #define mmDP1_DP_MSE_RATE_UPDATE 0x1fe3 |
4110 | #define mmDP2_DP_MSE_RATE_UPDATE 0x42e3 |
4111 | #define mmDP3_DP_MSE_RATE_UPDATE 0x45e3 |
4112 | #define mmDP4_DP_MSE_RATE_UPDATE 0x48e3 |
4113 | #define mmDP5_DP_MSE_RATE_UPDATE 0x4be3 |
4114 | #define mmDP6_DP_MSE_RATE_UPDATE 0x4ee3 |
4115 | #define mmDP_MSE_SAT0 0x1ce4 |
4116 | #define mmDP0_DP_MSE_SAT0 0x1ce4 |
4117 | #define mmDP1_DP_MSE_SAT0 0x1fe4 |
4118 | #define mmDP2_DP_MSE_SAT0 0x42e4 |
4119 | #define mmDP3_DP_MSE_SAT0 0x45e4 |
4120 | #define mmDP4_DP_MSE_SAT0 0x48e4 |
4121 | #define mmDP5_DP_MSE_SAT0 0x4be4 |
4122 | #define mmDP6_DP_MSE_SAT0 0x4ee4 |
4123 | #define mmDP_MSE_SAT1 0x1ce5 |
4124 | #define mmDP0_DP_MSE_SAT1 0x1ce5 |
4125 | #define mmDP1_DP_MSE_SAT1 0x1fe5 |
4126 | #define mmDP2_DP_MSE_SAT1 0x42e5 |
4127 | #define mmDP3_DP_MSE_SAT1 0x45e5 |
4128 | #define mmDP4_DP_MSE_SAT1 0x48e5 |
4129 | #define mmDP5_DP_MSE_SAT1 0x4be5 |
4130 | #define mmDP6_DP_MSE_SAT1 0x4ee5 |
4131 | #define mmDP_MSE_SAT2 0x1ce6 |
4132 | #define mmDP0_DP_MSE_SAT2 0x1ce6 |
4133 | #define mmDP1_DP_MSE_SAT2 0x1fe6 |
4134 | #define mmDP2_DP_MSE_SAT2 0x42e6 |
4135 | #define mmDP3_DP_MSE_SAT2 0x45e6 |
4136 | #define mmDP4_DP_MSE_SAT2 0x48e6 |
4137 | #define mmDP5_DP_MSE_SAT2 0x4be6 |
4138 | #define mmDP6_DP_MSE_SAT2 0x4ee6 |
4139 | #define mmDP_MSE_SAT_UPDATE 0x1ce7 |
4140 | #define mmDP0_DP_MSE_SAT_UPDATE 0x1ce7 |
4141 | #define mmDP1_DP_MSE_SAT_UPDATE 0x1fe7 |
4142 | #define mmDP2_DP_MSE_SAT_UPDATE 0x42e7 |
4143 | #define mmDP3_DP_MSE_SAT_UPDATE 0x45e7 |
4144 | #define mmDP4_DP_MSE_SAT_UPDATE 0x48e7 |
4145 | #define mmDP5_DP_MSE_SAT_UPDATE 0x4be7 |
4146 | #define mmDP6_DP_MSE_SAT_UPDATE 0x4ee7 |
4147 | #define mmDP_MSE_LINK_TIMING 0x1ce8 |
4148 | #define mmDP0_DP_MSE_LINK_TIMING 0x1ce8 |
4149 | #define mmDP1_DP_MSE_LINK_TIMING 0x1fe8 |
4150 | #define mmDP2_DP_MSE_LINK_TIMING 0x42e8 |
4151 | #define mmDP3_DP_MSE_LINK_TIMING 0x45e8 |
4152 | #define mmDP4_DP_MSE_LINK_TIMING 0x48e8 |
4153 | #define mmDP5_DP_MSE_LINK_TIMING 0x4be8 |
4154 | #define mmDP6_DP_MSE_LINK_TIMING 0x4ee8 |
4155 | #define mmDP_MSE_MISC_CNTL 0x1cdb |
4156 | #define mmDP0_DP_MSE_MISC_CNTL 0x1cdb |
4157 | #define mmDP1_DP_MSE_MISC_CNTL 0x1fdb |
4158 | #define mmDP2_DP_MSE_MISC_CNTL 0x42db |
4159 | #define mmDP3_DP_MSE_MISC_CNTL 0x45db |
4160 | #define mmDP4_DP_MSE_MISC_CNTL 0x48db |
4161 | #define mmDP5_DP_MSE_MISC_CNTL 0x4bdb |
4162 | #define mmDP6_DP_MSE_MISC_CNTL 0x4edb |
4163 | #define mmDP_TEST_DEBUG_INDEX 0x1cfc |
4164 | #define mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc |
4165 | #define mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc |
4166 | #define mmDP2_DP_TEST_DEBUG_INDEX 0x42fc |
4167 | #define mmDP3_DP_TEST_DEBUG_INDEX 0x45fc |
4168 | #define mmDP4_DP_TEST_DEBUG_INDEX 0x48fc |
4169 | #define mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc |
4170 | #define mmDP6_DP_TEST_DEBUG_INDEX 0x4efc |
4171 | #define mmDP_TEST_DEBUG_DATA 0x1cfd |
4172 | #define mmDP0_DP_TEST_DEBUG_DATA 0x1cfd |
4173 | #define mmDP1_DP_TEST_DEBUG_DATA 0x1ffd |
4174 | #define mmDP2_DP_TEST_DEBUG_DATA 0x42fd |
4175 | #define mmDP3_DP_TEST_DEBUG_DATA 0x45fd |
4176 | #define mmDP4_DP_TEST_DEBUG_DATA 0x48fd |
4177 | #define mmDP5_DP_TEST_DEBUG_DATA 0x4bfd |
4178 | #define mmDP6_DP_TEST_DEBUG_DATA 0x4efd |
4179 | #define mmAUX_CONTROL 0x1880 |
4180 | #define mmDP_AUX0_AUX_CONTROL 0x1880 |
4181 | #define mmDP_AUX1_AUX_CONTROL 0x1894 |
4182 | #define mmDP_AUX2_AUX_CONTROL 0x18a8 |
4183 | #define mmDP_AUX3_AUX_CONTROL 0x18c0 |
4184 | #define mmDP_AUX4_AUX_CONTROL 0x18d4 |
4185 | #define mmDP_AUX5_AUX_CONTROL 0x18e8 |
4186 | #define mmAUX_SW_CONTROL 0x1881 |
4187 | #define mmDP_AUX0_AUX_SW_CONTROL 0x1881 |
4188 | #define mmDP_AUX1_AUX_SW_CONTROL 0x1895 |
4189 | #define mmDP_AUX2_AUX_SW_CONTROL 0x18a9 |
4190 | #define mmDP_AUX3_AUX_SW_CONTROL 0x18c1 |
4191 | #define mmDP_AUX4_AUX_SW_CONTROL 0x18d5 |
4192 | #define mmDP_AUX5_AUX_SW_CONTROL 0x18e9 |
4193 | #define mmAUX_ARB_CONTROL 0x1882 |
4194 | #define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 |
4195 | #define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 |
4196 | #define mmDP_AUX2_AUX_ARB_CONTROL 0x18aa |
4197 | #define mmDP_AUX3_AUX_ARB_CONTROL 0x18c2 |
4198 | #define mmDP_AUX4_AUX_ARB_CONTROL 0x18d6 |
4199 | #define mmDP_AUX5_AUX_ARB_CONTROL 0x18ea |
4200 | #define mmAUX_INTERRUPT_CONTROL 0x1883 |
4201 | #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 |
4202 | #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 |
4203 | #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab |
4204 | #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3 |
4205 | #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7 |
4206 | #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb |
4207 | #define mmAUX_SW_STATUS 0x1884 |
4208 | #define mmDP_AUX0_AUX_SW_STATUS 0x1884 |
4209 | #define mmDP_AUX1_AUX_SW_STATUS 0x1898 |
4210 | #define mmDP_AUX2_AUX_SW_STATUS 0x18ac |
4211 | #define mmDP_AUX3_AUX_SW_STATUS 0x18c4 |
4212 | #define mmDP_AUX4_AUX_SW_STATUS 0x18d8 |
4213 | #define mmDP_AUX5_AUX_SW_STATUS 0x18ec |
4214 | #define mmAUX_LS_STATUS 0x1885 |
4215 | #define mmDP_AUX0_AUX_LS_STATUS 0x1885 |
4216 | #define mmDP_AUX1_AUX_LS_STATUS 0x1899 |
4217 | #define mmDP_AUX2_AUX_LS_STATUS 0x18ad |
4218 | #define mmDP_AUX3_AUX_LS_STATUS 0x18c5 |
4219 | #define mmDP_AUX4_AUX_LS_STATUS 0x18d9 |
4220 | #define mmDP_AUX5_AUX_LS_STATUS 0x18ed |
4221 | #define mmAUX_SW_DATA 0x1886 |
4222 | #define mmDP_AUX0_AUX_SW_DATA 0x1886 |
4223 | #define mmDP_AUX1_AUX_SW_DATA 0x189a |
4224 | #define mmDP_AUX2_AUX_SW_DATA 0x18ae |
4225 | #define mmDP_AUX3_AUX_SW_DATA 0x18c6 |
4226 | #define mmDP_AUX4_AUX_SW_DATA 0x18da |
4227 | #define mmDP_AUX5_AUX_SW_DATA 0x18ee |
4228 | #define mmAUX_LS_DATA 0x1887 |
4229 | #define mmDP_AUX0_AUX_LS_DATA 0x1887 |
4230 | #define mmDP_AUX1_AUX_LS_DATA 0x189b |
4231 | #define mmDP_AUX2_AUX_LS_DATA 0x18af |
4232 | #define mmDP_AUX3_AUX_LS_DATA 0x18c7 |
4233 | #define mmDP_AUX4_AUX_LS_DATA 0x18db |
4234 | #define mmDP_AUX5_AUX_LS_DATA 0x18ef |
4235 | #define mmAUX_DPHY_TX_REF_CONTROL 0x1888 |
4236 | #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 |
4237 | #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c |
4238 | #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0 |
4239 | #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8 |
4240 | #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc |
4241 | #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0 |
4242 | #define mmAUX_DPHY_TX_CONTROL 0x1889 |
4243 | #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 |
4244 | #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d |
4245 | #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1 |
4246 | #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9 |
4247 | #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd |
4248 | #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1 |
4249 | #define mmAUX_DPHY_RX_CONTROL0 0x188a |
4250 | #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a |
4251 | #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e |
4252 | #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2 |
4253 | #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca |
4254 | #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de |
4255 | #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2 |
4256 | #define mmAUX_DPHY_RX_CONTROL1 0x188b |
4257 | #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b |
4258 | #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f |
4259 | #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3 |
4260 | #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb |
4261 | #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df |
4262 | #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3 |
4263 | #define mmAUX_DPHY_TX_STATUS 0x188c |
4264 | #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c |
4265 | #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0 |
4266 | #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4 |
4267 | #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc |
4268 | #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0 |
4269 | #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4 |
4270 | #define mmAUX_DPHY_RX_STATUS 0x188d |
4271 | #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d |
4272 | #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1 |
4273 | #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5 |
4274 | #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd |
4275 | #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1 |
4276 | #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5 |
4277 | #define mmAUX_GTC_SYNC_CONTROL 0x188e |
4278 | #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e |
4279 | #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2 |
4280 | #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6 |
4281 | #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce |
4282 | #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2 |
4283 | #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6 |
4284 | #define mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f |
4285 | #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f |
4286 | #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3 |
4287 | #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7 |
4288 | #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf |
4289 | #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3 |
4290 | #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7 |
4291 | #define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 |
4292 | #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 |
4293 | #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4 |
4294 | #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8 |
4295 | #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0 |
4296 | #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4 |
4297 | #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8 |
4298 | #define mmAUX_GTC_SYNC_STATUS 0x1891 |
4299 | #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891 |
4300 | #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5 |
4301 | #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9 |
4302 | #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1 |
4303 | #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5 |
4304 | #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9 |
4305 | #define mmAUX_GTC_SYNC_DATA 0x1892 |
4306 | #define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892 |
4307 | #define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6 |
4308 | #define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba |
4309 | #define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2 |
4310 | #define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6 |
4311 | #define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa |
4312 | #define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 |
4313 | #define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 |
4314 | #define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7 |
4315 | #define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb |
4316 | #define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3 |
4317 | #define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7 |
4318 | #define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb |
4319 | #define mmDVO_ENABLE 0x1858 |
4320 | #define mmDVO_SOURCE_SELECT 0x1859 |
4321 | #define mmDVO_OUTPUT 0x185a |
4322 | #define mmDVO_CONTROL 0x185b |
4323 | #define mmDVO_CRC_EN 0x185c |
4324 | #define mmDVO_CRC2_SIG_MASK 0x185d |
4325 | #define mmDVO_CRC2_SIG_RESULT 0x185e |
4326 | #define mmDVO_FIFO_ERROR_STATUS 0x185f |
4327 | #define mmFBC_CNTL 0x16d0 |
4328 | #define mmFBC_IDLE_MASK 0x16d1 |
4329 | #define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2 |
4330 | #define mmFBC_START_STOP_DELAY 0x16d3 |
4331 | #define mmFBC_COMP_CNTL 0x16d4 |
4332 | #define mmFBC_COMP_MODE 0x16d5 |
4333 | #define mmFBC_DEBUG0 0x16d6 |
4334 | #define mmFBC_DEBUG1 0x16d7 |
4335 | #define mmFBC_DEBUG2 0x16d8 |
4336 | #define mmFBC_IND_LUT0 0x16d9 |
4337 | #define mmFBC_IND_LUT1 0x16da |
4338 | #define mmFBC_IND_LUT2 0x16db |
4339 | #define mmFBC_IND_LUT3 0x16dc |
4340 | #define mmFBC_IND_LUT4 0x16dd |
4341 | #define mmFBC_IND_LUT5 0x16de |
4342 | #define mmFBC_IND_LUT6 0x16df |
4343 | #define mmFBC_IND_LUT7 0x16e0 |
4344 | #define mmFBC_IND_LUT8 0x16e1 |
4345 | #define mmFBC_IND_LUT9 0x16e2 |
4346 | #define mmFBC_IND_LUT10 0x16e3 |
4347 | #define mmFBC_IND_LUT11 0x16e4 |
4348 | #define mmFBC_IND_LUT12 0x16e5 |
4349 | #define mmFBC_IND_LUT13 0x16e6 |
4350 | #define mmFBC_IND_LUT14 0x16e7 |
4351 | #define mmFBC_IND_LUT15 0x16e8 |
4352 | #define mmFBC_CSM_REGION_OFFSET_01 0x16e9 |
4353 | #define mmFBC_CSM_REGION_OFFSET_23 0x16ea |
4354 | #define mmFBC_CLIENT_REGION_MASK 0x16eb |
4355 | #define mmFBC_DEBUG_COMP 0x16ec |
4356 | #define mmFBC_DEBUG_CSR 0x16ed |
4357 | #define mmFBC_DEBUG_CSR_RDATA 0x16ee |
4358 | #define mmFBC_DEBUG_CSR_WDATA 0x16ef |
4359 | #define mmFBC_DEBUG_CSR_RDATA_HI 0x16f6 |
4360 | #define mmFBC_DEBUG_CSR_WDATA_HI 0x16f7 |
4361 | #define mmFBC_MISC 0x16f0 |
4362 | #define mmFBC_STATUS 0x16f1 |
4363 | #define mmFBC_TEST_DEBUG_INDEX 0x16f4 |
4364 | #define mmFBC_TEST_DEBUG_DATA 0x16f5 |
4365 | #define mmFMT_CLAMP_COMPONENT_R 0x1be8 |
4366 | #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 |
4367 | #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8 |
4368 | #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8 |
4369 | #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8 |
4370 | #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8 |
4371 | #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8 |
4372 | #define mmFMT_CLAMP_COMPONENT_G 0x1be9 |
4373 | #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 |
4374 | #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9 |
4375 | #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9 |
4376 | #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9 |
4377 | #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9 |
4378 | #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9 |
4379 | #define mmFMT_CLAMP_COMPONENT_B 0x1bea |
4380 | #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea |
4381 | #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea |
4382 | #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea |
4383 | #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea |
4384 | #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea |
4385 | #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea |
4386 | #define mmFMT_DYNAMIC_EXP_CNTL 0x1bed |
4387 | #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed |
4388 | #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed |
4389 | #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed |
4390 | #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed |
4391 | #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed |
4392 | #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed |
4393 | #define mmFMT_CONTROL 0x1bee |
4394 | #define mmFMT0_FMT_CONTROL 0x1bee |
4395 | #define mmFMT1_FMT_CONTROL 0x1eee |
4396 | #define mmFMT2_FMT_CONTROL 0x41ee |
4397 | #define mmFMT3_FMT_CONTROL 0x44ee |
4398 | #define mmFMT4_FMT_CONTROL 0x47ee |
4399 | #define mmFMT5_FMT_CONTROL 0x4aee |
4400 | #define mmFMT_FORCE_OUTPUT_CNTL 0x1bef |
4401 | #define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef |
4402 | #define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef |
4403 | #define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef |
4404 | #define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef |
4405 | #define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef |
4406 | #define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef |
4407 | #define mmFMT_FORCE_DATA_0_1 0x1bf0 |
4408 | #define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 |
4409 | #define mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0 |
4410 | #define mmFMT2_FMT_FORCE_DATA_0_1 0x41f0 |
4411 | #define mmFMT3_FMT_FORCE_DATA_0_1 0x44f0 |
4412 | #define mmFMT4_FMT_FORCE_DATA_0_1 0x47f0 |
4413 | #define mmFMT5_FMT_FORCE_DATA_0_1 0x4af0 |
4414 | #define mmFMT_FORCE_DATA_2_3 0x1bf1 |
4415 | #define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 |
4416 | #define mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1 |
4417 | #define mmFMT2_FMT_FORCE_DATA_2_3 0x41f1 |
4418 | #define mmFMT3_FMT_FORCE_DATA_2_3 0x44f1 |
4419 | #define mmFMT4_FMT_FORCE_DATA_2_3 0x47f1 |
4420 | #define mmFMT5_FMT_FORCE_DATA_2_3 0x4af1 |
4421 | #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 |
4422 | #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 |
4423 | #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2 |
4424 | #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2 |
4425 | #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2 |
4426 | #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2 |
4427 | #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2 |
4428 | #define mmFMT_DITHER_RAND_R_SEED 0x1bf3 |
4429 | #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 |
4430 | #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3 |
4431 | #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3 |
4432 | #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3 |
4433 | #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3 |
4434 | #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3 |
4435 | #define mmFMT_DITHER_RAND_G_SEED 0x1bf4 |
4436 | #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 |
4437 | #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4 |
4438 | #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4 |
4439 | #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4 |
4440 | #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4 |
4441 | #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4 |
4442 | #define mmFMT_DITHER_RAND_B_SEED 0x1bf5 |
4443 | #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 |
4444 | #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5 |
4445 | #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5 |
4446 | #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5 |
4447 | #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5 |
4448 | #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5 |
4449 | #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 |
4450 | #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 |
4451 | #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6 |
4452 | #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 |
4453 | #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6 |
4454 | #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6 |
4455 | #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6 |
4456 | #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 |
4457 | #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 |
4458 | #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7 |
4459 | #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 |
4460 | #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7 |
4461 | #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7 |
4462 | #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7 |
4463 | #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 |
4464 | #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 |
4465 | #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8 |
4466 | #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 |
4467 | #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8 |
4468 | #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8 |
4469 | #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8 |
4470 | #define mmFMT_CLAMP_CNTL 0x1bf9 |
4471 | #define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 |
4472 | #define mmFMT1_FMT_CLAMP_CNTL 0x1ef9 |
4473 | #define mmFMT2_FMT_CLAMP_CNTL 0x41f9 |
4474 | #define mmFMT3_FMT_CLAMP_CNTL 0x44f9 |
4475 | #define mmFMT4_FMT_CLAMP_CNTL 0x47f9 |
4476 | #define mmFMT5_FMT_CLAMP_CNTL 0x4af9 |
4477 | #define mmFMT_CRC_CNTL 0x1bfa |
4478 | #define mmFMT0_FMT_CRC_CNTL 0x1bfa |
4479 | #define mmFMT1_FMT_CRC_CNTL 0x1efa |
4480 | #define mmFMT2_FMT_CRC_CNTL 0x41fa |
4481 | #define mmFMT3_FMT_CRC_CNTL 0x44fa |
4482 | #define mmFMT4_FMT_CRC_CNTL 0x47fa |
4483 | #define mmFMT5_FMT_CRC_CNTL 0x4afa |
4484 | #define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb |
4485 | #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb |
4486 | #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb |
4487 | #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb |
4488 | #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb |
4489 | #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb |
4490 | #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb |
4491 | #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc |
4492 | #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc |
4493 | #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc |
4494 | #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc |
4495 | #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc |
4496 | #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc |
4497 | #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc |
4498 | #define mmFMT_CRC_SIG_RED_GREEN 0x1bfd |
4499 | #define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd |
4500 | #define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd |
4501 | #define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd |
4502 | #define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd |
4503 | #define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd |
4504 | #define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd |
4505 | #define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe |
4506 | #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe |
4507 | #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe |
4508 | #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe |
4509 | #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe |
4510 | #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe |
4511 | #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe |
4512 | #define mmFMT_DEBUG_CNTL 0x1bff |
4513 | #define mmFMT0_FMT_DEBUG_CNTL 0x1bff |
4514 | #define mmFMT1_FMT_DEBUG_CNTL 0x1eff |
4515 | #define mmFMT2_FMT_DEBUG_CNTL 0x41ff |
4516 | #define mmFMT3_FMT_DEBUG_CNTL 0x44ff |
4517 | #define mmFMT4_FMT_DEBUG_CNTL 0x47ff |
4518 | #define mmFMT5_FMT_DEBUG_CNTL 0x4aff |
4519 | #define mmFMT_TEST_DEBUG_INDEX 0x1beb |
4520 | #define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb |
4521 | #define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb |
4522 | #define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb |
4523 | #define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb |
4524 | #define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb |
4525 | #define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb |
4526 | #define mmFMT_TEST_DEBUG_DATA 0x1bec |
4527 | #define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec |
4528 | #define mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec |
4529 | #define mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec |
4530 | #define mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec |
4531 | #define mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec |
4532 | #define mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec |
4533 | #define ixFMT_DEBUG0 0x1 |
4534 | #define ixFMT_DEBUG1 0x2 |
4535 | #define ixFMT_DEBUG2 0x3 |
4536 | #define ixFMT_DEBUG_ID 0x0 |
4537 | #define mmLB_DATA_FORMAT 0x1ac0 |
4538 | #define mmLB0_LB_DATA_FORMAT 0x1ac0 |
4539 | #define mmLB1_LB_DATA_FORMAT 0x1dc0 |
4540 | #define mmLB2_LB_DATA_FORMAT 0x40c0 |
4541 | #define mmLB3_LB_DATA_FORMAT 0x43c0 |
4542 | #define mmLB4_LB_DATA_FORMAT 0x46c0 |
4543 | #define mmLB5_LB_DATA_FORMAT 0x49c0 |
4544 | #define mmLB_MEMORY_CTRL 0x1ac1 |
4545 | #define mmLB0_LB_MEMORY_CTRL 0x1ac1 |
4546 | #define mmLB1_LB_MEMORY_CTRL 0x1dc1 |
4547 | #define mmLB2_LB_MEMORY_CTRL 0x40c1 |
4548 | #define mmLB3_LB_MEMORY_CTRL 0x43c1 |
4549 | #define mmLB4_LB_MEMORY_CTRL 0x46c1 |
4550 | #define mmLB5_LB_MEMORY_CTRL 0x49c1 |
4551 | #define mmLB_MEMORY_SIZE_STATUS 0x1ac2 |
4552 | #define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 |
4553 | #define mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2 |
4554 | #define mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2 |
4555 | #define mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2 |
4556 | #define mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2 |
4557 | #define mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2 |
4558 | #define mmLB_DESKTOP_HEIGHT 0x1ac3 |
4559 | #define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 |
4560 | #define mmLB1_LB_DESKTOP_HEIGHT 0x1dc3 |
4561 | #define mmLB2_LB_DESKTOP_HEIGHT 0x40c3 |
4562 | #define mmLB3_LB_DESKTOP_HEIGHT 0x43c3 |
4563 | #define mmLB4_LB_DESKTOP_HEIGHT 0x46c3 |
4564 | #define mmLB5_LB_DESKTOP_HEIGHT 0x49c3 |
4565 | #define mmLB_VLINE_START_END 0x1ac4 |
4566 | #define mmLB0_LB_VLINE_START_END 0x1ac4 |
4567 | #define mmLB1_LB_VLINE_START_END 0x1dc4 |
4568 | #define mmLB2_LB_VLINE_START_END 0x40c4 |
4569 | #define mmLB3_LB_VLINE_START_END 0x43c4 |
4570 | #define mmLB4_LB_VLINE_START_END 0x46c4 |
4571 | #define mmLB5_LB_VLINE_START_END 0x49c4 |
4572 | #define mmLB_VLINE2_START_END 0x1ac5 |
4573 | #define mmLB0_LB_VLINE2_START_END 0x1ac5 |
4574 | #define mmLB1_LB_VLINE2_START_END 0x1dc5 |
4575 | #define mmLB2_LB_VLINE2_START_END 0x40c5 |
4576 | #define mmLB3_LB_VLINE2_START_END 0x43c5 |
4577 | #define mmLB4_LB_VLINE2_START_END 0x46c5 |
4578 | #define mmLB5_LB_VLINE2_START_END 0x49c5 |
4579 | #define mmLB_V_COUNTER 0x1ac6 |
4580 | #define mmLB0_LB_V_COUNTER 0x1ac6 |
4581 | #define mmLB1_LB_V_COUNTER 0x1dc6 |
4582 | #define mmLB2_LB_V_COUNTER 0x40c6 |
4583 | #define mmLB3_LB_V_COUNTER 0x43c6 |
4584 | #define mmLB4_LB_V_COUNTER 0x46c6 |
4585 | #define mmLB5_LB_V_COUNTER 0x49c6 |
4586 | #define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 |
4587 | #define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 |
4588 | #define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7 |
4589 | #define mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7 |
4590 | #define mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7 |
4591 | #define mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7 |
4592 | #define mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7 |
4593 | #define mmLB_INTERRUPT_MASK 0x1ac8 |
4594 | #define mmLB0_LB_INTERRUPT_MASK 0x1ac8 |
4595 | #define mmLB1_LB_INTERRUPT_MASK 0x1dc8 |
4596 | #define mmLB2_LB_INTERRUPT_MASK 0x40c8 |
4597 | #define mmLB3_LB_INTERRUPT_MASK 0x43c8 |
4598 | #define mmLB4_LB_INTERRUPT_MASK 0x46c8 |
4599 | #define mmLB5_LB_INTERRUPT_MASK 0x49c8 |
4600 | #define mmLB_VLINE_STATUS 0x1ac9 |
4601 | #define mmLB0_LB_VLINE_STATUS 0x1ac9 |
4602 | #define mmLB1_LB_VLINE_STATUS 0x1dc9 |
4603 | #define mmLB2_LB_VLINE_STATUS 0x40c9 |
4604 | #define mmLB3_LB_VLINE_STATUS 0x43c9 |
4605 | #define mmLB4_LB_VLINE_STATUS 0x46c9 |
4606 | #define mmLB5_LB_VLINE_STATUS 0x49c9 |
4607 | #define mmLB_VLINE2_STATUS 0x1aca |
4608 | #define mmLB0_LB_VLINE2_STATUS 0x1aca |
4609 | #define mmLB1_LB_VLINE2_STATUS 0x1dca |
4610 | #define mmLB2_LB_VLINE2_STATUS 0x40ca |
4611 | #define mmLB3_LB_VLINE2_STATUS 0x43ca |
4612 | #define mmLB4_LB_VLINE2_STATUS 0x46ca |
4613 | #define mmLB5_LB_VLINE2_STATUS 0x49ca |
4614 | #define mmLB_VBLANK_STATUS 0x1acb |
4615 | #define mmLB0_LB_VBLANK_STATUS 0x1acb |
4616 | #define mmLB1_LB_VBLANK_STATUS 0x1dcb |
4617 | #define mmLB2_LB_VBLANK_STATUS 0x40cb |
4618 | #define mmLB3_LB_VBLANK_STATUS 0x43cb |
4619 | #define mmLB4_LB_VBLANK_STATUS 0x46cb |
4620 | #define mmLB5_LB_VBLANK_STATUS 0x49cb |
4621 | #define mmLB_SYNC_RESET_SEL 0x1acc |
4622 | #define mmLB0_LB_SYNC_RESET_SEL 0x1acc |
4623 | #define mmLB1_LB_SYNC_RESET_SEL 0x1dcc |
4624 | #define mmLB2_LB_SYNC_RESET_SEL 0x40cc |
4625 | #define mmLB3_LB_SYNC_RESET_SEL 0x43cc |
4626 | #define mmLB4_LB_SYNC_RESET_SEL 0x46cc |
4627 | #define mmLB5_LB_SYNC_RESET_SEL 0x49cc |
4628 | #define mmLB_BLACK_KEYER_R_CR 0x1acd |
4629 | #define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd |
4630 | #define mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd |
4631 | #define mmLB2_LB_BLACK_KEYER_R_CR 0x40cd |
4632 | #define mmLB3_LB_BLACK_KEYER_R_CR 0x43cd |
4633 | #define mmLB4_LB_BLACK_KEYER_R_CR 0x46cd |
4634 | #define mmLB5_LB_BLACK_KEYER_R_CR 0x49cd |
4635 | #define mmLB_BLACK_KEYER_G_Y 0x1ace |
4636 | #define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace |
4637 | #define mmLB1_LB_BLACK_KEYER_G_Y 0x1dce |
4638 | #define mmLB2_LB_BLACK_KEYER_G_Y 0x40ce |
4639 | #define mmLB3_LB_BLACK_KEYER_G_Y 0x43ce |
4640 | #define mmLB4_LB_BLACK_KEYER_G_Y 0x46ce |
4641 | #define mmLB5_LB_BLACK_KEYER_G_Y 0x49ce |
4642 | #define mmLB_BLACK_KEYER_B_CB 0x1acf |
4643 | #define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf |
4644 | #define mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf |
4645 | #define mmLB2_LB_BLACK_KEYER_B_CB 0x40cf |
4646 | #define mmLB3_LB_BLACK_KEYER_B_CB 0x43cf |
4647 | #define mmLB4_LB_BLACK_KEYER_B_CB 0x46cf |
4648 | #define mmLB5_LB_BLACK_KEYER_B_CB 0x49cf |
4649 | #define mmLB_KEYER_COLOR_CTRL 0x1ad0 |
4650 | #define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 |
4651 | #define mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0 |
4652 | #define mmLB2_LB_KEYER_COLOR_CTRL 0x40d0 |
4653 | #define mmLB3_LB_KEYER_COLOR_CTRL 0x43d0 |
4654 | #define mmLB4_LB_KEYER_COLOR_CTRL 0x46d0 |
4655 | #define mmLB5_LB_KEYER_COLOR_CTRL 0x49d0 |
4656 | #define mmLB_KEYER_COLOR_R_CR 0x1ad1 |
4657 | #define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 |
4658 | #define mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1 |
4659 | #define mmLB2_LB_KEYER_COLOR_R_CR 0x40d1 |
4660 | #define mmLB3_LB_KEYER_COLOR_R_CR 0x43d1 |
4661 | #define mmLB4_LB_KEYER_COLOR_R_CR 0x46d1 |
4662 | #define mmLB5_LB_KEYER_COLOR_R_CR 0x49d1 |
4663 | #define mmLB_KEYER_COLOR_G_Y 0x1ad2 |
4664 | #define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 |
4665 | #define mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2 |
4666 | #define mmLB2_LB_KEYER_COLOR_G_Y 0x40d2 |
4667 | #define mmLB3_LB_KEYER_COLOR_G_Y 0x43d2 |
4668 | #define mmLB4_LB_KEYER_COLOR_G_Y 0x46d2 |
4669 | #define mmLB5_LB_KEYER_COLOR_G_Y 0x49d2 |
4670 | #define mmLB_KEYER_COLOR_B_CB 0x1ad3 |
4671 | #define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 |
4672 | #define mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3 |
4673 | #define mmLB2_LB_KEYER_COLOR_B_CB 0x40d3 |
4674 | #define mmLB3_LB_KEYER_COLOR_B_CB 0x43d3 |
4675 | #define mmLB4_LB_KEYER_COLOR_B_CB 0x46d3 |
4676 | #define mmLB5_LB_KEYER_COLOR_B_CB 0x49d3 |
4677 | #define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 |
4678 | #define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 |
4679 | #define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4 |
4680 | #define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4 |
4681 | #define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4 |
4682 | #define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4 |
4683 | #define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4 |
4684 | #define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 |
4685 | #define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 |
4686 | #define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5 |
4687 | #define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5 |
4688 | #define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5 |
4689 | #define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5 |
4690 | #define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5 |
4691 | #define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 |
4692 | #define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 |
4693 | #define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6 |
4694 | #define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6 |
4695 | #define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6 |
4696 | #define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6 |
4697 | #define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6 |
4698 | #define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 |
4699 | #define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 |
4700 | #define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7 |
4701 | #define mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7 |
4702 | #define mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7 |
4703 | #define mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7 |
4704 | #define mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7 |
4705 | #define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 |
4706 | #define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 |
4707 | #define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8 |
4708 | #define mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8 |
4709 | #define mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8 |
4710 | #define mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8 |
4711 | #define mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8 |
4712 | #define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 |
4713 | #define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 |
4714 | #define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9 |
4715 | #define mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9 |
4716 | #define mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9 |
4717 | #define mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9 |
4718 | #define mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9 |
4719 | #define mmLB_BUFFER_STATUS 0x1ada |
4720 | #define mmLB0_LB_BUFFER_STATUS 0x1ada |
4721 | #define mmLB1_LB_BUFFER_STATUS 0x1dda |
4722 | #define mmLB2_LB_BUFFER_STATUS 0x40da |
4723 | #define mmLB3_LB_BUFFER_STATUS 0x43da |
4724 | #define mmLB4_LB_BUFFER_STATUS 0x46da |
4725 | #define mmLB5_LB_BUFFER_STATUS 0x49da |
4726 | #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc |
4727 | #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc |
4728 | #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc |
4729 | #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc |
4730 | #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc |
4731 | #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc |
4732 | #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc |
4733 | #define mmMVP_AFR_FLIP_MODE 0x1ae0 |
4734 | #define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 |
4735 | #define mmLB1_MVP_AFR_FLIP_MODE 0x1de0 |
4736 | #define mmLB2_MVP_AFR_FLIP_MODE 0x40e0 |
4737 | #define mmLB3_MVP_AFR_FLIP_MODE 0x43e0 |
4738 | #define mmLB4_MVP_AFR_FLIP_MODE 0x46e0 |
4739 | #define mmLB5_MVP_AFR_FLIP_MODE 0x49e0 |
4740 | #define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 |
4741 | #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 |
4742 | #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1 |
4743 | #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 |
4744 | #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1 |
4745 | #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1 |
4746 | #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1 |
4747 | #define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 |
4748 | #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 |
4749 | #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2 |
4750 | #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2 |
4751 | #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2 |
4752 | #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2 |
4753 | #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2 |
4754 | #define mmDC_MVP_LB_CONTROL 0x1ae3 |
4755 | #define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 |
4756 | #define mmLB1_DC_MVP_LB_CONTROL 0x1de3 |
4757 | #define mmLB2_DC_MVP_LB_CONTROL 0x40e3 |
4758 | #define mmLB3_DC_MVP_LB_CONTROL 0x43e3 |
4759 | #define mmLB4_DC_MVP_LB_CONTROL 0x46e3 |
4760 | #define mmLB5_DC_MVP_LB_CONTROL 0x49e3 |
4761 | #define mmLB_DEBUG 0x1ae4 |
4762 | #define mmLB0_LB_DEBUG 0x1ae4 |
4763 | #define mmLB1_LB_DEBUG 0x1de4 |
4764 | #define mmLB2_LB_DEBUG 0x40e4 |
4765 | #define mmLB3_LB_DEBUG 0x43e4 |
4766 | #define mmLB4_LB_DEBUG 0x46e4 |
4767 | #define mmLB5_LB_DEBUG 0x49e4 |
4768 | #define mmLB_DEBUG2 0x1ae5 |
4769 | #define mmLB0_LB_DEBUG2 0x1ae5 |
4770 | #define mmLB1_LB_DEBUG2 0x1de5 |
4771 | #define mmLB2_LB_DEBUG2 0x40e5 |
4772 | #define mmLB3_LB_DEBUG2 0x43e5 |
4773 | #define mmLB4_LB_DEBUG2 0x46e5 |
4774 | #define mmLB5_LB_DEBUG2 0x49e5 |
4775 | #define mmLB_DEBUG3 0x1ae6 |
4776 | #define mmLB0_LB_DEBUG3 0x1ae6 |
4777 | #define mmLB1_LB_DEBUG3 0x1de6 |
4778 | #define mmLB2_LB_DEBUG3 0x40e6 |
4779 | #define mmLB3_LB_DEBUG3 0x43e6 |
4780 | #define mmLB4_LB_DEBUG3 0x46e6 |
4781 | #define mmLB5_LB_DEBUG3 0x49e6 |
4782 | #define mmLB_TEST_DEBUG_INDEX 0x1afe |
4783 | #define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe |
4784 | #define mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe |
4785 | #define mmLB2_LB_TEST_DEBUG_INDEX 0x40fe |
4786 | #define mmLB3_LB_TEST_DEBUG_INDEX 0x43fe |
4787 | #define mmLB4_LB_TEST_DEBUG_INDEX 0x46fe |
4788 | #define mmLB5_LB_TEST_DEBUG_INDEX 0x49fe |
4789 | #define mmLB_TEST_DEBUG_DATA 0x1aff |
4790 | #define mmLB0_LB_TEST_DEBUG_DATA 0x1aff |
4791 | #define mmLB1_LB_TEST_DEBUG_DATA 0x1dff |
4792 | #define mmLB2_LB_TEST_DEBUG_DATA 0x40ff |
4793 | #define mmLB3_LB_TEST_DEBUG_DATA 0x43ff |
4794 | #define mmLB4_LB_TEST_DEBUG_DATA 0x46ff |
4795 | #define mmLB5_LB_TEST_DEBUG_DATA 0x49ff |
4796 | #define mmMVP_CONTROL1 0x1680 |
4797 | #define mmMVP_CONTROL2 0x1681 |
4798 | #define mmMVP_FIFO_CONTROL 0x1682 |
4799 | #define mmMVP_FIFO_STATUS 0x1683 |
4800 | #define mmMVP_SLAVE_STATUS 0x1684 |
4801 | #define mmMVP_INBAND_CNTL_CAP 0x1685 |
4802 | #define mmMVP_BLACK_KEYER 0x1686 |
4803 | #define mmMVP_CRC_CNTL 0x1687 |
4804 | #define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 |
4805 | #define mmMVP_CRC_RESULT_RED 0x1689 |
4806 | #define mmMVP_CONTROL3 0x168a |
4807 | #define mmMVP_RECEIVE_CNT_CNTL1 0x168b |
4808 | #define mmMVP_RECEIVE_CNT_CNTL2 0x168c |
4809 | #define mmMVP_DEBUG 0x168f |
4810 | #define mmMVP_TEST_DEBUG_INDEX 0x168d |
4811 | #define mmMVP_TEST_DEBUG_DATA 0x168e |
4812 | #define ixMVP_DEBUG_12 0xc |
4813 | #define ixMVP_DEBUG_13 0xd |
4814 | #define ixMVP_DEBUG_14 0xe |
4815 | #define ixMVP_DEBUG_15 0xf |
4816 | #define ixMVP_DEBUG_16 0x10 |
4817 | #define ixMVP_DEBUG_17 0x11 |
4818 | #define mmSCL_COEF_RAM_SELECT 0x1b40 |
4819 | #define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 |
4820 | #define mmSCL1_SCL_COEF_RAM_SELECT 0x1e40 |
4821 | #define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 |
4822 | #define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 |
4823 | #define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 |
4824 | #define mmSCL5_SCL_COEF_RAM_SELECT 0x4a40 |
4825 | #define mmSCL_COEF_RAM_TAP_DATA 0x1b41 |
4826 | #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 |
4827 | #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41 |
4828 | #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 |
4829 | #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 |
4830 | #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 |
4831 | #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 |
4832 | #define mmSCL_MODE 0x1b42 |
4833 | #define mmSCL0_SCL_MODE 0x1b42 |
4834 | #define mmSCL1_SCL_MODE 0x1e42 |
4835 | #define mmSCL2_SCL_MODE 0x4142 |
4836 | #define mmSCL3_SCL_MODE 0x4442 |
4837 | #define mmSCL4_SCL_MODE 0x4742 |
4838 | #define mmSCL5_SCL_MODE 0x4a42 |
4839 | #define mmSCL_TAP_CONTROL 0x1b43 |
4840 | #define mmSCL0_SCL_TAP_CONTROL 0x1b43 |
4841 | #define mmSCL1_SCL_TAP_CONTROL 0x1e43 |
4842 | #define mmSCL2_SCL_TAP_CONTROL 0x4143 |
4843 | #define mmSCL3_SCL_TAP_CONTROL 0x4443 |
4844 | #define mmSCL4_SCL_TAP_CONTROL 0x4743 |
4845 | #define mmSCL5_SCL_TAP_CONTROL 0x4a43 |
4846 | #define mmSCL_CONTROL 0x1b44 |
4847 | #define mmSCL0_SCL_CONTROL 0x1b44 |
4848 | #define mmSCL1_SCL_CONTROL 0x1e44 |
4849 | #define mmSCL2_SCL_CONTROL 0x4144 |
4850 | #define mmSCL3_SCL_CONTROL 0x4444 |
4851 | #define mmSCL4_SCL_CONTROL 0x4744 |
4852 | #define mmSCL5_SCL_CONTROL 0x4a44 |
4853 | #define mmSCL_BYPASS_CONTROL 0x1b45 |
4854 | #define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 |
4855 | #define mmSCL1_SCL_BYPASS_CONTROL 0x1e45 |
4856 | #define mmSCL2_SCL_BYPASS_CONTROL 0x4145 |
4857 | #define mmSCL3_SCL_BYPASS_CONTROL 0x4445 |
4858 | #define mmSCL4_SCL_BYPASS_CONTROL 0x4745 |
4859 | #define mmSCL5_SCL_BYPASS_CONTROL 0x4a45 |
4860 | #define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 |
4861 | #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 |
4862 | #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46 |
4863 | #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 |
4864 | #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 |
4865 | #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 |
4866 | #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46 |
4867 | #define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 |
4868 | #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 |
4869 | #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47 |
4870 | #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 |
4871 | #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 |
4872 | #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 |
4873 | #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47 |
4874 | #define mmSCL_HORZ_FILTER_CONTROL 0x1b48 |
4875 | #define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 |
4876 | #define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48 |
4877 | #define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148 |
4878 | #define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448 |
4879 | #define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748 |
4880 | #define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48 |
4881 | #define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 |
4882 | #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 |
4883 | #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49 |
4884 | #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 |
4885 | #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449 |
4886 | #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749 |
4887 | #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49 |
4888 | #define mmSCL_HORZ_FILTER_INIT 0x1b4a |
4889 | #define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a |
4890 | #define mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a |
4891 | #define mmSCL2_SCL_HORZ_FILTER_INIT 0x414a |
4892 | #define mmSCL3_SCL_HORZ_FILTER_INIT 0x444a |
4893 | #define mmSCL4_SCL_HORZ_FILTER_INIT 0x474a |
4894 | #define mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a |
4895 | #define mmSCL_VERT_FILTER_CONTROL 0x1b4b |
4896 | #define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b |
4897 | #define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b |
4898 | #define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b |
4899 | #define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b |
4900 | #define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b |
4901 | #define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b |
4902 | #define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c |
4903 | #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c |
4904 | #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c |
4905 | #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c |
4906 | #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c |
4907 | #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c |
4908 | #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c |
4909 | #define mmSCL_VERT_FILTER_INIT 0x1b4d |
4910 | #define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d |
4911 | #define mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d |
4912 | #define mmSCL2_SCL_VERT_FILTER_INIT 0x414d |
4913 | #define mmSCL3_SCL_VERT_FILTER_INIT 0x444d |
4914 | #define mmSCL4_SCL_VERT_FILTER_INIT 0x474d |
4915 | #define mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d |
4916 | #define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e |
4917 | #define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e |
4918 | #define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e |
4919 | #define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e |
4920 | #define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e |
4921 | #define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e |
4922 | #define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e |
4923 | #define mmSCL_ROUND_OFFSET 0x1b4f |
4924 | #define mmSCL0_SCL_ROUND_OFFSET 0x1b4f |
4925 | #define mmSCL1_SCL_ROUND_OFFSET 0x1e4f |
4926 | #define mmSCL2_SCL_ROUND_OFFSET 0x414f |
4927 | #define mmSCL3_SCL_ROUND_OFFSET 0x444f |
4928 | #define mmSCL4_SCL_ROUND_OFFSET 0x474f |
4929 | #define mmSCL5_SCL_ROUND_OFFSET 0x4a4f |
4930 | #define mmSCL_UPDATE 0x1b51 |
4931 | #define mmSCL0_SCL_UPDATE 0x1b51 |
4932 | #define mmSCL1_SCL_UPDATE 0x1e51 |
4933 | #define mmSCL2_SCL_UPDATE 0x4151 |
4934 | #define mmSCL3_SCL_UPDATE 0x4451 |
4935 | #define mmSCL4_SCL_UPDATE 0x4751 |
4936 | #define mmSCL5_SCL_UPDATE 0x4a51 |
4937 | #define mmSCL_F_SHARP_CONTROL 0x1b53 |
4938 | #define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 |
4939 | #define mmSCL1_SCL_F_SHARP_CONTROL 0x1e53 |
4940 | #define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 |
4941 | #define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 |
4942 | #define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 |
4943 | #define mmSCL5_SCL_F_SHARP_CONTROL 0x4a53 |
4944 | #define mmSCL_ALU_CONTROL 0x1b54 |
4945 | #define mmSCL0_SCL_ALU_CONTROL 0x1b54 |
4946 | #define mmSCL1_SCL_ALU_CONTROL 0x1e54 |
4947 | #define mmSCL2_SCL_ALU_CONTROL 0x4154 |
4948 | #define mmSCL3_SCL_ALU_CONTROL 0x4454 |
4949 | #define mmSCL4_SCL_ALU_CONTROL 0x4754 |
4950 | #define mmSCL5_SCL_ALU_CONTROL 0x4a54 |
4951 | #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 |
4952 | #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 |
4953 | #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55 |
4954 | #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 |
4955 | #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 |
4956 | #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 |
4957 | #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55 |
4958 | #define mmVIEWPORT_START 0x1b5c |
4959 | #define mmSCL0_VIEWPORT_START 0x1b5c |
4960 | #define mmSCL1_VIEWPORT_START 0x1e5c |
4961 | #define mmSCL2_VIEWPORT_START 0x415c |
4962 | #define mmSCL3_VIEWPORT_START 0x445c |
4963 | #define mmSCL4_VIEWPORT_START 0x475c |
4964 | #define mmSCL5_VIEWPORT_START 0x4a5c |
4965 | #define mmVIEWPORT_SIZE 0x1b5d |
4966 | #define mmSCL0_VIEWPORT_SIZE 0x1b5d |
4967 | #define mmSCL1_VIEWPORT_SIZE 0x1e5d |
4968 | #define mmSCL2_VIEWPORT_SIZE 0x415d |
4969 | #define mmSCL3_VIEWPORT_SIZE 0x445d |
4970 | #define mmSCL4_VIEWPORT_SIZE 0x475d |
4971 | #define mmSCL5_VIEWPORT_SIZE 0x4a5d |
4972 | #define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e |
4973 | #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e |
4974 | #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e |
4975 | #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e |
4976 | #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e |
4977 | #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e |
4978 | #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e |
4979 | #define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f |
4980 | #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f |
4981 | #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f |
4982 | #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f |
4983 | #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f |
4984 | #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f |
4985 | #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f |
4986 | #define mmSCL_MODE_CHANGE_DET1 0x1b60 |
4987 | #define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 |
4988 | #define mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60 |
4989 | #define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 |
4990 | #define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 |
4991 | #define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 |
4992 | #define mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60 |
4993 | #define mmSCL_MODE_CHANGE_DET2 0x1b61 |
4994 | #define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 |
4995 | #define mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61 |
4996 | #define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 |
4997 | #define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 |
4998 | #define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 |
4999 | #define mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61 |
5000 | #define mmSCL_MODE_CHANGE_DET3 0x1b62 |
5001 | #define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 |
5002 | #define mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62 |
5003 | #define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 |
5004 | #define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 |
5005 | #define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 |
5006 | #define mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62 |
5007 | #define mmSCL_MODE_CHANGE_MASK 0x1b63 |
5008 | #define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 |
5009 | #define mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63 |
5010 | #define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 |
5011 | #define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 |
5012 | #define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 |
5013 | #define mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63 |
5014 | #define mmSCL_DEBUG2 0x1b69 |
5015 | #define mmSCL0_SCL_DEBUG2 0x1b69 |
5016 | #define mmSCL1_SCL_DEBUG2 0x1e69 |
5017 | #define mmSCL2_SCL_DEBUG2 0x4169 |
5018 | #define mmSCL3_SCL_DEBUG2 0x4469 |
5019 | #define mmSCL4_SCL_DEBUG2 0x4769 |
5020 | #define mmSCL5_SCL_DEBUG2 0x4a69 |
5021 | #define mmSCL_DEBUG 0x1b6a |
5022 | #define mmSCL0_SCL_DEBUG 0x1b6a |
5023 | #define mmSCL1_SCL_DEBUG 0x1e6a |
5024 | #define mmSCL2_SCL_DEBUG 0x416a |
5025 | #define mmSCL3_SCL_DEBUG 0x446a |
5026 | #define mmSCL4_SCL_DEBUG 0x476a |
5027 | #define mmSCL5_SCL_DEBUG 0x4a6a |
5028 | #define mmSCL_TEST_DEBUG_INDEX 0x1b6b |
5029 | #define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b |
5030 | #define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b |
5031 | #define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b |
5032 | #define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b |
5033 | #define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b |
5034 | #define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b |
5035 | #define mmSCL_TEST_DEBUG_DATA 0x1b6c |
5036 | #define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c |
5037 | #define mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c |
5038 | #define mmSCL2_SCL_TEST_DEBUG_DATA 0x416c |
5039 | #define mmSCL3_SCL_TEST_DEBUG_DATA 0x446c |
5040 | #define mmSCL4_SCL_TEST_DEBUG_DATA 0x476c |
5041 | #define mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c |
5042 | #define mmGENMO_WT 0xf0 |
5043 | #define mmGENMO_RD 0xf3 |
5044 | #define mmGENENB 0xf0 |
5045 | #define mmGENFC_WT 0xee |
5046 | #define mmVGA0_GENFC_WT 0xee |
5047 | #define mmVGA1_GENFC_WT 0xf6 |
5048 | #define mmGENFC_RD 0xf2 |
5049 | #define mmGENS0 0xf0 |
5050 | #define mmGENS1 0xee |
5051 | #define mmVGA0_GENS1 0xee |
5052 | #define mmVGA1_GENS1 0xf6 |
5053 | #define mmDAC_DATA 0xf2 |
5054 | #define mmDAC_MASK 0xf1 |
5055 | #define mmDAC_R_INDEX 0xf1 |
5056 | #define mmDAC_W_INDEX 0xf2 |
5057 | #define mmSEQ8_IDX 0xf1 |
5058 | #define mmSEQ8_DATA 0xf1 |
5059 | #define ixSEQ00 0x0 |
5060 | #define ixSEQ01 0x1 |
5061 | #define ixSEQ02 0x2 |
5062 | #define ixSEQ03 0x3 |
5063 | #define ixSEQ04 0x4 |
5064 | #define mmCRTC8_IDX 0xed |
5065 | #define mmVGA0_CRTC8_IDX 0xed |
5066 | #define mmVGA1_CRTC8_IDX 0xf5 |
5067 | #define mmCRTC8_DATA 0xed |
5068 | #define mmVGA0_CRTC8_DATA 0xed |
5069 | #define mmVGA1_CRTC8_DATA 0xf5 |
5070 | #define ixCRT00 0x0 |
5071 | #define ixCRT01 0x1 |
5072 | #define ixCRT02 0x2 |
5073 | #define ixCRT03 0x3 |
5074 | #define ixCRT04 0x4 |
5075 | #define ixCRT05 0x5 |
5076 | #define ixCRT06 0x6 |
5077 | #define ixCRT07 0x7 |
5078 | #define ixCRT08 0x8 |
5079 | #define ixCRT09 0x9 |
5080 | #define ixCRT0A 0xa |
5081 | #define ixCRT0B 0xb |
5082 | #define ixCRT0C 0xc |
5083 | #define ixCRT0D 0xd |
5084 | #define ixCRT0E 0xe |
5085 | #define ixCRT0F 0xf |
5086 | #define ixCRT10 0x10 |
5087 | #define ixCRT11 0x11 |
5088 | #define ixCRT12 0x12 |
5089 | #define ixCRT13 0x13 |
5090 | #define ixCRT14 0x14 |
5091 | #define ixCRT15 0x15 |
5092 | #define ixCRT16 0x16 |
5093 | #define ixCRT17 0x17 |
5094 | #define ixCRT18 0x18 |
5095 | #define ixCRT1E 0x1e |
5096 | #define ixCRT1F 0x1f |
5097 | #define ixCRT22 0x22 |
5098 | #define mmGRPH8_IDX 0xf3 |
5099 | #define mmGRPH8_DATA 0xf3 |
5100 | #define ixGRA00 0x0 |
5101 | #define ixGRA01 0x1 |
5102 | #define ixGRA02 0x2 |
5103 | #define ixGRA03 0x3 |
5104 | #define ixGRA04 0x4 |
5105 | #define ixGRA05 0x5 |
5106 | #define ixGRA06 0x6 |
5107 | #define ixGRA07 0x7 |
5108 | #define ixGRA08 0x8 |
5109 | #define mmATTRX 0xf0 |
5110 | #define mmATTRDW 0xf0 |
5111 | #define mmATTRDR 0xf0 |
5112 | #define ixATTR00 0x0 |
5113 | #define ixATTR01 0x1 |
5114 | #define ixATTR02 0x2 |
5115 | #define ixATTR03 0x3 |
5116 | #define ixATTR04 0x4 |
5117 | #define ixATTR05 0x5 |
5118 | #define ixATTR06 0x6 |
5119 | #define ixATTR07 0x7 |
5120 | #define ixATTR08 0x8 |
5121 | #define ixATTR09 0x9 |
5122 | #define ixATTR0A 0xa |
5123 | #define ixATTR0B 0xb |
5124 | #define ixATTR0C 0xc |
5125 | #define ixATTR0D 0xd |
5126 | #define ixATTR0E 0xe |
5127 | #define ixATTR0F 0xf |
5128 | #define ixATTR10 0x10 |
5129 | #define ixATTR11 0x11 |
5130 | #define ixATTR12 0x12 |
5131 | #define ixATTR13 0x13 |
5132 | #define ixATTR14 0x14 |
5133 | #define mmVGA_RENDER_CONTROL 0xc0 |
5134 | #define mmVGA_SOURCE_SELECT 0xfc |
5135 | #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 |
5136 | #define mmVGA_MODE_CONTROL 0xc2 |
5137 | #define mmVGA_SURFACE_PITCH_SELECT 0xc3 |
5138 | #define mmVGA_MEMORY_BASE_ADDRESS 0xc4 |
5139 | #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 |
5140 | #define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 |
5141 | #define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 |
5142 | #define mmVGA_HDP_CONTROL 0xca |
5143 | #define mmVGA_CACHE_CONTROL 0xcb |
5144 | #define mmD1VGA_CONTROL 0xcc |
5145 | #define mmD2VGA_CONTROL 0xce |
5146 | #define mmD3VGA_CONTROL 0xf8 |
5147 | #define mmD4VGA_CONTROL 0xf9 |
5148 | #define mmD5VGA_CONTROL 0xfa |
5149 | #define mmD6VGA_CONTROL 0xfb |
5150 | #define mmVGA_HW_DEBUG 0xcf |
5151 | #define mmVGA_STATUS 0xd0 |
5152 | #define mmVGA_INTERRUPT_CONTROL 0xd1 |
5153 | #define mmVGA_STATUS_CLEAR 0xd2 |
5154 | #define mmVGA_INTERRUPT_STATUS 0xd3 |
5155 | #define mmVGA_MAIN_CONTROL 0xd4 |
5156 | #define mmVGA_TEST_CONTROL 0xd5 |
5157 | #define mmVGA_DEBUG_READBACK_INDEX 0xd6 |
5158 | #define mmVGA_DEBUG_READBACK_DATA 0xd7 |
5159 | #define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 |
5160 | #define mmVGA_MEM_READ_PAGE_ADDR 0x13 |
5161 | #define mmVGA_TEST_DEBUG_INDEX 0xc5 |
5162 | #define mmVGA_TEST_DEBUG_DATA 0xc7 |
5163 | #define ixVGADCC_DBG_DCCIF_C 0x7e |
5164 | #define mmBPHYC_DAC_MACRO_CNTL 0x19fd |
5165 | #define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe |
5166 | #define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 |
5167 | #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 |
5168 | #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30 |
5169 | #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 |
5170 | #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 |
5171 | #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 |
5172 | #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30 |
5173 | #define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 |
5174 | #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 |
5175 | #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31 |
5176 | #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 |
5177 | #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 |
5178 | #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 |
5179 | #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31 |
5180 | #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 |
5181 | #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 |
5182 | #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32 |
5183 | #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132 |
5184 | #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432 |
5185 | #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732 |
5186 | #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32 |
5187 | #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 |
5188 | #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 |
5189 | #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33 |
5190 | #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 |
5191 | #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 |
5192 | #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 |
5193 | #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33 |
5194 | #define mmDPG_PIPE_DPM_CONTROL 0x1b34 |
5195 | #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 |
5196 | #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34 |
5197 | #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 |
5198 | #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 |
5199 | #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 |
5200 | #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34 |
5201 | #define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 |
5202 | #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 |
5203 | #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35 |
5204 | #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 |
5205 | #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 |
5206 | #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 |
5207 | #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35 |
5208 | #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 |
5209 | #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 |
5210 | #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36 |
5211 | #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 |
5212 | #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 |
5213 | #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 |
5214 | #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36 |
5215 | #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 |
5216 | #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 |
5217 | #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37 |
5218 | #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 |
5219 | #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 |
5220 | #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 |
5221 | #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37 |
5222 | #define mmDPG_REPEATER_PROGRAM 0x1b3a |
5223 | #define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a |
5224 | #define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a |
5225 | #define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a |
5226 | #define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a |
5227 | #define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a |
5228 | #define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a |
5229 | #define mmDPG_HW_DEBUG_A 0x1b3b |
5230 | #define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b |
5231 | #define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b |
5232 | #define mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b |
5233 | #define mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b |
5234 | #define mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b |
5235 | #define mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b |
5236 | #define mmDPG_HW_DEBUG_B 0x1b3c |
5237 | #define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c |
5238 | #define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c |
5239 | #define mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c |
5240 | #define mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c |
5241 | #define mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c |
5242 | #define mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c |
5243 | #define mmDPG_TEST_DEBUG_INDEX 0x1b38 |
5244 | #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 |
5245 | #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38 |
5246 | #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 |
5247 | #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 |
5248 | #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 |
5249 | #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38 |
5250 | #define mmDPG_TEST_DEBUG_DATA 0x1b39 |
5251 | #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 |
5252 | #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39 |
5253 | #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 |
5254 | #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 |
5255 | #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 |
5256 | #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39 |
5257 | #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 |
5258 | #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 |
5259 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 |
5260 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 |
5261 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 |
5262 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 |
5263 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 |
5264 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a |
5265 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b |
5266 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f |
5267 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 |
5268 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff |
5269 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 |
5270 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 |
5271 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 |
5272 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 |
5273 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 |
5274 | #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2 |
5275 | #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3 |
5276 | #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5 |
5277 | #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6 |
5278 | #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7 |
5279 | #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8 |
5280 | #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9 |
5281 | #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da |
5282 | #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db |
5283 | #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc |
5284 | #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd |
5285 | #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de |
5286 | #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4 |
5287 | #define mmAZALIA_F0_CODEC_DEBUG 0x17df |
5288 | #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1 |
5289 | #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2 |
5290 | #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3 |
5291 | #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4 |
5292 | #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5 |
5293 | #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6 |
5294 | #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7 |
5295 | #define mmGLOBAL_CAPABILITIES 0x0 |
5296 | #define mmMINOR_VERSION 0x0 |
5297 | #define mmMAJOR_VERSION 0x0 |
5298 | #define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 |
5299 | #define mmINPUT_PAYLOAD_CAPABILITY 0x1 |
5300 | #define mmGLOBAL_CONTROL 0x2 |
5301 | #define mmWAKE_ENABLE 0x3 |
5302 | #define mmSTATE_CHANGE_STATUS 0x3 |
5303 | #define mmGLOBAL_STATUS 0x4 |
5304 | #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 |
5305 | #define mmINTERRUPT_CONTROL 0x8 |
5306 | #define mmINTERRUPT_STATUS 0x9 |
5307 | #define mmWALL_CLOCK_COUNTER 0xc |
5308 | #define mmSTREAM_SYNCHRONIZATION 0xe |
5309 | #define mmCORB_LOWER_BASE_ADDRESS 0x10 |
5310 | #define mmCORB_UPPER_BASE_ADDRESS 0x11 |
5311 | #define mmCORB_WRITE_POINTER 0x12 |
5312 | #define mmCORB_READ_POINTER 0x12 |
5313 | #define mmCORB_CONTROL 0x13 |
5314 | #define mmCORB_STATUS 0x13 |
5315 | #define mmCORB_SIZE 0x13 |
5316 | #define mmRIRB_LOWER_BASE_ADDRESS 0x14 |
5317 | #define mmRIRB_UPPER_BASE_ADDRESS 0x15 |
5318 | #define mmRIRB_WRITE_POINTER 0x16 |
5319 | #define mmRESPONSE_INTERRUPT_COUNT 0x16 |
5320 | #define mmRIRB_CONTROL 0x17 |
5321 | #define mmRIRB_STATUS 0x17 |
5322 | #define mmRIRB_SIZE 0x17 |
5323 | #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 |
5324 | #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 |
5325 | #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 |
5326 | #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 |
5327 | #define mmIMMEDIATE_COMMAND_STATUS 0x1a |
5328 | #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c |
5329 | #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d |
5330 | #define mmWALL_CLOCK_COUNTER_ALIAS 0x80c |
5331 | #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 |
5332 | #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 |
5333 | #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 |
5334 | #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 |
5335 | #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 |
5336 | #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 |
5337 | #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 |
5338 | #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 |
5339 | #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 |
5340 | #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 |
5341 | #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 |
5342 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 |
5343 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a |
5344 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b |
5345 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 |
5346 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 |
5347 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d |
5348 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e |
5349 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e |
5350 | #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 |
5351 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 |
5352 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 |
5353 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 |
5354 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c |
5355 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e |
5356 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 |
5357 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 |
5358 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 |
5359 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 |
5360 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c |
5361 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d |
5362 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e |
5363 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f |
5364 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 |
5365 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 |
5366 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 |
5367 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 |
5368 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 |
5369 | #define ixAUDIO_DESCRIPTOR0 0x1 |
5370 | #define ixAUDIO_DESCRIPTOR1 0x2 |
5371 | #define ixAUDIO_DESCRIPTOR2 0x3 |
5372 | #define ixAUDIO_DESCRIPTOR3 0x4 |
5373 | #define ixAUDIO_DESCRIPTOR4 0x5 |
5374 | #define ixAUDIO_DESCRIPTOR5 0x6 |
5375 | #define ixAUDIO_DESCRIPTOR6 0x7 |
5376 | #define ixAUDIO_DESCRIPTOR7 0x8 |
5377 | #define ixAUDIO_DESCRIPTOR8 0x9 |
5378 | #define ixAUDIO_DESCRIPTOR9 0xa |
5379 | #define ixAUDIO_DESCRIPTOR10 0xb |
5380 | #define ixAUDIO_DESCRIPTOR11 0xc |
5381 | #define ixAUDIO_DESCRIPTOR12 0xd |
5382 | #define ixAUDIO_DESCRIPTOR13 0xe |
5383 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 |
5384 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 |
5385 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 |
5386 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a |
5387 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b |
5388 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c |
5389 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 |
5390 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 |
5391 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 |
5392 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 |
5393 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 |
5394 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 |
5395 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 |
5396 | #define ixSINK_DESCRIPTION0 0x5 |
5397 | #define ixSINK_DESCRIPTION1 0x6 |
5398 | #define ixSINK_DESCRIPTION2 0x7 |
5399 | #define ixSINK_DESCRIPTION3 0x8 |
5400 | #define ixSINK_DESCRIPTION4 0x9 |
5401 | #define ixSINK_DESCRIPTION5 0xa |
5402 | #define ixSINK_DESCRIPTION6 0xb |
5403 | #define ixSINK_DESCRIPTION7 0xc |
5404 | #define ixSINK_DESCRIPTION8 0xd |
5405 | #define ixSINK_DESCRIPTION9 0xe |
5406 | #define ixSINK_DESCRIPTION10 0xf |
5407 | #define ixSINK_DESCRIPTION11 0x10 |
5408 | #define ixSINK_DESCRIPTION12 0x11 |
5409 | #define ixSINK_DESCRIPTION13 0x12 |
5410 | #define ixSINK_DESCRIPTION14 0x13 |
5411 | #define ixSINK_DESCRIPTION15 0x14 |
5412 | #define ixSINK_DESCRIPTION16 0x15 |
5413 | #define ixSINK_DESCRIPTION17 0x16 |
5414 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 |
5415 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 |
5416 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 |
5417 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 |
5418 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 |
5419 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a |
5420 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b |
5421 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c |
5422 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d |
5423 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e |
5424 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f |
5425 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 |
5426 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 |
5427 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 |
5428 | #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 |
5429 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 |
5430 | #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9 |
5431 | #define mmAZALIA_AUDIO_DTO 0x17ba |
5432 | #define mmAZALIA_AUDIO_DTO_CONTROL 0x17bb |
5433 | #define mmAZALIA_SCLK_CONTROL 0x17bc |
5434 | #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd |
5435 | #define mmAZALIA_DATA_DMA_CONTROL 0x17be |
5436 | #define mmAZALIA_BDL_DMA_CONTROL 0x17bf |
5437 | #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 |
5438 | #define mmAZALIA_CORB_DMA_CONTROL 0x17c1 |
5439 | #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9 |
5440 | #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca |
5441 | #define mmAZALIA_GLOBAL_CAPABILITIES 0x17cb |
5442 | #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc |
5443 | #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd |
5444 | #define mmAZALIA_CONTROLLER_DEBUG 0x17cf |
5445 | #define mmAZALIA_CRC0_CONTROL0 0x17ae |
5446 | #define mmAZALIA_CRC0_CONTROL1 0x17af |
5447 | #define mmAZALIA_CRC0_CONTROL2 0x17b0 |
5448 | #define mmAZALIA_CRC0_CONTROL3 0x17b1 |
5449 | #define mmAZALIA_CRC0_RESULT 0x17b2 |
5450 | #define ixAZALIA_CRC0_CHANNEL0 0x0 |
5451 | #define ixAZALIA_CRC0_CHANNEL1 0x1 |
5452 | #define ixAZALIA_CRC0_CHANNEL2 0x2 |
5453 | #define ixAZALIA_CRC0_CHANNEL3 0x3 |
5454 | #define ixAZALIA_CRC0_CHANNEL4 0x4 |
5455 | #define ixAZALIA_CRC0_CHANNEL5 0x5 |
5456 | #define ixAZALIA_CRC0_CHANNEL6 0x6 |
5457 | #define ixAZALIA_CRC0_CHANNEL7 0x7 |
5458 | #define mmAZALIA_CRC1_CONTROL0 0x17b3 |
5459 | #define mmAZALIA_CRC1_CONTROL1 0x17b4 |
5460 | #define mmAZALIA_CRC1_CONTROL2 0x17b5 |
5461 | #define mmAZALIA_CRC1_CONTROL3 0x17b6 |
5462 | #define mmAZALIA_CRC1_RESULT 0x17b7 |
5463 | #define ixAZALIA_CRC1_CHANNEL0 0x0 |
5464 | #define ixAZALIA_CRC1_CHANNEL1 0x1 |
5465 | #define ixAZALIA_CRC1_CHANNEL2 0x2 |
5466 | #define ixAZALIA_CRC1_CHANNEL3 0x3 |
5467 | #define ixAZALIA_CRC1_CHANNEL4 0x4 |
5468 | #define ixAZALIA_CRC1_CHANNEL5 0x5 |
5469 | #define ixAZALIA_CRC1_CHANNEL6 0x6 |
5470 | #define ixAZALIA_CRC1_CHANNEL7 0x7 |
5471 | #define mmAZ_TEST_DEBUG_INDEX 0x17d0 |
5472 | #define mmAZ_TEST_DEBUG_DATA 0x17d1 |
5473 | #define mmAZALIA_STREAM_INDEX 0x17e8 |
5474 | #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8 |
5475 | #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec |
5476 | #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0 |
5477 | #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4 |
5478 | #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8 |
5479 | #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc |
5480 | #define mmAZALIA_STREAM_DATA 0x17e9 |
5481 | #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9 |
5482 | #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed |
5483 | #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1 |
5484 | #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5 |
5485 | #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9 |
5486 | #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd |
5487 | #define ixAZALIA_FIFO_SIZE_CONTROL 0x0 |
5488 | #define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 |
5489 | #define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 |
5490 | #define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 |
5491 | #define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 |
5492 | #define ixAZALIA_STREAM_DEBUG 0x5 |
5493 | #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 |
5494 | #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 |
5495 | #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 |
5496 | #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c |
5497 | #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 |
5498 | #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 |
5499 | #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e |
5500 | #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4 |
5501 | #define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 |
5502 | #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 |
5503 | #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 |
5504 | #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d |
5505 | #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 |
5506 | #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 |
5507 | #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f |
5508 | #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5 |
5509 | #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 |
5510 | #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 |
5511 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 |
5512 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 |
5513 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 |
5514 | #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 |
5515 | #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 |
5516 | #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 |
5517 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 |
5518 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 |
5519 | #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa |
5520 | #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc |
5521 | #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd |
5522 | #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe |
5523 | #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 |
5524 | #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 |
5525 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 |
5526 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 |
5527 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 |
5528 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 |
5529 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 |
5530 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 |
5531 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a |
5532 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b |
5533 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c |
5534 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d |
5535 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e |
5536 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f |
5537 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 |
5538 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 |
5539 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 |
5540 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 |
5541 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 |
5542 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 |
5543 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 |
5544 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 |
5545 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 |
5546 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 |
5547 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 |
5548 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a |
5549 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b |
5550 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c |
5551 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d |
5552 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e |
5553 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f |
5554 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 |
5555 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 |
5556 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 |
5557 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 |
5558 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 |
5559 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 |
5560 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 |
5561 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a |
5562 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b |
5563 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c |
5564 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d |
5565 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e |
5566 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f |
5567 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 |
5568 | #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 |
5569 | #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 |
5570 | #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 |
5571 | #define mmBLND_CONTROL 0x1b6d |
5572 | #define mmBLND0_BLND_CONTROL 0x1b6d |
5573 | #define mmBLND1_BLND_CONTROL 0x1e6d |
5574 | #define mmBLND2_BLND_CONTROL 0x416d |
5575 | #define mmBLND3_BLND_CONTROL 0x446d |
5576 | #define mmBLND4_BLND_CONTROL 0x476d |
5577 | #define mmBLND5_BLND_CONTROL 0x4a6d |
5578 | #define mmSM_CONTROL2 0x1b6e |
5579 | #define mmBLND0_SM_CONTROL2 0x1b6e |
5580 | #define mmBLND1_SM_CONTROL2 0x1e6e |
5581 | #define mmBLND2_SM_CONTROL2 0x416e |
5582 | #define mmBLND3_SM_CONTROL2 0x446e |
5583 | #define mmBLND4_SM_CONTROL2 0x476e |
5584 | #define mmBLND5_SM_CONTROL2 0x4a6e |
5585 | #define mmPTI_CONTROL 0x1b6f |
5586 | #define mmBLND0_PTI_CONTROL 0x1b6f |
5587 | #define mmBLND1_PTI_CONTROL 0x1e6f |
5588 | #define mmBLND2_PTI_CONTROL 0x416f |
5589 | #define mmBLND3_PTI_CONTROL 0x446f |
5590 | #define mmBLND4_PTI_CONTROL 0x476f |
5591 | #define mmBLND5_PTI_CONTROL 0x4a6f |
5592 | #define mmBLND_UPDATE 0x1b70 |
5593 | #define mmBLND0_BLND_UPDATE 0x1b70 |
5594 | #define mmBLND1_BLND_UPDATE 0x1e70 |
5595 | #define mmBLND2_BLND_UPDATE 0x4170 |
5596 | #define mmBLND3_BLND_UPDATE 0x4470 |
5597 | #define mmBLND4_BLND_UPDATE 0x4770 |
5598 | #define mmBLND5_BLND_UPDATE 0x4a70 |
5599 | #define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 |
5600 | #define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 |
5601 | #define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71 |
5602 | #define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171 |
5603 | #define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471 |
5604 | #define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771 |
5605 | #define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71 |
5606 | #define mmBLND_V_UPDATE_LOCK 0x1b73 |
5607 | #define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 |
5608 | #define mmBLND1_BLND_V_UPDATE_LOCK 0x1e73 |
5609 | #define mmBLND2_BLND_V_UPDATE_LOCK 0x4173 |
5610 | #define mmBLND3_BLND_V_UPDATE_LOCK 0x4473 |
5611 | #define mmBLND4_BLND_V_UPDATE_LOCK 0x4773 |
5612 | #define mmBLND5_BLND_V_UPDATE_LOCK 0x4a73 |
5613 | #define mmBLND_REG_UPDATE_STATUS 0x1b77 |
5614 | #define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 |
5615 | #define mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77 |
5616 | #define mmBLND2_BLND_REG_UPDATE_STATUS 0x4177 |
5617 | #define mmBLND3_BLND_REG_UPDATE_STATUS 0x4477 |
5618 | #define mmBLND4_BLND_REG_UPDATE_STATUS 0x4777 |
5619 | #define mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77 |
5620 | #define mmBLND_DEBUG 0x1b74 |
5621 | #define mmBLND0_BLND_DEBUG 0x1b74 |
5622 | #define mmBLND1_BLND_DEBUG 0x1e74 |
5623 | #define mmBLND2_BLND_DEBUG 0x4174 |
5624 | #define mmBLND3_BLND_DEBUG 0x4474 |
5625 | #define mmBLND4_BLND_DEBUG 0x4774 |
5626 | #define mmBLND5_BLND_DEBUG 0x4a74 |
5627 | #define mmBLND_TEST_DEBUG_INDEX 0x1b75 |
5628 | #define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 |
5629 | #define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75 |
5630 | #define mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175 |
5631 | #define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475 |
5632 | #define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775 |
5633 | #define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75 |
5634 | #define mmBLND_TEST_DEBUG_DATA 0x1b76 |
5635 | #define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 |
5636 | #define mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76 |
5637 | #define mmBLND2_BLND_TEST_DEBUG_DATA 0x4176 |
5638 | #define mmBLND3_BLND_TEST_DEBUG_DATA 0x4476 |
5639 | #define mmBLND4_BLND_TEST_DEBUG_DATA 0x4776 |
5640 | #define mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76 |
5641 | #define mmSI_ENABLE 0x4c00 |
5642 | #define mmSI_EC_CONFIG 0x4c01 |
5643 | #define mmCNV_MODE 0x4c02 |
5644 | #define mmCNV_WINDOW_START 0x4c03 |
5645 | #define mmCNV_WINDOW_SIZE 0x4c04 |
5646 | #define mmCNV_UPDATE 0x4c05 |
5647 | #define mmCNV_SOURCE_SIZE 0x4c06 |
5648 | #define mmCNV_CSC_CONTROL 0x4c07 |
5649 | #define mmCNV_CSC_C11_C12 0x4c08 |
5650 | #define mmCNV_CSC_C13_C14 0x4c09 |
5651 | #define mmCNV_CSC_C21_C22 0x4c0a |
5652 | #define mmCNV_CSC_C23_C24 0x4c0b |
5653 | #define mmCNV_CSC_C31_C32 0x4c0c |
5654 | #define mmCNV_CSC_C33_C34 0x4c0d |
5655 | #define mmCNV_CSC_ROUND_OFFSET_R 0x4c0e |
5656 | #define mmCNV_CSC_ROUND_OFFSET_G 0x4c0f |
5657 | #define mmCNV_CSC_ROUND_OFFSET_B 0x4c10 |
5658 | #define mmCNV_CSC_CLAMP_R 0x4c11 |
5659 | #define mmCNV_CSC_CLAMP_G 0x4c12 |
5660 | #define mmCNV_CSC_CLAMP_B 0x4c13 |
5661 | #define mmCNV_TEST_CNTL 0x4c14 |
5662 | #define mmCNV_TEST_CRC_RED 0x4c15 |
5663 | #define mmCNV_TEST_CRC_GREEN 0x4c16 |
5664 | #define mmCNV_TEST_CRC_BLUE 0x4c17 |
5665 | #define mmSI_DEBUG_CTRL 0x4c18 |
5666 | #define mmSI_DBG_MODE 0x4c1b |
5667 | #define mmSI_HARD_DEBUG 0x4c1c |
5668 | #define mmCNV_TEST_DEBUG_INDEX 0x4c19 |
5669 | #define mmCNV_TEST_DEBUG_DATA 0x4c1a |
5670 | #define mmSISCL_COEF_RAM_SELECT 0x4c20 |
5671 | #define mmSISCL_COEF_RAM_TAP_DATA 0x4c21 |
5672 | #define mmSISCL_MODE 0x4c22 |
5673 | #define mmSISCL_TAP_CONTROL 0x4c23 |
5674 | #define mmSISCL_DEST_SIZE 0x4c24 |
5675 | #define mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25 |
5676 | #define mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26 |
5677 | #define mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27 |
5678 | #define mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28 |
5679 | #define mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29 |
5680 | #define mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a |
5681 | #define mmSISCL_ROUND_OFFSET 0x4c2b |
5682 | #define mmSISCL_CLAMP 0x4c2c |
5683 | #define mmSISCL_OVERFLOW_STATUS 0x4c2d |
5684 | #define mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e |
5685 | #define mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f |
5686 | #define mmSISCL_TEST_CNTL 0x4c30 |
5687 | #define mmSISCL_TEST_CRC_RED 0x4c31 |
5688 | #define mmSISCL_TEST_CRC_GREEN 0x4c32 |
5689 | #define mmSISCL_TEST_CRC_BLUE 0x4c33 |
5690 | #define mmSISCL_BACKPRESSURE_CNT_EN 0x4c36 |
5691 | #define mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37 |
5692 | #define mmSISCL_TEST_DEBUG_INDEX 0x4c34 |
5693 | #define mmSISCL_TEST_DEBUG_DATA 0x4c35 |
5694 | #define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 |
5695 | #define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 |
5696 | #define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 |
5697 | #define mmXDMA_INTERRUPT 0x3e3 |
5698 | #define mmXDMA_CLOCK_GATING_CNTL 0x3e4 |
5699 | #define mmXDMA_MEM_POWER_CNTL 0x3e6 |
5700 | #define mmXDMA_IF_BIF_STATUS 0x3e7 |
5701 | #define mmXDMA_PERF_MEAS_STATUS 0x3e8 |
5702 | #define mmXDMA_IF_STATUS 0x3e9 |
5703 | #define mmXDMA_TEST_DEBUG_INDEX 0x3ea |
5704 | #define mmXDMA_TEST_DEBUG_DATA 0x3eb |
5705 | #define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 |
5706 | #define mmXDMA_PG_CONTROL 0x3f9 |
5707 | #define mmXDMA_PG_WDATA 0x3fa |
5708 | #define mmXDMA_PG_STATUS 0x3fb |
5709 | #define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc |
5710 | #define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd |
5711 | |
5712 | #endif /* DCE_8_0_D_H */ |
5713 | |