| 1 | /* |
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| 2 | * OSS_2_4 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef OSS_2_4_D_H |
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| 25 | #define OSS_2_4_D_H |
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| 26 | |
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| 27 | #define mmIH_VMID_0_LUT 0xe00 |
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| 28 | #define mmIH_VMID_1_LUT 0xe01 |
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| 29 | #define mmIH_VMID_2_LUT 0xe02 |
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| 30 | #define mmIH_VMID_3_LUT 0xe03 |
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| 31 | #define mmIH_VMID_4_LUT 0xe04 |
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| 32 | #define mmIH_VMID_5_LUT 0xe05 |
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| 33 | #define mmIH_VMID_6_LUT 0xe06 |
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| 34 | #define mmIH_VMID_7_LUT 0xe07 |
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| 35 | #define mmIH_VMID_8_LUT 0xe08 |
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| 36 | #define mmIH_VMID_9_LUT 0xe09 |
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| 37 | #define mmIH_VMID_10_LUT 0xe0a |
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| 38 | #define mmIH_VMID_11_LUT 0xe0b |
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| 39 | #define mmIH_VMID_12_LUT 0xe0c |
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| 40 | #define mmIH_VMID_13_LUT 0xe0d |
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| 41 | #define mmIH_VMID_14_LUT 0xe0e |
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| 42 | #define mmIH_VMID_15_LUT 0xe0f |
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| 43 | #define mmIH_RB_CNTL 0xe30 |
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| 44 | #define mmIH_RB_BASE 0xe31 |
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| 45 | #define mmIH_RB_RPTR 0xe32 |
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| 46 | #define mmIH_RB_WPTR 0xe33 |
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| 47 | #define mmIH_RB_WPTR_ADDR_HI 0xe34 |
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| 48 | #define mmIH_RB_WPTR_ADDR_LO 0xe35 |
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| 49 | #define mmIH_CNTL 0xe36 |
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| 50 | #define mmIH_LEVEL_STATUS 0xe37 |
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| 51 | #define mmIH_STATUS 0xe38 |
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| 52 | #define mmIH_PERFMON_CNTL 0xe39 |
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| 53 | #define mmIH_PERFCOUNTER0_RESULT 0xe3a |
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| 54 | #define mmIH_PERFCOUNTER1_RESULT 0xe3b |
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| 55 | #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d |
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| 56 | #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e |
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| 57 | #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f |
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| 58 | #define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 |
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| 59 | #define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 |
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| 60 | #define mmIH_VERSION 0xe42 |
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| 61 | #define mmSEM_MCIF_CONFIG 0xf90 |
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| 62 | #define mmSDMA_CONFIG 0xf91 |
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| 63 | #define mmSDMA1_CONFIG 0xf92 |
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| 64 | #define mmUVD_CONFIG 0xf93 |
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| 65 | #define mmVCE_CONFIG 0xf94 |
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| 66 | #define mmACP_CONFIG 0xf95 |
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| 67 | #define mmCPG_CONFIG 0xf96 |
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| 68 | #define mmCPC1_CONFIG 0xf97 |
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| 69 | #define mmCPC2_CONFIG 0xf98 |
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| 70 | #define mmSEM_STATUS 0xf99 |
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| 71 | #define mmSEM_EDC_CONFIG 0xf9a |
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| 72 | #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b |
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| 73 | #define mmSEM_MAILBOX 0xf9c |
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| 74 | #define mmSEM_MAILBOX_CONTROL 0xf9d |
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| 75 | #define mmSEM_CHICKEN_BITS 0xf9e |
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| 76 | #define 0xf9f |
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| 77 | #define mmSRBM_CNTL 0x390 |
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| 78 | #define mmSRBM_GFX_CNTL 0x391 |
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| 79 | #define mmSRBM_READ_CNTL 0x392 |
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| 80 | #define mmSRBM_STATUS2 0x393 |
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| 81 | #define mmSRBM_STATUS 0x394 |
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| 82 | #define mmSRBM_STATUS3 0x395 |
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| 83 | #define mmSRBM_SOFT_RESET 0x398 |
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| 84 | #define mmSRBM_DEBUG_CNTL 0x399 |
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| 85 | #define mmSRBM_DEBUG_DATA 0x39a |
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| 86 | #define mmSRBM_CHIP_REVISION 0x39b |
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| 87 | #define mmCC_SYS_RB_REDUNDANCY 0x39f |
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| 88 | #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 |
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| 89 | #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 |
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| 90 | #define mmSRBM_MC_CLKEN_CNTL 0x3b3 |
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| 91 | #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 |
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| 92 | #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 |
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| 93 | #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 |
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| 94 | #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 |
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| 95 | #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 |
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| 96 | #define mmSRBM_ISP_CLKEN_CNTL 0x3b9 |
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| 97 | #define mmSRBM_DEBUG 0x3a4 |
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| 98 | #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 |
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| 99 | #define mmSRBM_DEBUG_SNAPSHOT2 0x3ad |
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| 100 | #define mmSRBM_READ_ERROR 0x3a6 |
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| 101 | #define mmSRBM_READ_ERROR2 0x3ae |
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| 102 | #define mmSRBM_INT_CNTL 0x3a8 |
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| 103 | #define mmSRBM_INT_STATUS 0x3a9 |
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| 104 | #define mmSRBM_INT_ACK 0x3aa |
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| 105 | #define mmSRBM_FIREWALL_ERROR_SRC 0x3ab |
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| 106 | #define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac |
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| 107 | #define mmSRBM_DSM_TRIG_CNTL0 0x3af |
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| 108 | #define mmSRBM_DSM_TRIG_CNTL1 0x3b0 |
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| 109 | #define mmSRBM_DSM_TRIG_MASK0 0x3b1 |
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| 110 | #define mmSRBM_DSM_TRIG_MASK1 0x3b2 |
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| 111 | #define mmSRBM_PERFMON_CNTL 0x7c00 |
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| 112 | #define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 |
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| 113 | #define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 |
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| 114 | #define mmSRBM_PERFCOUNTER0_LO 0x7c03 |
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| 115 | #define mmSRBM_PERFCOUNTER0_HI 0x7c04 |
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| 116 | #define mmSRBM_PERFCOUNTER1_LO 0x7c05 |
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| 117 | #define mmSRBM_PERFCOUNTER1_HI 0x7c06 |
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| 118 | #define mmSRBM_CAM_INDEX 0xfe34 |
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| 119 | #define mmSRBM_CAM_DATA 0xfe35 |
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| 120 | #define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 |
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| 121 | #define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 |
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| 122 | #define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 |
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| 123 | #define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 |
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| 124 | #define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 |
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| 125 | #define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 |
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| 126 | #define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 |
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| 127 | #define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 |
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| 128 | #define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 |
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| 129 | #define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a |
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| 130 | #define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b |
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| 131 | #define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c |
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| 132 | #define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d |
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| 133 | #define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e |
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| 134 | #define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 |
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| 135 | #define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 |
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| 136 | #define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 |
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| 137 | #define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 |
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| 138 | #define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 |
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| 139 | #define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 |
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| 140 | #define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 |
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| 141 | #define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 |
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| 142 | #define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 |
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| 143 | #define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a |
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| 144 | #define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c |
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| 145 | #define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d |
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| 146 | #define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e |
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| 147 | #define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 |
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| 148 | #define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 |
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| 149 | #define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 |
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| 150 | #define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c |
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| 151 | #define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d |
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| 152 | #define mmSRBM_GFX_CNTL_SELECT 0xfa2e |
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| 153 | #define mmSRBM_GFX_CNTL_DATA 0xfa2f |
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| 154 | #define mmSRBM_VF_ENABLE 0xfa30 |
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| 155 | #define mmSRBM_VIRT_CNTL 0xfa31 |
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| 156 | #define mmSRBM_VIRT_RESET_REQ 0xfa32 |
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| 157 | #define mmSDMA0_UCODE_ADDR 0x3400 |
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| 158 | #define mmSDMA0_UCODE_DATA 0x3401 |
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| 159 | #define mmSDMA0_POWER_CNTL 0x3402 |
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| 160 | #define mmSDMA0_CLK_CTRL 0x3403 |
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| 161 | #define mmSDMA0_CNTL 0x3404 |
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| 162 | #define mmSDMA0_CHICKEN_BITS 0x3405 |
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| 163 | #define mmSDMA0_TILING_CONFIG 0x3406 |
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| 164 | #define mmSDMA0_HASH 0x3407 |
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| 165 | #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 |
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| 166 | #define mmSDMA0_RB_RPTR_FETCH 0x340a |
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| 167 | #define mmSDMA0_IB_OFFSET_FETCH 0x340b |
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| 168 | #define mmSDMA0_PROGRAM 0x340c |
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| 169 | #define mmSDMA0_STATUS_REG 0x340d |
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| 170 | #define mmSDMA0_STATUS1_REG 0x340e |
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| 171 | #define mmSDMA0_PERFMON_CNTL 0x9000 |
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| 172 | #define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 |
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| 173 | #define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 |
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| 174 | #define mmSDMA0_F32_CNTL 0x3412 |
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| 175 | #define mmSDMA0_FREEZE 0x3413 |
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| 176 | #define mmSDMA0_PHASE0_QUANTUM 0x3414 |
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| 177 | #define mmSDMA0_PHASE1_QUANTUM 0x3415 |
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| 178 | #define mmSDMA_POWER_GATING 0x3416 |
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| 179 | #define mmSDMA_PGFSM_CONFIG 0x3417 |
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| 180 | #define mmSDMA_PGFSM_WRITE 0x3418 |
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| 181 | #define mmSDMA_PGFSM_READ 0x3419 |
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| 182 | #define mmSDMA0_EDC_CONFIG 0x341a |
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| 183 | #define mmSDMA0_BA_THRESHOLD 0x341b |
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| 184 | #define mmSDMA0_ID 0x341c |
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| 185 | #define mmSDMA0_VERSION 0x341d |
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| 186 | #define mmSDMA0_STATUS2_REG 0x341e |
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| 187 | #define mmSDMA0_GFX_RB_CNTL 0x3480 |
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| 188 | #define mmSDMA0_GFX_RB_BASE 0x3481 |
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| 189 | #define mmSDMA0_GFX_RB_BASE_HI 0x3482 |
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| 190 | #define mmSDMA0_GFX_RB_RPTR 0x3483 |
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| 191 | #define mmSDMA0_GFX_RB_WPTR 0x3484 |
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| 192 | #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 |
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| 193 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 |
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| 194 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 |
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| 195 | #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 |
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| 196 | #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 |
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| 197 | #define mmSDMA0_GFX_IB_CNTL 0x348a |
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| 198 | #define mmSDMA0_GFX_IB_RPTR 0x348b |
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| 199 | #define mmSDMA0_GFX_IB_OFFSET 0x348c |
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| 200 | #define mmSDMA0_GFX_IB_BASE_LO 0x348d |
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| 201 | #define mmSDMA0_GFX_IB_BASE_HI 0x348e |
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| 202 | #define mmSDMA0_GFX_IB_SIZE 0x348f |
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| 203 | #define mmSDMA0_GFX_SKIP_CNTL 0x3490 |
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| 204 | #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 |
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| 205 | #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 |
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| 206 | #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 |
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| 207 | #define mmSDMA0_GFX_APE1_CNTL 0x34a8 |
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| 208 | #define mmSDMA0_GFX_WATERMARK 0x34aa |
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| 209 | #define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac |
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| 210 | #define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad |
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| 211 | #define mmSDMA0_GFX_DUMMY_REG 0x34ae |
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| 212 | #define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af |
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| 213 | #define mmSDMA0_GFX_PREEMPT 0x34b0 |
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| 214 | #define mmSDMA0_RLC0_RB_CNTL 0x3500 |
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| 215 | #define mmSDMA0_RLC0_RB_BASE 0x3501 |
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| 216 | #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 |
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| 217 | #define mmSDMA0_RLC0_RB_RPTR 0x3503 |
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| 218 | #define mmSDMA0_RLC0_RB_WPTR 0x3504 |
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| 219 | #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 |
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| 220 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 |
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| 221 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 |
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| 222 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 |
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| 223 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 |
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| 224 | #define mmSDMA0_RLC0_IB_CNTL 0x350a |
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| 225 | #define mmSDMA0_RLC0_IB_RPTR 0x350b |
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| 226 | #define mmSDMA0_RLC0_IB_OFFSET 0x350c |
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| 227 | #define mmSDMA0_RLC0_IB_BASE_LO 0x350d |
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| 228 | #define mmSDMA0_RLC0_IB_BASE_HI 0x350e |
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| 229 | #define mmSDMA0_RLC0_IB_SIZE 0x350f |
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| 230 | #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 |
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| 231 | #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 |
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| 232 | #define mmSDMA0_RLC0_DOORBELL 0x3512 |
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| 233 | #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 |
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| 234 | #define mmSDMA0_RLC0_APE1_CNTL 0x3528 |
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| 235 | #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 |
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| 236 | #define mmSDMA0_RLC0_WATERMARK 0x352a |
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| 237 | #define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c |
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| 238 | #define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d |
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| 239 | #define mmSDMA0_RLC0_DUMMY_REG 0x352e |
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| 240 | #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f |
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| 241 | #define mmSDMA0_RLC0_PREEMPT 0x3530 |
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| 242 | #define mmSDMA0_RLC1_RB_CNTL 0x3580 |
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| 243 | #define mmSDMA0_RLC1_RB_BASE 0x3581 |
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| 244 | #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 |
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| 245 | #define mmSDMA0_RLC1_RB_RPTR 0x3583 |
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| 246 | #define mmSDMA0_RLC1_RB_WPTR 0x3584 |
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| 247 | #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 |
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| 248 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 |
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| 249 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 |
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| 250 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 |
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| 251 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 |
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| 252 | #define mmSDMA0_RLC1_IB_CNTL 0x358a |
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| 253 | #define mmSDMA0_RLC1_IB_RPTR 0x358b |
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| 254 | #define mmSDMA0_RLC1_IB_OFFSET 0x358c |
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| 255 | #define mmSDMA0_RLC1_IB_BASE_LO 0x358d |
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| 256 | #define mmSDMA0_RLC1_IB_BASE_HI 0x358e |
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| 257 | #define mmSDMA0_RLC1_IB_SIZE 0x358f |
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| 258 | #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 |
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| 259 | #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 |
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| 260 | #define mmSDMA0_RLC1_DOORBELL 0x3592 |
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| 261 | #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 |
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| 262 | #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 |
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| 263 | #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 |
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| 264 | #define mmSDMA0_RLC1_WATERMARK 0x35aa |
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| 265 | #define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac |
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| 266 | #define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad |
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| 267 | #define mmSDMA0_RLC1_DUMMY_REG 0x35ae |
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| 268 | #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af |
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| 269 | #define mmSDMA0_RLC1_PREEMPT 0x35b0 |
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| 270 | #define mmSDMA1_UCODE_ADDR 0x3600 |
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| 271 | #define mmSDMA1_UCODE_DATA 0x3601 |
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| 272 | #define mmSDMA1_POWER_CNTL 0x3602 |
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| 273 | #define mmSDMA1_CLK_CTRL 0x3603 |
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| 274 | #define mmSDMA1_CNTL 0x3604 |
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| 275 | #define mmSDMA1_CHICKEN_BITS 0x3605 |
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| 276 | #define mmSDMA1_TILING_CONFIG 0x3606 |
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| 277 | #define mmSDMA1_HASH 0x3607 |
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| 278 | #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 |
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| 279 | #define mmSDMA1_RB_RPTR_FETCH 0x360a |
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| 280 | #define mmSDMA1_IB_OFFSET_FETCH 0x360b |
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| 281 | #define mmSDMA1_PROGRAM 0x360c |
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| 282 | #define mmSDMA1_STATUS_REG 0x360d |
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| 283 | #define mmSDMA1_STATUS1_REG 0x360e |
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| 284 | #define mmSDMA1_PERFMON_CNTL 0x9010 |
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| 285 | #define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 |
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| 286 | #define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 |
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| 287 | #define mmSDMA1_F32_CNTL 0x3612 |
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| 288 | #define mmSDMA1_FREEZE 0x3613 |
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| 289 | #define mmSDMA1_PHASE0_QUANTUM 0x3614 |
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| 290 | #define mmSDMA1_PHASE1_QUANTUM 0x3615 |
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| 291 | #define mmSDMA1_EDC_CONFIG 0x361a |
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| 292 | #define mmSDMA1_BA_THRESHOLD 0x361b |
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| 293 | #define mmSDMA1_ID 0x361c |
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| 294 | #define mmSDMA1_VERSION 0x361d |
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| 295 | #define mmSDMA1_STATUS2_REG 0x361e |
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| 296 | #define mmSDMA1_GFX_RB_CNTL 0x3680 |
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| 297 | #define mmSDMA1_GFX_RB_BASE 0x3681 |
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| 298 | #define mmSDMA1_GFX_RB_BASE_HI 0x3682 |
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| 299 | #define mmSDMA1_GFX_RB_RPTR 0x3683 |
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| 300 | #define mmSDMA1_GFX_RB_WPTR 0x3684 |
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| 301 | #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 |
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| 302 | #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 |
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| 303 | #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 |
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| 304 | #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 |
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| 305 | #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 |
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| 306 | #define mmSDMA1_GFX_IB_CNTL 0x368a |
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| 307 | #define mmSDMA1_GFX_IB_RPTR 0x368b |
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| 308 | #define mmSDMA1_GFX_IB_OFFSET 0x368c |
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| 309 | #define mmSDMA1_GFX_IB_BASE_LO 0x368d |
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| 310 | #define mmSDMA1_GFX_IB_BASE_HI 0x368e |
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| 311 | #define mmSDMA1_GFX_IB_SIZE 0x368f |
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| 312 | #define mmSDMA1_GFX_SKIP_CNTL 0x3690 |
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| 313 | #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 |
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| 314 | #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 |
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| 315 | #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 |
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| 316 | #define mmSDMA1_GFX_APE1_CNTL 0x36a8 |
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| 317 | #define mmSDMA1_GFX_WATERMARK 0x36aa |
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| 318 | #define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac |
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| 319 | #define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad |
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| 320 | #define mmSDMA1_GFX_DUMMY_REG 0x36ae |
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| 321 | #define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af |
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| 322 | #define mmSDMA1_GFX_PREEMPT 0x36b0 |
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| 323 | #define mmSDMA1_RLC0_RB_CNTL 0x3700 |
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| 324 | #define mmSDMA1_RLC0_RB_BASE 0x3701 |
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| 325 | #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 |
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| 326 | #define mmSDMA1_RLC0_RB_RPTR 0x3703 |
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| 327 | #define mmSDMA1_RLC0_RB_WPTR 0x3704 |
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| 328 | #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 |
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| 329 | #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 |
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| 330 | #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 |
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| 331 | #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 |
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| 332 | #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 |
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| 333 | #define mmSDMA1_RLC0_IB_CNTL 0x370a |
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| 334 | #define mmSDMA1_RLC0_IB_RPTR 0x370b |
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| 335 | #define mmSDMA1_RLC0_IB_OFFSET 0x370c |
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| 336 | #define mmSDMA1_RLC0_IB_BASE_LO 0x370d |
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| 337 | #define mmSDMA1_RLC0_IB_BASE_HI 0x370e |
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| 338 | #define mmSDMA1_RLC0_IB_SIZE 0x370f |
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| 339 | #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 |
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| 340 | #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 |
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| 341 | #define mmSDMA1_RLC0_DOORBELL 0x3712 |
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| 342 | #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 |
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| 343 | #define mmSDMA1_RLC0_APE1_CNTL 0x3728 |
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| 344 | #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 |
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| 345 | #define mmSDMA1_RLC0_WATERMARK 0x372a |
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| 346 | #define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c |
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| 347 | #define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d |
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| 348 | #define mmSDMA1_RLC0_DUMMY_REG 0x372e |
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| 349 | #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f |
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| 350 | #define mmSDMA1_RLC0_PREEMPT 0x3730 |
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| 351 | #define mmSDMA1_RLC1_RB_CNTL 0x3780 |
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| 352 | #define mmSDMA1_RLC1_RB_BASE 0x3781 |
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| 353 | #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 |
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| 354 | #define mmSDMA1_RLC1_RB_RPTR 0x3783 |
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| 355 | #define mmSDMA1_RLC1_RB_WPTR 0x3784 |
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| 356 | #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 |
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| 357 | #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 |
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| 358 | #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 |
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| 359 | #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 |
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| 360 | #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 |
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| 361 | #define mmSDMA1_RLC1_IB_CNTL 0x378a |
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| 362 | #define mmSDMA1_RLC1_IB_RPTR 0x378b |
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| 363 | #define mmSDMA1_RLC1_IB_OFFSET 0x378c |
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| 364 | #define mmSDMA1_RLC1_IB_BASE_LO 0x378d |
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| 365 | #define mmSDMA1_RLC1_IB_BASE_HI 0x378e |
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| 366 | #define mmSDMA1_RLC1_IB_SIZE 0x378f |
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| 367 | #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 |
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| 368 | #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 |
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| 369 | #define mmSDMA1_RLC1_DOORBELL 0x3792 |
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| 370 | #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 |
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| 371 | #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 |
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| 372 | #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 |
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| 373 | #define mmSDMA1_RLC1_WATERMARK 0x37aa |
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| 374 | #define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac |
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| 375 | #define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad |
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| 376 | #define mmSDMA1_RLC1_DUMMY_REG 0x37ae |
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| 377 | #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af |
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| 378 | #define mmSDMA1_RLC1_PREEMPT 0x37b0 |
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| 379 | #define mmHDP_HOST_PATH_CNTL 0xb00 |
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| 380 | #define mmHDP_NONSURFACE_BASE 0xb01 |
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| 381 | #define mmHDP_NONSURFACE_INFO 0xb02 |
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| 382 | #define mmHDP_NONSURFACE_SIZE 0xb03 |
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| 383 | #define mmHDP_NONSURF_FLAGS 0xbc9 |
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| 384 | #define mmHDP_NONSURF_FLAGS_CLR 0xbca |
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| 385 | #define mmHDP_SW_SEMAPHORE 0xbcb |
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| 386 | #define mmHDP_DEBUG0 0xbcc |
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| 387 | #define mmHDP_DEBUG1 0xbcd |
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| 388 | #define mmHDP_LAST_SURFACE_HIT 0xbce |
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| 389 | #define mmHDP_TILING_CONFIG 0xbcf |
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| 390 | #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 |
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| 391 | #define mmHDP_OUTSTANDING_REQ 0xbd1 |
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| 392 | #define mmHDP_ADDR_CONFIG 0xbd2 |
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| 393 | #define mmHDP_MISC_CNTL 0xbd3 |
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| 394 | #define mmHDP_MEM_POWER_LS 0xbd4 |
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| 395 | #define mmHDP_NONSURFACE_PREFETCH 0xbd5 |
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| 396 | #define mmHDP_MEMIO_CNTL 0xbf6 |
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| 397 | #define mmHDP_MEMIO_ADDR 0xbf7 |
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| 398 | #define mmHDP_MEMIO_STATUS 0xbf8 |
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| 399 | #define mmHDP_MEMIO_WR_DATA 0xbf9 |
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| 400 | #define mmHDP_MEMIO_RD_DATA 0xbfa |
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| 401 | #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 |
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| 402 | #define mmHDP_XDP_D2H_FLUSH 0xc01 |
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| 403 | #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 |
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| 404 | #define mmHDP_XDP_D2H_RSVD_3 0xc03 |
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| 405 | #define mmHDP_XDP_D2H_RSVD_4 0xc04 |
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| 406 | #define mmHDP_XDP_D2H_RSVD_5 0xc05 |
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| 407 | #define mmHDP_XDP_D2H_RSVD_6 0xc06 |
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| 408 | #define mmHDP_XDP_D2H_RSVD_7 0xc07 |
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| 409 | #define mmHDP_XDP_D2H_RSVD_8 0xc08 |
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| 410 | #define mmHDP_XDP_D2H_RSVD_9 0xc09 |
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| 411 | #define mmHDP_XDP_D2H_RSVD_10 0xc0a |
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| 412 | #define mmHDP_XDP_D2H_RSVD_11 0xc0b |
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| 413 | #define mmHDP_XDP_D2H_RSVD_12 0xc0c |
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| 414 | #define mmHDP_XDP_D2H_RSVD_13 0xc0d |
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| 415 | #define mmHDP_XDP_D2H_RSVD_14 0xc0e |
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| 416 | #define mmHDP_XDP_D2H_RSVD_15 0xc0f |
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| 417 | #define mmHDP_XDP_D2H_RSVD_16 0xc10 |
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| 418 | #define mmHDP_XDP_D2H_RSVD_17 0xc11 |
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| 419 | #define mmHDP_XDP_D2H_RSVD_18 0xc12 |
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| 420 | #define mmHDP_XDP_D2H_RSVD_19 0xc13 |
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| 421 | #define mmHDP_XDP_D2H_RSVD_20 0xc14 |
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| 422 | #define mmHDP_XDP_D2H_RSVD_21 0xc15 |
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| 423 | #define mmHDP_XDP_D2H_RSVD_22 0xc16 |
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| 424 | #define mmHDP_XDP_D2H_RSVD_23 0xc17 |
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| 425 | #define mmHDP_XDP_D2H_RSVD_24 0xc18 |
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| 426 | #define mmHDP_XDP_D2H_RSVD_25 0xc19 |
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| 427 | #define mmHDP_XDP_D2H_RSVD_26 0xc1a |
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| 428 | #define mmHDP_XDP_D2H_RSVD_27 0xc1b |
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| 429 | #define mmHDP_XDP_D2H_RSVD_28 0xc1c |
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| 430 | #define mmHDP_XDP_D2H_RSVD_29 0xc1d |
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| 431 | #define mmHDP_XDP_D2H_RSVD_30 0xc1e |
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| 432 | #define mmHDP_XDP_D2H_RSVD_31 0xc1f |
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| 433 | #define mmHDP_XDP_D2H_RSVD_32 0xc20 |
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| 434 | #define mmHDP_XDP_D2H_RSVD_33 0xc21 |
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| 435 | #define mmHDP_XDP_D2H_RSVD_34 0xc22 |
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| 436 | #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 |
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| 437 | #define mmHDP_XDP_P2P_BAR_CFG 0xc24 |
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| 438 | #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 |
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| 439 | #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 |
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| 440 | #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 |
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| 441 | #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 |
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| 442 | #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 |
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| 443 | #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a |
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| 444 | #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b |
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| 445 | #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c |
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| 446 | #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d |
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| 447 | #define mmHDP_XDP_HDP_MC_CFG 0xc2e |
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| 448 | #define mmHDP_XDP_HST_CFG 0xc2f |
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| 449 | #define mmHDP_XDP_SID_CFG 0xc30 |
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| 450 | #define mmHDP_XDP_HDP_IPH_CFG 0xc31 |
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| 451 | #define mmHDP_XDP_SRBM_CFG 0xc32 |
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| 452 | #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 |
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| 453 | #define mmHDP_XDP_P2P_BAR0 0xc34 |
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| 454 | #define mmHDP_XDP_P2P_BAR1 0xc35 |
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| 455 | #define mmHDP_XDP_P2P_BAR2 0xc36 |
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| 456 | #define mmHDP_XDP_P2P_BAR3 0xc37 |
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| 457 | #define mmHDP_XDP_P2P_BAR4 0xc38 |
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| 458 | #define mmHDP_XDP_P2P_BAR5 0xc39 |
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| 459 | #define mmHDP_XDP_P2P_BAR6 0xc3a |
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| 460 | #define mmHDP_XDP_P2P_BAR7 0xc3b |
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| 461 | #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c |
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| 462 | #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d |
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| 463 | #define mmHDP_XDP_BUSY_STS 0xc3e |
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| 464 | #define mmHDP_XDP_STICKY 0xc3f |
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| 465 | #define mmHDP_XDP_CHKN 0xc40 |
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| 466 | #define mmHDP_XDP_DBG_ADDR 0xc41 |
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| 467 | #define mmHDP_XDP_DBG_DATA 0xc42 |
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| 468 | #define mmHDP_XDP_DBG_MASK 0xc43 |
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| 469 | #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 |
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| 470 | |
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| 471 | #endif /* OSS_2_4_D_H */ |
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| 472 | |
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