1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _HARDWARE_MANAGER_H_ |
24 | #define _HARDWARE_MANAGER_H_ |
25 | |
26 | |
27 | |
28 | struct pp_hwmgr; |
29 | struct pp_hw_power_state; |
30 | struct pp_power_state; |
31 | enum amd_dpm_forced_level; |
32 | struct PP_TemperatureRange; |
33 | |
34 | |
35 | struct phm_fan_speed_info { |
36 | uint32_t min_percent; |
37 | uint32_t max_percent; |
38 | uint32_t min_rpm; |
39 | uint32_t max_rpm; |
40 | bool supports_percent_read; |
41 | bool supports_percent_write; |
42 | bool supports_rpm_read; |
43 | bool supports_rpm_write; |
44 | }; |
45 | |
46 | /* Automatic Power State Throttling */ |
47 | enum PHM_AutoThrottleSource { |
48 | PHM_AutoThrottleSource_Thermal, |
49 | PHM_AutoThrottleSource_External |
50 | }; |
51 | |
52 | typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource; |
53 | |
54 | enum phm_platform_caps { |
55 | PHM_PlatformCaps_AtomBiosPpV1 = 0, |
56 | PHM_PlatformCaps_PowerPlaySupport, |
57 | PHM_PlatformCaps_ACOverdriveSupport, |
58 | PHM_PlatformCaps_BacklightSupport, |
59 | PHM_PlatformCaps_ThermalController, |
60 | PHM_PlatformCaps_BiosPowerSourceControl, |
61 | PHM_PlatformCaps_DisableVoltageTransition, |
62 | PHM_PlatformCaps_DisableEngineTransition, |
63 | PHM_PlatformCaps_DisableMemoryTransition, |
64 | PHM_PlatformCaps_DynamicPowerManagement, |
65 | PHM_PlatformCaps_EnableASPML0s, |
66 | PHM_PlatformCaps_EnableASPML1, |
67 | PHM_PlatformCaps_OD5inACSupport, |
68 | PHM_PlatformCaps_OD5inDCSupport, |
69 | PHM_PlatformCaps_SoftStateOD5, |
70 | PHM_PlatformCaps_NoOD5Support, |
71 | PHM_PlatformCaps_ContinuousHardwarePerformanceRange, |
72 | PHM_PlatformCaps_ActivityReporting, |
73 | PHM_PlatformCaps_EnableBackbias, |
74 | PHM_PlatformCaps_OverdriveDisabledByPowerBudget, |
75 | PHM_PlatformCaps_ShowPowerBudgetWarning, |
76 | PHM_PlatformCaps_PowerBudgetWaiverAvailable, |
77 | PHM_PlatformCaps_GFXClockGatingSupport, |
78 | PHM_PlatformCaps_MMClockGatingSupport, |
79 | PHM_PlatformCaps_AutomaticDCTransition, |
80 | PHM_PlatformCaps_GeminiPrimary, |
81 | PHM_PlatformCaps_MemorySpreadSpectrumSupport, |
82 | PHM_PlatformCaps_EngineSpreadSpectrumSupport, |
83 | PHM_PlatformCaps_StepVddc, |
84 | PHM_PlatformCaps_DynamicPCIEGen2Support, |
85 | PHM_PlatformCaps_SMC, |
86 | PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */ |
87 | PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */ |
88 | PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */ |
89 | PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */ |
90 | PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */ |
91 | PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */ |
92 | PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */ |
93 | PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */ |
94 | PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */ |
95 | PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */ |
96 | PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */ |
97 | PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */ |
98 | PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */ |
99 | PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */ |
100 | PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */ |
101 | PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */ |
102 | PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */ |
103 | PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */ |
104 | PHM_PlatformCaps_ABM, /* ABM support.*/ |
105 | PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */ |
106 | PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */ |
107 | PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */ |
108 | PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */ |
109 | PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */ |
110 | PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */ |
111 | PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */ |
112 | PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */ |
113 | PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */ |
114 | PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */ |
115 | PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */ |
116 | PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */ |
117 | PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */ |
118 | PHM_PlatformCaps_AdjustUVDPriorityForSP, |
119 | PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */ |
120 | PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */ |
121 | PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */ |
122 | PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */ |
123 | PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */ |
124 | PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */ |
125 | PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */ |
126 | PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */ |
127 | PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */ |
128 | PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */ |
129 | PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */ |
130 | PHM_PlatformCaps_BLControlledByGPU, /* support varibright */ |
131 | PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */ |
132 | PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */ |
133 | PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */ |
134 | PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */ |
135 | PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */ |
136 | PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */ |
137 | PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */ |
138 | PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */ |
139 | PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */ |
140 | PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */ |
141 | PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */ |
142 | PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */ |
143 | PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */ |
144 | PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */ |
145 | PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */ |
146 | PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/ |
147 | PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */ |
148 | PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */ |
149 | PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */ |
150 | PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */ |
151 | PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */ |
152 | PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */ |
153 | PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */ |
154 | PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */ |
155 | PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */ |
156 | PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */ |
157 | PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ |
158 | PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */ |
159 | PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */ |
160 | PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ |
161 | PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */ |
162 | PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */ |
163 | PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */ |
164 | PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */ |
165 | PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */ |
166 | PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature */ |
167 | PHM_PlatformCaps_DBRamping, /* for dI/dT feature */ |
168 | PHM_PlatformCaps_TDRamping, /* for dI/dT feature */ |
169 | PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */ |
170 | PHM_PlatformCaps_DBRRamping, /* for dI/dT feature */ |
171 | PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature */ |
172 | PHM_PlatformCaps_GCEDC, /* for dI/dT feature */ |
173 | PHM_PlatformCaps_PSM, /* for dI/dT feature */ |
174 | PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */ |
175 | PHM_PlatformCaps_FPS, /* FPS support */ |
176 | PHM_PlatformCaps_ACP, /* ACP support */ |
177 | PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */ |
178 | PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */ |
179 | PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */ |
180 | PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */ |
181 | PHM_PlatformCaps_VddNBDirectRequest, |
182 | PHM_PlatformCaps_PauseMMSessions, |
183 | PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */ |
184 | PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */ |
185 | PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */ |
186 | PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */ |
187 | PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */ |
188 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */ |
189 | PHM_PlatformCaps_ForceMclkHigh, /* Disable memory clock switching by forcing memory clock high */ |
190 | PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */ |
191 | PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */ |
192 | PHM_PlatformCaps_IOIC3, |
193 | PHM_PlatformCaps_ConnectedStandby, |
194 | PHM_PlatformCaps_EVV, |
195 | PHM_PlatformCaps_EnableLongIdleBACOSupport, |
196 | PHM_PlatformCaps_CombinePCCWithThermalSignal, |
197 | PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc, |
198 | PHM_PlatformCaps_StablePState, |
199 | PHM_PlatformCaps_OD6PlusinACSupport, |
200 | PHM_PlatformCaps_OD6PlusinDCSupport, |
201 | PHM_PlatformCaps_ODThermalLimitUnlock, |
202 | PHM_PlatformCaps_ReducePowerLimit, |
203 | PHM_PlatformCaps_ODFuzzyFanControlSupport, |
204 | PHM_PlatformCaps_GeminiRegulatorFanControlSupport, |
205 | PHM_PlatformCaps_ControlVDDGFX, |
206 | PHM_PlatformCaps_BBBSupported, |
207 | PHM_PlatformCaps_DisableVoltageIsland, |
208 | PHM_PlatformCaps_FanSpeedInTableIsRPM, |
209 | PHM_PlatformCaps_GFXClockGatingManagedInCAIL, |
210 | PHM_PlatformCaps_IcelandULPSSWWorkAround, |
211 | PHM_PlatformCaps_FPSEnhancement, |
212 | PHM_PlatformCaps_LoadPostProductionFirmware, |
213 | PHM_PlatformCaps_VpuRecoveryInProgress, |
214 | PHM_PlatformCaps_Falcon_QuickTransition, |
215 | PHM_PlatformCaps_AVFS, |
216 | PHM_PlatformCaps_ClockStretcher, |
217 | PHM_PlatformCaps_TablelessHardwareInterface, |
218 | PHM_PlatformCaps_EnableDriverEVV, |
219 | PHM_PlatformCaps_SPLLShutdownSupport, |
220 | PHM_PlatformCaps_VirtualBatteryState, |
221 | PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs, |
222 | PHM_PlatformCaps_DisableMclkSwitchForVR, |
223 | PHM_PlatformCaps_SMU8, |
224 | PHM_PlatformCaps_VRHotPolarityHigh, |
225 | PHM_PlatformCaps_IPS_UlpsExclusive, |
226 | PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme, |
227 | PHM_PlatformCaps_GeminiAsymmetricPower, |
228 | PHM_PlatformCaps_OCLPowerOptimization, |
229 | PHM_PlatformCaps_MaxPCIEBandWidth, |
230 | PHM_PlatformCaps_PerfPerWattOptimizationSupport, |
231 | PHM_PlatformCaps_UVDClientMCTuning, |
232 | PHM_PlatformCaps_ODNinACSupport, |
233 | PHM_PlatformCaps_ODNinDCSupport, |
234 | PHM_PlatformCaps_OD8inACSupport, |
235 | PHM_PlatformCaps_OD8inDCSupport, |
236 | PHM_PlatformCaps_UMDPState, |
237 | PHM_PlatformCaps_AutoWattmanSupport, |
238 | PHM_PlatformCaps_AutoWattmanEnable_CCCState, |
239 | PHM_PlatformCaps_FreeSyncActive, |
240 | PHM_PlatformCaps_EnableShadowPstate, |
241 | PHM_PlatformCaps_customThermalManagement, |
242 | PHM_PlatformCaps_staticFanControl, |
243 | PHM_PlatformCaps_Virtual_System, |
244 | PHM_PlatformCaps_LowestUclkReservedForUlv, |
245 | PHM_PlatformCaps_EnableBoostState, |
246 | PHM_PlatformCaps_AVFSSupport, |
247 | PHM_PlatformCaps_ThermalPolicyDelay, |
248 | PHM_PlatformCaps_CustomFanControlSupport, |
249 | PHM_PlatformCaps_BAMACO, |
250 | PHM_PlatformCaps_Max |
251 | }; |
252 | |
253 | #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8) |
254 | |
255 | /* Number of uint32_t entries used by CAPS table */ |
256 | #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \ |
257 | ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD)) |
258 | |
259 | struct pp_hw_descriptor { |
260 | uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; |
261 | }; |
262 | |
263 | enum PHM_PerformanceLevelDesignation { |
264 | PHM_PerformanceLevelDesignation_Activity, |
265 | PHM_PerformanceLevelDesignation_PowerContainment |
266 | }; |
267 | |
268 | typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation; |
269 | |
270 | struct PHM_PerformanceLevel { |
271 | uint32_t coreClock; |
272 | uint32_t memory_clock; |
273 | uint32_t vddc; |
274 | uint32_t vddci; |
275 | uint32_t nonLocalMemoryFreq; |
276 | uint32_t nonLocalMemoryWidth; |
277 | }; |
278 | |
279 | typedef struct PHM_PerformanceLevel PHM_PerformanceLevel; |
280 | |
281 | /* Function for setting a platform cap */ |
282 | static inline void phm_cap_set(uint32_t *caps, |
283 | enum phm_platform_caps c) |
284 | { |
285 | caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL << |
286 | (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); |
287 | } |
288 | |
289 | static inline void phm_cap_unset(uint32_t *caps, |
290 | enum phm_platform_caps c) |
291 | { |
292 | caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); |
293 | } |
294 | |
295 | static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c) |
296 | { |
297 | return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] & |
298 | (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); |
299 | } |
300 | |
301 | #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c)) |
302 | |
303 | #define PP_PCIEGenInvalid 0xffff |
304 | enum PP_PCIEGen { |
305 | PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */ |
306 | PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */ |
307 | PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */ |
308 | }; |
309 | |
310 | typedef enum PP_PCIEGen PP_PCIEGen; |
311 | |
312 | #define PP_Min_PCIEGen PP_PCIEGen1 |
313 | #define PP_Max_PCIEGen PP_PCIEGen3 |
314 | #define PP_Min_PCIELane 1 |
315 | #define PP_Max_PCIELane 16 |
316 | |
317 | enum phm_clock_Type { |
318 | PHM_DispClock = 1, |
319 | PHM_SClock, |
320 | PHM_MemClock |
321 | }; |
322 | |
323 | #define MAX_NUM_CLOCKS 16 |
324 | |
325 | struct PP_Clocks { |
326 | uint32_t engineClock; |
327 | uint32_t memoryClock; |
328 | uint32_t BusBandwidth; |
329 | uint32_t engineClockInSR; |
330 | uint32_t dcefClock; |
331 | uint32_t dcefClockInSR; |
332 | }; |
333 | |
334 | struct pp_clock_info { |
335 | uint32_t min_mem_clk; |
336 | uint32_t max_mem_clk; |
337 | uint32_t min_eng_clk; |
338 | uint32_t max_eng_clk; |
339 | uint32_t min_bus_bandwidth; |
340 | uint32_t max_bus_bandwidth; |
341 | }; |
342 | |
343 | struct phm_platform_descriptor { |
344 | uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; |
345 | uint32_t vbiosInterruptId; |
346 | struct PP_Clocks overdriveLimit; |
347 | struct PP_Clocks clockStep; |
348 | uint32_t hardwareActivityPerformanceLevels; |
349 | uint32_t minimumClocksReductionPercentage; |
350 | uint32_t minOverdriveVDDC; |
351 | uint32_t maxOverdriveVDDC; |
352 | uint32_t overdriveVDDCStep; |
353 | uint32_t hardwarePerformanceLevels; |
354 | uint16_t powerBudget; |
355 | uint32_t TDPLimit; |
356 | uint32_t nearTDPLimit; |
357 | uint32_t nearTDPLimitAdjusted; |
358 | uint32_t SQRampingThreshold; |
359 | uint32_t CACLeakage; |
360 | uint16_t TDPODLimit; |
361 | uint32_t TDPAdjustment; |
362 | bool TDPAdjustmentPolarity; |
363 | uint16_t LoadLineSlope; |
364 | uint32_t VidMinLimit; |
365 | uint32_t VidMaxLimit; |
366 | uint32_t VidStep; |
367 | uint32_t VidAdjustment; |
368 | bool VidAdjustmentPolarity; |
369 | }; |
370 | |
371 | struct phm_clocks { |
372 | uint32_t num_of_entries; |
373 | uint32_t clock[MAX_NUM_CLOCKS]; |
374 | }; |
375 | |
376 | #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 |
377 | #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 |
378 | #define DPMTABLE_UPDATE_SCLK 0x00000004 |
379 | #define DPMTABLE_UPDATE_MCLK 0x00000008 |
380 | #define DPMTABLE_OD_UPDATE_VDDC 0x00000010 |
381 | #define DPMTABLE_UPDATE_SOCCLK 0x00000020 |
382 | |
383 | struct phm_odn_performance_level { |
384 | uint32_t clock; |
385 | uint32_t vddc; |
386 | bool enabled; |
387 | }; |
388 | |
389 | struct phm_odn_clock_levels { |
390 | uint32_t size; |
391 | uint32_t options; |
392 | uint32_t flags; |
393 | uint32_t num_of_pl; |
394 | /* variable-sized array, specify by num_of_pl. */ |
395 | struct phm_odn_performance_level entries[8]; |
396 | }; |
397 | |
398 | extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr); |
399 | extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr); |
400 | extern int phm_setup_asic(struct pp_hwmgr *hwmgr); |
401 | extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr); |
402 | extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr); |
403 | extern int phm_set_power_state(struct pp_hwmgr *hwmgr, |
404 | const struct pp_hw_power_state *pcurrent_state, |
405 | const struct pp_hw_power_state *pnew_power_state); |
406 | |
407 | extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, |
408 | struct pp_power_state *adjusted_ps, |
409 | const struct pp_power_state *current_ps); |
410 | |
411 | extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr); |
412 | |
413 | extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level); |
414 | extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr); |
415 | extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr); |
416 | extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); |
417 | extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr); |
418 | extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr); |
419 | extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr); |
420 | extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr); |
421 | |
422 | extern int phm_check_states_equal(struct pp_hwmgr *hwmgr, |
423 | const struct pp_hw_power_state *pstate1, |
424 | const struct pp_hw_power_state *pstate2, |
425 | bool *equal); |
426 | |
427 | extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, |
428 | const struct amd_pp_display_configuration *display_config); |
429 | |
430 | extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr, |
431 | struct amd_pp_simple_clock_info *info); |
432 | |
433 | extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr); |
434 | |
435 | extern int phm_power_down_asic(struct pp_hwmgr *hwmgr); |
436 | |
437 | extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, |
438 | PHM_PerformanceLevelDesignation designation, uint32_t index, |
439 | PHM_PerformanceLevel *level); |
440 | |
441 | extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, |
442 | struct pp_clock_info *pclock_info, |
443 | PHM_PerformanceLevelDesignation designation); |
444 | |
445 | extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); |
446 | |
447 | extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); |
448 | |
449 | extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, |
450 | enum amd_pp_clock_type type, |
451 | struct pp_clock_levels_with_latency *clocks); |
452 | extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, |
453 | enum amd_pp_clock_type type, |
454 | struct pp_clock_levels_with_voltage *clocks); |
455 | extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, |
456 | void *clock_ranges); |
457 | extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, |
458 | struct pp_display_clock_request *clock); |
459 | |
460 | extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); |
461 | extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr); |
462 | |
463 | extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count); |
464 | |
465 | #endif /* _HARDWARE_MANAGER_H_ */ |
466 | |
467 | |