1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
4 *
5 */
6#include <linux/gcd.h>
7#include <linux/gpio/consumer.h>
8#include <linux/i2c.h>
9#include <linux/interrupt.h>
10#include <linux/iopoll.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/mutex.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/slab.h>
17#include <linux/types.h>
18#include <linux/workqueue.h>
19
20#include <linux/of_graph.h>
21#include <linux/of_platform.h>
22
23#include <drm/display/drm_dp_aux_bus.h>
24#include <drm/display/drm_dp_helper.h>
25#include <drm/display/drm_hdcp_helper.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_bridge.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_mipi_dsi.h>
30#include <drm/drm_of.h>
31#include <drm/drm_panel.h>
32#include <drm/drm_print.h>
33#include <drm/drm_probe_helper.h>
34
35#include <media/v4l2-fwnode.h>
36#include <sound/hdmi-codec.h>
37#include <video/display_timing.h>
38
39#include "anx7625.h"
40
41/*
42 * There is a sync issue while access I2C register between AP(CPU) and
43 * internal firmware(OCM), to avoid the race condition, AP should access
44 * the reserved slave address before slave address occurs changes.
45 */
46static int i2c_access_workaround(struct anx7625_data *ctx,
47 struct i2c_client *client)
48{
49 u8 offset;
50 struct device *dev = &client->dev;
51 int ret;
52
53 if (client == ctx->last_client)
54 return 0;
55
56 ctx->last_client = client;
57
58 if (client == ctx->i2c.tcpc_client)
59 offset = RSVD_00_ADDR;
60 else if (client == ctx->i2c.tx_p0_client)
61 offset = RSVD_D1_ADDR;
62 else if (client == ctx->i2c.tx_p1_client)
63 offset = RSVD_60_ADDR;
64 else if (client == ctx->i2c.rx_p0_client)
65 offset = RSVD_39_ADDR;
66 else if (client == ctx->i2c.rx_p1_client)
67 offset = RSVD_7F_ADDR;
68 else
69 offset = RSVD_00_ADDR;
70
71 ret = i2c_smbus_write_byte_data(client, command: offset, value: 0x00);
72 if (ret < 0)
73 DRM_DEV_ERROR(dev,
74 "fail to access i2c id=%x\n:%x",
75 client->addr, offset);
76
77 return ret;
78}
79
80static int anx7625_reg_read(struct anx7625_data *ctx,
81 struct i2c_client *client, u8 reg_addr)
82{
83 int ret;
84 struct device *dev = &client->dev;
85
86 i2c_access_workaround(ctx, client);
87
88 ret = i2c_smbus_read_byte_data(client, command: reg_addr);
89 if (ret < 0)
90 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
91 client->addr, reg_addr);
92
93 return ret;
94}
95
96static int anx7625_reg_block_read(struct anx7625_data *ctx,
97 struct i2c_client *client,
98 u8 reg_addr, u8 len, u8 *buf)
99{
100 int ret;
101 struct device *dev = &client->dev;
102
103 i2c_access_workaround(ctx, client);
104
105 ret = i2c_smbus_read_i2c_block_data(client, command: reg_addr, length: len, values: buf);
106 if (ret < 0)
107 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
108 client->addr, reg_addr);
109
110 return ret;
111}
112
113static int anx7625_reg_write(struct anx7625_data *ctx,
114 struct i2c_client *client,
115 u8 reg_addr, u8 reg_val)
116{
117 int ret;
118 struct device *dev = &client->dev;
119
120 i2c_access_workaround(ctx, client);
121
122 ret = i2c_smbus_write_byte_data(client, command: reg_addr, value: reg_val);
123
124 if (ret < 0)
125 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
126 client->addr, reg_addr);
127
128 return ret;
129}
130
131static int anx7625_reg_block_write(struct anx7625_data *ctx,
132 struct i2c_client *client,
133 u8 reg_addr, u8 len, u8 *buf)
134{
135 int ret;
136 struct device *dev = &client->dev;
137
138 i2c_access_workaround(ctx, client);
139
140 ret = i2c_smbus_write_i2c_block_data(client, command: reg_addr, length: len, values: buf);
141 if (ret < 0)
142 dev_err(dev, "write i2c block failed id=%x\n:%x",
143 client->addr, reg_addr);
144
145 return ret;
146}
147
148static int anx7625_write_or(struct anx7625_data *ctx,
149 struct i2c_client *client,
150 u8 offset, u8 mask)
151{
152 int val;
153
154 val = anx7625_reg_read(ctx, client, reg_addr: offset);
155 if (val < 0)
156 return val;
157
158 return anx7625_reg_write(ctx, client, reg_addr: offset, reg_val: (val | (mask)));
159}
160
161static int anx7625_write_and(struct anx7625_data *ctx,
162 struct i2c_client *client,
163 u8 offset, u8 mask)
164{
165 int val;
166
167 val = anx7625_reg_read(ctx, client, reg_addr: offset);
168 if (val < 0)
169 return val;
170
171 return anx7625_reg_write(ctx, client, reg_addr: offset, reg_val: (val & (mask)));
172}
173
174static int anx7625_write_and_or(struct anx7625_data *ctx,
175 struct i2c_client *client,
176 u8 offset, u8 and_mask, u8 or_mask)
177{
178 int val;
179
180 val = anx7625_reg_read(ctx, client, reg_addr: offset);
181 if (val < 0)
182 return val;
183
184 return anx7625_reg_write(ctx, client,
185 reg_addr: offset, reg_val: (val & and_mask) | (or_mask));
186}
187
188static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
189{
190 int i, ret;
191
192 ret = anx7625_write_or(ctx, client: ctx->i2c.tx_p2_client,
193 AUDIO_CONTROL_REGISTER, mask: 0x80);
194 for (i = 0; i < 13; i++)
195 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p2_client,
196 VIDEO_BIT_MATRIX_12 + i,
197 reg_val: 0x18 + i);
198
199 return ret;
200}
201
202static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
203{
204 return anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
205}
206
207static int wait_aux_op_finish(struct anx7625_data *ctx)
208{
209 struct device *dev = ctx->dev;
210 int val;
211 int ret;
212
213 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
214 ctx, val,
215 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
216 2000,
217 2000 * 150);
218 if (ret) {
219 DRM_DEV_ERROR(dev, "aux operation fail!\n");
220 return -EIO;
221 }
222
223 val = anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client,
224 AP_AUX_CTRL_STATUS);
225 if (val < 0 || (val & 0x0F)) {
226 DRM_DEV_ERROR(dev, "aux status %02x\n", val);
227 return -EIO;
228 }
229
230 return 0;
231}
232
233static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
234 u8 len, u8 *buf)
235{
236 struct device *dev = ctx->dev;
237 int ret;
238 u8 addrh, addrm, addrl;
239 u8 cmd;
240 bool is_write = !(op & DP_AUX_I2C_READ);
241
242 if (len > DP_AUX_MAX_PAYLOAD_BYTES) {
243 dev_err(dev, "exceed aux buffer len.\n");
244 return -EINVAL;
245 }
246
247 if (!len)
248 return len;
249
250 addrl = address & 0xFF;
251 addrm = (address >> 8) & 0xFF;
252 addrh = (address >> 16) & 0xFF;
253
254 if (!is_write)
255 op &= ~DP_AUX_I2C_MOT;
256 cmd = DPCD_CMD(len, op);
257
258 /* Set command and length */
259 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
260 AP_AUX_COMMAND, reg_val: cmd);
261
262 /* Set aux access address */
263 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
264 AP_AUX_ADDR_7_0, reg_val: addrl);
265 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
266 AP_AUX_ADDR_15_8, reg_val: addrm);
267 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
268 AP_AUX_ADDR_19_16, reg_val: addrh);
269
270 if (is_write)
271 ret |= anx7625_reg_block_write(ctx, client: ctx->i2c.rx_p0_client,
272 AP_AUX_BUFF_START, len, buf);
273 /* Enable aux access */
274 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
276
277 if (ret < 0) {
278 dev_err(dev, "cannot access aux related register.\n");
279 return -EIO;
280 }
281
282 ret = wait_aux_op_finish(ctx);
283 if (ret < 0) {
284 dev_err(dev, "aux IO error: wait aux op finish.\n");
285 return ret;
286 }
287
288 /* Write done */
289 if (is_write)
290 return len;
291
292 /* Read done, read out dpcd data */
293 ret = anx7625_reg_block_read(ctx, client: ctx->i2c.rx_p0_client,
294 AP_AUX_BUFF_START, len, buf);
295 if (ret < 0) {
296 dev_err(dev, "read dpcd register failed\n");
297 return -EIO;
298 }
299
300 return len;
301}
302
303static int anx7625_video_mute_control(struct anx7625_data *ctx,
304 u8 status)
305{
306 int ret;
307
308 if (status) {
309 /* Set mute on flag */
310 ret = anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
311 AP_AV_STATUS, AP_MIPI_MUTE);
312 /* Clear mipi RX en */
313 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
314 AP_AV_STATUS, mask: (u8)~AP_MIPI_RX_EN);
315 } else {
316 /* Mute off flag */
317 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
318 AP_AV_STATUS, mask: (u8)~AP_MIPI_MUTE);
319 /* Set MIPI RX EN */
320 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
321 AP_AV_STATUS, AP_MIPI_RX_EN);
322 }
323
324 return ret;
325}
326
327/* Reduction of fraction a/b */
328static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
329{
330 unsigned long gcd_num;
331 unsigned long tmp_a, tmp_b;
332 u32 i = 1;
333
334 gcd_num = gcd(a: *a, b: *b);
335 *a /= gcd_num;
336 *b /= gcd_num;
337
338 tmp_a = *a;
339 tmp_b = *b;
340
341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
342 i++;
343 *a = tmp_a / i;
344 *b = tmp_b / i;
345 }
346
347 /*
348 * In the end, make a, b larger to have higher ODFC PLL
349 * output frequency accuracy
350 */
351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
352 *a <<= 1;
353 *b <<= 1;
354 }
355
356 *a >>= 1;
357 *b >>= 1;
358}
359
360static int anx7625_calculate_m_n(u32 pixelclock,
361 unsigned long *m,
362 unsigned long *n,
363 u8 *post_divider)
364{
365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
366 /* Pixel clock frequency is too high */
367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
368 pixelclock,
369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
370 return -EINVAL;
371 }
372
373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
374 /* Pixel clock frequency is too low */
375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
376 pixelclock,
377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
378 return -EINVAL;
379 }
380
381 for (*post_divider = 1;
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
383 *post_divider += 1;
384
385 if (*post_divider > POST_DIVIDER_MAX) {
386 for (*post_divider = 1;
387 (pixelclock <
388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
389 *post_divider += 1;
390
391 if (*post_divider > POST_DIVIDER_MAX) {
392 DRM_ERROR("cannot find property post_divider(%d)\n",
393 *post_divider);
394 return -EDOM;
395 }
396 }
397
398 /* Patch to improve the accuracy */
399 if (*post_divider == 7) {
400 /* 27,000,000 is not divisible by 7 */
401 *post_divider = 8;
402 } else if (*post_divider == 11) {
403 /* 27,000,000 is not divisible by 11 */
404 *post_divider = 12;
405 } else if ((*post_divider == 13) || (*post_divider == 14)) {
406 /* 27,000,000 is not divisible by 13 or 14 */
407 *post_divider = 15;
408 }
409
410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
412 pixelclock * (*post_divider),
413 PLL_OUT_FREQ_ABS_MAX);
414 return -EDOM;
415 }
416
417 *m = pixelclock;
418 *n = XTAL_FRQ / (*post_divider);
419
420 anx7625_reduction_of_a_fraction(a: m, b: n);
421
422 return 0;
423}
424
425static int anx7625_odfc_config(struct anx7625_data *ctx,
426 u8 post_divider)
427{
428 int ret;
429 struct device *dev = ctx->dev;
430
431 /* Config input reference clock frequency 27MHz/19.2MHz */
432 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
433 mask: ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
434 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
435 mask: (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
436 /* Post divider */
437 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client,
438 MIPI_DIGITAL_PLL_8, mask: 0x0f);
439 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
440 mask: post_divider << 4);
441
442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
443 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
444 mask: ~MIPI_PLL_VCO_TUNE_REG_VAL);
445
446 /* Reset ODFC PLL */
447 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
448 mask: ~MIPI_PLL_RESET_N);
449 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
450 MIPI_PLL_RESET_N);
451
452 if (ret < 0)
453 DRM_DEV_ERROR(dev, "IO error.\n");
454
455 return ret;
456}
457
458/*
459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
460 * anx7625 defined K ratio for matching MIPI input video clock and
461 * DP output video clock. Increase K value can match bigger video data
462 * variation. IVO panel has small variation than DP CTS spec, need
463 * decrease the K value.
464 */
465static int anx7625_set_k_value(struct anx7625_data *ctx)
466{
467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
468
469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
470 return anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
471 MIPI_DIGITAL_ADJ_1, reg_val: 0x3B);
472
473 return anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
474 MIPI_DIGITAL_ADJ_1, reg_val: 0x3D);
475}
476
477static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
478{
479 struct device *dev = ctx->dev;
480 unsigned long m, n;
481 u16 htotal;
482 int ret;
483 u8 post_divider = 0;
484
485 ret = anx7625_calculate_m_n(pixelclock: ctx->dt.pixelclock.min * 1000,
486 m: &m, n: &n, post_divider: &post_divider);
487
488 if (ret) {
489 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
490 return ret;
491 }
492
493 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
494 m, n, post_divider);
495
496 /* Configure pixel clock */
497 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
498 reg_val: (ctx->dt.pixelclock.min / 1000) & 0xFF);
499 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
500 reg_val: (ctx->dt.pixelclock.min / 1000) >> 8);
501 /* Lane count */
502 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client,
503 MIPI_LANE_CTRL_0, mask: 0xfc);
504 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client,
505 MIPI_LANE_CTRL_0, mask: ctx->pdata.mipi_lanes - 1);
506
507 /* Htotal */
508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
510 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
511 HORIZONTAL_TOTAL_PIXELS_L, reg_val: htotal & 0xFF);
512 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
513 HORIZONTAL_TOTAL_PIXELS_H, reg_val: htotal >> 8);
514 /* Hactive */
515 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
516 HORIZONTAL_ACTIVE_PIXELS_L, reg_val: ctx->dt.hactive.min & 0xFF);
517 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_H, reg_val: ctx->dt.hactive.min >> 8);
519 /* HFP */
520 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
521 HORIZONTAL_FRONT_PORCH_L, reg_val: ctx->dt.hfront_porch.min);
522 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
523 HORIZONTAL_FRONT_PORCH_H,
524 reg_val: ctx->dt.hfront_porch.min >> 8);
525 /* HWS */
526 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
527 HORIZONTAL_SYNC_WIDTH_L, reg_val: ctx->dt.hsync_len.min);
528 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_H, reg_val: ctx->dt.hsync_len.min >> 8);
530 /* HBP */
531 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
532 HORIZONTAL_BACK_PORCH_L, reg_val: ctx->dt.hback_porch.min);
533 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_H, reg_val: ctx->dt.hback_porch.min >> 8);
535 /* Vactive */
536 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
537 reg_val: ctx->dt.vactive.min);
538 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
539 reg_val: ctx->dt.vactive.min >> 8);
540 /* VFP */
541 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
542 VERTICAL_FRONT_PORCH, reg_val: ctx->dt.vfront_porch.min);
543 /* VWS */
544 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
545 VERTICAL_SYNC_WIDTH, reg_val: ctx->dt.vsync_len.min);
546 /* VBP */
547 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p2_client,
548 VERTICAL_BACK_PORCH, reg_val: ctx->dt.vback_porch.min);
549 /* M value */
550 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
551 MIPI_PLL_M_NUM_23_16, reg_val: (m >> 16) & 0xff);
552 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
553 MIPI_PLL_M_NUM_15_8, reg_val: (m >> 8) & 0xff);
554 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
555 MIPI_PLL_M_NUM_7_0, reg_val: (m & 0xff));
556 /* N value */
557 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
558 MIPI_PLL_N_NUM_23_16, reg_val: (n >> 16) & 0xff);
559 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
560 MIPI_PLL_N_NUM_15_8, reg_val: (n >> 8) & 0xff);
561 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
562 reg_val: (n & 0xff));
563
564 anx7625_set_k_value(ctx);
565
566 ret |= anx7625_odfc_config(ctx, post_divider: post_divider - 1);
567
568 if (ret < 0)
569 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
570
571 return ret;
572}
573
574static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
575{
576 int val;
577 struct device *dev = ctx->dev;
578
579 /* Swap MIPI-DSI data lane 3 P and N */
580 val = anx7625_reg_read(ctx, client: ctx->i2c.rx_p1_client, MIPI_SWAP);
581 if (val < 0) {
582 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
583 return -EIO;
584 }
585
586 val |= (1 << MIPI_SWAP_CH3);
587 return anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client, MIPI_SWAP, reg_val: val);
588}
589
590static int anx7625_api_dsi_config(struct anx7625_data *ctx)
591
592{
593 int val, ret;
594 struct device *dev = ctx->dev;
595
596 /* Swap MIPI-DSI data lane 3 P and N */
597 ret = anx7625_swap_dsi_lane3(ctx);
598 if (ret < 0) {
599 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
600 return ret;
601 }
602
603 /* DSI clock settings */
604 val = (0 << MIPI_HS_PWD_CLK) |
605 (0 << MIPI_HS_RT_CLK) |
606 (0 << MIPI_PD_CLK) |
607 (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
608 (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
609 (0 << MIPI_CLK_DET_DET_BYPASS) |
610 (0 << MIPI_CLK_MISS_CTRL) |
611 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
612 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
613 MIPI_PHY_CONTROL_3, reg_val: val);
614
615 /*
616 * Decreased HS prepare timing delay from 160ns to 80ns work with
617 * a) Dragon board 810 series (Qualcomm AP)
618 * b) Moving Pixel DSI source (PG3A pattern generator +
619 * P332 D-PHY Probe) default D-PHY timing
620 * 5ns/step
621 */
622 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
623 MIPI_TIME_HS_PRPR, reg_val: 0x10);
624
625 /* Enable DSI mode*/
626 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
627 SELECT_DSI << MIPI_DPI_SELECT);
628
629 ret |= anx7625_dsi_video_timing_config(ctx);
630 if (ret < 0) {
631 DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
632 return ret;
633 }
634
635 /* Toggle m, n ready */
636 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
637 mask: ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
638 usleep_range(min: 1000, max: 1100);
639 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
640 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
641
642 /* Configure integer stable register */
643 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
644 MIPI_VIDEO_STABLE_CNT, reg_val: 0x02);
645 /* Power on MIPI RX */
646 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
647 MIPI_LANE_CTRL_10, reg_val: 0x00);
648 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
649 MIPI_LANE_CTRL_10, reg_val: 0x80);
650
651 if (ret < 0)
652 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
653
654 return ret;
655}
656
657static int anx7625_dsi_config(struct anx7625_data *ctx)
658{
659 struct device *dev = ctx->dev;
660 int ret;
661
662 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
663
664 /* DSC disable */
665 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
666 R_DSC_CTRL_0, mask: ~DSC_EN);
667
668 ret |= anx7625_api_dsi_config(ctx);
669
670 if (ret < 0) {
671 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
672 return ret;
673 }
674
675 /* Set MIPI RX EN */
676 ret = anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
677 AP_AV_STATUS, AP_MIPI_RX_EN);
678 /* Clear mute flag */
679 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
680 AP_AV_STATUS, mask: (u8)~AP_MIPI_MUTE);
681 if (ret < 0)
682 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
683 else
684 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
685
686 return ret;
687}
688
689static int anx7625_api_dpi_config(struct anx7625_data *ctx)
690{
691 struct device *dev = ctx->dev;
692 u16 freq = ctx->dt.pixelclock.min / 1000;
693 int ret;
694
695 /* configure pixel clock */
696 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
697 PIXEL_CLOCK_L, reg_val: freq & 0xFF);
698 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
699 PIXEL_CLOCK_H, reg_val: (freq >> 8));
700
701 /* set DPI mode */
702 /* set to DPI PLL module sel */
703 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
704 MIPI_DIGITAL_PLL_9, reg_val: 0x20);
705 /* power down MIPI */
706 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
707 MIPI_LANE_CTRL_10, reg_val: 0x08);
708 /* enable DPI mode */
709 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p1_client,
710 MIPI_DIGITAL_PLL_18, reg_val: 0x1C);
711 /* set first edge */
712 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p2_client,
713 VIDEO_CONTROL_0, reg_val: 0x06);
714 if (ret < 0)
715 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
716
717 return ret;
718}
719
720static int anx7625_dpi_config(struct anx7625_data *ctx)
721{
722 struct device *dev = ctx->dev;
723 int ret;
724
725 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
726
727 /* DSC disable */
728 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
729 R_DSC_CTRL_0, mask: ~DSC_EN);
730 if (ret < 0) {
731 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
732 return ret;
733 }
734
735 ret = anx7625_config_bit_matrix(ctx);
736 if (ret < 0) {
737 DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
738 return ret;
739 }
740
741 ret = anx7625_api_dpi_config(ctx);
742 if (ret < 0) {
743 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
744 return ret;
745 }
746
747 /* set MIPI RX EN */
748 ret = anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
749 AP_AV_STATUS, AP_MIPI_RX_EN);
750 /* clear mute flag */
751 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
752 AP_AV_STATUS, mask: (u8)~AP_MIPI_MUTE);
753 if (ret < 0)
754 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
755
756 return ret;
757}
758
759static int anx7625_read_flash_status(struct anx7625_data *ctx)
760{
761 return anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client, R_RAM_CTRL);
762}
763
764static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
765{
766 int ret, val;
767 struct device *dev = ctx->dev;
768 u8 ident[FLASH_BUF_LEN];
769
770 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
771 FLASH_ADDR_HIGH, reg_val: 0x91);
772 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
773 FLASH_ADDR_LOW, reg_val: 0xA0);
774 if (ret < 0) {
775 dev_err(dev, "IO error : set key flash address.\n");
776 return ret;
777 }
778
779 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
780 FLASH_LEN_HIGH, reg_val: (FLASH_BUF_LEN - 1) >> 8);
781 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
782 FLASH_LEN_LOW, reg_val: (FLASH_BUF_LEN - 1) & 0xFF);
783 if (ret < 0) {
784 dev_err(dev, "IO error : set key flash len.\n");
785 return ret;
786 }
787
788 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
789 R_FLASH_RW_CTRL, FLASH_READ);
790 ret |= readx_poll_timeout(anx7625_read_flash_status,
791 ctx, val,
792 ((val & FLASH_DONE) || (val < 0)),
793 2000,
794 2000 * 150);
795 if (ret) {
796 dev_err(dev, "flash read access fail!\n");
797 return -EIO;
798 }
799
800 ret = anx7625_reg_block_read(ctx, client: ctx->i2c.rx_p0_client,
801 FLASH_BUF_BASE_ADDR,
802 FLASH_BUF_LEN, buf: ident);
803 if (ret < 0) {
804 dev_err(dev, "read flash data fail!\n");
805 return -EIO;
806 }
807
808 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
809 return -EINVAL;
810
811 return 0;
812}
813
814static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
815{
816 int ret;
817 struct device *dev = ctx->dev;
818
819 /* Select HDCP 1.4 KEY */
820 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
821 R_BOOT_RETRY, reg_val: 0x12);
822 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
823 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
824 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
825 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
826 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
827 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
828 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
829 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
830
831 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
832 R_RAM_ADDR_H, reg_val: 0);
833 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
834 R_RAM_ADDR_L, reg_val: 0);
835 /* Enable HDCP 1.4 KEY load */
836 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
837 R_RAM_CTRL, DECRYPT_EN | LOAD_START);
838 dev_dbg(dev, "load HDCP 1.4 key done\n");
839 return ret;
840}
841
842static int anx7625_hdcp_disable(struct anx7625_data *ctx)
843{
844 int ret;
845 struct device *dev = ctx->dev;
846
847 dev_dbg(dev, "disable HDCP 1.4\n");
848
849 /* Disable HDCP */
850 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, offset: 0xee, mask: 0x9f);
851 /* Try auth flag */
852 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xec, mask: 0x10);
853 /* Interrupt for DRM */
854 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xff, mask: 0x01);
855 if (ret < 0)
856 dev_err(dev, "fail to disable HDCP\n");
857
858 return anx7625_write_and(ctx, client: ctx->i2c.tx_p0_client,
859 TX_HDCP_CTRL0, mask: ~HARD_AUTH_EN & 0xFF);
860}
861
862static int anx7625_hdcp_enable(struct anx7625_data *ctx)
863{
864 u8 bcap;
865 int ret;
866 struct device *dev = ctx->dev;
867
868 ret = anx7625_hdcp_key_probe(ctx);
869 if (ret) {
870 dev_dbg(dev, "no key found, not to do hdcp\n");
871 return ret;
872 }
873
874 /* Read downstream capability */
875 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, len: 1, buf: &bcap);
876 if (ret < 0)
877 return ret;
878
879 if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) {
880 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
881 return 0;
882 }
883
884 dev_dbg(dev, "enable HDCP 1.4\n");
885
886 /* First clear HDCP state */
887 ret = anx7625_reg_write(ctx, client: ctx->i2c.tx_p0_client,
888 TX_HDCP_CTRL0,
889 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
890 usleep_range(min: 1000, max: 1100);
891 /* Second clear HDCP state */
892 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p0_client,
893 TX_HDCP_CTRL0,
894 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
895
896 /* Set time for waiting KSVR */
897 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p0_client,
898 SP_TX_WAIT_KSVR_TIME, reg_val: 0xc8);
899 /* Set time for waiting R0 */
900 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p0_client,
901 SP_TX_WAIT_R0_TIME, reg_val: 0xb0);
902 ret |= anx7625_hdcp_key_load(ctx);
903 if (ret) {
904 pr_warn("prepare HDCP key failed.\n");
905 return ret;
906 }
907
908 ret = anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xee, mask: 0x20);
909
910 /* Try auth flag */
911 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xec, mask: 0x10);
912 /* Interrupt for DRM */
913 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xff, mask: 0x01);
914 if (ret < 0)
915 dev_err(dev, "fail to enable HDCP\n");
916
917 return anx7625_write_or(ctx, client: ctx->i2c.tx_p0_client,
918 TX_HDCP_CTRL0, HARD_AUTH_EN);
919}
920
921static void anx7625_dp_start(struct anx7625_data *ctx)
922{
923 int ret;
924 struct device *dev = ctx->dev;
925 u8 data;
926
927 if (!ctx->display_timing_valid) {
928 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
929 return;
930 }
931
932 dev_dbg(dev, "set downstream sink into normal\n");
933 /* Downstream sink enter into normal mode */
934 data = DP_SET_POWER_D0;
935 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, len: 1, buf: &data);
936 if (ret < 0)
937 dev_err(dev, "IO error : set sink into normal mode fail\n");
938
939 /* Disable HDCP */
940 anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, offset: 0xee, mask: 0x9f);
941
942 if (ctx->pdata.is_dpi)
943 ret = anx7625_dpi_config(ctx);
944 else
945 ret = anx7625_dsi_config(ctx);
946
947 if (ret < 0)
948 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
949
950 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
951
952 ctx->dp_en = 1;
953}
954
955static void anx7625_dp_stop(struct anx7625_data *ctx)
956{
957 struct device *dev = ctx->dev;
958 int ret;
959 u8 data;
960
961 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
962
963 /*
964 * Video disable: 0x72:08 bit 7 = 0;
965 * Audio disable: 0x70:87 bit 0 = 0;
966 */
967 ret = anx7625_write_and(ctx, client: ctx->i2c.tx_p0_client, offset: 0x87, mask: 0xfe);
968 ret |= anx7625_write_and(ctx, client: ctx->i2c.tx_p2_client, offset: 0x08, mask: 0x7f);
969
970 ret |= anx7625_video_mute_control(ctx, status: 1);
971
972 dev_dbg(dev, "notify downstream enter into standby\n");
973 /* Downstream monitor enter into standby mode */
974 data = DP_SET_POWER_D3;
975 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, len: 1, buf: &data);
976 if (ret < 0)
977 DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
978
979 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
980
981 ctx->dp_en = 0;
982}
983
984static int sp_tx_rst_aux(struct anx7625_data *ctx)
985{
986 int ret;
987
988 ret = anx7625_write_or(ctx, client: ctx->i2c.tx_p2_client, RST_CTRL2,
989 AUX_RST);
990 ret |= anx7625_write_and(ctx, client: ctx->i2c.tx_p2_client, RST_CTRL2,
991 mask: ~AUX_RST);
992 return ret;
993}
994
995static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
996{
997 int ret;
998
999 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1000 AP_AUX_BUFF_START, reg_val: offset);
1001 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1002 AP_AUX_COMMAND, reg_val: 0x04);
1003 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
1004 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1005 return (ret | wait_aux_op_finish(ctx));
1006}
1007
1008static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1009{
1010 int ret;
1011
1012 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1013 AP_AUX_COMMAND, reg_val: len_cmd);
1014 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
1015 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1016 return (ret | wait_aux_op_finish(ctx));
1017}
1018
1019static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1020{
1021 int c = 0;
1022 struct device *dev = ctx->dev;
1023
1024 sp_tx_aux_wr(ctx, offset: 0x7e);
1025 sp_tx_aux_rd(ctx, len_cmd: 0x01);
1026 c = anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1027 if (c < 0) {
1028 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
1029 return -EIO;
1030 }
1031
1032 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
1033
1034 if (c > MAX_EDID_BLOCK)
1035 c = 1;
1036
1037 return c;
1038}
1039
1040static int edid_read(struct anx7625_data *ctx,
1041 u8 offset, u8 *pblock_buf)
1042{
1043 int ret, cnt;
1044 struct device *dev = ctx->dev;
1045
1046 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1047 sp_tx_aux_wr(ctx, offset);
1048 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1049 ret = sp_tx_aux_rd(ctx, len_cmd: 0xf1);
1050
1051 if (ret) {
1052 ret = sp_tx_rst_aux(ctx);
1053 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
1054 } else {
1055 ret = anx7625_reg_block_read(ctx, client: ctx->i2c.rx_p0_client,
1056 AP_AUX_BUFF_START,
1057 MAX_DPCD_BUFFER_SIZE,
1058 buf: pblock_buf);
1059 if (ret > 0)
1060 break;
1061 }
1062 }
1063
1064 if (cnt > EDID_TRY_CNT)
1065 return -EIO;
1066
1067 return ret;
1068}
1069
1070static int segments_edid_read(struct anx7625_data *ctx,
1071 u8 segment, u8 *buf, u8 offset)
1072{
1073 u8 cnt;
1074 int ret;
1075 struct device *dev = ctx->dev;
1076
1077 /* Write address only */
1078 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1079 AP_AUX_ADDR_7_0, reg_val: 0x30);
1080 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1081 AP_AUX_COMMAND, reg_val: 0x04);
1082 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1083 AP_AUX_CTRL_STATUS,
1084 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
1085
1086 ret |= wait_aux_op_finish(ctx);
1087 /* Write segment address */
1088 ret |= sp_tx_aux_wr(ctx, offset: segment);
1089 /* Data read */
1090 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1091 AP_AUX_ADDR_7_0, reg_val: 0x50);
1092 if (ret) {
1093 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
1094 return ret;
1095 }
1096
1097 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1098 sp_tx_aux_wr(ctx, offset);
1099 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1100 ret = sp_tx_aux_rd(ctx, len_cmd: 0xf1);
1101
1102 if (ret) {
1103 ret = sp_tx_rst_aux(ctx);
1104 DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
1105 } else {
1106 ret = anx7625_reg_block_read(ctx, client: ctx->i2c.rx_p0_client,
1107 AP_AUX_BUFF_START,
1108 MAX_DPCD_BUFFER_SIZE, buf);
1109 if (ret > 0)
1110 break;
1111 }
1112 }
1113
1114 if (cnt > EDID_TRY_CNT)
1115 return -EIO;
1116
1117 return ret;
1118}
1119
1120static int sp_tx_edid_read(struct anx7625_data *ctx,
1121 u8 *pedid_blocks_buf)
1122{
1123 u8 offset;
1124 int edid_pos;
1125 int count, blocks_num;
1126 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
1127 u8 i, j;
1128 int g_edid_break = 0;
1129 int ret;
1130 struct device *dev = ctx->dev;
1131
1132 /* Address initial */
1133 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1134 AP_AUX_ADDR_7_0, reg_val: 0x50);
1135 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1136 AP_AUX_ADDR_15_8, reg_val: 0);
1137 ret |= anx7625_write_and(ctx, client: ctx->i2c.rx_p0_client,
1138 AP_AUX_ADDR_19_16, mask: 0xf0);
1139 if (ret < 0) {
1140 DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
1141 return -EIO;
1142 }
1143
1144 blocks_num = sp_tx_get_edid_block(ctx);
1145 if (blocks_num < 0)
1146 return blocks_num;
1147
1148 count = 0;
1149
1150 do {
1151 switch (count) {
1152 case 0:
1153 case 1:
1154 for (i = 0; i < 8; i++) {
1155 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
1156 g_edid_break = edid_read(ctx, offset,
1157 pblock_buf);
1158
1159 if (g_edid_break < 0)
1160 break;
1161
1162 memcpy(&pedid_blocks_buf[offset],
1163 pblock_buf,
1164 MAX_DPCD_BUFFER_SIZE);
1165 }
1166
1167 break;
1168 case 2:
1169 offset = 0x00;
1170
1171 for (j = 0; j < 8; j++) {
1172 edid_pos = (j + count * 8) *
1173 MAX_DPCD_BUFFER_SIZE;
1174
1175 if (g_edid_break == 1)
1176 break;
1177
1178 ret = segments_edid_read(ctx, segment: count / 2,
1179 buf: pblock_buf, offset);
1180 if (ret < 0)
1181 return ret;
1182
1183 memcpy(&pedid_blocks_buf[edid_pos],
1184 pblock_buf,
1185 MAX_DPCD_BUFFER_SIZE);
1186 offset = offset + 0x10;
1187 }
1188
1189 break;
1190 case 3:
1191 offset = 0x80;
1192
1193 for (j = 0; j < 8; j++) {
1194 edid_pos = (j + count * 8) *
1195 MAX_DPCD_BUFFER_SIZE;
1196 if (g_edid_break == 1)
1197 break;
1198
1199 ret = segments_edid_read(ctx, segment: count / 2,
1200 buf: pblock_buf, offset);
1201 if (ret < 0)
1202 return ret;
1203
1204 memcpy(&pedid_blocks_buf[edid_pos],
1205 pblock_buf,
1206 MAX_DPCD_BUFFER_SIZE);
1207 offset = offset + 0x10;
1208 }
1209
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 count++;
1216
1217 } while (blocks_num >= count);
1218
1219 /* Check edid data */
1220 if (!drm_edid_is_valid(edid: (struct edid *)pedid_blocks_buf)) {
1221 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
1222 return -EINVAL;
1223 }
1224
1225 /* Reset aux channel */
1226 ret = sp_tx_rst_aux(ctx);
1227 if (ret < 0) {
1228 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n");
1229 return ret;
1230 }
1231
1232 return (blocks_num + 1);
1233}
1234
1235static void anx7625_power_on(struct anx7625_data *ctx)
1236{
1237 struct device *dev = ctx->dev;
1238 int ret, i;
1239
1240 if (!ctx->pdata.low_power_mode) {
1241 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1242 return;
1243 }
1244
1245 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1246 ret = regulator_enable(regulator: ctx->pdata.supplies[i].consumer);
1247 if (ret < 0) {
1248 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
1249 i, ret);
1250 goto reg_err;
1251 }
1252 usleep_range(min: 2000, max: 2100);
1253 }
1254
1255 usleep_range(min: 11000, max: 12000);
1256
1257 /* Power on pin enable */
1258 gpiod_set_value(desc: ctx->pdata.gpio_p_on, value: 1);
1259 usleep_range(min: 10000, max: 11000);
1260 /* Power reset pin enable */
1261 gpiod_set_value(desc: ctx->pdata.gpio_reset, value: 1);
1262 usleep_range(min: 10000, max: 11000);
1263
1264 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
1265 return;
1266reg_err:
1267 for (--i; i >= 0; i--)
1268 regulator_disable(regulator: ctx->pdata.supplies[i].consumer);
1269}
1270
1271static void anx7625_power_standby(struct anx7625_data *ctx)
1272{
1273 struct device *dev = ctx->dev;
1274 int ret;
1275
1276 if (!ctx->pdata.low_power_mode) {
1277 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1278 return;
1279 }
1280
1281 gpiod_set_value(desc: ctx->pdata.gpio_reset, value: 0);
1282 usleep_range(min: 1000, max: 1100);
1283 gpiod_set_value(desc: ctx->pdata.gpio_p_on, value: 0);
1284 usleep_range(min: 1000, max: 1100);
1285
1286 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1287 consumers: ctx->pdata.supplies);
1288 if (ret < 0)
1289 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
1290
1291 DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
1292}
1293
1294/* Basic configurations of ANX7625 */
1295static void anx7625_config(struct anx7625_data *ctx)
1296{
1297 anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1298 XTAL_FRQ_SEL, XTAL_FRQ_27M);
1299}
1300
1301static int anx7625_hpd_timer_config(struct anx7625_data *ctx)
1302{
1303 int ret;
1304
1305 /* Set irq detect window to 2ms */
1306 ret = anx7625_reg_write(ctx, client: ctx->i2c.tx_p2_client,
1307 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
1308 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p2_client,
1309 HPD_DET_TIMER_BIT8_15,
1310 reg_val: (HPD_TIME >> 8) & 0xFF);
1311 ret |= anx7625_reg_write(ctx, client: ctx->i2c.tx_p2_client,
1312 HPD_DET_TIMER_BIT16_23,
1313 reg_val: (HPD_TIME >> 16) & 0xFF);
1314
1315 return ret;
1316}
1317
1318static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx)
1319{
1320 return anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client, GPIO_CTRL_2);
1321}
1322
1323static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1324{
1325 struct device *dev = ctx->dev;
1326 int ret, val;
1327
1328 /* Reset main ocm */
1329 ret = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client, reg_addr: 0x88, reg_val: 0x40);
1330 /* Disable PD */
1331 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1332 AP_AV_STATUS, AP_DISABLE_PD);
1333 /* Release main ocm */
1334 ret |= anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client, reg_addr: 0x88, reg_val: 0x00);
1335
1336 if (ret < 0)
1337 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
1338 else
1339 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
1340
1341 /*
1342 * Make sure the HPD GPIO already be configured after OCM release before
1343 * setting HPD detect window register. Here we poll the status register
1344 * at maximum 40ms, then config HPD irq detect window register
1345 */
1346 readx_poll_timeout(anx7625_read_hpd_gpio_config_status,
1347 ctx, val,
1348 ((val & HPD_SOURCE) || (val < 0)),
1349 2000, 2000 * 20);
1350
1351 /* Set HPD irq detect window to 2ms */
1352 anx7625_hpd_timer_config(ctx);
1353}
1354
1355static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1356{
1357 int ret;
1358 struct device *dev = ctx->dev;
1359
1360 /* Check interface workable */
1361 ret = anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client,
1362 FLASH_LOAD_STA);
1363 if (ret < 0) {
1364 DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
1365 return ret;
1366 }
1367 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
1368 return -ENODEV;
1369
1370 anx7625_disable_pd_protocol(ctx);
1371
1372 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
1373 anx7625_reg_read(ctx,
1374 ctx->i2c.rx_p0_client,
1375 OCM_FW_VERSION),
1376 anx7625_reg_read(ctx,
1377 ctx->i2c.rx_p0_client,
1378 OCM_FW_REVERSION));
1379 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
1380 ANX7625_DRV_VERSION);
1381
1382 return 0;
1383}
1384
1385static void anx7625_power_on_init(struct anx7625_data *ctx)
1386{
1387 int retry_count, i;
1388
1389 for (retry_count = 0; retry_count < 3; retry_count++) {
1390 anx7625_power_on(ctx);
1391 anx7625_config(ctx);
1392
1393 for (i = 0; i < OCM_LOADING_TIME; i++) {
1394 if (!anx7625_ocm_loading_check(ctx))
1395 return;
1396 usleep_range(min: 1000, max: 1100);
1397 }
1398 anx7625_power_standby(ctx);
1399 }
1400}
1401
1402static void anx7625_init_gpio(struct anx7625_data *platform)
1403{
1404 struct device *dev = platform->dev;
1405
1406 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1407
1408 /* Gpio for chip power enable */
1409 platform->pdata.gpio_p_on =
1410 devm_gpiod_get_optional(dev, con_id: "enable", flags: GPIOD_OUT_LOW);
1411 if (IS_ERR_OR_NULL(ptr: platform->pdata.gpio_p_on)) {
1412 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n");
1413 platform->pdata.gpio_p_on = NULL;
1414 }
1415
1416 /* Gpio for chip reset */
1417 platform->pdata.gpio_reset =
1418 devm_gpiod_get_optional(dev, con_id: "reset", flags: GPIOD_OUT_LOW);
1419 if (IS_ERR_OR_NULL(ptr: platform->pdata.gpio_reset)) {
1420 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n");
1421 platform->pdata.gpio_reset = NULL;
1422 }
1423
1424 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1425 platform->pdata.low_power_mode = 1;
1426 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1427 desc_to_gpio(platform->pdata.gpio_p_on),
1428 desc_to_gpio(platform->pdata.gpio_reset));
1429 } else {
1430 platform->pdata.low_power_mode = 0;
1431 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1432 }
1433}
1434
1435static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1436{
1437 ctx->hpd_status = 0;
1438 ctx->hpd_high_cnt = 0;
1439}
1440
1441static void anx7625_start_dp_work(struct anx7625_data *ctx)
1442{
1443 int ret;
1444 struct device *dev = ctx->dev;
1445
1446 if (ctx->hpd_high_cnt >= 2) {
1447 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1448 return;
1449 }
1450
1451 ctx->hpd_status = 1;
1452 ctx->hpd_high_cnt++;
1453
1454 /* Not support HDCP */
1455 ret = anx7625_write_and(ctx, client: ctx->i2c.rx_p1_client, offset: 0xee, mask: 0x9f);
1456
1457 /* Try auth flag */
1458 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xec, mask: 0x10);
1459 /* Interrupt for DRM */
1460 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p1_client, offset: 0xff, mask: 0x01);
1461 if (ret < 0) {
1462 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
1463 return;
1464 }
1465
1466 ret = anx7625_reg_read(ctx, client: ctx->i2c.rx_p1_client, reg_addr: 0x86);
1467 if (ret < 0)
1468 return;
1469
1470 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1471}
1472
1473static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1474{
1475 return anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1476}
1477
1478static int _anx7625_hpd_polling(struct anx7625_data *ctx,
1479 unsigned long wait_us)
1480{
1481 int ret, val;
1482 struct device *dev = ctx->dev;
1483
1484 /* Interrupt mode, no need poll HPD status, just return */
1485 if (ctx->pdata.intp_irq)
1486 return 0;
1487
1488 ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1489 ctx, val,
1490 ((val & HPD_STATUS) || (val < 0)),
1491 wait_us / 100,
1492 wait_us);
1493 if (ret) {
1494 DRM_DEV_ERROR(dev, "no hpd.\n");
1495 return ret;
1496 }
1497
1498 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1499 anx7625_reg_write(ctx, client: ctx->i2c.tcpc_client,
1500 INTR_ALERT_1, reg_val: 0xFF);
1501 anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1502 INTERFACE_CHANGE_INT, reg_val: 0);
1503
1504 anx7625_start_dp_work(ctx);
1505
1506 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1507 drm_helper_hpd_irq_event(dev: ctx->bridge.dev);
1508
1509 return 0;
1510}
1511
1512static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux,
1513 unsigned long wait_us)
1514{
1515 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1516 struct device *dev = ctx->dev;
1517 int ret;
1518
1519 pm_runtime_get_sync(dev);
1520 ret = _anx7625_hpd_polling(ctx, wait_us);
1521 pm_runtime_mark_last_busy(dev);
1522 pm_runtime_put_autosuspend(dev);
1523
1524 return ret;
1525}
1526
1527static void anx7625_remove_edid(struct anx7625_data *ctx)
1528{
1529 ctx->slimport_edid_p.edid_block_num = -1;
1530}
1531
1532static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1533{
1534 int i;
1535
1536 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1537 anx7625_reg_write(ctx, client: ctx->i2c.tx_p1_client,
1538 DP_TX_LANE0_SWING_REG0 + i,
1539 reg_val: ctx->pdata.lane0_reg_data[i]);
1540
1541 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1542 anx7625_reg_write(ctx, client: ctx->i2c.tx_p1_client,
1543 DP_TX_LANE1_SWING_REG0 + i,
1544 reg_val: ctx->pdata.lane1_reg_data[i]);
1545}
1546
1547static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1548{
1549 struct device *dev = ctx->dev;
1550
1551 /* HPD changed */
1552 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1553 (u32)on);
1554
1555 if (on == 0) {
1556 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1557 anx7625_remove_edid(ctx);
1558 anx7625_stop_dp_work(ctx);
1559 } else {
1560 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1561 anx7625_start_dp_work(ctx);
1562 anx7625_dp_adjust_swing(ctx);
1563 }
1564}
1565
1566static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1567{
1568 int intr_vector, status;
1569 struct device *dev = ctx->dev;
1570
1571 status = anx7625_reg_write(ctx, client: ctx->i2c.tcpc_client,
1572 INTR_ALERT_1, reg_val: 0xFF);
1573 if (status < 0) {
1574 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1575 return status;
1576 }
1577
1578 intr_vector = anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client,
1579 INTERFACE_CHANGE_INT);
1580 if (intr_vector < 0) {
1581 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1582 return intr_vector;
1583 }
1584 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1585 status = anx7625_reg_write(ctx, client: ctx->i2c.rx_p0_client,
1586 INTERFACE_CHANGE_INT,
1587 reg_val: intr_vector & (~intr_vector));
1588 if (status < 0) {
1589 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1590 return status;
1591 }
1592
1593 if (!(intr_vector & HPD_STATUS_CHANGE))
1594 return -ENOENT;
1595
1596 status = anx7625_reg_read(ctx, client: ctx->i2c.rx_p0_client,
1597 SYSTEM_STSTUS);
1598 if (status < 0) {
1599 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1600 return status;
1601 }
1602
1603 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1604 dp_hpd_change_handler(ctx, on: status & HPD_STATUS);
1605
1606 return 0;
1607}
1608
1609static void anx7625_work_func(struct work_struct *work)
1610{
1611 int event;
1612 struct anx7625_data *ctx = container_of(work,
1613 struct anx7625_data, work);
1614
1615 mutex_lock(&ctx->lock);
1616
1617 if (pm_runtime_suspended(dev: ctx->dev)) {
1618 mutex_unlock(lock: &ctx->lock);
1619 return;
1620 }
1621
1622 event = anx7625_hpd_change_detect(ctx);
1623
1624 mutex_unlock(lock: &ctx->lock);
1625
1626 if (event < 0)
1627 return;
1628
1629 if (ctx->bridge_attached)
1630 drm_helper_hpd_irq_event(dev: ctx->bridge.dev);
1631}
1632
1633static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1634{
1635 struct anx7625_data *ctx = (struct anx7625_data *)data;
1636
1637 queue_work(wq: ctx->workqueue, work: &ctx->work);
1638
1639 return IRQ_HANDLED;
1640}
1641
1642static int anx7625_get_swing_setting(struct device *dev,
1643 struct anx7625_platform_data *pdata)
1644{
1645 int num_regs;
1646
1647 if (of_get_property(node: dev->of_node,
1648 name: "analogix,lane0-swing", lenp: &num_regs)) {
1649 if (num_regs > DP_TX_SWING_REG_CNT)
1650 num_regs = DP_TX_SWING_REG_CNT;
1651
1652 pdata->dp_lane0_swing_reg_cnt = num_regs;
1653 of_property_read_u8_array(np: dev->of_node, propname: "analogix,lane0-swing",
1654 out_values: pdata->lane0_reg_data, sz: num_regs);
1655 }
1656
1657 if (of_get_property(node: dev->of_node,
1658 name: "analogix,lane1-swing", lenp: &num_regs)) {
1659 if (num_regs > DP_TX_SWING_REG_CNT)
1660 num_regs = DP_TX_SWING_REG_CNT;
1661
1662 pdata->dp_lane1_swing_reg_cnt = num_regs;
1663 of_property_read_u8_array(np: dev->of_node, propname: "analogix,lane1-swing",
1664 out_values: pdata->lane1_reg_data, sz: num_regs);
1665 }
1666
1667 return 0;
1668}
1669
1670static int anx7625_parse_dt(struct device *dev,
1671 struct anx7625_platform_data *pdata)
1672{
1673 struct device_node *np = dev->of_node, *ep0;
1674 int bus_type, mipi_lanes;
1675
1676 anx7625_get_swing_setting(dev, pdata);
1677
1678 pdata->is_dpi = 0; /* default dsi mode */
1679 of_node_put(node: pdata->mipi_host_node);
1680 pdata->mipi_host_node = of_graph_get_remote_node(node: np, port: 0, endpoint: 0);
1681 if (!pdata->mipi_host_node) {
1682 DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1683 return -ENODEV;
1684 }
1685
1686 bus_type = 0;
1687 mipi_lanes = MAX_LANES_SUPPORT;
1688 ep0 = of_graph_get_endpoint_by_regs(parent: np, port_reg: 0, reg: 0);
1689 if (ep0) {
1690 if (of_property_read_u32(np: ep0, propname: "bus-type", out_value: &bus_type))
1691 bus_type = 0;
1692
1693 mipi_lanes = drm_of_get_data_lanes_count(endpoint: ep0, min: 1, MAX_LANES_SUPPORT);
1694 of_node_put(node: ep0);
1695 }
1696
1697 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */
1698 pdata->is_dpi = 1;
1699
1700 pdata->mipi_lanes = MAX_LANES_SUPPORT;
1701 if (mipi_lanes > 0)
1702 pdata->mipi_lanes = mipi_lanes;
1703
1704 if (pdata->is_dpi)
1705 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n");
1706 else
1707 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");
1708
1709 if (of_property_read_bool(np, propname: "analogix,audio-enable"))
1710 pdata->audio_en = 1;
1711
1712 return 0;
1713}
1714
1715static int anx7625_parse_dt_panel(struct device *dev,
1716 struct anx7625_platform_data *pdata)
1717{
1718 struct device_node *np = dev->of_node;
1719
1720 pdata->panel_bridge = devm_drm_of_get_bridge(dev, node: np, port: 1, endpoint: 0);
1721 if (IS_ERR(ptr: pdata->panel_bridge)) {
1722 if (PTR_ERR(ptr: pdata->panel_bridge) == -ENODEV) {
1723 pdata->panel_bridge = NULL;
1724 return 0;
1725 }
1726
1727 return PTR_ERR(ptr: pdata->panel_bridge);
1728 }
1729
1730 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1731
1732 return 0;
1733}
1734
1735static bool anx7625_of_panel_on_aux_bus(struct device *dev)
1736{
1737 struct device_node *bus, *panel;
1738
1739 bus = of_get_child_by_name(node: dev->of_node, name: "aux-bus");
1740 if (!bus)
1741 return false;
1742
1743 panel = of_get_child_by_name(node: bus, name: "panel");
1744 of_node_put(node: bus);
1745 if (!panel)
1746 return false;
1747 of_node_put(node: panel);
1748
1749 return true;
1750}
1751
1752static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1753{
1754 return container_of(bridge, struct anx7625_data, bridge);
1755}
1756
1757static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux,
1758 struct drm_dp_aux_msg *msg)
1759{
1760 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1761 struct device *dev = ctx->dev;
1762 u8 request = msg->request & ~DP_AUX_I2C_MOT;
1763 int ret = 0;
1764
1765 mutex_lock(&ctx->aux_lock);
1766 pm_runtime_get_sync(dev);
1767 msg->reply = 0;
1768 switch (request) {
1769 case DP_AUX_NATIVE_WRITE:
1770 case DP_AUX_I2C_WRITE:
1771 case DP_AUX_NATIVE_READ:
1772 case DP_AUX_I2C_READ:
1773 break;
1774 default:
1775 ret = -EINVAL;
1776 }
1777 if (!ret)
1778 ret = anx7625_aux_trans(ctx, op: msg->request, address: msg->address,
1779 len: msg->size, buf: msg->buffer);
1780 pm_runtime_mark_last_busy(dev);
1781 pm_runtime_put_autosuspend(dev);
1782 mutex_unlock(lock: &ctx->aux_lock);
1783
1784 return ret;
1785}
1786
1787static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx)
1788{
1789 struct device *dev = ctx->dev;
1790 struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1791 int edid_num;
1792
1793 if (ctx->slimport_edid_p.edid_block_num > 0)
1794 goto out;
1795
1796 pm_runtime_get_sync(dev);
1797 _anx7625_hpd_polling(ctx, wait_us: 5000 * 100);
1798 edid_num = sp_tx_edid_read(ctx, pedid_blocks_buf: p_edid->edid_raw_data);
1799 pm_runtime_put_sync(dev);
1800
1801 if (edid_num < 1) {
1802 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1803 return NULL;
1804 }
1805
1806 p_edid->edid_block_num = edid_num;
1807
1808out:
1809 return drm_edid_alloc(edid: ctx->slimport_edid_p.edid_raw_data,
1810 FOUR_BLOCK_SIZE);
1811}
1812
1813static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1814{
1815 struct device *dev = ctx->dev;
1816
1817 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n");
1818
1819 if (ctx->pdata.panel_bridge)
1820 return connector_status_connected;
1821
1822 return ctx->hpd_status ? connector_status_connected :
1823 connector_status_disconnected;
1824}
1825
1826static int anx7625_audio_hw_params(struct device *dev, void *data,
1827 struct hdmi_codec_daifmt *fmt,
1828 struct hdmi_codec_params *params)
1829{
1830 struct anx7625_data *ctx = dev_get_drvdata(dev);
1831 int wl, ch, rate;
1832 int ret = 0;
1833
1834 if (anx7625_sink_detect(ctx) == connector_status_disconnected) {
1835 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n");
1836 return 0;
1837 }
1838
1839 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) {
1840 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n");
1841 return -EINVAL;
1842 }
1843
1844 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n",
1845 params->sample_rate, params->sample_width,
1846 params->cea.channels);
1847
1848 if (fmt->fmt == HDMI_DSP_A)
1849 ret = anx7625_write_and_or(ctx, client: ctx->i2c.tx_p2_client,
1850 AUDIO_CHANNEL_STATUS_6,
1851 and_mask: ~I2S_SLAVE_MODE,
1852 TDM_SLAVE_MODE);
1853 else
1854 ret = anx7625_write_and_or(ctx, client: ctx->i2c.tx_p2_client,
1855 AUDIO_CHANNEL_STATUS_6,
1856 and_mask: ~TDM_SLAVE_MODE,
1857 I2S_SLAVE_MODE);
1858
1859 /* Word length */
1860 switch (params->sample_width) {
1861 case 16:
1862 wl = AUDIO_W_LEN_16_20MAX;
1863 break;
1864 case 18:
1865 wl = AUDIO_W_LEN_18_20MAX;
1866 break;
1867 case 20:
1868 wl = AUDIO_W_LEN_20_20MAX;
1869 break;
1870 case 24:
1871 wl = AUDIO_W_LEN_24_24MAX;
1872 break;
1873 default:
1874 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
1875 params->sample_width);
1876 return -EINVAL;
1877 }
1878 ret |= anx7625_write_and_or(ctx, client: ctx->i2c.tx_p2_client,
1879 AUDIO_CHANNEL_STATUS_5,
1880 and_mask: 0xf0, or_mask: wl);
1881
1882 /* Channel num */
1883 switch (params->cea.channels) {
1884 case 2:
1885 ch = I2S_CH_2;
1886 break;
1887 case 4:
1888 ch = TDM_CH_4;
1889 break;
1890 case 6:
1891 ch = TDM_CH_6;
1892 break;
1893 case 8:
1894 ch = TDM_CH_8;
1895 break;
1896 default:
1897 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
1898 params->cea.channels);
1899 return -EINVAL;
1900 }
1901 ret |= anx7625_write_and_or(ctx, client: ctx->i2c.tx_p2_client,
1902 AUDIO_CHANNEL_STATUS_6, and_mask: 0x1f, or_mask: ch << 5);
1903 if (ch > I2S_CH_2)
1904 ret |= anx7625_write_or(ctx, client: ctx->i2c.tx_p2_client,
1905 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT);
1906 else
1907 ret |= anx7625_write_and(ctx, client: ctx->i2c.tx_p2_client,
1908 AUDIO_CHANNEL_STATUS_6, mask: ~AUDIO_LAYOUT);
1909
1910 /* FS */
1911 switch (params->sample_rate) {
1912 case 32000:
1913 rate = AUDIO_FS_32K;
1914 break;
1915 case 44100:
1916 rate = AUDIO_FS_441K;
1917 break;
1918 case 48000:
1919 rate = AUDIO_FS_48K;
1920 break;
1921 case 88200:
1922 rate = AUDIO_FS_882K;
1923 break;
1924 case 96000:
1925 rate = AUDIO_FS_96K;
1926 break;
1927 case 176400:
1928 rate = AUDIO_FS_1764K;
1929 break;
1930 case 192000:
1931 rate = AUDIO_FS_192K;
1932 break;
1933 default:
1934 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support",
1935 params->sample_rate);
1936 return -EINVAL;
1937 }
1938 ret |= anx7625_write_and_or(ctx, client: ctx->i2c.tx_p2_client,
1939 AUDIO_CHANNEL_STATUS_4,
1940 and_mask: 0xf0, or_mask: rate);
1941 ret |= anx7625_write_or(ctx, client: ctx->i2c.rx_p0_client,
1942 AP_AV_STATUS, AP_AUDIO_CHG);
1943 if (ret < 0) {
1944 DRM_DEV_ERROR(dev, "IO error : config audio.\n");
1945 return -EIO;
1946 }
1947
1948 return 0;
1949}
1950
1951static void anx7625_audio_shutdown(struct device *dev, void *data)
1952{
1953 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n");
1954}
1955
1956static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
1957 struct device_node *endpoint)
1958{
1959 struct of_endpoint of_ep;
1960 int ret;
1961
1962 ret = of_graph_parse_endpoint(node: endpoint, endpoint: &of_ep);
1963 if (ret < 0)
1964 return ret;
1965
1966 /*
1967 * HDMI sound should be located at external DPI port
1968 * Didn't have good way to check where is internal(DSI)
1969 * or external(DPI) bridge
1970 */
1971 return 0;
1972}
1973
1974static void
1975anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1976 enum drm_connector_status status)
1977{
1978 if (ctx->plugged_cb && ctx->codec_dev) {
1979 ctx->plugged_cb(ctx->codec_dev,
1980 status == connector_status_connected);
1981 }
1982}
1983
1984static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data,
1985 hdmi_codec_plugged_cb fn,
1986 struct device *codec_dev)
1987{
1988 struct anx7625_data *ctx = data;
1989
1990 ctx->plugged_cb = fn;
1991 ctx->codec_dev = codec_dev;
1992 anx7625_audio_update_connector_status(ctx, status: anx7625_sink_detect(ctx));
1993
1994 return 0;
1995}
1996
1997static int anx7625_audio_get_eld(struct device *dev, void *data,
1998 u8 *buf, size_t len)
1999{
2000 struct anx7625_data *ctx = dev_get_drvdata(dev);
2001
2002 if (!ctx->connector) {
2003 /* Pass en empty ELD if connector not available */
2004 memset(buf, 0, len);
2005 } else {
2006 dev_dbg(dev, "audio copy eld\n");
2007 memcpy(buf, ctx->connector->eld,
2008 min(sizeof(ctx->connector->eld), len));
2009 }
2010
2011 return 0;
2012}
2013
2014static const struct hdmi_codec_ops anx7625_codec_ops = {
2015 .hw_params = anx7625_audio_hw_params,
2016 .audio_shutdown = anx7625_audio_shutdown,
2017 .get_eld = anx7625_audio_get_eld,
2018 .get_dai_id = anx7625_hdmi_i2s_get_dai_id,
2019 .hook_plugged_cb = anx7625_audio_hook_plugged_cb,
2020};
2021
2022static void anx7625_unregister_audio(struct anx7625_data *ctx)
2023{
2024 struct device *dev = ctx->dev;
2025
2026 if (ctx->audio_pdev) {
2027 platform_device_unregister(ctx->audio_pdev);
2028 ctx->audio_pdev = NULL;
2029 }
2030
2031 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME);
2032}
2033
2034static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
2035{
2036 struct hdmi_codec_pdata codec_data = {
2037 .ops = &anx7625_codec_ops,
2038 .max_i2s_channels = 8,
2039 .i2s = 1,
2040 .data = ctx,
2041 };
2042
2043 ctx->audio_pdev = platform_device_register_data(parent: dev,
2044 HDMI_CODEC_DRV_NAME,
2045 PLATFORM_DEVID_AUTO,
2046 data: &codec_data,
2047 size: sizeof(codec_data));
2048
2049 if (IS_ERR(ptr: ctx->audio_pdev))
2050 return PTR_ERR(ptr: ctx->audio_pdev);
2051
2052 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME);
2053
2054 return 0;
2055}
2056
2057static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
2058{
2059 struct mipi_dsi_device *dsi;
2060 struct device *dev = ctx->dev;
2061 struct mipi_dsi_host *host;
2062 const struct mipi_dsi_device_info info = {
2063 .type = "anx7625",
2064 .channel = 0,
2065 .node = NULL,
2066 };
2067
2068 host = of_find_mipi_dsi_host_by_node(node: ctx->pdata.mipi_host_node);
2069 if (!host) {
2070 DRM_DEV_ERROR(dev, "fail to find dsi host.\n");
2071 return -EPROBE_DEFER;
2072 }
2073
2074 dsi = devm_mipi_dsi_device_register_full(dev, host, info: &info);
2075 if (IS_ERR(ptr: dsi)) {
2076 DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
2077 return -EINVAL;
2078 }
2079
2080 dsi->lanes = ctx->pdata.mipi_lanes;
2081 dsi->format = MIPI_DSI_FMT_RGB888;
2082 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
2083 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2084 MIPI_DSI_MODE_VIDEO_HSE |
2085 MIPI_DSI_HS_PKT_END_ALIGNED;
2086
2087 ctx->dsi = dsi;
2088
2089 return 0;
2090}
2091
2092static int anx7625_attach_dsi(struct anx7625_data *ctx)
2093{
2094 struct device *dev = ctx->dev;
2095 int ret;
2096
2097 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2098
2099 ret = devm_mipi_dsi_attach(dev, dsi: ctx->dsi);
2100 if (ret) {
2101 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2102 return ret;
2103 }
2104
2105 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2106
2107 return 0;
2108}
2109
2110static void hdcp_check_work_func(struct work_struct *work)
2111{
2112 u8 status;
2113 struct delayed_work *dwork;
2114 struct anx7625_data *ctx;
2115 struct device *dev;
2116 struct drm_device *drm_dev;
2117
2118 dwork = to_delayed_work(work);
2119 ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2120 dev = ctx->dev;
2121
2122 if (!ctx->connector) {
2123 dev_err(dev, "HDCP connector is null!");
2124 return;
2125 }
2126
2127 drm_dev = ctx->connector->dev;
2128 drm_modeset_lock(lock: &drm_dev->mode_config.connection_mutex, NULL);
2129 mutex_lock(&ctx->hdcp_wq_lock);
2130
2131 status = anx7625_reg_read(ctx, client: ctx->i2c.tx_p0_client, reg_addr: 0);
2132 dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
2133 if (status & BIT(1)) {
2134 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2135 drm_hdcp_update_content_protection(connector: ctx->connector,
2136 val: ctx->hdcp_cp);
2137 dev_dbg(dev, "update CP to ENABLE\n");
2138 }
2139
2140 mutex_unlock(lock: &ctx->hdcp_wq_lock);
2141 drm_modeset_unlock(lock: &drm_dev->mode_config.connection_mutex);
2142}
2143
2144static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2145 struct drm_connector_state *state)
2146{
2147 struct device *dev = ctx->dev;
2148 int cp;
2149
2150 dev_dbg(dev, "hdcp state check\n");
2151 cp = state->content_protection;
2152
2153 if (cp == ctx->hdcp_cp)
2154 return 0;
2155
2156 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2157 if (ctx->dp_en) {
2158 dev_dbg(dev, "enable HDCP\n");
2159 anx7625_hdcp_enable(ctx);
2160
2161 queue_delayed_work(wq: ctx->hdcp_workqueue,
2162 dwork: &ctx->hdcp_work,
2163 delay: msecs_to_jiffies(m: 2000));
2164 }
2165 }
2166
2167 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
2168 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2169 dev_err(dev, "current CP is not ENABLED\n");
2170 return -EINVAL;
2171 }
2172 anx7625_hdcp_disable(ctx);
2173 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2174 drm_hdcp_update_content_protection(connector: ctx->connector,
2175 val: ctx->hdcp_cp);
2176 dev_dbg(dev, "update CP to UNDESIRE\n");
2177 }
2178
2179 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2180 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
2181 return -EINVAL;
2182 }
2183
2184 return 0;
2185}
2186
2187static int anx7625_bridge_attach(struct drm_bridge *bridge,
2188 enum drm_bridge_attach_flags flags)
2189{
2190 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2191 int err;
2192 struct device *dev = ctx->dev;
2193
2194 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
2195 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2196 return -EINVAL;
2197
2198 if (!bridge->encoder) {
2199 DRM_DEV_ERROR(dev, "Parent encoder object not found");
2200 return -ENODEV;
2201 }
2202
2203 ctx->aux.drm_dev = bridge->dev;
2204 err = drm_dp_aux_register(aux: &ctx->aux);
2205 if (err) {
2206 dev_err(dev, "failed to register aux channel: %d\n", err);
2207 return err;
2208 }
2209
2210 if (ctx->pdata.panel_bridge) {
2211 err = drm_bridge_attach(encoder: bridge->encoder,
2212 bridge: ctx->pdata.panel_bridge,
2213 previous: &ctx->bridge, flags);
2214 if (err)
2215 return err;
2216 }
2217
2218 ctx->bridge_attached = 1;
2219
2220 return 0;
2221}
2222
2223static void anx7625_bridge_detach(struct drm_bridge *bridge)
2224{
2225 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2226
2227 drm_dp_aux_unregister(aux: &ctx->aux);
2228}
2229
2230static enum drm_mode_status
2231anx7625_bridge_mode_valid(struct drm_bridge *bridge,
2232 const struct drm_display_info *info,
2233 const struct drm_display_mode *mode)
2234{
2235 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2236 struct device *dev = ctx->dev;
2237
2238 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
2239
2240 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2241 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2242 DRM_DEV_DEBUG_DRIVER(dev,
2243 "drm mode invalid, pixelclock too high.\n");
2244 return MODE_CLOCK_HIGH;
2245 }
2246
2247 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
2248
2249 return MODE_OK;
2250}
2251
2252static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
2253 const struct drm_display_mode *old_mode,
2254 const struct drm_display_mode *mode)
2255{
2256 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2257 struct device *dev = ctx->dev;
2258
2259 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
2260
2261 ctx->dt.pixelclock.min = mode->clock;
2262 ctx->dt.hactive.min = mode->hdisplay;
2263 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2264 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2265 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2266 ctx->dt.vactive.min = mode->vdisplay;
2267 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2268 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2269 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2270
2271 ctx->display_timing_valid = 1;
2272
2273 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2274 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
2275 ctx->dt.hactive.min,
2276 ctx->dt.hsync_len.min,
2277 ctx->dt.hfront_porch.min,
2278 ctx->dt.hback_porch.min);
2279 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
2280 ctx->dt.vactive.min,
2281 ctx->dt.vsync_len.min,
2282 ctx->dt.vfront_porch.min,
2283 ctx->dt.vback_porch.min);
2284 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
2285 mode->hdisplay,
2286 mode->hsync_start);
2287 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
2288 mode->hsync_end,
2289 mode->htotal);
2290 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
2291 mode->vdisplay,
2292 mode->vsync_start);
2293 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
2294 mode->vsync_end,
2295 mode->vtotal);
2296}
2297
2298static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
2299 const struct drm_display_mode *mode,
2300 struct drm_display_mode *adj)
2301{
2302 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2303 struct device *dev = ctx->dev;
2304 u32 hsync, hfp, hbp, hblanking;
2305 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
2306 u32 vref, adj_clock;
2307
2308 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
2309
2310 /* No need fixup for external monitor */
2311 if (!ctx->pdata.panel_bridge)
2312 return true;
2313
2314 hsync = mode->hsync_end - mode->hsync_start;
2315 hfp = mode->hsync_start - mode->hdisplay;
2316 hbp = mode->htotal - mode->hsync_end;
2317 hblanking = mode->htotal - mode->hdisplay;
2318
2319 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
2320 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2321 hsync, hfp, hbp, adj->clock);
2322 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2323 adj->hsync_start, adj->hsync_end, adj->htotal);
2324
2325 adj_hfp = hfp;
2326 adj_hsync = hsync;
2327 adj_hbp = hbp;
2328 adj_hblanking = hblanking;
2329
2330 /* HFP needs to be even */
2331 if (hfp & 0x1) {
2332 adj_hfp += 1;
2333 adj_hblanking += 1;
2334 }
2335
2336 /* HBP needs to be even */
2337 if (hbp & 0x1) {
2338 adj_hbp -= 1;
2339 adj_hblanking -= 1;
2340 }
2341
2342 /* HSYNC needs to be even */
2343 if (hsync & 0x1) {
2344 if (adj_hblanking < hblanking)
2345 adj_hsync += 1;
2346 else
2347 adj_hsync -= 1;
2348 }
2349
2350 /*
2351 * Once illegal timing detected, use default HFP, HSYNC, HBP
2352 * This adjusting made for built-in eDP panel, for the externel
2353 * DP monitor, may need return false.
2354 */
2355 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
2356 adj_hsync = SYNC_LEN_DEF;
2357 adj_hfp = HFP_HBP_DEF;
2358 adj_hbp = HFP_HBP_DEF;
2359 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2360 if (hblanking < HBLANKING_MIN) {
2361 delta_adj = HBLANKING_MIN - hblanking;
2362 adj_clock = vref * delta_adj * adj->vtotal;
2363 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2364 } else {
2365 delta_adj = hblanking - HBLANKING_MIN;
2366 adj_clock = vref * delta_adj * adj->vtotal;
2367 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2368 }
2369
2370 DRM_WARN("illegal hblanking timing, use default.\n");
2371 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
2372 } else if (adj_hfp < HP_MIN) {
2373 /* Adjust hfp if hfp less than HP_MIN */
2374 delta_adj = HP_MIN - adj_hfp;
2375 adj_hfp = HP_MIN;
2376
2377 /*
2378 * Balance total HBlanking pixel, if HBP does not have enough
2379 * space, adjust HSYNC length, otherwise adjust HBP
2380 */
2381 if ((adj_hbp - delta_adj) < HP_MIN)
2382 /* HBP not enough space */
2383 adj_hsync -= delta_adj;
2384 else
2385 adj_hbp -= delta_adj;
2386 } else if (adj_hbp < HP_MIN) {
2387 delta_adj = HP_MIN - adj_hbp;
2388 adj_hbp = HP_MIN;
2389
2390 /*
2391 * Balance total HBlanking pixel, if HBP hasn't enough space,
2392 * adjust HSYNC length, otherwize adjust HBP
2393 */
2394 if ((adj_hfp - delta_adj) < HP_MIN)
2395 /* HFP not enough space */
2396 adj_hsync -= delta_adj;
2397 else
2398 adj_hfp -= delta_adj;
2399 }
2400
2401 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
2402 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2403 adj_hsync, adj_hfp, adj_hbp, adj->clock);
2404
2405 /* Reconstruct timing */
2406 adj->hsync_start = adj->hdisplay + adj_hfp;
2407 adj->hsync_end = adj->hsync_start + adj_hsync;
2408 adj->htotal = adj->hsync_end + adj_hbp;
2409 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2410 adj->hsync_start, adj->hsync_end, adj->htotal);
2411
2412 return true;
2413}
2414
2415static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
2416 struct drm_bridge_state *bridge_state,
2417 struct drm_crtc_state *crtc_state,
2418 struct drm_connector_state *conn_state)
2419{
2420 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2421 struct device *dev = ctx->dev;
2422
2423 dev_dbg(dev, "drm bridge atomic check\n");
2424
2425 anx7625_bridge_mode_fixup(bridge, mode: &crtc_state->mode,
2426 adj: &crtc_state->adjusted_mode);
2427
2428 return anx7625_connector_atomic_check(ctx, state: conn_state);
2429}
2430
2431static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
2432 struct drm_bridge_state *state)
2433{
2434 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2435 struct device *dev = ctx->dev;
2436 struct drm_connector *connector;
2437
2438 dev_dbg(dev, "drm atomic enable\n");
2439
2440 if (!bridge->encoder) {
2441 dev_err(dev, "Parent encoder object not found");
2442 return;
2443 }
2444
2445 connector = drm_atomic_get_new_connector_for_encoder(state: state->base.state,
2446 encoder: bridge->encoder);
2447 if (!connector)
2448 return;
2449
2450 ctx->connector = connector;
2451
2452 pm_runtime_get_sync(dev);
2453 _anx7625_hpd_polling(ctx, wait_us: 5000 * 100);
2454
2455 anx7625_dp_start(ctx);
2456}
2457
2458static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
2459 struct drm_bridge_state *old)
2460{
2461 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2462 struct device *dev = ctx->dev;
2463
2464 dev_dbg(dev, "drm atomic disable\n");
2465
2466 ctx->connector = NULL;
2467 anx7625_dp_stop(ctx);
2468
2469 mutex_lock(&ctx->aux_lock);
2470 pm_runtime_put_sync_suspend(dev);
2471 mutex_unlock(lock: &ctx->aux_lock);
2472}
2473
2474static enum drm_connector_status
2475anx7625_bridge_detect(struct drm_bridge *bridge)
2476{
2477 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2478 struct device *dev = ctx->dev;
2479
2480 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
2481
2482 return anx7625_sink_detect(ctx);
2483}
2484
2485static const struct drm_edid *anx7625_bridge_edid_read(struct drm_bridge *bridge,
2486 struct drm_connector *connector)
2487{
2488 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2489 struct device *dev = ctx->dev;
2490
2491 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
2492
2493 return anx7625_edid_read(ctx);
2494}
2495
2496static const struct drm_bridge_funcs anx7625_bridge_funcs = {
2497 .attach = anx7625_bridge_attach,
2498 .detach = anx7625_bridge_detach,
2499 .mode_valid = anx7625_bridge_mode_valid,
2500 .mode_set = anx7625_bridge_mode_set,
2501 .atomic_check = anx7625_bridge_atomic_check,
2502 .atomic_enable = anx7625_bridge_atomic_enable,
2503 .atomic_disable = anx7625_bridge_atomic_disable,
2504 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2505 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2506 .atomic_reset = drm_atomic_helper_bridge_reset,
2507 .detect = anx7625_bridge_detect,
2508 .edid_read = anx7625_bridge_edid_read,
2509};
2510
2511static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2512 struct i2c_client *client)
2513{
2514 struct device *dev = ctx->dev;
2515
2516 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2517 TX_P0_ADDR >> 1);
2518 if (IS_ERR(ptr: ctx->i2c.tx_p0_client))
2519 return PTR_ERR(ptr: ctx->i2c.tx_p0_client);
2520
2521 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2522 TX_P1_ADDR >> 1);
2523 if (IS_ERR(ptr: ctx->i2c.tx_p1_client))
2524 return PTR_ERR(ptr: ctx->i2c.tx_p1_client);
2525
2526 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2527 TX_P2_ADDR >> 1);
2528 if (IS_ERR(ptr: ctx->i2c.tx_p2_client))
2529 return PTR_ERR(ptr: ctx->i2c.tx_p2_client);
2530
2531 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2532 RX_P0_ADDR >> 1);
2533 if (IS_ERR(ptr: ctx->i2c.rx_p0_client))
2534 return PTR_ERR(ptr: ctx->i2c.rx_p0_client);
2535
2536 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2537 RX_P1_ADDR >> 1);
2538 if (IS_ERR(ptr: ctx->i2c.rx_p1_client))
2539 return PTR_ERR(ptr: ctx->i2c.rx_p1_client);
2540
2541 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2542 RX_P2_ADDR >> 1);
2543 if (IS_ERR(ptr: ctx->i2c.rx_p2_client))
2544 return PTR_ERR(ptr: ctx->i2c.rx_p2_client);
2545
2546 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, adap: client->adapter,
2547 TCPC_INTERFACE_ADDR >> 1);
2548 if (IS_ERR(ptr: ctx->i2c.tcpc_client))
2549 return PTR_ERR(ptr: ctx->i2c.tcpc_client);
2550
2551 return 0;
2552}
2553
2554static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
2555{
2556 struct anx7625_data *ctx = dev_get_drvdata(dev);
2557
2558 mutex_lock(&ctx->lock);
2559
2560 anx7625_stop_dp_work(ctx);
2561 anx7625_power_standby(ctx);
2562
2563 mutex_unlock(lock: &ctx->lock);
2564
2565 return 0;
2566}
2567
2568static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
2569{
2570 struct anx7625_data *ctx = dev_get_drvdata(dev);
2571
2572 mutex_lock(&ctx->lock);
2573
2574 anx7625_power_on_init(ctx);
2575
2576 mutex_unlock(lock: &ctx->lock);
2577
2578 return 0;
2579}
2580
2581static const struct dev_pm_ops anx7625_pm_ops = {
2582 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2583 pm_runtime_force_resume)
2584 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
2585 anx7625_runtime_pm_resume, NULL)
2586};
2587
2588static void anx7625_runtime_disable(void *data)
2589{
2590 pm_runtime_dont_use_autosuspend(dev: data);
2591 pm_runtime_disable(dev: data);
2592}
2593
2594static int anx7625_link_bridge(struct drm_dp_aux *aux)
2595{
2596 struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux);
2597 struct device *dev = aux->dev;
2598 int ret;
2599
2600 ret = anx7625_parse_dt_panel(dev, pdata: &platform->pdata);
2601 if (ret) {
2602 DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret);
2603 return ret;
2604 }
2605
2606 platform->bridge.funcs = &anx7625_bridge_funcs;
2607 platform->bridge.of_node = dev->of_node;
2608 if (!anx7625_of_panel_on_aux_bus(dev))
2609 platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2610 if (!platform->pdata.panel_bridge)
2611 platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2612 DRM_BRIDGE_OP_DETECT;
2613 platform->bridge.type = platform->pdata.panel_bridge ?
2614 DRM_MODE_CONNECTOR_eDP :
2615 DRM_MODE_CONNECTOR_DisplayPort;
2616
2617 drm_bridge_add(bridge: &platform->bridge);
2618
2619 if (!platform->pdata.is_dpi) {
2620 ret = anx7625_attach_dsi(ctx: platform);
2621 if (ret)
2622 drm_bridge_remove(bridge: &platform->bridge);
2623 }
2624
2625 return ret;
2626}
2627
2628static int anx7625_i2c_probe(struct i2c_client *client)
2629{
2630 struct anx7625_data *platform;
2631 struct anx7625_platform_data *pdata;
2632 int ret = 0;
2633 struct device *dev = &client->dev;
2634
2635 if (!i2c_check_functionality(adap: client->adapter,
2636 I2C_FUNC_SMBUS_I2C_BLOCK)) {
2637 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
2638 return -ENODEV;
2639 }
2640
2641 platform = devm_kzalloc(dev, size: sizeof(*platform), GFP_KERNEL);
2642 if (!platform) {
2643 DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
2644 return -ENOMEM;
2645 }
2646
2647 pdata = &platform->pdata;
2648
2649 platform->dev = &client->dev;
2650 i2c_set_clientdata(client, data: platform);
2651
2652 pdata->supplies[0].supply = "vdd10";
2653 pdata->supplies[1].supply = "vdd18";
2654 pdata->supplies[2].supply = "vdd33";
2655 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2656 consumers: pdata->supplies);
2657 if (ret) {
2658 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
2659 return ret;
2660 }
2661 anx7625_init_gpio(platform);
2662
2663 mutex_init(&platform->lock);
2664 mutex_init(&platform->hdcp_wq_lock);
2665 mutex_init(&platform->aux_lock);
2666
2667 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2668 platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2669 if (!platform->hdcp_workqueue) {
2670 dev_err(dev, "fail to create work queue\n");
2671 ret = -ENOMEM;
2672 return ret;
2673 }
2674
2675 platform->pdata.intp_irq = client->irq;
2676 if (platform->pdata.intp_irq) {
2677 INIT_WORK(&platform->work, anx7625_work_func);
2678 platform->workqueue = alloc_workqueue(fmt: "anx7625_work",
2679 flags: WQ_FREEZABLE | WQ_MEM_RECLAIM, max_active: 1);
2680 if (!platform->workqueue) {
2681 DRM_DEV_ERROR(dev, "fail to create work queue\n");
2682 ret = -ENOMEM;
2683 goto free_hdcp_wq;
2684 }
2685
2686 ret = devm_request_threaded_irq(dev, irq: platform->pdata.intp_irq,
2687 NULL, thread_fn: anx7625_intr_hpd_isr,
2688 IRQF_TRIGGER_FALLING |
2689 IRQF_ONESHOT,
2690 devname: "anx7625-intp", dev_id: platform);
2691 if (ret) {
2692 DRM_DEV_ERROR(dev, "fail to request irq\n");
2693 goto free_wq;
2694 }
2695 }
2696
2697 platform->aux.name = "anx7625-aux";
2698 platform->aux.dev = dev;
2699 platform->aux.transfer = anx7625_aux_transfer;
2700 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2701 drm_dp_aux_init(aux: &platform->aux);
2702
2703 ret = anx7625_parse_dt(dev, pdata);
2704 if (ret) {
2705 if (ret != -EPROBE_DEFER)
2706 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2707 goto free_wq;
2708 }
2709
2710 if (!platform->pdata.is_dpi) {
2711 ret = anx7625_setup_dsi_device(ctx: platform);
2712 if (ret < 0)
2713 goto free_wq;
2714 }
2715
2716 /*
2717 * Registering the i2c devices will retrigger deferred probe, so it
2718 * needs to be done after calls that might return EPROBE_DEFER,
2719 * otherwise we can get an infinite loop.
2720 */
2721 if (anx7625_register_i2c_dummy_clients(ctx: platform, client) != 0) {
2722 ret = -ENOMEM;
2723 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
2724 goto free_wq;
2725 }
2726
2727 pm_runtime_enable(dev);
2728 pm_runtime_set_autosuspend_delay(dev, delay: 1000);
2729 pm_runtime_use_autosuspend(dev);
2730 pm_suspend_ignore_children(dev, enable: true);
2731 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev);
2732 if (ret)
2733 goto free_wq;
2734
2735 /*
2736 * Populating the aux bus will retrigger deferred probe, so it needs to
2737 * be done after calls that might return EPROBE_DEFER, otherwise we can
2738 * get an infinite loop.
2739 */
2740 ret = devm_of_dp_aux_populate_bus(aux: &platform->aux, done_probing: anx7625_link_bridge);
2741 if (ret) {
2742 if (ret != -ENODEV) {
2743 DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret);
2744 goto free_wq;
2745 }
2746
2747 ret = anx7625_link_bridge(aux: &platform->aux);
2748 if (ret)
2749 goto free_wq;
2750 }
2751
2752 if (!platform->pdata.low_power_mode) {
2753 anx7625_disable_pd_protocol(ctx: platform);
2754 pm_runtime_get_sync(dev);
2755 _anx7625_hpd_polling(ctx: platform, wait_us: 5000 * 100);
2756 }
2757
2758 /* Add work function */
2759 if (platform->pdata.intp_irq)
2760 queue_work(wq: platform->workqueue, work: &platform->work);
2761
2762 if (platform->pdata.audio_en)
2763 anx7625_register_audio(dev, ctx: platform);
2764
2765 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
2766
2767 return 0;
2768
2769free_wq:
2770 if (platform->workqueue)
2771 destroy_workqueue(wq: platform->workqueue);
2772
2773free_hdcp_wq:
2774 if (platform->hdcp_workqueue)
2775 destroy_workqueue(wq: platform->hdcp_workqueue);
2776
2777 return ret;
2778}
2779
2780static void anx7625_i2c_remove(struct i2c_client *client)
2781{
2782 struct anx7625_data *platform = i2c_get_clientdata(client);
2783
2784 drm_bridge_remove(bridge: &platform->bridge);
2785
2786 if (platform->pdata.intp_irq)
2787 destroy_workqueue(wq: platform->workqueue);
2788
2789 if (platform->hdcp_workqueue) {
2790 cancel_delayed_work(dwork: &platform->hdcp_work);
2791 flush_workqueue(platform->hdcp_workqueue);
2792 destroy_workqueue(wq: platform->hdcp_workqueue);
2793 }
2794
2795 if (!platform->pdata.low_power_mode)
2796 pm_runtime_put_sync_suspend(dev: &client->dev);
2797
2798 if (platform->pdata.audio_en)
2799 anx7625_unregister_audio(ctx: platform);
2800}
2801
2802static const struct i2c_device_id anx7625_id[] = {
2803 {"anx7625", 0},
2804 {}
2805};
2806
2807MODULE_DEVICE_TABLE(i2c, anx7625_id);
2808
2809static const struct of_device_id anx_match_table[] = {
2810 {.compatible = "analogix,anx7625",},
2811 {},
2812};
2813MODULE_DEVICE_TABLE(of, anx_match_table);
2814
2815static struct i2c_driver anx7625_driver = {
2816 .driver = {
2817 .name = "anx7625",
2818 .of_match_table = anx_match_table,
2819 .pm = &anx7625_pm_ops,
2820 },
2821 .probe = anx7625_i2c_probe,
2822 .remove = anx7625_i2c_remove,
2823
2824 .id_table = anx7625_id,
2825};
2826
2827module_i2c_driver(anx7625_driver);
2828
2829MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
2830MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
2831MODULE_LICENSE("GPL v2");
2832MODULE_VERSION(ANX7625_DRV_VERSION);
2833

source code of linux/drivers/gpu/drm/bridge/analogix/anx7625.c