1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright © 2006-2011 Intel Corporation
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 */
8
9#include <linux/delay.h>
10#include <linux/i2c.h>
11
12#include <drm/drm_crtc.h>
13#include <drm/drm_modeset_helper_vtables.h>
14
15#include "cdv_device.h"
16#include "framebuffer.h"
17#include "gma_display.h"
18#include "power.h"
19#include "psb_drv.h"
20#include "psb_intel_drv.h"
21#include "psb_intel_reg.h"
22
23static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
24 struct drm_crtc *crtc, int target,
25 int refclk, struct gma_clock_t *best_clock);
26
27
28#define CDV_LIMIT_SINGLE_LVDS_96 0
29#define CDV_LIMIT_SINGLE_LVDS_100 1
30#define CDV_LIMIT_DAC_HDMI_27 2
31#define CDV_LIMIT_DAC_HDMI_96 3
32#define CDV_LIMIT_DP_27 4
33#define CDV_LIMIT_DP_100 5
34
35static const struct gma_limit_t cdv_intel_limits[] = {
36 { /* CDV_SINGLE_LVDS_96MHz */
37 .dot = {.min = 20000, .max = 115500},
38 .vco = {.min = 1800000, .max = 3600000},
39 .n = {.min = 2, .max = 6},
40 .m = {.min = 60, .max = 160},
41 .m1 = {.min = 0, .max = 0},
42 .m2 = {.min = 58, .max = 158},
43 .p = {.min = 28, .max = 140},
44 .p1 = {.min = 2, .max = 10},
45 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
46 .find_pll = gma_find_best_pll,
47 },
48 { /* CDV_SINGLE_LVDS_100MHz */
49 .dot = {.min = 20000, .max = 115500},
50 .vco = {.min = 1800000, .max = 3600000},
51 .n = {.min = 2, .max = 6},
52 .m = {.min = 60, .max = 160},
53 .m1 = {.min = 0, .max = 0},
54 .m2 = {.min = 58, .max = 158},
55 .p = {.min = 28, .max = 140},
56 .p1 = {.min = 2, .max = 10},
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
59 */
60 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
61 .find_pll = gma_find_best_pll,
62 },
63 { /* CDV_DAC_HDMI_27MHz */
64 .dot = {.min = 20000, .max = 400000},
65 .vco = {.min = 1809000, .max = 3564000},
66 .n = {.min = 1, .max = 1},
67 .m = {.min = 67, .max = 132},
68 .m1 = {.min = 0, .max = 0},
69 .m2 = {.min = 65, .max = 130},
70 .p = {.min = 5, .max = 90},
71 .p1 = {.min = 1, .max = 9},
72 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
73 .find_pll = gma_find_best_pll,
74 },
75 { /* CDV_DAC_HDMI_96MHz */
76 .dot = {.min = 20000, .max = 400000},
77 .vco = {.min = 1800000, .max = 3600000},
78 .n = {.min = 2, .max = 6},
79 .m = {.min = 60, .max = 160},
80 .m1 = {.min = 0, .max = 0},
81 .m2 = {.min = 58, .max = 158},
82 .p = {.min = 5, .max = 100},
83 .p1 = {.min = 1, .max = 10},
84 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
85 .find_pll = gma_find_best_pll,
86 },
87 { /* CDV_DP_27MHz */
88 .dot = {.min = 160000, .max = 272000},
89 .vco = {.min = 1809000, .max = 3564000},
90 .n = {.min = 1, .max = 1},
91 .m = {.min = 67, .max = 132},
92 .m1 = {.min = 0, .max = 0},
93 .m2 = {.min = 65, .max = 130},
94 .p = {.min = 5, .max = 90},
95 .p1 = {.min = 1, .max = 9},
96 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
97 .find_pll = cdv_intel_find_dp_pll,
98 },
99 { /* CDV_DP_100MHz */
100 .dot = {.min = 160000, .max = 272000},
101 .vco = {.min = 1800000, .max = 3600000},
102 .n = {.min = 2, .max = 6},
103 .m = {.min = 60, .max = 164},
104 .m1 = {.min = 0, .max = 0},
105 .m2 = {.min = 58, .max = 162},
106 .p = {.min = 5, .max = 100},
107 .p1 = {.min = 1, .max = 10},
108 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
109 .find_pll = cdv_intel_find_dp_pll,
110 }
111};
112
113#define _wait_for(COND, MS, W) ({ \
114 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
115 int ret__ = 0; \
116 while (!(COND)) { \
117 if (time_after(jiffies, timeout__)) { \
118 ret__ = -ETIMEDOUT; \
119 break; \
120 } \
121 if (W && !in_dbg_master()) \
122 msleep(W); \
123 } \
124 ret__; \
125})
126
127#define wait_for(COND, MS) _wait_for(COND, MS, 1)
128
129
130int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
131{
132 int ret;
133
134 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
135 if (ret) {
136 DRM_ERROR("timeout waiting for SB to idle before read\n");
137 return ret;
138 }
139
140 REG_WRITE(SB_ADDR, reg);
141 REG_WRITE(SB_PCKT,
142 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
143 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
144 SET_FIELD(0xf, SB_BYTE_ENABLE));
145
146 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
147 if (ret) {
148 DRM_ERROR("timeout waiting for SB to idle after read\n");
149 return ret;
150 }
151
152 *val = REG_READ(SB_DATA);
153
154 return 0;
155}
156
157int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
158{
159 int ret;
160 static bool dpio_debug = true;
161 u32 temp;
162
163 if (dpio_debug) {
164 if (cdv_sb_read(dev, reg, val: &temp) == 0)
165 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
166 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
167 }
168
169 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
170 if (ret) {
171 DRM_ERROR("timeout waiting for SB to idle before write\n");
172 return ret;
173 }
174
175 REG_WRITE(SB_ADDR, reg);
176 REG_WRITE(SB_DATA, val);
177 REG_WRITE(SB_PCKT,
178 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
179 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
180 SET_FIELD(0xf, SB_BYTE_ENABLE));
181
182 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
183 if (ret) {
184 DRM_ERROR("timeout waiting for SB to idle after write\n");
185 return ret;
186 }
187
188 if (dpio_debug) {
189 if (cdv_sb_read(dev, reg, val: &temp) == 0)
190 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
191 }
192
193 return 0;
194}
195
196/* Reset the DPIO configuration register. The BIOS does this at every
197 * mode set.
198 */
199void cdv_sb_reset(struct drm_device *dev)
200{
201
202 REG_WRITE(DPIO_CFG, 0);
203 REG_READ(DPIO_CFG);
204 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
205}
206
207/* Unlike most Intel display engines, on Cedarview the DPLL registers
208 * are behind this sideband bus. They must be programmed while the
209 * DPLL reference clock is on in the DPLL control register, but before
210 * the DPLL is enabled in the DPLL control register.
211 */
212static int
213cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
214 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
215{
216 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
217 int pipe = gma_crtc->pipe;
218 u32 m, n_vco, p;
219 int ret = 0;
220 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
221 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
222 u32 ref_value;
223 u32 lane_reg, lane_value;
224
225 cdv_sb_reset(dev);
226
227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
228
229 udelay(100);
230
231 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
232 ref_value = 0x68A701;
233
234 cdv_sb_write(dev, SB_REF_SFR(pipe), val: ref_value);
235
236 /* We don't know what the other fields of these regs are, so
237 * leave them in place.
238 */
239 /*
240 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
241 * for the pipe A/B. Display spec 1.06 has wrong definition.
242 * Correct definition is like below:
243 *
244 * refclka mean use clock from same PLL
245 *
246 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
247 *
248 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
249 *
250 */
251 ret = cdv_sb_read(dev, reg: ref_sfr, val: &ref_value);
252 if (ret)
253 return ret;
254 ref_value &= ~(REF_CLK_MASK);
255
256 /* use DPLL_A for pipeB on CRT/HDMI */
257 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
258 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
259 ref_value |= REF_CLK_DPLLA;
260 } else {
261 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
262 ref_value |= REF_CLK_DPLL;
263 }
264 ret = cdv_sb_write(dev, reg: ref_sfr, val: ref_value);
265 if (ret)
266 return ret;
267
268 ret = cdv_sb_read(dev, SB_M(pipe), val: &m);
269 if (ret)
270 return ret;
271 m &= ~SB_M_DIVIDER_MASK;
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
273 ret = cdv_sb_write(dev, SB_M(pipe), val: m);
274 if (ret)
275 return ret;
276
277 ret = cdv_sb_read(dev, SB_N_VCO(pipe), val: &n_vco);
278 if (ret)
279 return ret;
280
281 /* Follow the BIOS to program the N_DIVIDER REG */
282 n_vco &= 0xFFFF;
283 n_vco |= 0x107;
284 n_vco &= ~(SB_N_VCO_SEL_MASK |
285 SB_N_DIVIDER_MASK |
286 SB_N_CB_TUNE_MASK);
287
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
289
290 if (clock->vco < 2250000) {
291 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
292 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
293 } else if (clock->vco < 2750000) {
294 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
295 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
296 } else if (clock->vco < 3300000) {
297 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
298 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
299 } else {
300 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
301 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
302 }
303
304 ret = cdv_sb_write(dev, SB_N_VCO(pipe), val: n_vco);
305 if (ret)
306 return ret;
307
308 ret = cdv_sb_read(dev, SB_P(pipe), val: &p);
309 if (ret)
310 return ret;
311 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
312 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
313 switch (clock->p2) {
314 case 5:
315 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
316 break;
317 case 10:
318 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
319 break;
320 case 14:
321 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
322 break;
323 case 7:
324 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
325 break;
326 default:
327 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
328 return -EINVAL;
329 }
330 ret = cdv_sb_write(dev, SB_P(pipe), val: p);
331 if (ret)
332 return ret;
333
334 if (ddi_select) {
335 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
336 lane_reg = PSB_LANE0;
337 cdv_sb_read(dev, reg: lane_reg, val: &lane_value);
338 lane_value &= ~(LANE_PLL_MASK);
339 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
340 cdv_sb_write(dev, reg: lane_reg, val: lane_value);
341
342 lane_reg = PSB_LANE1;
343 cdv_sb_read(dev, reg: lane_reg, val: &lane_value);
344 lane_value &= ~(LANE_PLL_MASK);
345 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
346 cdv_sb_write(dev, reg: lane_reg, val: lane_value);
347 } else {
348 lane_reg = PSB_LANE2;
349 cdv_sb_read(dev, reg: lane_reg, val: &lane_value);
350 lane_value &= ~(LANE_PLL_MASK);
351 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
352 cdv_sb_write(dev, reg: lane_reg, val: lane_value);
353
354 lane_reg = PSB_LANE3;
355 cdv_sb_read(dev, reg: lane_reg, val: &lane_value);
356 lane_value &= ~(LANE_PLL_MASK);
357 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
358 cdv_sb_write(dev, reg: lane_reg, val: lane_value);
359 }
360 }
361 return 0;
362}
363
364static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
365 int refclk)
366{
367 const struct gma_limit_t *limit;
368 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 /*
370 * Now only single-channel LVDS is supported on CDV. If it is
371 * incorrect, please add the dual-channel LVDS.
372 */
373 if (refclk == 96000)
374 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
375 else
376 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
377 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
378 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
379 if (refclk == 27000)
380 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
381 else
382 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
383 } else {
384 if (refclk == 27000)
385 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
386 else
387 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
388 }
389 return limit;
390}
391
392/* m1 is reserved as 0 in CDV, n is a ring counter */
393static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
394{
395 clock->m = clock->m2 + 2;
396 clock->p = clock->p1 * clock->p2;
397 clock->vco = (refclk * clock->m) / clock->n;
398 clock->dot = clock->vco / clock->p;
399}
400
401static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
402 struct drm_crtc *crtc, int target,
403 int refclk,
404 struct gma_clock_t *best_clock)
405{
406 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
407 struct gma_clock_t clock;
408
409 memset(&clock, 0, sizeof(clock));
410
411 switch (refclk) {
412 case 27000:
413 if (target < 200000) {
414 clock.p1 = 2;
415 clock.p2 = 10;
416 clock.n = 1;
417 clock.m1 = 0;
418 clock.m2 = 118;
419 } else {
420 clock.p1 = 1;
421 clock.p2 = 10;
422 clock.n = 1;
423 clock.m1 = 0;
424 clock.m2 = 98;
425 }
426 break;
427
428 case 100000:
429 if (target < 200000) {
430 clock.p1 = 2;
431 clock.p2 = 10;
432 clock.n = 5;
433 clock.m1 = 0;
434 clock.m2 = 160;
435 } else {
436 clock.p1 = 1;
437 clock.p2 = 10;
438 clock.n = 5;
439 clock.m1 = 0;
440 clock.m2 = 133;
441 }
442 break;
443
444 default:
445 return false;
446 }
447
448 gma_crtc->clock_funcs->clock(refclk, &clock);
449 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
450 return true;
451}
452
453#define FIFO_PIPEA (1 << 0)
454#define FIFO_PIPEB (1 << 1)
455
456static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
457{
458 struct drm_crtc *crtc;
459 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
460 struct gma_crtc *gma_crtc = NULL;
461
462 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
463 gma_crtc = to_gma_crtc(crtc);
464
465 if (crtc->primary->fb == NULL || !gma_crtc->active)
466 return false;
467 return true;
468}
469
470void cdv_disable_sr(struct drm_device *dev)
471{
472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
473
474 /* Disable self-refresh before adjust WM */
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
476 REG_READ(FW_BLC_SELF);
477
478 gma_wait_for_vblank(dev);
479
480 /* Cedarview workaround to write ovelay plane, which force to leave
481 * MAX_FIFO state.
482 */
483 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
484 REG_READ(OV_OVADD);
485
486 gma_wait_for_vblank(dev);
487 }
488
489}
490
491void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
492{
493 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
494 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
495
496 /* Is only one pipe enabled? */
497 if (cdv_intel_pipe_enabled(dev, pipe: 0) ^ cdv_intel_pipe_enabled(dev, pipe: 1)) {
498 u32 fw;
499
500 fw = REG_READ(DSPFW1);
501 fw &= ~DSP_FIFO_SR_WM_MASK;
502 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
503 fw &= ~CURSOR_B_FIFO_WM_MASK;
504 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
505 REG_WRITE(DSPFW1, fw);
506
507 fw = REG_READ(DSPFW2);
508 fw &= ~CURSOR_A_FIFO_WM_MASK;
509 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
510 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
511 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
512 REG_WRITE(DSPFW2, fw);
513
514 REG_WRITE(DSPFW3, 0x36000000);
515
516 /* ignore FW4 */
517
518 /* Is pipe b lvds ? */
519 if (gma_crtc->pipe == 1 &&
520 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 REG_WRITE(DSPFW5, 0x00040330);
522 } else {
523 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
524 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
525 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
526 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
527 REG_WRITE(DSPFW5, fw);
528 }
529
530 REG_WRITE(DSPFW6, 0x10);
531
532 gma_wait_for_vblank(dev);
533
534 /* enable self-refresh for single pipe active */
535 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
536 REG_READ(FW_BLC_SELF);
537 gma_wait_for_vblank(dev);
538
539 } else {
540
541 /* HW team suggested values... */
542 REG_WRITE(DSPFW1, 0x3f880808);
543 REG_WRITE(DSPFW2, 0x0b020202);
544 REG_WRITE(DSPFW3, 0x24000000);
545 REG_WRITE(DSPFW4, 0x08030202);
546 REG_WRITE(DSPFW5, 0x01010101);
547 REG_WRITE(DSPFW6, 0x1d0);
548
549 gma_wait_for_vblank(dev);
550
551 dev_priv->ops->disable_sr(dev);
552 }
553}
554
555/*
556 * Return the pipe currently connected to the panel fitter,
557 * or -1 if the panel fitter is not present or not in use
558 */
559static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
560{
561 u32 pfit_control;
562
563 pfit_control = REG_READ(PFIT_CONTROL);
564
565 /* See if the panel fitter is in use */
566 if ((pfit_control & PFIT_ENABLE) == 0)
567 return -1;
568 return (pfit_control >> 29) & 0x3;
569}
570
571static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
572 struct drm_display_mode *mode,
573 struct drm_display_mode *adjusted_mode,
574 int x, int y,
575 struct drm_framebuffer *old_fb)
576{
577 struct drm_device *dev = crtc->dev;
578 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
579 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
580 int pipe = gma_crtc->pipe;
581 const struct psb_offset *map = &dev_priv->regmap[pipe];
582 int refclk;
583 struct gma_clock_t clock;
584 u32 dpll = 0, dspcntr, pipeconf;
585 bool ok;
586 bool is_lvds = false;
587 bool is_dp = false;
588 struct drm_connector_list_iter conn_iter;
589 struct drm_connector *connector;
590 const struct gma_limit_t *limit;
591 u32 ddi_select = 0;
592 bool is_edp = false;
593
594 drm_connector_list_iter_begin(dev, iter: &conn_iter);
595 drm_for_each_connector_iter(connector, &conn_iter) {
596 struct gma_encoder *gma_encoder =
597 gma_attached_encoder(connector);
598
599 if (!connector->encoder
600 || connector->encoder->crtc != crtc)
601 continue;
602
603 ddi_select = gma_encoder->ddi_select;
604 switch (gma_encoder->type) {
605 case INTEL_OUTPUT_LVDS:
606 is_lvds = true;
607 break;
608 case INTEL_OUTPUT_ANALOG:
609 case INTEL_OUTPUT_HDMI:
610 break;
611 case INTEL_OUTPUT_DISPLAYPORT:
612 is_dp = true;
613 break;
614 case INTEL_OUTPUT_EDP:
615 is_edp = true;
616 break;
617 default:
618 drm_connector_list_iter_end(iter: &conn_iter);
619 DRM_ERROR("invalid output type.\n");
620 return 0;
621 }
622
623 break;
624 }
625 drm_connector_list_iter_end(iter: &conn_iter);
626
627 if (dev_priv->dplla_96mhz)
628 /* low-end sku, 96/100 mhz */
629 refclk = 96000;
630 else
631 /* high-end sku, 27/100 mhz */
632 refclk = 27000;
633 if (is_dp || is_edp) {
634 /*
635 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
636 * unnecessary to consider it for DP/eDP.
637 * On the high-end SKU, it will use the 27/100M reference clk
638 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
639 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
640 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
641 */
642 if (pipe == 0)
643 refclk = 27000;
644 else
645 refclk = 100000;
646 }
647
648 if (is_lvds && dev_priv->lvds_use_ssc) {
649 refclk = dev_priv->lvds_ssc_freq * 1000;
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
651 }
652
653 drm_mode_debug_printmodeline(mode: adjusted_mode);
654
655 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
656
657 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
658 &clock);
659 if (!ok) {
660 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
661 adjusted_mode->clock, clock.dot);
662 return 0;
663 }
664
665 dpll = DPLL_VGA_MODE_DIS;
666
667 if (is_dp || is_edp) {
668 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
669 } else {
670 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
671 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
672 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
673 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
674 }
675
676 dpll |= DPLL_SYNCLOCK_ENABLE;
677/* if (is_lvds)
678 dpll |= DPLLB_MODE_LVDS;
679 else
680 dpll |= DPLLB_MODE_DAC_SERIAL; */
681 /* dpll |= (2 << 11); */
682
683 /* setup pipeconf */
684 pipeconf = REG_READ(map->conf);
685
686 pipeconf &= ~(PIPE_BPC_MASK);
687 if (is_edp) {
688 switch (dev_priv->edp.bpp) {
689 case 24:
690 pipeconf |= PIPE_8BPC;
691 break;
692 case 18:
693 pipeconf |= PIPE_6BPC;
694 break;
695 case 30:
696 pipeconf |= PIPE_10BPC;
697 break;
698 default:
699 pipeconf |= PIPE_8BPC;
700 break;
701 }
702 } else if (is_lvds) {
703 /* the BPC will be 6 if it is 18-bit LVDS panel */
704 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
705 pipeconf |= PIPE_8BPC;
706 else
707 pipeconf |= PIPE_6BPC;
708 } else
709 pipeconf |= PIPE_8BPC;
710
711 /* Set up the display plane register */
712 dspcntr = DISPPLANE_GAMMA_ENABLE;
713
714 if (pipe == 0)
715 dspcntr |= DISPPLANE_SEL_PIPE_A;
716 else
717 dspcntr |= DISPPLANE_SEL_PIPE_B;
718
719 dspcntr |= DISPLAY_PLANE_ENABLE;
720 pipeconf |= PIPEACONF_ENABLE;
721
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
723 REG_READ(map->dpll);
724
725 cdv_dpll_set_clock_cdv(dev, crtc, clock: &clock, is_lvds, ddi_select);
726
727 udelay(150);
728
729
730 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
731 * This is an exception to the general rule that mode_set doesn't turn
732 * things on.
733 */
734 if (is_lvds) {
735 u32 lvds = REG_READ(LVDS);
736
737 lvds |=
738 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
739 LVDS_PIPEB_SELECT;
740 /* Set the B0-B3 data pairs corresponding to
741 * whether we're going to
742 * set the DPLLs for dual-channel mode or not.
743 */
744 if (clock.p2 == 7)
745 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
746 else
747 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
748
749 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
750 * appropriately here, but we need to look more
751 * thoroughly into how panels behave in the two modes.
752 */
753
754 REG_WRITE(LVDS, lvds);
755 REG_READ(LVDS);
756 }
757
758 dpll |= DPLL_VCO_ENABLE;
759
760 /* Disable the panel fitter if it was on our pipe */
761 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
762 REG_WRITE(PFIT_CONTROL, 0);
763
764 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
765 drm_mode_debug_printmodeline(mode);
766
767 REG_WRITE(map->dpll,
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
769 REG_READ(map->dpll);
770 /* Wait for the clocks to stabilize. */
771 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
772
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
774 dev_err(dev->dev, "Failed to get DPLL lock\n");
775 return -EBUSY;
776 }
777
778 {
779 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
780 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
781 }
782
783 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
784 ((adjusted_mode->crtc_htotal - 1) << 16));
785 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
786 ((adjusted_mode->crtc_hblank_end - 1) << 16));
787 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
788 ((adjusted_mode->crtc_hsync_end - 1) << 16));
789 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
790 ((adjusted_mode->crtc_vtotal - 1) << 16));
791 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
792 ((adjusted_mode->crtc_vblank_end - 1) << 16));
793 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
794 ((adjusted_mode->crtc_vsync_end - 1) << 16));
795 /* pipesrc and dspsize control the size that is scaled from,
796 * which should always be the user's requested size.
797 */
798 REG_WRITE(map->size,
799 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
800 REG_WRITE(map->pos, 0);
801 REG_WRITE(map->src,
802 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
803 REG_WRITE(map->conf, pipeconf);
804 REG_READ(map->conf);
805
806 gma_wait_for_vblank(dev);
807
808 REG_WRITE(map->cntr, dspcntr);
809
810 /* Flush the plane changes */
811 {
812 const struct drm_crtc_helper_funcs *crtc_funcs =
813 crtc->helper_private;
814 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
815 }
816
817 gma_wait_for_vblank(dev);
818
819 return 0;
820}
821
822/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
823
824/* FIXME: why are we using this, should it be cdv_ in this tree ? */
825
826static void i8xx_clock(int refclk, struct gma_clock_t *clock)
827{
828 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
829 clock->p = clock->p1 * clock->p2;
830 clock->vco = refclk * clock->m / (clock->n + 2);
831 clock->dot = clock->vco / clock->p;
832}
833
834/* Returns the clock of the currently programmed mode of the given pipe. */
835static int cdv_intel_crtc_clock_get(struct drm_device *dev,
836 struct drm_crtc *crtc)
837{
838 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
839 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
840 int pipe = gma_crtc->pipe;
841 const struct psb_offset *map = &dev_priv->regmap[pipe];
842 u32 dpll;
843 u32 fp;
844 struct gma_clock_t clock;
845 bool is_lvds;
846 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
847
848 if (gma_power_begin(dev, force: false)) {
849 dpll = REG_READ(map->dpll);
850 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
851 fp = REG_READ(map->fp0);
852 else
853 fp = REG_READ(map->fp1);
854 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
855 gma_power_end(dev);
856 } else {
857 dpll = p->dpll;
858 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
859 fp = p->fp0;
860 else
861 fp = p->fp1;
862
863 is_lvds = (pipe == 1) &&
864 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
865 }
866
867 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
868 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
870
871 if (is_lvds) {
872 clock.p1 =
873 ffs((dpll &
874 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
875 DPLL_FPA01_P1_POST_DIV_SHIFT);
876 if (clock.p1 == 0) {
877 clock.p1 = 4;
878 dev_err(dev->dev, "PLL %d\n", dpll);
879 }
880 clock.p2 = 14;
881
882 if ((dpll & PLL_REF_INPUT_MASK) ==
883 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
884 /* XXX: might not be 66MHz */
885 i8xx_clock(refclk: 66000, clock: &clock);
886 } else
887 i8xx_clock(refclk: 48000, clock: &clock);
888 } else {
889 if (dpll & PLL_P1_DIVIDE_BY_TWO)
890 clock.p1 = 2;
891 else {
892 clock.p1 =
893 ((dpll &
894 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
895 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
896 }
897 if (dpll & PLL_P2_DIVIDE_BY_4)
898 clock.p2 = 4;
899 else
900 clock.p2 = 2;
901
902 i8xx_clock(refclk: 48000, clock: &clock);
903 }
904
905 /* XXX: It would be nice to validate the clocks, but we can't reuse
906 * i830PllIsValid() because it relies on the xf86_config connector
907 * configuration being accurate, which it isn't necessarily.
908 */
909
910 return clock.dot;
911}
912
913/** Returns the currently programmed mode of the given pipe. */
914struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
915 struct drm_crtc *crtc)
916{
917 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
918 int pipe = gma_crtc->pipe;
919 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
920 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
921 const struct psb_offset *map = &dev_priv->regmap[pipe];
922 struct drm_display_mode *mode;
923 int htot;
924 int hsync;
925 int vtot;
926 int vsync;
927
928 if (gma_power_begin(dev, force: false)) {
929 htot = REG_READ(map->htotal);
930 hsync = REG_READ(map->hsync);
931 vtot = REG_READ(map->vtotal);
932 vsync = REG_READ(map->vsync);
933 gma_power_end(dev);
934 } else {
935 htot = p->htotal;
936 hsync = p->hsync;
937 vtot = p->vtotal;
938 vsync = p->vsync;
939 }
940
941 mode = kzalloc(size: sizeof(*mode), GFP_KERNEL);
942 if (!mode)
943 return NULL;
944
945 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
946 mode->hdisplay = (htot & 0xffff) + 1;
947 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
948 mode->hsync_start = (hsync & 0xffff) + 1;
949 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
950 mode->vdisplay = (vtot & 0xffff) + 1;
951 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
952 mode->vsync_start = (vsync & 0xffff) + 1;
953 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
954
955 drm_mode_set_name(mode);
956 drm_mode_set_crtcinfo(p: mode, adjust_flags: 0);
957
958 return mode;
959}
960
961const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
962 .dpms = gma_crtc_dpms,
963 .mode_set = cdv_intel_crtc_mode_set,
964 .mode_set_base = gma_pipe_set_base,
965 .prepare = gma_crtc_prepare,
966 .commit = gma_crtc_commit,
967 .disable = gma_crtc_disable,
968};
969
970const struct gma_clock_funcs cdv_clock_funcs = {
971 .clock = cdv_intel_clock,
972 .limit = cdv_intel_limit,
973 .pll_is_valid = gma_pll_is_valid,
974};
975

source code of linux/drivers/gpu/drm/gma500/cdv_intel_display.c