1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /************************************************************************** |
3 | * Copyright (c) 2007-2011, Intel Corporation. |
4 | * All Rights Reserved. |
5 | * |
6 | **************************************************************************/ |
7 | |
8 | #ifndef _PSB_DRV_H_ |
9 | #define _PSB_DRV_H_ |
10 | |
11 | #include <linux/kref.h> |
12 | #include <linux/mm_types.h> |
13 | |
14 | #include <drm/drm_device.h> |
15 | |
16 | #include "gtt.h" |
17 | #include "intel_bios.h" |
18 | #include "mmu.h" |
19 | #include "oaktrail.h" |
20 | #include "opregion.h" |
21 | #include "power.h" |
22 | #include "psb_intel_drv.h" |
23 | #include "psb_reg.h" |
24 | |
25 | #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others" |
26 | |
27 | #define DRIVER_NAME "gma500" |
28 | #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650" |
29 | #define DRIVER_DATE "20140314" |
30 | |
31 | #define DRIVER_MAJOR 1 |
32 | #define DRIVER_MINOR 0 |
33 | #define DRIVER_PATCHLEVEL 0 |
34 | |
35 | /* Append new drm mode definition here, align with libdrm definition */ |
36 | #define DRM_MODE_SCALE_NO_SCALE 2 |
37 | |
38 | #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108) |
39 | #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100) |
40 | #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0) |
41 | |
42 | /* Hardware offsets */ |
43 | #define PSB_VDC_OFFSET 0x00000000 |
44 | #define PSB_VDC_SIZE 0x000080000 |
45 | #define MRST_MMIO_SIZE 0x0000C0000 |
46 | #define PSB_SGX_SIZE 0x8000 |
47 | #define PSB_SGX_OFFSET 0x00040000 |
48 | #define MRST_SGX_OFFSET 0x00080000 |
49 | |
50 | /* PCI resource identifiers */ |
51 | #define PSB_MMIO_RESOURCE 0 |
52 | #define PSB_AUX_RESOURCE 0 |
53 | #define PSB_GATT_RESOURCE 2 |
54 | #define PSB_GTT_RESOURCE 3 |
55 | |
56 | /* PCI configuration */ |
57 | #define PSB_GMCH_CTRL 0x52 |
58 | #define PSB_BSM 0x5C |
59 | #define _PSB_GMCH_ENABLED 0x4 |
60 | #define PSB_PGETBL_CTL 0x2020 |
61 | #define _PSB_PGETBL_ENABLED 0x00000001 |
62 | #define PSB_SGX_2D_SLAVE_PORT 0x4000 |
63 | #define PSB_LPC_GBA 0x44 |
64 | |
65 | /* TODO: To get rid of */ |
66 | #define PSB_TT_PRIV0_LIMIT (256*1024*1024) |
67 | #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) |
68 | |
69 | /* SGX side MMU definitions (these can probably go) */ |
70 | |
71 | /* Flags for external memory type field */ |
72 | #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ |
73 | #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ |
74 | #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ |
75 | |
76 | /* PTE's and PDE's */ |
77 | #define PSB_PDE_MASK 0x003FFFFF |
78 | #define PSB_PDE_SHIFT 22 |
79 | #define PSB_PTE_SHIFT 12 |
80 | |
81 | /* Cache control */ |
82 | #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ |
83 | #define PSB_PTE_WO 0x0002 /* Write only */ |
84 | #define PSB_PTE_RO 0x0004 /* Read only */ |
85 | #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ |
86 | |
87 | /* VDC registers and bits */ |
88 | #define PSB_MSVDX_CLOCKGATING 0x2064 |
89 | #define PSB_TOPAZ_CLOCKGATING 0x2068 |
90 | #define PSB_HWSTAM 0x2098 |
91 | #define PSB_INSTPM 0x20C0 |
92 | #define PSB_INT_IDENTITY_R 0x20A4 |
93 | #define _PSB_IRQ_ASLE (1<<0) |
94 | #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) |
95 | #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) |
96 | #define _PSB_DPST_PIPEB_FLAG (1<<4) |
97 | #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) |
98 | #define _PSB_VSYNC_PIPEB_FLAG (1<<5) |
99 | #define _PSB_DPST_PIPEA_FLAG (1<<6) |
100 | #define _PSB_PIPEA_EVENT_FLAG (1<<6) |
101 | #define _PSB_VSYNC_PIPEA_FLAG (1<<7) |
102 | #define _PSB_IRQ_DISP_HOTSYNC (1<<17) |
103 | #define _PSB_IRQ_SGX_FLAG (1<<18) |
104 | #define _PSB_IRQ_MSVDX_FLAG (1<<19) |
105 | #define _LNC_IRQ_TOPAZ_FLAG (1<<20) |
106 | |
107 | #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ |
108 | _PSB_VSYNC_PIPEB_FLAG) |
109 | |
110 | #define PSB_INT_IDENTITY_R 0x20A4 |
111 | #define PSB_INT_MASK_R 0x20A8 |
112 | #define PSB_INT_ENABLE_R 0x20A0 |
113 | |
114 | #define _PSB_MMU_ER_MASK 0x0001FF00 |
115 | #define _PSB_MMU_ER_HOST (1 << 16) |
116 | #define GPIOA 0x5010 |
117 | #define GPIOB 0x5014 |
118 | #define GPIOC 0x5018 |
119 | #define GPIOD 0x501c |
120 | #define GPIOE 0x5020 |
121 | #define GPIOF 0x5024 |
122 | #define GPIOG 0x5028 |
123 | #define GPIOH 0x502c |
124 | #define GPIO_CLOCK_DIR_MASK (1 << 0) |
125 | #define GPIO_CLOCK_DIR_IN (0 << 1) |
126 | #define GPIO_CLOCK_DIR_OUT (1 << 1) |
127 | #define GPIO_CLOCK_VAL_MASK (1 << 2) |
128 | #define GPIO_CLOCK_VAL_OUT (1 << 3) |
129 | #define GPIO_CLOCK_VAL_IN (1 << 4) |
130 | #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
131 | #define GPIO_DATA_DIR_MASK (1 << 8) |
132 | #define GPIO_DATA_DIR_IN (0 << 9) |
133 | #define GPIO_DATA_DIR_OUT (1 << 9) |
134 | #define GPIO_DATA_VAL_MASK (1 << 10) |
135 | #define GPIO_DATA_VAL_OUT (1 << 11) |
136 | #define GPIO_DATA_VAL_IN (1 << 12) |
137 | #define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
138 | |
139 | #define VCLK_DIVISOR_VGA0 0x6000 |
140 | #define VCLK_DIVISOR_VGA1 0x6004 |
141 | #define VCLK_POST_DIV 0x6010 |
142 | |
143 | #define PSB_COMM_2D (PSB_ENGINE_2D << 4) |
144 | #define PSB_COMM_3D (PSB_ENGINE_3D << 4) |
145 | #define PSB_COMM_TA (PSB_ENGINE_TA << 4) |
146 | #define PSB_COMM_HP (PSB_ENGINE_HP << 4) |
147 | #define PSB_COMM_USER_IRQ (1024 >> 2) |
148 | #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) |
149 | #define PSB_COMM_FW (2048 >> 2) |
150 | |
151 | #define PSB_UIRQ_VISTEST 1 |
152 | #define PSB_UIRQ_OOM_REPLY 2 |
153 | #define PSB_UIRQ_FIRE_TA_REPLY 3 |
154 | #define PSB_UIRQ_FIRE_RASTER_REPLY 4 |
155 | |
156 | #define PSB_2D_SIZE (256*1024*1024) |
157 | #define PSB_MAX_RELOC_PAGES 1024 |
158 | |
159 | #define PSB_LOW_REG_OFFS 0x0204 |
160 | #define PSB_HIGH_REG_OFFS 0x0600 |
161 | |
162 | #define PSB_NUM_VBLANKS 2 |
163 | |
164 | #define PSB_WATCHDOG_DELAY (HZ * 2) |
165 | #define PSB_LID_DELAY (HZ / 10) |
166 | |
167 | #define PSB_MAX_BRIGHTNESS 100 |
168 | |
169 | #define PSB_PWR_STATE_ON 1 |
170 | #define PSB_PWR_STATE_OFF 2 |
171 | |
172 | #define PSB_PMPOLICY_NOPM 0 |
173 | #define PSB_PMPOLICY_CLOCKGATING 1 |
174 | #define PSB_PMPOLICY_POWERDOWN 2 |
175 | |
176 | #define PSB_PMSTATE_POWERUP 0 |
177 | #define PSB_PMSTATE_CLOCKGATED 1 |
178 | #define PSB_PMSTATE_POWERDOWN 2 |
179 | #define PSB_PCIx_MSI_ADDR_LOC 0x94 |
180 | #define PSB_PCIx_MSI_DATA_LOC 0x98 |
181 | |
182 | /* Medfield crystal settings */ |
183 | #define KSEL_CRYSTAL_19 1 |
184 | #define KSEL_BYPASS_19 5 |
185 | #define KSEL_BYPASS_25 6 |
186 | #define KSEL_BYPASS_83_100 7 |
187 | |
188 | struct ; |
189 | struct opregion_acpi; |
190 | struct opregion_swsci; |
191 | struct opregion_asle; |
192 | |
193 | struct psb_intel_opregion { |
194 | struct opregion_header *; |
195 | struct opregion_acpi *acpi; |
196 | struct opregion_swsci *swsci; |
197 | struct opregion_asle *asle; |
198 | void *vbt; |
199 | u32 __iomem *lid_state; |
200 | struct work_struct asle_work; |
201 | }; |
202 | |
203 | struct sdvo_device_mapping { |
204 | u8 initialized; |
205 | u8 dvo_port; |
206 | u8 slave_addr; |
207 | u8 dvo_wiring; |
208 | u8 i2c_pin; |
209 | u8 i2c_speed; |
210 | u8 ddc_pin; |
211 | }; |
212 | |
213 | struct intel_gmbus { |
214 | struct i2c_adapter adapter; |
215 | struct i2c_adapter *force_bit; |
216 | u32 reg0; |
217 | }; |
218 | |
219 | /* Register offset maps */ |
220 | struct psb_offset { |
221 | u32 fp0; |
222 | u32 fp1; |
223 | u32 cntr; |
224 | u32 conf; |
225 | u32 src; |
226 | u32 dpll; |
227 | u32 dpll_md; |
228 | u32 htotal; |
229 | u32 hblank; |
230 | u32 hsync; |
231 | u32 vtotal; |
232 | u32 vblank; |
233 | u32 vsync; |
234 | u32 stride; |
235 | u32 size; |
236 | u32 pos; |
237 | u32 surf; |
238 | u32 addr; |
239 | u32 base; |
240 | u32 status; |
241 | u32 linoff; |
242 | u32 tileoff; |
243 | u32 palette; |
244 | }; |
245 | |
246 | /* |
247 | * Register save state. This is used to hold the context when the |
248 | * device is powered off. In the case of Oaktrail this can (but does not |
249 | * yet) include screen blank. Operations occuring during the save |
250 | * update the register cache instead. |
251 | */ |
252 | |
253 | /* Common status for pipes */ |
254 | struct psb_pipe { |
255 | u32 fp0; |
256 | u32 fp1; |
257 | u32 cntr; |
258 | u32 conf; |
259 | u32 src; |
260 | u32 dpll; |
261 | u32 dpll_md; |
262 | u32 htotal; |
263 | u32 hblank; |
264 | u32 hsync; |
265 | u32 vtotal; |
266 | u32 vblank; |
267 | u32 vsync; |
268 | u32 stride; |
269 | u32 size; |
270 | u32 pos; |
271 | u32 base; |
272 | u32 surf; |
273 | u32 addr; |
274 | u32 status; |
275 | u32 linoff; |
276 | u32 tileoff; |
277 | u32 palette[256]; |
278 | }; |
279 | |
280 | struct psb_state { |
281 | uint32_t saveVCLK_DIVISOR_VGA0; |
282 | uint32_t saveVCLK_DIVISOR_VGA1; |
283 | uint32_t saveVCLK_POST_DIV; |
284 | uint32_t saveVGACNTRL; |
285 | uint32_t saveADPA; |
286 | uint32_t saveLVDS; |
287 | uint32_t saveDVOA; |
288 | uint32_t saveDVOB; |
289 | uint32_t saveDVOC; |
290 | uint32_t savePP_ON; |
291 | uint32_t savePP_OFF; |
292 | uint32_t savePP_CONTROL; |
293 | uint32_t savePP_CYCLE; |
294 | uint32_t savePFIT_CONTROL; |
295 | uint32_t saveCLOCKGATING; |
296 | uint32_t saveDSPARB; |
297 | uint32_t savePFIT_AUTO_RATIOS; |
298 | uint32_t savePFIT_PGM_RATIOS; |
299 | uint32_t savePP_ON_DELAYS; |
300 | uint32_t savePP_OFF_DELAYS; |
301 | uint32_t savePP_DIVISOR; |
302 | uint32_t saveBCLRPAT_A; |
303 | uint32_t saveBCLRPAT_B; |
304 | uint32_t savePERF_MODE; |
305 | uint32_t saveDSPFW1; |
306 | uint32_t saveDSPFW2; |
307 | uint32_t saveDSPFW3; |
308 | uint32_t saveDSPFW4; |
309 | uint32_t saveDSPFW5; |
310 | uint32_t saveDSPFW6; |
311 | uint32_t saveCHICKENBIT; |
312 | uint32_t saveDSPACURSOR_CTRL; |
313 | uint32_t saveDSPBCURSOR_CTRL; |
314 | uint32_t saveDSPACURSOR_BASE; |
315 | uint32_t saveDSPBCURSOR_BASE; |
316 | uint32_t saveDSPACURSOR_POS; |
317 | uint32_t saveDSPBCURSOR_POS; |
318 | uint32_t saveOV_OVADD; |
319 | uint32_t saveOV_OGAMC0; |
320 | uint32_t saveOV_OGAMC1; |
321 | uint32_t saveOV_OGAMC2; |
322 | uint32_t saveOV_OGAMC3; |
323 | uint32_t saveOV_OGAMC4; |
324 | uint32_t saveOV_OGAMC5; |
325 | uint32_t saveOVC_OVADD; |
326 | uint32_t saveOVC_OGAMC0; |
327 | uint32_t saveOVC_OGAMC1; |
328 | uint32_t saveOVC_OGAMC2; |
329 | uint32_t saveOVC_OGAMC3; |
330 | uint32_t saveOVC_OGAMC4; |
331 | uint32_t saveOVC_OGAMC5; |
332 | |
333 | /* DPST register save */ |
334 | uint32_t saveHISTOGRAM_INT_CONTROL_REG; |
335 | uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; |
336 | uint32_t savePWM_CONTROL_LOGIC; |
337 | }; |
338 | |
339 | struct cdv_state { |
340 | uint32_t saveDSPCLK_GATE_D; |
341 | uint32_t saveRAMCLK_GATE_D; |
342 | uint32_t saveDSPARB; |
343 | uint32_t saveDSPFW[6]; |
344 | uint32_t saveADPA; |
345 | uint32_t savePP_CONTROL; |
346 | uint32_t savePFIT_PGM_RATIOS; |
347 | uint32_t saveLVDS; |
348 | uint32_t savePFIT_CONTROL; |
349 | uint32_t savePP_ON_DELAYS; |
350 | uint32_t savePP_OFF_DELAYS; |
351 | uint32_t savePP_CYCLE; |
352 | uint32_t saveVGACNTRL; |
353 | uint32_t saveIER; |
354 | uint32_t saveIMR; |
355 | u8 saveLBB; |
356 | }; |
357 | |
358 | struct psb_save_area { |
359 | struct psb_pipe pipe[3]; |
360 | uint32_t saveBSM; |
361 | uint32_t saveVBT; |
362 | union { |
363 | struct psb_state psb; |
364 | struct cdv_state cdv; |
365 | }; |
366 | uint32_t saveBLC_PWM_CTL2; |
367 | uint32_t saveBLC_PWM_CTL; |
368 | }; |
369 | |
370 | struct psb_ops; |
371 | |
372 | #define PSB_NUM_PIPE 3 |
373 | |
374 | struct intel_scu_ipc_dev; |
375 | |
376 | struct drm_psb_private { |
377 | struct drm_device dev; |
378 | |
379 | struct pci_dev *aux_pdev; /* Currently only used by mrst */ |
380 | struct pci_dev *lpc_pdev; /* Currently only used by mrst */ |
381 | const struct psb_ops *ops; |
382 | const struct psb_offset *regmap; |
383 | |
384 | struct child_device_config *child_dev; |
385 | int child_dev_num; |
386 | |
387 | struct psb_gtt gtt; |
388 | |
389 | /* GTT Memory manager */ |
390 | struct psb_gtt_mm *gtt_mm; |
391 | struct page *scratch_page; |
392 | u32 __iomem *gtt_map; |
393 | uint32_t stolen_base; |
394 | u8 __iomem *vram_addr; |
395 | unsigned long vram_stolen_size; |
396 | u16 gmch_ctrl; /* Saved GTT setup */ |
397 | u32 pge_ctl; |
398 | |
399 | struct mutex gtt_mutex; |
400 | struct resource *gtt_mem; /* Our PCI resource */ |
401 | |
402 | struct mutex mmap_mutex; |
403 | |
404 | struct psb_mmu_driver *mmu; |
405 | struct psb_mmu_pd *pf_pd; |
406 | |
407 | /* Register base */ |
408 | uint8_t __iomem *sgx_reg; |
409 | uint8_t __iomem *vdc_reg; |
410 | uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */ |
411 | uint16_t lpc_gpio_base; |
412 | uint32_t gatt_free_offset; |
413 | |
414 | /* Fencing / irq */ |
415 | uint32_t vdc_irq_mask; |
416 | uint32_t pipestat[PSB_NUM_PIPE]; |
417 | |
418 | spinlock_t irqmask_lock; |
419 | bool irq_enabled; |
420 | |
421 | /* Power */ |
422 | bool pm_initialized; |
423 | |
424 | /* Modesetting */ |
425 | struct psb_intel_mode_device mode_dev; |
426 | bool modeset; /* true if we have done the mode_device setup */ |
427 | |
428 | struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; |
429 | struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; |
430 | uint32_t num_pipe; |
431 | |
432 | /* OSPM info (Power management base) (TODO: can go ?) */ |
433 | uint32_t ospm_base; |
434 | |
435 | /* Sizes info */ |
436 | u32 fuse_reg_value; |
437 | u32 video_device_fuse; |
438 | |
439 | /* PCI revision ID for B0:D2:F0 */ |
440 | uint8_t platform_rev_id; |
441 | |
442 | /* gmbus */ |
443 | struct intel_gmbus *gmbus; |
444 | uint8_t __iomem *gmbus_reg; |
445 | |
446 | /* Used by SDVO */ |
447 | int crt_ddc_pin; |
448 | /* FIXME: The mappings should be parsed from bios but for now we can |
449 | pretend there are no mappings available */ |
450 | struct sdvo_device_mapping sdvo_mappings[2]; |
451 | u32 hotplug_supported_mask; |
452 | struct drm_property *broadcast_rgb_property; |
453 | struct drm_property *force_audio_property; |
454 | |
455 | /* LVDS info */ |
456 | int backlight_duty_cycle; /* restore backlight to this value */ |
457 | bool panel_wants_dither; |
458 | struct drm_display_mode *panel_fixed_mode; |
459 | struct drm_display_mode *lfp_lvds_vbt_mode; |
460 | struct drm_display_mode *sdvo_lvds_vbt_mode; |
461 | |
462 | struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ |
463 | struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ |
464 | |
465 | /* Feature bits from the VBIOS */ |
466 | unsigned int int_tv_support:1; |
467 | unsigned int lvds_dither:1; |
468 | unsigned int lvds_vbt:1; |
469 | unsigned int int_crt_support:1; |
470 | unsigned int lvds_use_ssc:1; |
471 | int lvds_ssc_freq; |
472 | bool is_lvds_on; |
473 | bool is_mipi_on; |
474 | bool lvds_enabled_in_vbt; |
475 | u32 mipi_ctrl_display; |
476 | |
477 | unsigned int core_freq; |
478 | uint32_t iLVDS_enable; |
479 | |
480 | /* MID specific */ |
481 | bool use_msi; |
482 | bool has_gct; |
483 | struct oaktrail_gct_data gct_data; |
484 | |
485 | /* Oaktrail HDMI state */ |
486 | struct oaktrail_hdmi_dev *hdmi_priv; |
487 | |
488 | /* Register state */ |
489 | struct psb_save_area regs; |
490 | |
491 | /* Hotplug handling */ |
492 | struct work_struct hotplug_work; |
493 | |
494 | /* LID-Switch */ |
495 | spinlock_t lid_lock; |
496 | struct timer_list lid_timer; |
497 | struct psb_intel_opregion opregion; |
498 | u32 lid_last_state; |
499 | |
500 | /* Watchdog */ |
501 | uint32_t apm_reg; |
502 | uint16_t apm_base; |
503 | |
504 | /* |
505 | * Used for modifying backlight from |
506 | * xrandr -- consider removing and using HAL instead |
507 | */ |
508 | struct intel_scu_ipc_dev *scu; |
509 | struct backlight_device *backlight_device; |
510 | struct drm_property *backlight_property; |
511 | bool backlight_enabled; |
512 | int backlight_level; |
513 | uint32_t blc_adj1; |
514 | uint32_t blc_adj2; |
515 | |
516 | bool dsr_enable; |
517 | u32 dsr_fb_update; |
518 | bool dpi_panel_on[3]; |
519 | void *dsi_configs[2]; |
520 | u32 bpp; |
521 | u32 bpp2; |
522 | |
523 | u32 pipeconf[3]; |
524 | u32 dspcntr[3]; |
525 | |
526 | bool dplla_96mhz; /* DPLL data from the VBT */ |
527 | |
528 | struct { |
529 | int rate; |
530 | int lanes; |
531 | int preemphasis; |
532 | int vswing; |
533 | |
534 | bool initialized; |
535 | bool support; |
536 | int bpp; |
537 | struct edp_power_seq pps; |
538 | } edp; |
539 | uint8_t panel_type; |
540 | }; |
541 | |
542 | static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev) |
543 | { |
544 | return container_of(dev, struct drm_psb_private, dev); |
545 | } |
546 | |
547 | /* Operations for each board type */ |
548 | struct psb_ops { |
549 | const char *name; |
550 | int pipes; /* Number of output pipes */ |
551 | int crtcs; /* Number of CRTCs */ |
552 | int sgx_offset; /* Base offset of SGX device */ |
553 | int hdmi_mask; /* Mask of HDMI CRTCs */ |
554 | int lvds_mask; /* Mask of LVDS CRTCs */ |
555 | int sdvo_mask; /* Mask of SDVO CRTCs */ |
556 | int cursor_needs_phys; /* If cursor base reg need physical address */ |
557 | |
558 | /* Sub functions */ |
559 | struct drm_crtc_helper_funcs const *crtc_helper; |
560 | const struct gma_clock_funcs *clock_funcs; |
561 | |
562 | /* Setup hooks */ |
563 | int (*chip_setup)(struct drm_device *dev); |
564 | void (*chip_teardown)(struct drm_device *dev); |
565 | /* Optional helper caller after modeset */ |
566 | void (*errata)(struct drm_device *dev); |
567 | |
568 | /* Display management hooks */ |
569 | int (*output_init)(struct drm_device *dev); |
570 | int (*hotplug)(struct drm_device *dev); |
571 | void (*hotplug_enable)(struct drm_device *dev, bool on); |
572 | /* Power management hooks */ |
573 | void (*init_pm)(struct drm_device *dev); |
574 | int (*save_regs)(struct drm_device *dev); |
575 | int (*restore_regs)(struct drm_device *dev); |
576 | void (*save_crtc)(struct drm_crtc *crtc); |
577 | void (*restore_crtc)(struct drm_crtc *crtc); |
578 | int (*power_up)(struct drm_device *dev); |
579 | int (*power_down)(struct drm_device *dev); |
580 | void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); |
581 | void (*disable_sr)(struct drm_device *dev); |
582 | |
583 | void (*lvds_bl_power)(struct drm_device *dev, bool on); |
584 | |
585 | /* Backlight */ |
586 | int (*backlight_init)(struct drm_device *dev); |
587 | void (*backlight_set)(struct drm_device *dev, int level); |
588 | int (*backlight_get)(struct drm_device *dev); |
589 | const char *backlight_name; |
590 | |
591 | int i2c_bus; /* I2C bus identifier for Moorestown */ |
592 | }; |
593 | |
594 | /* psb_lid.c */ |
595 | extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); |
596 | extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); |
597 | |
598 | /* modesetting */ |
599 | extern void psb_modeset_init(struct drm_device *dev); |
600 | extern void psb_modeset_cleanup(struct drm_device *dev); |
601 | |
602 | /* framebuffer */ |
603 | struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, |
604 | const struct drm_mode_fb_cmd2 *mode_cmd, |
605 | struct drm_gem_object *obj); |
606 | |
607 | /* fbdev */ |
608 | #if defined(CONFIG_DRM_FBDEV_EMULATION) |
609 | void psb_fbdev_setup(struct drm_psb_private *dev_priv); |
610 | #else |
611 | static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv) |
612 | { } |
613 | #endif |
614 | |
615 | /* backlight.c */ |
616 | int gma_backlight_init(struct drm_device *dev); |
617 | void gma_backlight_exit(struct drm_device *dev); |
618 | void gma_backlight_disable(struct drm_device *dev); |
619 | void gma_backlight_enable(struct drm_device *dev); |
620 | void gma_backlight_set(struct drm_device *dev, int v); |
621 | |
622 | /* oaktrail_crtc.c */ |
623 | extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; |
624 | |
625 | /* oaktrail_lvds.c */ |
626 | extern void oaktrail_lvds_init(struct drm_device *dev, |
627 | struct psb_intel_mode_device *mode_dev); |
628 | |
629 | /* psb_intel_display.c */ |
630 | extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; |
631 | |
632 | /* psb_intel_lvds.c */ |
633 | extern const struct drm_connector_helper_funcs |
634 | psb_intel_lvds_connector_helper_funcs; |
635 | extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; |
636 | |
637 | /* gem.c */ |
638 | extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
639 | struct drm_mode_create_dumb *args); |
640 | |
641 | /* psb_device.c */ |
642 | extern const struct psb_ops psb_chip_ops; |
643 | |
644 | /* oaktrail_device.c */ |
645 | extern const struct psb_ops oaktrail_chip_ops; |
646 | |
647 | /* cdv_device.c */ |
648 | extern const struct psb_ops cdv_chip_ops; |
649 | |
650 | /* Utilities */ |
651 | static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) |
652 | { |
653 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
654 | return ioread32(dev_priv->vdc_reg + reg); |
655 | } |
656 | |
657 | static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) |
658 | { |
659 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
660 | return ioread32(dev_priv->aux_reg + reg); |
661 | } |
662 | |
663 | #define REG_READ(reg) REGISTER_READ(dev, (reg)) |
664 | #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) |
665 | |
666 | /* Useful for post reads */ |
667 | static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, |
668 | uint32_t reg, int aux) |
669 | { |
670 | uint32_t val; |
671 | |
672 | if (aux) |
673 | val = REG_READ_AUX(reg); |
674 | else |
675 | val = REG_READ(reg); |
676 | |
677 | return val; |
678 | } |
679 | |
680 | #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) |
681 | |
682 | static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, |
683 | uint32_t val) |
684 | { |
685 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
686 | iowrite32((val), dev_priv->vdc_reg + (reg)); |
687 | } |
688 | |
689 | static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, |
690 | uint32_t val) |
691 | { |
692 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
693 | iowrite32((val), dev_priv->aux_reg + (reg)); |
694 | } |
695 | |
696 | #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) |
697 | #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) |
698 | |
699 | static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, |
700 | uint32_t val, int aux) |
701 | { |
702 | if (aux) |
703 | REG_WRITE_AUX(reg, val); |
704 | else |
705 | REG_WRITE(reg, val); |
706 | } |
707 | |
708 | #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) |
709 | |
710 | static inline void REGISTER_WRITE16(struct drm_device *dev, |
711 | uint32_t reg, uint32_t val) |
712 | { |
713 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
714 | iowrite16((val), dev_priv->vdc_reg + (reg)); |
715 | } |
716 | |
717 | #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) |
718 | |
719 | static inline void REGISTER_WRITE8(struct drm_device *dev, |
720 | uint32_t reg, uint32_t val) |
721 | { |
722 | struct drm_psb_private *dev_priv = to_drm_psb_private(dev); |
723 | iowrite8((val), dev_priv->vdc_reg + (reg)); |
724 | } |
725 | |
726 | #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) |
727 | |
728 | #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) |
729 | #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) |
730 | |
731 | #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) |
732 | #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) |
733 | |
734 | #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) |
735 | #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) |
736 | |
737 | #endif |
738 | |