1	/*
2	* Copyright © 2008-2015 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.
22	*
23	*/
24
25	#include <linux/dma-fence-array.h>
26	#include <linux/dma-fence-chain.h>
27	#include <linux/irq_work.h>
28	#include <linux/prefetch.h>
29	#include <linux/sched.h>
30	#include <linux/sched/clock.h>
31	#include <linux/sched/signal.h>
32	#include <linux/sched/mm.h>
33
34	#include "gem/i915_gem_context.h"
35	#include "gt/intel_breadcrumbs.h"
36	#include "gt/intel_context.h"
37	#include "gt/intel_engine.h"
38	#include "gt/intel_engine_heartbeat.h"
39	#include "gt/intel_engine_regs.h"
40	#include "gt/intel_gpu_commands.h"
41	#include "gt/intel_reset.h"
42	#include "gt/intel_ring.h"
43	#include "gt/intel_rps.h"
44
45	#include "i915_active.h"
46	#include "i915_config.h"
47	#include "i915_deps.h"
48	#include "i915_driver.h"
49	#include "i915_drv.h"
50	#include "i915_trace.h"
51
52	struct execute_cb {
53	struct irq_work work;
54	struct i915_sw_fence *fence;
55	};
56
57	static struct kmem_cache *slab_requests;
58	static struct kmem_cache *slab_execute_cbs;
59
60	static const char *i915_fence_get_driver_name(struct dma_fence *fence)
61	{
62	return dev_name(dev: to_request(fence)->i915->drm.dev);
63	}
64
65	static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
66	{
67	const struct i915_gem_context *ctx;
68
69	/*
70	* The timeline struct (as part of the ppgtt underneath a context)
71	* may be freed when the request is no longer in use by the GPU.
72	* We could extend the life of a context to beyond that of all
73	* fences, possibly keeping the hw resource around indefinitely,
74	* or we just give them a false name. Since
75	* dma_fence_ops.get_timeline_name is a debug feature, the occasional
76	* lie seems justifiable.
77	*/
78	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
79	return "signaled";
80
81	ctx = i915_request_gem_context(rq: to_request(fence));
82	if (!ctx)
83	return "[" DRIVER_NAME "]";
84
85	return ctx->name;
86	}
87
88	static bool i915_fence_signaled(struct dma_fence *fence)
89	{
90	return i915_request_completed(rq: to_request(fence));
91	}
92
93	static bool i915_fence_enable_signaling(struct dma_fence *fence)
94	{
95	return i915_request_enable_breadcrumb(request: to_request(fence));
96	}
97
98	static signed long i915_fence_wait(struct dma_fence *fence,
99	bool interruptible,
100	signed long timeout)
101	{
102	return i915_request_wait_timeout(rq: to_request(fence),
103	flags: interruptible | I915_WAIT_PRIORITY,
104	timeout);
105	}
106
107	struct kmem_cache *i915_request_slab_cache(void)
108	{
109	return slab_requests;
110	}
111
112	static void i915_fence_release(struct dma_fence *fence)
113	{
114	struct i915_request *rq = to_request(fence);
115
116	GEM_BUG_ON(rq->guc_prio != GUC_PRIO_INIT &&
117	rq->guc_prio != GUC_PRIO_FINI);
118
119	i915_request_free_capture_list(fetch_and_zero(&rq->capture_list));
120	if (rq->batch_res) {
121	i915_vma_resource_put(vma_res: rq->batch_res);
122	rq->batch_res = NULL;
123	}
124
125	/*
126	* The request is put onto a RCU freelist (i.e. the address
127	* is immediately reused), mark the fences as being freed now.
128	* Otherwise the debugobjects for the fences are only marked as
129	* freed when the slab cache itself is freed, and so we would get
130	* caught trying to reuse dead objects.
131	*/
132	i915_sw_fence_fini(fence: &rq->submit);
133	i915_sw_fence_fini(fence: &rq->semaphore);
134
135	/*
136	* Keep one request on each engine for reserved use under mempressure.
137	*
138	* We do not hold a reference to the engine here and so have to be
139	* very careful in what rq->engine we poke. The virtual engine is
140	* referenced via the rq->context and we released that ref during
141	* i915_request_retire(), ergo we must not dereference a virtual
142	* engine here. Not that we would want to, as the only consumer of
143	* the reserved engine->request_pool is the power management parking,
144	* which must-not-fail, and that is only run on the physical engines.
145	*
146	* Since the request must have been executed to be have completed,
147	* we know that it will have been processed by the HW and will
148	* not be unsubmitted again, so rq->engine and rq->execution_mask
149	* at this point is stable. rq->execution_mask will be a single
150	* bit if the last and _only_ engine it could execution on was a
151	* physical engine, if it's multiple bits then it started on and
152	* could still be on a virtual engine. Thus if the mask is not a
153	* power-of-two we assume that rq->engine may still be a virtual
154	* engine and so a dangling invalid pointer that we cannot dereference
155	*
156	* For example, consider the flow of a bonded request through a virtual
157	* engine. The request is created with a wide engine mask (all engines
158	* that we might execute on). On processing the bond, the request mask
159	* is reduced to one or more engines. If the request is subsequently
160	* bound to a single engine, it will then be constrained to only
161	* execute on that engine and never returned to the virtual engine
162	* after timeslicing away, see __unwind_incomplete_requests(). Thus we
163	* know that if the rq->execution_mask is a single bit, rq->engine
164	* can be a physical engine with the exact corresponding mask.
165	*/
166	if (is_power_of_2(n: rq->execution_mask) &&
167	!cmpxchg(&rq->engine->request_pool, NULL, rq))
168	return;
169
170	kmem_cache_free(s: slab_requests, objp: rq);
171	}
172
173	const struct dma_fence_ops i915_fence_ops = {
174	.get_driver_name = i915_fence_get_driver_name,
175	.get_timeline_name = i915_fence_get_timeline_name,
176	.enable_signaling = i915_fence_enable_signaling,
177	.signaled = i915_fence_signaled,
178	.wait = i915_fence_wait,
179	.release = i915_fence_release,
180	};
181
182	static void irq_execute_cb(struct irq_work *wrk)
183	{
184	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
185
186	i915_sw_fence_complete(fence: cb->fence);
187	kmem_cache_free(s: slab_execute_cbs, objp: cb);
188	}
189
190	static __always_inline void
191	__notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
192	{
193	struct execute_cb *cb, *cn;
194
195	if (llist_empty(head: &rq->execute_cb))
196	return;
197
198	llist_for_each_entry_safe(cb, cn,
199	llist_del_all(&rq->execute_cb),
200	work.node.llist)
201	fn(&cb->work);
202	}
203
204	static void __notify_execute_cb_irq(struct i915_request *rq)
205	{
206	__notify_execute_cb(rq, fn: irq_work_queue);
207	}
208
209	static bool irq_work_imm(struct irq_work *wrk)
210	{
211	wrk->func(wrk);
212	return false;
213	}
214
215	void i915_request_notify_execute_cb_imm(struct i915_request *rq)
216	{
217	__notify_execute_cb(rq, fn: irq_work_imm);
218	}
219
220	static void __i915_request_fill(struct i915_request *rq, u8 val)
221	{
222	void *vaddr = rq->ring->vaddr;
223	u32 head;
224
225	head = rq->infix;
226	if (rq->postfix < head) {
227	memset(vaddr + head, val, rq->ring->size - head);
228	head = 0;
229	}
230	memset(vaddr + head, val, rq->postfix - head);
231	}
232
233	/**
234	* i915_request_active_engine
235	* @rq: request to inspect
236	* @active: pointer in which to return the active engine
237	*
238	* Fills the currently active engine to the @active pointer if the request
239	* is active and still not completed.
240	*
241	* Returns true if request was active or false otherwise.
242	*/
243	bool
244	i915_request_active_engine(struct i915_request *rq,
245	struct intel_engine_cs **active)
246	{
247	struct intel_engine_cs *engine, *locked;
248	bool ret = false;
249
250	/*
251	* Serialise with __i915_request_submit() so that it sees
252	* is-banned?, or we know the request is already inflight.
253	*
254	* Note that rq->engine is unstable, and so we double
255	* check that we have acquired the lock on the final engine.
256	*/
257	locked = READ_ONCE(rq->engine);
258	spin_lock_irq(lock: &locked->sched_engine->lock);
259	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
260	spin_unlock(lock: &locked->sched_engine->lock);
261	locked = engine;
262	spin_lock(lock: &locked->sched_engine->lock);
263	}
264
265	if (i915_request_is_active(rq)) {
266	if (!__i915_request_is_complete(rq))
267	*active = locked;
268	ret = true;
269	}
270
271	spin_unlock_irq(lock: &locked->sched_engine->lock);
272
273	return ret;
274	}
275
276	static void __rq_init_watchdog(struct i915_request *rq)
277	{
278	rq->watchdog.timer.function = NULL;
279	}
280
281	static enum hrtimer_restart __rq_watchdog_expired(struct hrtimer *hrtimer)
282	{
283	struct i915_request *rq =
284	container_of(hrtimer, struct i915_request, watchdog.timer);
285	struct intel_gt *gt = rq->engine->gt;
286
287	if (!i915_request_completed(rq)) {
288	if (llist_add(new: &rq->watchdog.link, head: &gt->watchdog.list))
289	queue_work(wq: gt->i915->unordered_wq, work: &gt->watchdog.work);
290	} else {
291	i915_request_put(rq);
292	}
293
294	return HRTIMER_NORESTART;
295	}
296
297	static void __rq_arm_watchdog(struct i915_request *rq)
298	{
299	struct i915_request_watchdog *wdg = &rq->watchdog;
300	struct intel_context *ce = rq->context;
301
302	if (!ce->watchdog.timeout_us)
303	return;
304
305	i915_request_get(rq);
306
307	hrtimer_init(timer: &wdg->timer, CLOCK_MONOTONIC, mode: HRTIMER_MODE_REL);
308	wdg->timer.function = __rq_watchdog_expired;
309	hrtimer_start_range_ns(timer: &wdg->timer,
310	tim: ns_to_ktime(ns: ce->watchdog.timeout_us *
311	NSEC_PER_USEC),
312	NSEC_PER_MSEC,
313	mode: HRTIMER_MODE_REL);
314	}
315
316	static void __rq_cancel_watchdog(struct i915_request *rq)
317	{
318	struct i915_request_watchdog *wdg = &rq->watchdog;
319
320	if (wdg->timer.function && hrtimer_try_to_cancel(timer: &wdg->timer) > 0)
321	i915_request_put(rq);
322	}
323
324	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
325
326	/**
327	* i915_request_free_capture_list - Free a capture list
328	* @capture: Pointer to the first list item or NULL
329	*
330	*/
331	void i915_request_free_capture_list(struct i915_capture_list *capture)
332	{
333	while (capture) {
334	struct i915_capture_list *next = capture->next;
335
336	i915_vma_resource_put(vma_res: capture->vma_res);
337	kfree(objp: capture);
338	capture = next;
339	}
340	}
341
342	#define assert_capture_list_is_null(_rq) GEM_BUG_ON((_rq)->capture_list)
343
344	#define clear_capture_list(_rq) ((_rq)->capture_list = NULL)
345
346	#else
347
348	#define i915_request_free_capture_list(_a) do {} while (0)
349
350	#define assert_capture_list_is_null(_a) do {} while (0)
351
352	#define clear_capture_list(_rq) do {} while (0)
353
354	#endif
355
356	bool i915_request_retire(struct i915_request *rq)
357	{
358	if (!__i915_request_is_complete(rq))
359	return false;
360
361	RQ_TRACE(rq, "\n");
362
363	GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
364	trace_i915_request_retire(rq);
365	i915_request_mark_complete(rq);
366
367	__rq_cancel_watchdog(rq);
368
369	/*
370	* We know the GPU must have read the request to have
371	* sent us the seqno + interrupt, so use the position
372	* of tail of the request to update the last known position
373	* of the GPU head.
374	*
375	* Note this requires that we are always called in request
376	* completion order.
377	*/
378	GEM_BUG_ON(!list_is_first(&rq->link,
379	&i915_request_timeline(rq)->requests));
380	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
381	/* Poison before we release our space in the ring */
382	__i915_request_fill(rq, POISON_FREE);
383	rq->ring->head = rq->postfix;
384
385	if (!i915_request_signaled(rq)) {
386	spin_lock_irq(lock: &rq->lock);
387	dma_fence_signal_locked(fence: &rq->fence);
388	spin_unlock_irq(lock: &rq->lock);
389	}
390
391	if (test_and_set_bit(nr: I915_FENCE_FLAG_BOOST, addr: &rq->fence.flags))
392	intel_rps_dec_waiters(rps: &rq->engine->gt->rps);
393
394	/*
395	* We only loosely track inflight requests across preemption,
396	* and so we may find ourselves attempting to retire a _completed_
397	* request that we have removed from the HW and put back on a run
398	* queue.
399	*
400	* As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
401	* after removing the breadcrumb and signaling it, so that we do not
402	* inadvertently attach the breadcrumb to a completed request.
403	*/
404	rq->engine->remove_active_request(rq);
405	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
406
407	__list_del_entry(entry: &rq->link); /* poison neither prev/next (RCU walks) */
408
409	intel_context_exit(ce: rq->context);
410	intel_context_unpin(ce: rq->context);
411
412	i915_sched_node_fini(node: &rq->sched);
413	i915_request_put(rq);
414
415	return true;
416	}
417
418	void i915_request_retire_upto(struct i915_request *rq)
419	{
420	struct intel_timeline * const tl = i915_request_timeline(rq);
421	struct i915_request *tmp;
422
423	RQ_TRACE(rq, "\n");
424	GEM_BUG_ON(!__i915_request_is_complete(rq));
425
426	do {
427	tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
428	GEM_BUG_ON(!i915_request_completed(tmp));
429	} while (i915_request_retire(rq: tmp) && tmp != rq);
430	}
431
432	static struct i915_request * const *
433	__engine_active(struct intel_engine_cs *engine)
434	{
435	return READ_ONCE(engine->execlists.active);
436	}
437
438	static bool __request_in_flight(const struct i915_request *signal)
439	{
440	struct i915_request * const *port, *rq;
441	bool inflight = false;
442
443	if (!i915_request_is_ready(rq: signal))
444	return false;
445
446	/*
447	* Even if we have unwound the request, it may still be on
448	* the GPU (preempt-to-busy). If that request is inside an
449	* unpreemptible critical section, it will not be removed. Some
450	* GPU functions may even be stuck waiting for the paired request
451	* (__await_execution) to be submitted and cannot be preempted
452	* until the bond is executing.
453	*
454	* As we know that there are always preemption points between
455	* requests, we know that only the currently executing request
456	* may be still active even though we have cleared the flag.
457	* However, we can't rely on our tracking of ELSP[0] to know
458	* which request is currently active and so maybe stuck, as
459	* the tracking maybe an event behind. Instead assume that
460	* if the context is still inflight, then it is still active
461	* even if the active flag has been cleared.
462	*
463	* To further complicate matters, if there a pending promotion, the HW
464	* may either perform a context switch to the second inflight execlists,
465	* or it may switch to the pending set of execlists. In the case of the
466	* latter, it may send the ACK and we process the event copying the
467	* pending[] over top of inflight[], _overwriting_ our *active. Since
468	* this implies the HW is arbitrating and not struck in *active, we do
469	* not worry about complete accuracy, but we do require no read/write
470	* tearing of the pointer [the read of the pointer must be valid, even
471	* as the array is being overwritten, for which we require the writes
472	* to avoid tearing.]
473	*
474	* Note that the read of *execlists->active may race with the promotion
475	* of execlists->pending[] to execlists->inflight[], overwritting
476	* the value at *execlists->active. This is fine. The promotion implies
477	* that we received an ACK from the HW, and so the context is not
478	* stuck -- if we do not see ourselves in *active, the inflight status
479	* is valid. If instead we see ourselves being copied into *active,
480	* we are inflight and may signal the callback.
481	*/
482	if (!intel_context_inflight(signal->context))
483	return false;
484
485	rcu_read_lock();
486	for (port = __engine_active(engine: signal->engine);
487	(rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
488	port++) {
489	if (rq->context == signal->context) {
490	inflight = i915_seqno_passed(seq1: rq->fence.seqno,
491	seq2: signal->fence.seqno);
492	break;
493	}
494	}
495	rcu_read_unlock();
496
497	return inflight;
498	}
499
500	static int
501	__await_execution(struct i915_request *rq,
502	struct i915_request *signal,
503	gfp_t gfp)
504	{
505	struct execute_cb *cb;
506
507	if (i915_request_is_active(rq: signal))
508	return 0;
509
510	cb = kmem_cache_alloc(cachep: slab_execute_cbs, flags: gfp);
511	if (!cb)
512	return -ENOMEM;
513
514	cb->fence = &rq->submit;
515	i915_sw_fence_await(fence: cb->fence);
516	init_irq_work(work: &cb->work, func: irq_execute_cb);
517
518	/*
519	* Register the callback first, then see if the signaler is already
520	* active. This ensures that if we race with the
521	* __notify_execute_cb from i915_request_submit() and we are not
522	* included in that list, we get a second bite of the cherry and
523	* execute it ourselves. After this point, a future
524	* i915_request_submit() will notify us.
525	*
526	* In i915_request_retire() we set the ACTIVE bit on a completed
527	* request (then flush the execute_cb). So by registering the
528	* callback first, then checking the ACTIVE bit, we serialise with
529	* the completed/retired request.
530	*/
531	if (llist_add(new: &cb->work.node.llist, head: &signal->execute_cb)) {
532	if (i915_request_is_active(rq: signal) ||
533	__request_in_flight(signal))
534	i915_request_notify_execute_cb_imm(rq: signal);
535	}
536
537	return 0;
538	}
539
540	static bool fatal_error(int error)
541	{
542	switch (error) {
543	case 0: /* not an error! */
544	case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
545	case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
546	return false;
547	default:
548	return true;
549	}
550	}
551
552	void __i915_request_skip(struct i915_request *rq)
553	{
554	GEM_BUG_ON(!fatal_error(rq->fence.error));
555
556	if (rq->infix == rq->postfix)
557	return;
558
559	RQ_TRACE(rq, "error: %d\n", rq->fence.error);
560
561	/*
562	* As this request likely depends on state from the lost
563	* context, clear out all the user operations leaving the
564	* breadcrumb at the end (so we get the fence notifications).
565	*/
566	__i915_request_fill(rq, val: 0);
567	rq->infix = rq->postfix;
568	}
569
570	bool i915_request_set_error_once(struct i915_request *rq, int error)
571	{
572	int old;
573
574	GEM_BUG_ON(!IS_ERR_VALUE((long)error));
575
576	if (i915_request_signaled(rq))
577	return false;
578
579	old = READ_ONCE(rq->fence.error);
580	do {
581	if (fatal_error(error: old))
582	return false;
583	} while (!try_cmpxchg(&rq->fence.error, &old, error));
584
585	return true;
586	}
587
588	struct i915_request *i915_request_mark_eio(struct i915_request *rq)
589	{
590	if (__i915_request_is_complete(rq))
591	return NULL;
592
593	GEM_BUG_ON(i915_request_signaled(rq));
594
595	/* As soon as the request is completed, it may be retired */
596	rq = i915_request_get(rq);
597
598	i915_request_set_error_once(rq, error: -EIO);
599	i915_request_mark_complete(rq);
600
601	return rq;
602	}
603
604	bool __i915_request_submit(struct i915_request *request)
605	{
606	struct intel_engine_cs *engine = request->engine;
607	bool result = false;
608
609	RQ_TRACE(request, "\n");
610
611	GEM_BUG_ON(!irqs_disabled());
612	lockdep_assert_held(&engine->sched_engine->lock);
613
614	/*
615	* With the advent of preempt-to-busy, we frequently encounter
616	* requests that we have unsubmitted from HW, but left running
617	* until the next ack and so have completed in the meantime. On
618	* resubmission of that completed request, we can skip
619	* updating the payload, and execlists can even skip submitting
620	* the request.
621	*
622	* We must remove the request from the caller's priority queue,
623	* and the caller must only call us when the request is in their
624	* priority queue, under the sched_engine->lock. This ensures that the
625	* request has *not* yet been retired and we can safely move
626	* the request into the engine->active.list where it will be
627	* dropped upon retiring. (Otherwise if resubmit a *retired*
628	* request, this would be a horrible use-after-free.)
629	*/
630	if (__i915_request_is_complete(rq: request)) {
631	list_del_init(entry: &request->sched.link);
632	goto active;
633	}
634
635	if (unlikely(!intel_context_is_schedulable(request->context)))
636	i915_request_set_error_once(rq: request, error: -EIO);
637
638	if (unlikely(fatal_error(request->fence.error)))
639	__i915_request_skip(rq: request);
640
641	/*
642	* Are we using semaphores when the gpu is already saturated?
643	*
644	* Using semaphores incurs a cost in having the GPU poll a
645	* memory location, busywaiting for it to change. The continual
646	* memory reads can have a noticeable impact on the rest of the
647	* system with the extra bus traffic, stalling the cpu as it too
648	* tries to access memory across the bus (perf stat -e bus-cycles).
649	*
650	* If we installed a semaphore on this request and we only submit
651	* the request after the signaler completed, that indicates the
652	* system is overloaded and using semaphores at this time only
653	* increases the amount of work we are doing. If so, we disable
654	* further use of semaphores until we are idle again, whence we
655	* optimistically try again.
656	*/
657	if (request->sched.semaphores &&
658	i915_sw_fence_signaled(fence: &request->semaphore))
659	engine->saturated |= request->sched.semaphores;
660
661	engine->emit_fini_breadcrumb(request,
662	request->ring->vaddr + request->postfix);
663
664	trace_i915_request_execute(rq: request);
665	if (engine->bump_serial)
666	engine->bump_serial(engine);
667	else
668	engine->serial++;
669
670	result = true;
671
672	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
673	engine->add_active_request(request);
674	active:
675	clear_bit(nr: I915_FENCE_FLAG_PQUEUE, addr: &request->fence.flags);
676	set_bit(nr: I915_FENCE_FLAG_ACTIVE, addr: &request->fence.flags);
677
678	/*
679	* XXX Rollback bonded-execution on __i915_request_unsubmit()?
680	*
681	* In the future, perhaps when we have an active time-slicing scheduler,
682	* it will be interesting to unsubmit parallel execution and remove
683	* busywaits from the GPU until their master is restarted. This is
684	* quite hairy, we have to carefully rollback the fence and do a
685	* preempt-to-idle cycle on the target engine, all the while the
686	* master execute_cb may refire.
687	*/
688	__notify_execute_cb_irq(rq: request);
689
690	/* We may be recursing from the signal callback of another i915 fence */
691	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
692	i915_request_enable_breadcrumb(request);
693
694	return result;
695	}
696
697	void i915_request_submit(struct i915_request *request)
698	{
699	struct intel_engine_cs *engine = request->engine;
700	unsigned long flags;
701
702	/* Will be called from irq-context when using foreign fences. */
703	spin_lock_irqsave(&engine->sched_engine->lock, flags);
704
705	__i915_request_submit(request);
706
707	spin_unlock_irqrestore(lock: &engine->sched_engine->lock, flags);
708	}
709
710	void __i915_request_unsubmit(struct i915_request *request)
711	{
712	struct intel_engine_cs *engine = request->engine;
713
714	/*
715	* Only unwind in reverse order, required so that the per-context list
716	* is kept in seqno/ring order.
717	*/
718	RQ_TRACE(request, "\n");
719
720	GEM_BUG_ON(!irqs_disabled());
721	lockdep_assert_held(&engine->sched_engine->lock);
722
723	/*
724	* Before we remove this breadcrumb from the signal list, we have
725	* to ensure that a concurrent dma_fence_enable_signaling() does not
726	* attach itself. We first mark the request as no longer active and
727	* make sure that is visible to other cores, and then remove the
728	* breadcrumb if attached.
729	*/
730	GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
731	clear_bit_unlock(nr: I915_FENCE_FLAG_ACTIVE, addr: &request->fence.flags);
732	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
733	i915_request_cancel_breadcrumb(request);
734
735	/* We've already spun, don't charge on resubmitting. */
736	if (request->sched.semaphores && __i915_request_has_started(rq: request))
737	request->sched.semaphores = 0;
738
739	/*
740	* We don't need to wake_up any waiters on request->execute, they
741	* will get woken by any other event or us re-adding this request
742	* to the engine timeline (__i915_request_submit()). The waiters
743	* should be quite adapt at finding that the request now has a new
744	* global_seqno to the one they went to sleep on.
745	*/
746	}
747
748	void i915_request_unsubmit(struct i915_request *request)
749	{
750	struct intel_engine_cs *engine = request->engine;
751	unsigned long flags;
752
753	/* Will be called from irq-context when using foreign fences. */
754	spin_lock_irqsave(&engine->sched_engine->lock, flags);
755
756	__i915_request_unsubmit(request);
757
758	spin_unlock_irqrestore(lock: &engine->sched_engine->lock, flags);
759	}
760
761	void i915_request_cancel(struct i915_request *rq, int error)
762	{
763	if (!i915_request_set_error_once(rq, error))
764	return;
765
766	set_bit(nr: I915_FENCE_FLAG_SENTINEL, addr: &rq->fence.flags);
767
768	intel_context_cancel_request(ce: rq->context, rq);
769	}
770
771	static int
772	submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
773	{
774	struct i915_request *request =
775	container_of(fence, typeof(*request), submit);
776
777	switch (state) {
778	case FENCE_COMPLETE:
779	trace_i915_request_submit(rq: request);
780
781	if (unlikely(fence->error))
782	i915_request_set_error_once(rq: request, error: fence->error);
783	else
784	__rq_arm_watchdog(rq: request);
785
786	/*
787	* We need to serialize use of the submit_request() callback
788	* with its hotplugging performed during an emergency
789	* i915_gem_set_wedged(). We use the RCU mechanism to mark the
790	* critical section in order to force i915_gem_set_wedged() to
791	* wait until the submit_request() is completed before
792	* proceeding.
793	*/
794	rcu_read_lock();
795	request->engine->submit_request(request);
796	rcu_read_unlock();
797	break;
798
799	case FENCE_FREE:
800	i915_request_put(rq: request);
801	break;
802	}
803
804	return NOTIFY_DONE;
805	}
806
807	static int
808	semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
809	{
810	struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
811
812	switch (state) {
813	case FENCE_COMPLETE:
814	break;
815
816	case FENCE_FREE:
817	i915_request_put(rq);
818	break;
819	}
820
821	return NOTIFY_DONE;
822	}
823
824	static void retire_requests(struct intel_timeline *tl)
825	{
826	struct i915_request *rq, *rn;
827
828	list_for_each_entry_safe(rq, rn, &tl->requests, link)
829	if (!i915_request_retire(rq))
830	break;
831	}
832
833	static noinline struct i915_request *
834	request_alloc_slow(struct intel_timeline *tl,
835	struct i915_request **rsvd,
836	gfp_t gfp)
837	{
838	struct i915_request *rq;
839
840	/* If we cannot wait, dip into our reserves */
841	if (!gfpflags_allow_blocking(gfp_flags: gfp)) {
842	rq = xchg(rsvd, NULL);
843	if (!rq) /* Use the normal failure path for one final WARN */
844	goto out;
845
846	return rq;
847	}
848
849	if (list_empty(head: &tl->requests))
850	goto out;
851
852	/* Move our oldest request to the slab-cache (if not in use!) */
853	rq = list_first_entry(&tl->requests, typeof(*rq), link);
854	i915_request_retire(rq);
855
856	rq = kmem_cache_alloc(cachep: slab_requests,
857	flags: gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
858	if (rq)
859	return rq;
860
861	/* Ratelimit ourselves to prevent oom from malicious clients */
862	rq = list_last_entry(&tl->requests, typeof(*rq), link);
863	cond_synchronize_rcu(oldstate: rq->rcustate);
864
865	/* Retire our old requests in the hope that we free some */
866	retire_requests(tl);
867
868	out:
869	return kmem_cache_alloc(cachep: slab_requests, flags: gfp);
870	}
871
872	static void __i915_request_ctor(void *arg)
873	{
874	struct i915_request *rq = arg;
875
876	spin_lock_init(&rq->lock);
877	i915_sched_node_init(node: &rq->sched);
878	i915_sw_fence_init(&rq->submit, submit_notify);
879	i915_sw_fence_init(&rq->semaphore, semaphore_notify);
880
881	clear_capture_list(rq);
882	rq->batch_res = NULL;
883
884	init_llist_head(list: &rq->execute_cb);
885	}
886
887	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
888	#define clear_batch_ptr(_rq) ((_rq)->batch = NULL)
889	#else
890	#define clear_batch_ptr(_a) do {} while (0)
891	#endif
892
893	struct i915_request *
894	__i915_request_create(struct intel_context *ce, gfp_t gfp)
895	{
896	struct intel_timeline *tl = ce->timeline;
897	struct i915_request *rq;
898	u32 seqno;
899	int ret;
900
901	might_alloc(gfp_mask: gfp);
902
903	/* Check that the caller provided an already pinned context */
904	__intel_context_pin(ce);
905
906	/*
907	* Beware: Dragons be flying overhead.
908	*
909	* We use RCU to look up requests in flight. The lookups may
910	* race with the request being allocated from the slab freelist.
911	* That is the request we are writing to here, may be in the process
912	* of being read by __i915_active_request_get_rcu(). As such,
913	* we have to be very careful when overwriting the contents. During
914	* the RCU lookup, we change chase the request->engine pointer,
915	* read the request->global_seqno and increment the reference count.
916	*
917	* The reference count is incremented atomically. If it is zero,
918	* the lookup knows the request is unallocated and complete. Otherwise,
919	* it is either still in use, or has been reallocated and reset
920	* with dma_fence_init(). This increment is safe for release as we
921	* check that the request we have a reference to and matches the active
922	* request.
923	*
924	* Before we increment the refcount, we chase the request->engine
925	* pointer. We must not call kmem_cache_zalloc() or else we set
926	* that pointer to NULL and cause a crash during the lookup. If
927	* we see the request is completed (based on the value of the
928	* old engine and seqno), the lookup is complete and reports NULL.
929	* If we decide the request is not completed (new engine or seqno),
930	* then we grab a reference and double check that it is still the
931	* active request - which it won't be and restart the lookup.
932	*
933	* Do not use kmem_cache_zalloc() here!
934	*/
935	rq = kmem_cache_alloc(cachep: slab_requests,
936	flags: gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
937	if (unlikely(!rq)) {
938	rq = request_alloc_slow(tl, rsvd: &ce->engine->request_pool, gfp);
939	if (!rq) {
940	ret = -ENOMEM;
941	goto err_unreserve;
942	}
943	}
944
945	rq->context = ce;
946	rq->engine = ce->engine;
947	rq->ring = ce->ring;
948	rq->execution_mask = ce->engine->mask;
949	rq->i915 = ce->engine->i915;
950
951	ret = intel_timeline_get_seqno(tl, rq, seqno: &seqno);
952	if (ret)
953	goto err_free;
954
955	dma_fence_init(fence: &rq->fence, ops: &i915_fence_ops, lock: &rq->lock,
956	context: tl->fence_context, seqno);
957
958	RCU_INIT_POINTER(rq->timeline, tl);
959	rq->hwsp_seqno = tl->hwsp_seqno;
960	GEM_BUG_ON(__i915_request_is_complete(rq));
961
962	rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
963
964	rq->guc_prio = GUC_PRIO_INIT;
965
966	/* We bump the ref for the fence chain */
967	i915_sw_fence_reinit(fence: &i915_request_get(rq)->submit);
968	i915_sw_fence_reinit(fence: &i915_request_get(rq)->semaphore);
969
970	i915_sched_node_reinit(node: &rq->sched);
971
972	/* No zalloc, everything must be cleared after use */
973	clear_batch_ptr(rq);
974	__rq_init_watchdog(rq);
975	assert_capture_list_is_null(rq);
976	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
977	GEM_BUG_ON(rq->batch_res);
978
979	/*
980	* Reserve space in the ring buffer for all the commands required to
981	* eventually emit this request. This is to guarantee that the
982	* i915_request_add() call can't fail. Note that the reserve may need
983	* to be redone if the request is not actually submitted straight
984	* away, e.g. because a GPU scheduler has deferred it.
985	*
986	* Note that due to how we add reserved_space to intel_ring_begin()
987	* we need to double our request to ensure that if we need to wrap
988	* around inside i915_request_add() there is sufficient space at
989	* the beginning of the ring as well.
990	*/
991	rq->reserved_space =
992	2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
993
994	/*
995	* Record the position of the start of the request so that
996	* should we detect the updated seqno part-way through the
997	* GPU processing the request, we never over-estimate the
998	* position of the head.
999	*/
1000	rq->head = rq->ring->emit;
1001
1002	ret = rq->engine->request_alloc(rq);
1003	if (ret)
1004	goto err_unwind;
1005
1006	rq->infix = rq->ring->emit; /* end of header; start of user payload */
1007
1008	intel_context_mark_active(ce);
1009	list_add_tail_rcu(new: &rq->link, head: &tl->requests);
1010
1011	return rq;
1012
1013	err_unwind:
1014	ce->ring->emit = rq->head;
1015
1016	/* Make sure we didn't add ourselves to external state before freeing */
1017	GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
1018	GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
1019
1020	err_free:
1021	kmem_cache_free(s: slab_requests, objp: rq);
1022	err_unreserve:
1023	intel_context_unpin(ce);
1024	return ERR_PTR(error: ret);
1025	}
1026
1027	struct i915_request *
1028	i915_request_create(struct intel_context *ce)
1029	{
1030	struct i915_request *rq;
1031	struct intel_timeline *tl;
1032
1033	tl = intel_context_timeline_lock(ce);
1034	if (IS_ERR(ptr: tl))
1035	return ERR_CAST(ptr: tl);
1036
1037	/* Move our oldest request to the slab-cache (if not in use!) */
1038	rq = list_first_entry(&tl->requests, typeof(*rq), link);
1039	if (!list_is_last(list: &rq->link, head: &tl->requests))
1040	i915_request_retire(rq);
1041
1042	intel_context_enter(ce);
1043	rq = __i915_request_create(ce, GFP_KERNEL);
1044	intel_context_exit(ce); /* active reference transferred to request */
1045	if (IS_ERR(ptr: rq))
1046	goto err_unlock;
1047
1048	/* Check that we do not interrupt ourselves with a new request */
1049	rq->cookie = lockdep_pin_lock(&tl->mutex);
1050
1051	return rq;
1052
1053	err_unlock:
1054	intel_context_timeline_unlock(tl);
1055	return rq;
1056	}
1057
1058	static int
1059	i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
1060	{
1061	struct dma_fence *fence;
1062	int err;
1063
1064	if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
1065	return 0;
1066
1067	if (i915_request_started(rq: signal))
1068	return 0;
1069
1070	/*
1071	* The caller holds a reference on @signal, but we do not serialise
1072	* against it being retired and removed from the lists.
1073	*
1074	* We do not hold a reference to the request before @signal, and
1075	* so must be very careful to ensure that it is not _recycled_ as
1076	* we follow the link backwards.
1077	*/
1078	fence = NULL;
1079	rcu_read_lock();
1080	do {
1081	struct list_head *pos = READ_ONCE(signal->link.prev);
1082	struct i915_request *prev;
1083
1084	/* Confirm signal has not been retired, the link is valid */
1085	if (unlikely(__i915_request_has_started(signal)))
1086	break;
1087
1088	/* Is signal the earliest request on its timeline? */
1089	if (pos == &rcu_dereference(signal->timeline)->requests)
1090	break;
1091
1092	/*
1093	* Peek at the request before us in the timeline. That
1094	* request will only be valid before it is retired, so
1095	* after acquiring a reference to it, confirm that it is
1096	* still part of the signaler's timeline.
1097	*/
1098	prev = list_entry(pos, typeof(*prev), link);
1099	if (!i915_request_get_rcu(rq: prev))
1100	break;
1101
1102	/* After the strong barrier, confirm prev is still attached */
1103	if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
1104	i915_request_put(rq: prev);
1105	break;
1106	}
1107
1108	fence = &prev->fence;
1109	} while (0);
1110	rcu_read_unlock();
1111	if (!fence)
1112	return 0;
1113
1114	err = 0;
1115	if (!intel_timeline_sync_is_later(tl: i915_request_timeline(rq), fence))
1116	err = i915_sw_fence_await_dma_fence(fence: &rq->submit,
1117	dma: fence, timeout: 0,
1118	I915_FENCE_GFP);
1119	dma_fence_put(fence);
1120
1121	return err;
1122	}
1123
1124	static intel_engine_mask_t
1125	already_busywaiting(struct i915_request *rq)
1126	{
1127	/*
1128	* Polling a semaphore causes bus traffic, delaying other users of
1129	* both the GPU and CPU. We want to limit the impact on others,
1130	* while taking advantage of early submission to reduce GPU
1131	* latency. Therefore we restrict ourselves to not using more
1132	* than one semaphore from each source, and not using a semaphore
1133	* if we have detected the engine is saturated (i.e. would not be
1134	* submitted early and cause bus traffic reading an already passed
1135	* semaphore).
1136	*
1137	* See the are-we-too-late? check in __i915_request_submit().
1138	*/
1139	return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1140	}
1141
1142	static int
1143	__emit_semaphore_wait(struct i915_request *to,
1144	struct i915_request *from,
1145	u32 seqno)
1146	{
1147	const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;
1148	u32 hwsp_offset;
1149	int len, err;
1150	u32 *cs;
1151
1152	GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);
1153	GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1154
1155	/* We need to pin the signaler's HWSP until we are finished reading. */
1156	err = intel_timeline_read_hwsp(from, until: to, hwsp_offset: &hwsp_offset);
1157	if (err)
1158	return err;
1159
1160	len = 4;
1161	if (has_token)
1162	len += 2;
1163
1164	cs = intel_ring_begin(rq: to, num_dwords: len);
1165	if (IS_ERR(ptr: cs))
1166	return PTR_ERR(ptr: cs);
1167
1168	/*
1169	* Using greater-than-or-equal here means we have to worry
1170	* about seqno wraparound. To side step that issue, we swap
1171	* the timeline HWSP upon wrapping, so that everyone listening
1172	* for the old (pre-wrap) values do not see the much smaller
1173	* (post-wrap) values than they were expecting (and so wait
1174	* forever).
1175	*/
1176	*cs++ = (MI_SEMAPHORE_WAIT |
1177	MI_SEMAPHORE_GLOBAL_GTT |
1178	MI_SEMAPHORE_POLL |
1179	MI_SEMAPHORE_SAD_GTE_SDD) +
1180	has_token;
1181	*cs++ = seqno;
1182	*cs++ = hwsp_offset;
1183	*cs++ = 0;
1184	if (has_token) {
1185	*cs++ = 0;
1186	*cs++ = MI_NOOP;
1187	}
1188
1189	intel_ring_advance(rq: to, cs);
1190	return 0;
1191	}
1192
1193	static bool
1194	can_use_semaphore_wait(struct i915_request *to, struct i915_request *from)
1195	{
1196	return to->engine->gt->ggtt == from->engine->gt->ggtt;
1197	}
1198
1199	static int
1200	emit_semaphore_wait(struct i915_request *to,
1201	struct i915_request *from,
1202	gfp_t gfp)
1203	{
1204	const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1205	struct i915_sw_fence *wait = &to->submit;
1206
1207	if (!can_use_semaphore_wait(to, from))
1208	goto await_fence;
1209
1210	if (!intel_context_use_semaphores(ce: to->context))
1211	goto await_fence;
1212
1213	if (i915_request_has_initial_breadcrumb(rq: to))
1214	goto await_fence;
1215
1216	/*
1217	* If this or its dependents are waiting on an external fence
1218	* that may fail catastrophically, then we want to avoid using
1219	* semaphores as they bypass the fence signaling metadata, and we
1220	* lose the fence->error propagation.
1221	*/
1222	if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1223	goto await_fence;
1224
1225	/* Just emit the first semaphore we see as request space is limited. */
1226	if (already_busywaiting(rq: to) & mask)
1227	goto await_fence;
1228
1229	if (i915_request_await_start(rq: to, signal: from) < 0)
1230	goto await_fence;
1231
1232	/* Only submit our spinner after the signaler is running! */
1233	if (__await_execution(rq: to, signal: from, gfp))
1234	goto await_fence;
1235
1236	if (__emit_semaphore_wait(to, from, seqno: from->fence.seqno))
1237	goto await_fence;
1238
1239	to->sched.semaphores |= mask;
1240	wait = &to->semaphore;
1241
1242	await_fence:
1243	return i915_sw_fence_await_dma_fence(fence: wait,
1244	dma: &from->fence, timeout: 0,
1245	I915_FENCE_GFP);
1246	}
1247
1248	static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1249	struct dma_fence *fence)
1250	{
1251	return __intel_timeline_sync_is_later(tl,
1252	context: fence->context,
1253	seqno: fence->seqno - 1);
1254	}
1255
1256	static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1257	const struct dma_fence *fence)
1258	{
1259	return __intel_timeline_sync_set(tl, context: fence->context, seqno: fence->seqno - 1);
1260	}
1261
1262	static int
1263	__i915_request_await_execution(struct i915_request *to,
1264	struct i915_request *from)
1265	{
1266	int err;
1267
1268	GEM_BUG_ON(intel_context_is_barrier(from->context));
1269
1270	/* Submit both requests at the same time */
1271	err = __await_execution(rq: to, signal: from, I915_FENCE_GFP);
1272	if (err)
1273	return err;
1274
1275	/* Squash repeated depenendices to the same timelines */
1276	if (intel_timeline_sync_has_start(tl: i915_request_timeline(rq: to),
1277	fence: &from->fence))
1278	return 0;
1279
1280	/*
1281	* Wait until the start of this request.
1282	*
1283	* The execution cb fires when we submit the request to HW. But in
1284	* many cases this may be long before the request itself is ready to
1285	* run (consider that we submit 2 requests for the same context, where
1286	* the request of interest is behind an indefinite spinner). So we hook
1287	* up to both to reduce our queues and keep the execution lag minimised
1288	* in the worst case, though we hope that the await_start is elided.
1289	*/
1290	err = i915_request_await_start(rq: to, signal: from);
1291	if (err < 0)
1292	return err;
1293
1294	/*
1295	* Ensure both start together [after all semaphores in signal]
1296	*
1297	* Now that we are queued to the HW at roughly the same time (thanks
1298	* to the execute cb) and are ready to run at roughly the same time
1299	* (thanks to the await start), our signaler may still be indefinitely
1300	* delayed by waiting on a semaphore from a remote engine. If our
1301	* signaler depends on a semaphore, so indirectly do we, and we do not
1302	* want to start our payload until our signaler also starts theirs.
1303	* So we wait.
1304	*
1305	* However, there is also a second condition for which we need to wait
1306	* for the precise start of the signaler. Consider that the signaler
1307	* was submitted in a chain of requests following another context
1308	* (with just an ordinary intra-engine fence dependency between the
1309	* two). In this case the signaler is queued to HW, but not for
1310	* immediate execution, and so we must wait until it reaches the
1311	* active slot.
1312	*/
1313	if (can_use_semaphore_wait(to, from) &&
1314	intel_engine_has_semaphores(engine: to->engine) &&
1315	!i915_request_has_initial_breadcrumb(rq: to)) {
1316	err = __emit_semaphore_wait(to, from, seqno: from->fence.seqno - 1);
1317	if (err < 0)
1318	return err;
1319	}
1320
1321	/* Couple the dependency tree for PI on this exposed to->fence */
1322	if (to->engine->sched_engine->schedule) {
1323	err = i915_sched_node_add_dependency(node: &to->sched,
1324	signal: &from->sched,
1325	I915_DEPENDENCY_WEAK);
1326	if (err < 0)
1327	return err;
1328	}
1329
1330	return intel_timeline_sync_set_start(tl: i915_request_timeline(rq: to),
1331	fence: &from->fence);
1332	}
1333
1334	static void mark_external(struct i915_request *rq)
1335	{
1336	/*
1337	* The downside of using semaphores is that we lose metadata passing
1338	* along the signaling chain. This is particularly nasty when we
1339	* need to pass along a fatal error such as EFAULT or EDEADLK. For
1340	* fatal errors we want to scrub the request before it is executed,
1341	* which means that we cannot preload the request onto HW and have
1342	* it wait upon a semaphore.
1343	*/
1344	rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1345	}
1346
1347	static int
1348	__i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1349	{
1350	mark_external(rq);
1351	return i915_sw_fence_await_dma_fence(fence: &rq->submit, dma: fence,
1352	timeout: i915_fence_context_timeout(i915: rq->i915,
1353	context: fence->context),
1354	I915_FENCE_GFP);
1355	}
1356
1357	static int
1358	i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1359	{
1360	struct dma_fence *iter;
1361	int err = 0;
1362
1363	if (!to_dma_fence_chain(fence))
1364	return __i915_request_await_external(rq, fence);
1365
1366	dma_fence_chain_for_each(iter, fence) {
1367	struct dma_fence_chain *chain = to_dma_fence_chain(fence: iter);
1368
1369	if (!dma_fence_is_i915(fence: chain->fence)) {
1370	err = __i915_request_await_external(rq, fence: iter);
1371	break;
1372	}
1373
1374	err = i915_request_await_dma_fence(rq, fence: chain->fence);
1375	if (err < 0)
1376	break;
1377	}
1378
1379	dma_fence_put(fence: iter);
1380	return err;
1381	}
1382
1383	static inline bool is_parallel_rq(struct i915_request *rq)
1384	{
1385	return intel_context_is_parallel(ce: rq->context);
1386	}
1387
1388	static inline struct intel_context *request_to_parent(struct i915_request *rq)
1389	{
1390	return intel_context_to_parent(ce: rq->context);
1391	}
1392
1393	static bool is_same_parallel_context(struct i915_request *to,
1394	struct i915_request *from)
1395	{
1396	if (is_parallel_rq(rq: to))
1397	return request_to_parent(rq: to) == request_to_parent(rq: from);
1398
1399	return false;
1400	}
1401
1402	int
1403	i915_request_await_execution(struct i915_request *rq,
1404	struct dma_fence *fence)
1405	{
1406	struct dma_fence **child = &fence;
1407	unsigned int nchild = 1;
1408	int ret;
1409
1410	if (dma_fence_is_array(fence)) {
1411	struct dma_fence_array *array = to_dma_fence_array(fence);
1412
1413	/* XXX Error for signal-on-any fence arrays */
1414
1415	child = array->fences;
1416	nchild = array->num_fences;
1417	GEM_BUG_ON(!nchild);
1418	}
1419
1420	do {
1421	fence = *child++;
1422	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1423	continue;
1424
1425	if (fence->context == rq->fence.context)
1426	continue;
1427
1428	/*
1429	* We don't squash repeated fence dependencies here as we
1430	* want to run our callback in all cases.
1431	*/
1432
1433	if (dma_fence_is_i915(fence)) {
1434	if (is_same_parallel_context(to: rq, from: to_request(fence)))
1435	continue;
1436	ret = __i915_request_await_execution(to: rq,
1437	from: to_request(fence));
1438	} else {
1439	ret = i915_request_await_external(rq, fence);
1440	}
1441	if (ret < 0)
1442	return ret;
1443	} while (--nchild);
1444
1445	return 0;
1446	}
1447
1448	static int
1449	await_request_submit(struct i915_request *to, struct i915_request *from)
1450	{
1451	/*
1452	* If we are waiting on a virtual engine, then it may be
1453	* constrained to execute on a single engine *prior* to submission.
1454	* When it is submitted, it will be first submitted to the virtual
1455	* engine and then passed to the physical engine. We cannot allow
1456	* the waiter to be submitted immediately to the physical engine
1457	* as it may then bypass the virtual request.
1458	*/
1459	if (to->engine == READ_ONCE(from->engine))
1460	return i915_sw_fence_await_sw_fence_gfp(fence: &to->submit,
1461	after: &from->submit,
1462	I915_FENCE_GFP);
1463	else
1464	return __i915_request_await_execution(to, from);
1465	}
1466
1467	static int
1468	i915_request_await_request(struct i915_request *to, struct i915_request *from)
1469	{
1470	int ret;
1471
1472	GEM_BUG_ON(to == from);
1473	GEM_BUG_ON(to->timeline == from->timeline);
1474
1475	if (i915_request_completed(rq: from)) {
1476	i915_sw_fence_set_error_once(fence: &to->submit, error: from->fence.error);
1477	return 0;
1478	}
1479
1480	if (to->engine->sched_engine->schedule) {
1481	ret = i915_sched_node_add_dependency(node: &to->sched,
1482	signal: &from->sched,
1483	I915_DEPENDENCY_EXTERNAL);
1484	if (ret < 0)
1485	return ret;
1486	}
1487
1488	if (!intel_engine_uses_guc(engine: to->engine) &&
1489	is_power_of_2(n: to->execution_mask | READ_ONCE(from->execution_mask)))
1490	ret = await_request_submit(to, from);
1491	else
1492	ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1493	if (ret < 0)
1494	return ret;
1495
1496	return 0;
1497	}
1498
1499	int
1500	i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1501	{
1502	struct dma_fence **child = &fence;
1503	unsigned int nchild = 1;
1504	int ret;
1505
1506	/*
1507	* Note that if the fence-array was created in signal-on-any mode,
1508	* we should *not* decompose it into its individual fences. However,
1509	* we don't currently store which mode the fence-array is operating
1510	* in. Fortunately, the only user of signal-on-any is private to
1511	* amdgpu and we should not see any incoming fence-array from
1512	* sync-file being in signal-on-any mode.
1513	*/
1514	if (dma_fence_is_array(fence)) {
1515	struct dma_fence_array *array = to_dma_fence_array(fence);
1516
1517	child = array->fences;
1518	nchild = array->num_fences;
1519	GEM_BUG_ON(!nchild);
1520	}
1521
1522	do {
1523	fence = *child++;
1524	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1525	continue;
1526
1527	/*
1528	* Requests on the same timeline are explicitly ordered, along
1529	* with their dependencies, by i915_request_add() which ensures
1530	* that requests are submitted in-order through each ring.
1531	*/
1532	if (fence->context == rq->fence.context)
1533	continue;
1534
1535	/* Squash repeated waits to the same timelines */
1536	if (fence->context &&
1537	intel_timeline_sync_is_later(tl: i915_request_timeline(rq),
1538	fence))
1539	continue;
1540
1541	if (dma_fence_is_i915(fence)) {
1542	if (is_same_parallel_context(to: rq, from: to_request(fence)))
1543	continue;
1544	ret = i915_request_await_request(to: rq, from: to_request(fence));
1545	} else {
1546	ret = i915_request_await_external(rq, fence);
1547	}
1548	if (ret < 0)
1549	return ret;
1550
1551	/* Record the latest fence used against each timeline */
1552	if (fence->context)
1553	intel_timeline_sync_set(tl: i915_request_timeline(rq),
1554	fence);
1555	} while (--nchild);
1556
1557	return 0;
1558	}
1559
1560	/**
1561	* i915_request_await_deps - set this request to (async) wait upon a struct
1562	* i915_deps dma_fence collection
1563	* @rq: request we are wishing to use
1564	* @deps: The struct i915_deps containing the dependencies.
1565	*
1566	* Returns 0 if successful, negative error code on error.
1567	*/
1568	int i915_request_await_deps(struct i915_request *rq, const struct i915_deps *deps)
1569	{
1570	int i, err;
1571
1572	for (i = 0; i < deps->num_deps; ++i) {
1573	err = i915_request_await_dma_fence(rq, fence: deps->fences[i]);
1574	if (err)
1575	return err;
1576	}
1577
1578	return 0;
1579	}
1580
1581	/**
1582	* i915_request_await_object - set this request to (async) wait upon a bo
1583	* @to: request we are wishing to use
1584	* @obj: object which may be in use on another ring.
1585	* @write: whether the wait is on behalf of a writer
1586	*
1587	* This code is meant to abstract object synchronization with the GPU.
1588	* Conceptually we serialise writes between engines inside the GPU.
1589	* We only allow one engine to write into a buffer at any time, but
1590	* multiple readers. To ensure each has a coherent view of memory, we must:
1591	*
1592	* - If there is an outstanding write request to the object, the new
1593	* request must wait for it to complete (either CPU or in hw, requests
1594	* on the same ring will be naturally ordered).
1595	*
1596	* - If we are a write request (pending_write_domain is set), the new
1597	* request must wait for outstanding read requests to complete.
1598	*
1599	* Returns 0 if successful, else propagates up the lower layer error.
1600	*/
1601	int
1602	i915_request_await_object(struct i915_request *to,
1603	struct drm_i915_gem_object *obj,
1604	bool write)
1605	{
1606	struct dma_resv_iter cursor;
1607	struct dma_fence *fence;
1608	int ret = 0;
1609
1610	dma_resv_for_each_fence(&cursor, obj->base.resv,
1611	dma_resv_usage_rw(write), fence) {
1612	ret = i915_request_await_dma_fence(rq: to, fence);
1613	if (ret)
1614	break;
1615	}
1616
1617	return ret;
1618	}
1619
1620	static void i915_request_await_huc(struct i915_request *rq)
1621	{
1622	struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
1623
1624	/* don't stall kernel submissions! */
1625	if (!rcu_access_pointer(rq->context->gem_context))
1626	return;
1627
1628	if (intel_huc_wait_required(huc))
1629	i915_sw_fence_await_sw_fence(fence: &rq->submit,
1630	after: &huc->delayed_load.fence,
1631	wq: &rq->hucq);
1632	}
1633
1634	static struct i915_request *
1635	__i915_request_ensure_parallel_ordering(struct i915_request *rq,
1636	struct intel_timeline *timeline)
1637	{
1638	struct i915_request *prev;
1639
1640	GEM_BUG_ON(!is_parallel_rq(rq));
1641
1642	prev = request_to_parent(rq)->parallel.last_rq;
1643	if (prev) {
1644	if (!__i915_request_is_complete(rq: prev)) {
1645	i915_sw_fence_await_sw_fence(fence: &rq->submit,
1646	after: &prev->submit,
1647	wq: &rq->submitq);
1648
1649	if (rq->engine->sched_engine->schedule)
1650	__i915_sched_node_add_dependency(node: &rq->sched,
1651	signal: &prev->sched,
1652	dep: &rq->dep,
1653	flags: 0);
1654	}
1655	i915_request_put(rq: prev);
1656	}
1657
1658	request_to_parent(rq)->parallel.last_rq = i915_request_get(rq);
1659
1660	/*
1661	* Users have to put a reference potentially got by
1662	* __i915_active_fence_set() to the returned request
1663	* when no longer needed
1664	*/
1665	return to_request(fence: __i915_active_fence_set(active: &timeline->last_request,
1666	fence: &rq->fence));
1667	}
1668
1669	static struct i915_request *
1670	__i915_request_ensure_ordering(struct i915_request *rq,
1671	struct intel_timeline *timeline)
1672	{
1673	struct i915_request *prev;
1674
1675	GEM_BUG_ON(is_parallel_rq(rq));
1676
1677	prev = to_request(fence: __i915_active_fence_set(active: &timeline->last_request,
1678	fence: &rq->fence));
1679
1680	if (prev && !__i915_request_is_complete(rq: prev)) {
1681	bool uses_guc = intel_engine_uses_guc(engine: rq->engine);
1682	bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask |
1683	rq->engine->mask);
1684	bool same_context = prev->context == rq->context;
1685
1686	/*
1687	* The requests are supposed to be kept in order. However,
1688	* we need to be wary in case the timeline->last_request
1689	* is used as a barrier for external modification to this
1690	* context.
1691	*/
1692	GEM_BUG_ON(same_context &&
1693	i915_seqno_passed(prev->fence.seqno,
1694	rq->fence.seqno));
1695
1696	if ((same_context && uses_guc) || (!uses_guc && pow2))
1697	i915_sw_fence_await_sw_fence(fence: &rq->submit,
1698	after: &prev->submit,
1699	wq: &rq->submitq);
1700	else
1701	__i915_sw_fence_await_dma_fence(fence: &rq->submit,
1702	dma: &prev->fence,
1703	cb: &rq->dmaq);
1704	if (rq->engine->sched_engine->schedule)
1705	__i915_sched_node_add_dependency(node: &rq->sched,
1706	signal: &prev->sched,
1707	dep: &rq->dep,
1708	flags: 0);
1709	}
1710
1711	/*
1712	* Users have to put the reference to prev potentially got
1713	* by __i915_active_fence_set() when no longer needed
1714	*/
1715	return prev;
1716	}
1717
1718	static struct i915_request *
1719	__i915_request_add_to_timeline(struct i915_request *rq)
1720	{
1721	struct intel_timeline *timeline = i915_request_timeline(rq);
1722	struct i915_request *prev;
1723
1724	/*
1725	* Media workloads may require HuC, so stall them until HuC loading is
1726	* complete. Note that HuC not being loaded when a user submission
1727	* arrives can only happen when HuC is loaded via GSC and in that case
1728	* we still expect the window between us starting to accept submissions
1729	* and HuC loading completion to be small (a few hundred ms).
1730	*/
1731	if (rq->engine->class == VIDEO_DECODE_CLASS)
1732	i915_request_await_huc(rq);
1733
1734	/*
1735	* Dependency tracking and request ordering along the timeline
1736	* is special cased so that we can eliminate redundant ordering
1737	* operations while building the request (we know that the timeline
1738	* itself is ordered, and here we guarantee it).
1739	*
1740	* As we know we will need to emit tracking along the timeline,
1741	* we embed the hooks into our request struct -- at the cost of
1742	* having to have specialised no-allocation interfaces (which will
1743	* be beneficial elsewhere).
1744	*
1745	* A second benefit to open-coding i915_request_await_request is
1746	* that we can apply a slight variant of the rules specialised
1747	* for timelines that jump between engines (such as virtual engines).
1748	* If we consider the case of virtual engine, we must emit a dma-fence
1749	* to prevent scheduling of the second request until the first is
1750	* complete (to maximise our greedy late load balancing) and this
1751	* precludes optimising to use semaphores serialisation of a single
1752	* timeline across engines.
1753	*
1754	* We do not order parallel submission requests on the timeline as each
1755	* parallel submission context has its own timeline and the ordering
1756	* rules for parallel requests are that they must be submitted in the
1757	* order received from the execbuf IOCTL. So rather than using the
1758	* timeline we store a pointer to last request submitted in the
1759	* relationship in the gem context and insert a submission fence
1760	* between that request and request passed into this function or
1761	* alternatively we use completion fence if gem context has a single
1762	* timeline and this is the first submission of an execbuf IOCTL.
1763	*/
1764	if (likely(!is_parallel_rq(rq)))
1765	prev = __i915_request_ensure_ordering(rq, timeline);
1766	else
1767	prev = __i915_request_ensure_parallel_ordering(rq, timeline);
1768	if (prev)
1769	i915_request_put(rq: prev);
1770
1771	/*
1772	* Make sure that no request gazumped us - if it was allocated after
1773	* our i915_request_alloc() and called __i915_request_add() before
1774	* us, the timeline will hold its seqno which is later than ours.
1775	*/
1776	GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1777
1778	return prev;
1779	}
1780
1781	/*
1782	* NB: This function is not allowed to fail. Doing so would mean the the
1783	* request is not being tracked for completion but the work itself is
1784	* going to happen on the hardware. This would be a Bad Thing(tm).
1785	*/
1786	struct i915_request *__i915_request_commit(struct i915_request *rq)
1787	{
1788	struct intel_engine_cs *engine = rq->engine;
1789	struct intel_ring *ring = rq->ring;
1790	u32 *cs;
1791
1792	RQ_TRACE(rq, "\n");
1793
1794	/*
1795	* To ensure that this call will not fail, space for its emissions
1796	* should already have been reserved in the ring buffer. Let the ring
1797	* know that it is time to use that space up.
1798	*/
1799	GEM_BUG_ON(rq->reserved_space > ring->space);
1800	rq->reserved_space = 0;
1801	rq->emitted_jiffies = jiffies;
1802
1803	/*
1804	* Record the position of the start of the breadcrumb so that
1805	* should we detect the updated seqno part-way through the
1806	* GPU processing the request, we never over-estimate the
1807	* position of the ring's HEAD.
1808	*/
1809	cs = intel_ring_begin(rq, num_dwords: engine->emit_fini_breadcrumb_dw);
1810	GEM_BUG_ON(IS_ERR(cs));
1811	rq->postfix = intel_ring_offset(rq, addr: cs);
1812
1813	return __i915_request_add_to_timeline(rq);
1814	}
1815
1816	void __i915_request_queue_bh(struct i915_request *rq)
1817	{
1818	i915_sw_fence_commit(fence: &rq->semaphore);
1819	i915_sw_fence_commit(fence: &rq->submit);
1820	}
1821
1822	void __i915_request_queue(struct i915_request *rq,
1823	const struct i915_sched_attr *attr)
1824	{
1825	/*
1826	* Let the backend know a new request has arrived that may need
1827	* to adjust the existing execution schedule due to a high priority
1828	* request - i.e. we may want to preempt the current request in order
1829	* to run a high priority dependency chain *before* we can execute this
1830	* request.
1831	*
1832	* This is called before the request is ready to run so that we can
1833	* decide whether to preempt the entire chain so that it is ready to
1834	* run at the earliest possible convenience.
1835	*/
1836	if (attr && rq->engine->sched_engine->schedule)
1837	rq->engine->sched_engine->schedule(rq, attr);
1838
1839	local_bh_disable();
1840	__i915_request_queue_bh(rq);
1841	local_bh_enable(); /* kick tasklets */
1842	}
1843
1844	void i915_request_add(struct i915_request *rq)
1845	{
1846	struct intel_timeline * const tl = i915_request_timeline(rq);
1847	struct i915_sched_attr attr = {};
1848	struct i915_gem_context *ctx;
1849
1850	lockdep_assert_held(&tl->mutex);
1851	lockdep_unpin_lock(&tl->mutex, rq->cookie);
1852
1853	trace_i915_request_add(rq);
1854	__i915_request_commit(rq);
1855
1856	/* XXX placeholder for selftests */
1857	rcu_read_lock();
1858	ctx = rcu_dereference(rq->context->gem_context);
1859	if (ctx)
1860	attr = ctx->sched;
1861	rcu_read_unlock();
1862
1863	__i915_request_queue(rq, attr: &attr);
1864
1865	mutex_unlock(lock: &tl->mutex);
1866	}
1867
1868	static unsigned long local_clock_ns(unsigned int *cpu)
1869	{
1870	unsigned long t;
1871
1872	/*
1873	* Cheaply and approximately convert from nanoseconds to microseconds.
1874	* The result and subsequent calculations are also defined in the same
1875	* approximate microseconds units. The principal source of timing
1876	* error here is from the simple truncation.
1877	*
1878	* Note that local_clock() is only defined wrt to the current CPU;
1879	* the comparisons are no longer valid if we switch CPUs. Instead of
1880	* blocking preemption for the entire busywait, we can detect the CPU
1881	* switch and use that as indicator of system load and a reason to
1882	* stop busywaiting, see busywait_stop().
1883	*/
1884	*cpu = get_cpu();
1885	t = local_clock();
1886	put_cpu();
1887
1888	return t;
1889	}
1890
1891	static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1892	{
1893	unsigned int this_cpu;
1894
1895	if (time_after(local_clock_ns(&this_cpu), timeout))
1896	return true;
1897
1898	return this_cpu != cpu;
1899	}
1900
1901	static bool __i915_spin_request(struct i915_request * const rq, int state)
1902	{
1903	unsigned long timeout_ns;
1904	unsigned int cpu;
1905
1906	/*
1907	* Only wait for the request if we know it is likely to complete.
1908	*
1909	* We don't track the timestamps around requests, nor the average
1910	* request length, so we do not have a good indicator that this
1911	* request will complete within the timeout. What we do know is the
1912	* order in which requests are executed by the context and so we can
1913	* tell if the request has been started. If the request is not even
1914	* running yet, it is a fair assumption that it will not complete
1915	* within our relatively short timeout.
1916	*/
1917	if (!i915_request_is_running(rq))
1918	return false;
1919
1920	/*
1921	* When waiting for high frequency requests, e.g. during synchronous
1922	* rendering split between the CPU and GPU, the finite amount of time
1923	* required to set up the irq and wait upon it limits the response
1924	* rate. By busywaiting on the request completion for a short while we
1925	* can service the high frequency waits as quick as possible. However,
1926	* if it is a slow request, we want to sleep as quickly as possible.
1927	* The tradeoff between waiting and sleeping is roughly the time it
1928	* takes to sleep on a request, on the order of a microsecond.
1929	*/
1930
1931	timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1932	timeout_ns += local_clock_ns(cpu: &cpu);
1933	do {
1934	if (dma_fence_is_signaled(fence: &rq->fence))
1935	return true;
1936
1937	if (signal_pending_state(state, current))
1938	break;
1939
1940	if (busywait_stop(timeout: timeout_ns, cpu))
1941	break;
1942
1943	cpu_relax();
1944	} while (!need_resched());
1945
1946	return false;
1947	}
1948
1949	struct request_wait {
1950	struct dma_fence_cb cb;
1951	struct task_struct *tsk;
1952	};
1953
1954	static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1955	{
1956	struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1957
1958	wake_up_process(fetch_and_zero(&wait->tsk));
1959	}
1960
1961	/**
1962	* i915_request_wait_timeout - wait until execution of request has finished
1963	* @rq: the request to wait upon
1964	* @flags: how to wait
1965	* @timeout: how long to wait in jiffies
1966	*
1967	* i915_request_wait_timeout() waits for the request to be completed, for a
1968	* maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1969	* unbounded wait).
1970	*
1971	* Returns the remaining time (in jiffies) if the request completed, which may
1972	* be zero if the request is unfinished after the timeout expires.
1973	* If the timeout is 0, it will return 1 if the fence is signaled.
1974	*
1975	* May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1976	* pending before the request completes.
1977	*
1978	* NOTE: This function has the same wait semantics as dma-fence.
1979	*/
1980	long i915_request_wait_timeout(struct i915_request *rq,
1981	unsigned int flags,
1982	long timeout)
1983	{
1984	const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1985	TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1986	struct request_wait wait;
1987
1988	might_sleep();
1989	GEM_BUG_ON(timeout < 0);
1990
1991	if (dma_fence_is_signaled(fence: &rq->fence))
1992	return timeout ?: 1;
1993
1994	if (!timeout)
1995	return -ETIME;
1996
1997	trace_i915_request_wait_begin(rq, flags);
1998
1999	/*
2000	* We must never wait on the GPU while holding a lock as we
2001	* may need to perform a GPU reset. So while we don't need to
2002	* serialise wait/reset with an explicit lock, we do want
2003	* lockdep to detect potential dependency cycles.
2004	*/
2005	mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
2006
2007	/*
2008	* Optimistic spin before touching IRQs.
2009	*
2010	* We may use a rather large value here to offset the penalty of
2011	* switching away from the active task. Frequently, the client will
2012	* wait upon an old swapbuffer to throttle itself to remain within a
2013	* frame of the gpu. If the client is running in lockstep with the gpu,
2014	* then it should not be waiting long at all, and a sleep now will incur
2015	* extra scheduler latency in producing the next frame. To try to
2016	* avoid adding the cost of enabling/disabling the interrupt to the
2017	* short wait, we first spin to see if the request would have completed
2018	* in the time taken to setup the interrupt.
2019	*
2020	* We need upto 5us to enable the irq, and upto 20us to hide the
2021	* scheduler latency of a context switch, ignoring the secondary
2022	* impacts from a context switch such as cache eviction.
2023	*
2024	* The scheme used for low-latency IO is called "hybrid interrupt
2025	* polling". The suggestion there is to sleep until just before you
2026	* expect to be woken by the device interrupt and then poll for its
2027	* completion. That requires having a good predictor for the request
2028	* duration, which we currently lack.
2029	*/
2030	if (CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT &&
2031	__i915_spin_request(rq, state))
2032	goto out;
2033
2034	/*
2035	* This client is about to stall waiting for the GPU. In many cases
2036	* this is undesirable and limits the throughput of the system, as
2037	* many clients cannot continue processing user input/output whilst
2038	* blocked. RPS autotuning may take tens of milliseconds to respond
2039	* to the GPU load and thus incurs additional latency for the client.
2040	* We can circumvent that by promoting the GPU frequency to maximum
2041	* before we sleep. This makes the GPU throttle up much more quickly
2042	* (good for benchmarks and user experience, e.g. window animations),
2043	* but at a cost of spending more power processing the workload
2044	* (bad for battery).
2045	*/
2046	if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
2047	intel_rps_boost(rq);
2048
2049	wait.tsk = current;
2050	if (dma_fence_add_callback(fence: &rq->fence, cb: &wait.cb, func: request_wait_wake))
2051	goto out;
2052
2053	/*
2054	* Flush the submission tasklet, but only if it may help this request.
2055	*
2056	* We sometimes experience some latency between the HW interrupts and
2057	* tasklet execution (mostly due to ksoftirqd latency, but it can also
2058	* be due to lazy CS events), so lets run the tasklet manually if there
2059	* is a chance it may submit this request. If the request is not ready
2060	* to run, as it is waiting for other fences to be signaled, flushing
2061	* the tasklet is busy work without any advantage for this client.
2062	*
2063	* If the HW is being lazy, this is the last chance before we go to
2064	* sleep to catch any pending events. We will check periodically in
2065	* the heartbeat to flush the submission tasklets as a last resort
2066	* for unhappy HW.
2067	*/
2068	if (i915_request_is_ready(rq))
2069	__intel_engine_flush_submission(engine: rq->engine, sync: false);
2070
2071	for (;;) {
2072	set_current_state(state);
2073
2074	if (dma_fence_is_signaled(fence: &rq->fence))
2075	break;
2076
2077	if (signal_pending_state(state, current)) {
2078	timeout = -ERESTARTSYS;
2079	break;
2080	}
2081
2082	if (!timeout) {
2083	timeout = -ETIME;
2084	break;
2085	}
2086
2087	timeout = io_schedule_timeout(timeout);
2088	}
2089	__set_current_state(TASK_RUNNING);
2090
2091	if (READ_ONCE(wait.tsk))
2092	dma_fence_remove_callback(fence: &rq->fence, cb: &wait.cb);
2093	GEM_BUG_ON(!list_empty(&wait.cb.node));
2094
2095	out:
2096	mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
2097	trace_i915_request_wait_end(rq);
2098	return timeout;
2099	}
2100
2101	/**
2102	* i915_request_wait - wait until execution of request has finished
2103	* @rq: the request to wait upon
2104	* @flags: how to wait
2105	* @timeout: how long to wait in jiffies
2106	*
2107	* i915_request_wait() waits for the request to be completed, for a
2108	* maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
2109	* unbounded wait).
2110	*
2111	* Returns the remaining time (in jiffies) if the request completed, which may
2112	* be zero or -ETIME if the request is unfinished after the timeout expires.
2113	* May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
2114	* pending before the request completes.
2115	*
2116	* NOTE: This function behaves differently from dma-fence wait semantics for
2117	* timeout = 0. It returns 0 on success, and -ETIME if not signaled.
2118	*/
2119	long i915_request_wait(struct i915_request *rq,
2120	unsigned int flags,
2121	long timeout)
2122	{
2123	long ret = i915_request_wait_timeout(rq, flags, timeout);
2124
2125	if (!ret)
2126	return -ETIME;
2127
2128	if (ret > 0 && !timeout)
2129	return 0;
2130
2131	return ret;
2132	}
2133
2134	static int print_sched_attr(const struct i915_sched_attr *attr,
2135	char *buf, int x, int len)
2136	{
2137	if (attr->priority == I915_PRIORITY_INVALID)
2138	return x;
2139
2140	x += snprintf(buf: buf + x, size: len - x,
2141	fmt: " prio=%d", attr->priority);
2142
2143	return x;
2144	}
2145
2146	static char queue_status(const struct i915_request *rq)
2147	{
2148	if (i915_request_is_active(rq))
2149	return 'E';
2150
2151	if (i915_request_is_ready(rq))
2152	return intel_engine_is_virtual(engine: rq->engine) ? 'V' : 'R';
2153
2154	return 'U';
2155	}
2156
2157	static const char *run_status(const struct i915_request *rq)
2158	{
2159	if (__i915_request_is_complete(rq))
2160	return "!";
2161
2162	if (__i915_request_has_started(rq))
2163	return "*";
2164
2165	if (!i915_sw_fence_signaled(fence: &rq->semaphore))
2166	return "&";
2167
2168	return "";
2169	}
2170
2171	static const char *fence_status(const struct i915_request *rq)
2172	{
2173	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
2174	return "+";
2175
2176	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
2177	return "-";
2178
2179	return "";
2180	}
2181
2182	void i915_request_show(struct drm_printer *m,
2183	const struct i915_request *rq,
2184	const char *prefix,
2185	int indent)
2186	{
2187	const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
2188	char buf[80] = "";
2189	int x = 0;
2190
2191	/*
2192	* The prefix is used to show the queue status, for which we use
2193	* the following flags:
2194	*
2195	* U [Unready]
2196	* - initial status upon being submitted by the user
2197	*
2198	* - the request is not ready for execution as it is waiting
2199	* for external fences
2200	*
2201	* R [Ready]
2202	* - all fences the request was waiting on have been signaled,
2203	* and the request is now ready for execution and will be
2204	* in a backend queue
2205	*
2206	* - a ready request may still need to wait on semaphores
2207	* [internal fences]
2208	*
2209	* V [Ready/virtual]
2210	* - same as ready, but queued over multiple backends
2211	*
2212	* E [Executing]
2213	* - the request has been transferred from the backend queue and
2214	* submitted for execution on HW
2215	*
2216	* - a completed request may still be regarded as executing, its
2217	* status may not be updated until it is retired and removed
2218	* from the lists
2219	*/
2220
2221	x = print_sched_attr(attr: &rq->sched.attr, buf, x, len: sizeof(buf));
2222
2223	drm_printf(p: m, f: "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n",
2224	prefix, indent, " ",
2225	queue_status(rq),
2226	rq->fence.context, rq->fence.seqno,
2227	run_status(rq),
2228	fence_status(rq),
2229	buf,
2230	jiffies_to_msecs(j: jiffies - rq->emitted_jiffies),
2231	name);
2232	}
2233
2234	static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq)
2235	{
2236	u32 ring = ENGINE_READ(engine, RING_START);
2237
2238	return ring == i915_ggtt_offset(vma: rq->ring->vma);
2239	}
2240
2241	static bool match_ring(struct i915_request *rq)
2242	{
2243	struct intel_engine_cs *engine;
2244	bool found;
2245	int i;
2246
2247	if (!intel_engine_is_virtual(engine: rq->engine))
2248	return engine_match_ring(engine: rq->engine, rq);
2249
2250	found = false;
2251	i = 0;
2252	while ((engine = intel_engine_get_sibling(engine: rq->engine, sibling: i++))) {
2253	found = engine_match_ring(engine, rq);
2254	if (found)
2255	break;
2256	}
2257
2258	return found;
2259	}
2260
2261	enum i915_request_state i915_test_request_state(struct i915_request *rq)
2262	{
2263	if (i915_request_completed(rq))
2264	return I915_REQUEST_COMPLETE;
2265
2266	if (!i915_request_started(rq))
2267	return I915_REQUEST_PENDING;
2268
2269	if (match_ring(rq))
2270	return I915_REQUEST_ACTIVE;
2271
2272	return I915_REQUEST_QUEUED;
2273	}
2274
2275	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2276	#include "selftests/mock_request.c"
2277	#include "selftests/i915_request.c"
2278	#endif
2279
2280	void i915_request_module_exit(void)
2281	{
2282	kmem_cache_destroy(s: slab_execute_cbs);
2283	kmem_cache_destroy(s: slab_requests);
2284	}
2285
2286	int __init i915_request_module_init(void)
2287	{
2288	slab_requests =
2289	kmem_cache_create(name: "i915_request",
2290	size: sizeof(struct i915_request),
2291	align: __alignof__(struct i915_request),
2292	SLAB_HWCACHE_ALIGN |
2293	SLAB_RECLAIM_ACCOUNT |
2294	SLAB_TYPESAFE_BY_RCU,
2295	ctor: __i915_request_ctor);
2296	if (!slab_requests)
2297	return -ENOMEM;
2298
2299	slab_execute_cbs = KMEM_CACHE(execute_cb,
2300	SLAB_HWCACHE_ALIGN |
2301	SLAB_RECLAIM_ACCOUNT |
2302	SLAB_TYPESAFE_BY_RCU);
2303	if (!slab_execute_cbs)
2304	goto err_requests;
2305
2306	return 0;
2307
2308	err_requests:
2309	kmem_cache_destroy(s: slab_requests);
2310	return -ENOMEM;
2311	}
2312