1 | #ifndef A2XX_XML |
2 | #define A2XX_XML |
3 | |
4 | /* Autogenerated file, DO NOT EDIT manually! |
5 | |
6 | This file was generated by the rules-ng-ng gen_header.py tool in this git repository: |
7 | http://gitlab.freedesktop.org/mesa/mesa/ |
8 | git clone https://gitlab.freedesktop.org/mesa/mesa.git |
9 | |
10 | The rules-ng-ng source files this header was generated from are: |
11 | |
12 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from Fri Jun 2 14:59:26 2023) |
13 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) |
14 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) |
15 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) |
16 | |
17 | Copyright (C) 2013-2024 by the following authors: |
18 | - Rob Clark <robdclark@gmail.com> Rob Clark |
19 | - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin |
20 | |
21 | Permission is hereby granted, free of charge, to any person obtaining |
22 | a copy of this software and associated documentation files (the |
23 | "Software"), to deal in the Software without restriction, including |
24 | without limitation the rights to use, copy, modify, merge, publish, |
25 | distribute, sublicense, and/or sell copies of the Software, and to |
26 | permit persons to whom the Software is furnished to do so, subject to |
27 | the following conditions: |
28 | |
29 | The above copyright notice and this permission notice (including the |
30 | next paragraph) shall be included in all copies or substantial |
31 | portions of the Software. |
32 | |
33 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
34 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
35 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
36 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
37 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
38 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
39 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
40 | |
41 | */ |
42 | |
43 | #ifdef __KERNEL__ |
44 | #include <linux/bug.h> |
45 | #define assert(x) BUG_ON(!(x)) |
46 | #else |
47 | #include <assert.h> |
48 | #endif |
49 | |
50 | #ifdef __cplusplus |
51 | #define __struct_cast(X) |
52 | #else |
53 | #define __struct_cast(X) (struct X) |
54 | #endif |
55 | |
56 | enum a2xx_rb_dither_type { |
57 | DITHER_PIXEL = 0, |
58 | DITHER_SUBPIXEL = 1, |
59 | }; |
60 | |
61 | enum a2xx_colorformatx { |
62 | COLORX_4_4_4_4 = 0, |
63 | COLORX_1_5_5_5 = 1, |
64 | COLORX_5_6_5 = 2, |
65 | COLORX_8 = 3, |
66 | COLORX_8_8 = 4, |
67 | COLORX_8_8_8_8 = 5, |
68 | COLORX_S8_8_8_8 = 6, |
69 | COLORX_16_FLOAT = 7, |
70 | COLORX_16_16_FLOAT = 8, |
71 | COLORX_16_16_16_16_FLOAT = 9, |
72 | COLORX_32_FLOAT = 10, |
73 | COLORX_32_32_FLOAT = 11, |
74 | COLORX_32_32_32_32_FLOAT = 12, |
75 | COLORX_2_3_3 = 13, |
76 | COLORX_8_8_8 = 14, |
77 | }; |
78 | |
79 | enum a2xx_sq_surfaceformat { |
80 | FMT_1_REVERSE = 0, |
81 | FMT_1 = 1, |
82 | FMT_8 = 2, |
83 | FMT_1_5_5_5 = 3, |
84 | FMT_5_6_5 = 4, |
85 | FMT_6_5_5 = 5, |
86 | FMT_8_8_8_8 = 6, |
87 | FMT_2_10_10_10 = 7, |
88 | FMT_8_A = 8, |
89 | FMT_8_B = 9, |
90 | FMT_8_8 = 10, |
91 | FMT_Cr_Y1_Cb_Y0 = 11, |
92 | FMT_Y1_Cr_Y0_Cb = 12, |
93 | FMT_5_5_5_1 = 13, |
94 | FMT_8_8_8_8_A = 14, |
95 | FMT_4_4_4_4 = 15, |
96 | FMT_8_8_8 = 16, |
97 | FMT_DXT1 = 18, |
98 | FMT_DXT2_3 = 19, |
99 | FMT_DXT4_5 = 20, |
100 | FMT_10_10_10_2 = 21, |
101 | FMT_24_8 = 22, |
102 | FMT_16 = 24, |
103 | FMT_16_16 = 25, |
104 | FMT_16_16_16_16 = 26, |
105 | FMT_16_EXPAND = 27, |
106 | FMT_16_16_EXPAND = 28, |
107 | FMT_16_16_16_16_EXPAND = 29, |
108 | FMT_16_FLOAT = 30, |
109 | FMT_16_16_FLOAT = 31, |
110 | FMT_16_16_16_16_FLOAT = 32, |
111 | FMT_32 = 33, |
112 | FMT_32_32 = 34, |
113 | FMT_32_32_32_32 = 35, |
114 | FMT_32_FLOAT = 36, |
115 | FMT_32_32_FLOAT = 37, |
116 | FMT_32_32_32_32_FLOAT = 38, |
117 | FMT_ATI_TC_RGB = 39, |
118 | FMT_ATI_TC_RGBA = 40, |
119 | FMT_ATI_TC_555_565_RGB = 41, |
120 | FMT_ATI_TC_555_565_RGBA = 42, |
121 | FMT_ATI_TC_RGBA_INTERP = 43, |
122 | FMT_ATI_TC_555_565_RGBA_INTERP = 44, |
123 | FMT_ETC1_RGBA_INTERP = 46, |
124 | FMT_ETC1_RGB = 47, |
125 | FMT_ETC1_RGBA = 48, |
126 | FMT_DXN = 49, |
127 | FMT_2_3_3 = 51, |
128 | FMT_2_10_10_10_AS_16_16_16_16 = 54, |
129 | FMT_10_10_10_2_AS_16_16_16_16 = 55, |
130 | FMT_32_32_32_FLOAT = 57, |
131 | FMT_DXT3A = 58, |
132 | FMT_DXT5A = 59, |
133 | FMT_CTX1 = 60, |
134 | }; |
135 | |
136 | enum a2xx_sq_ps_vtx_mode { |
137 | POSITION_1_VECTOR = 0, |
138 | POSITION_2_VECTORS_UNUSED = 1, |
139 | POSITION_2_VECTORS_SPRITE = 2, |
140 | POSITION_2_VECTORS_EDGE = 3, |
141 | POSITION_2_VECTORS_KILL = 4, |
142 | POSITION_2_VECTORS_SPRITE_KILL = 5, |
143 | POSITION_2_VECTORS_EDGE_KILL = 6, |
144 | MULTIPASS = 7, |
145 | }; |
146 | |
147 | enum a2xx_sq_sample_cntl { |
148 | CENTROIDS_ONLY = 0, |
149 | CENTERS_ONLY = 1, |
150 | CENTROIDS_AND_CENTERS = 2, |
151 | }; |
152 | |
153 | enum a2xx_dx_clip_space { |
154 | DXCLIP_OPENGL = 0, |
155 | DXCLIP_DIRECTX = 1, |
156 | }; |
157 | |
158 | enum a2xx_pa_su_sc_polymode { |
159 | POLY_DISABLED = 0, |
160 | POLY_DUALMODE = 1, |
161 | }; |
162 | |
163 | enum a2xx_rb_edram_mode { |
164 | EDRAM_NOP = 0, |
165 | COLOR_DEPTH = 4, |
166 | DEPTH_ONLY = 5, |
167 | EDRAM_COPY = 6, |
168 | }; |
169 | |
170 | enum a2xx_pa_sc_pattern_bit_order { |
171 | LITTLE = 0, |
172 | BIG = 1, |
173 | }; |
174 | |
175 | enum a2xx_pa_sc_auto_reset_cntl { |
176 | NEVER = 0, |
177 | EACH_PRIMITIVE = 1, |
178 | EACH_PACKET = 2, |
179 | }; |
180 | |
181 | enum a2xx_pa_pixcenter { |
182 | PIXCENTER_D3D = 0, |
183 | PIXCENTER_OGL = 1, |
184 | }; |
185 | |
186 | enum a2xx_pa_roundmode { |
187 | TRUNCATE = 0, |
188 | ROUND = 1, |
189 | ROUNDTOEVEN = 2, |
190 | ROUNDTOODD = 3, |
191 | }; |
192 | |
193 | enum a2xx_pa_quantmode { |
194 | ONE_SIXTEENTH = 0, |
195 | ONE_EIGTH = 1, |
196 | ONE_QUARTER = 2, |
197 | ONE_HALF = 3, |
198 | ONE = 4, |
199 | }; |
200 | |
201 | enum a2xx_rb_copy_sample_select { |
202 | SAMPLE_0 = 0, |
203 | SAMPLE_1 = 1, |
204 | SAMPLE_2 = 2, |
205 | SAMPLE_3 = 3, |
206 | SAMPLE_01 = 4, |
207 | SAMPLE_23 = 5, |
208 | SAMPLE_0123 = 6, |
209 | }; |
210 | |
211 | enum a2xx_rb_blend_opcode { |
212 | BLEND2_DST_PLUS_SRC = 0, |
213 | BLEND2_SRC_MINUS_DST = 1, |
214 | BLEND2_MIN_DST_SRC = 2, |
215 | BLEND2_MAX_DST_SRC = 3, |
216 | BLEND2_DST_MINUS_SRC = 4, |
217 | BLEND2_DST_PLUS_SRC_BIAS = 5, |
218 | }; |
219 | |
220 | enum a2xx_su_perfcnt_select { |
221 | PERF_PAPC_PASX_REQ = 0, |
222 | PERF_PAPC_PASX_FIRST_VECTOR = 2, |
223 | PERF_PAPC_PASX_SECOND_VECTOR = 3, |
224 | PERF_PAPC_PASX_FIRST_DEAD = 4, |
225 | PERF_PAPC_PASX_SECOND_DEAD = 5, |
226 | PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, |
227 | PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, |
228 | PERF_PAPC_PA_INPUT_PRIM = 8, |
229 | PERF_PAPC_PA_INPUT_NULL_PRIM = 9, |
230 | PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, |
231 | PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, |
232 | PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, |
233 | PERF_PAPC_CLPR_CULL_PRIM = 13, |
234 | PERF_PAPC_CLPR_VV_CULL_PRIM = 15, |
235 | PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, |
236 | PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, |
237 | PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, |
238 | PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, |
239 | PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, |
240 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, |
241 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, |
242 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, |
243 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, |
244 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, |
245 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, |
246 | PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, |
247 | PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, |
248 | PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, |
249 | PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, |
250 | PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, |
251 | PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, |
252 | PERF_PAPC_CLSM_NULL_PRIM = 36, |
253 | PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, |
254 | PERF_PAPC_CLSM_CLIP_PRIM = 38, |
255 | PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, |
256 | PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, |
257 | PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, |
258 | PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, |
259 | PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, |
260 | PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, |
261 | PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, |
262 | PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, |
263 | PERF_PAPC_SU_INPUT_PRIM = 47, |
264 | PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, |
265 | PERF_PAPC_SU_INPUT_NULL_PRIM = 49, |
266 | PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, |
267 | PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, |
268 | PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, |
269 | PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, |
270 | PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, |
271 | PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, |
272 | PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, |
273 | PERF_PAPC_SU_OUTPUT_PRIM = 57, |
274 | PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, |
275 | PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, |
276 | PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, |
277 | PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, |
278 | PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, |
279 | PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, |
280 | PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, |
281 | PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, |
282 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, |
283 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, |
284 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, |
285 | PERF_PAPC_PASX_REQ_IDLE = 69, |
286 | PERF_PAPC_PASX_REQ_BUSY = 70, |
287 | PERF_PAPC_PASX_REQ_STALLED = 71, |
288 | PERF_PAPC_PASX_REC_IDLE = 72, |
289 | PERF_PAPC_PASX_REC_BUSY = 73, |
290 | PERF_PAPC_PASX_REC_STARVED_SX = 74, |
291 | PERF_PAPC_PASX_REC_STALLED = 75, |
292 | PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, |
293 | PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, |
294 | PERF_PAPC_CCGSM_IDLE = 78, |
295 | PERF_PAPC_CCGSM_BUSY = 79, |
296 | PERF_PAPC_CCGSM_STALLED = 80, |
297 | PERF_PAPC_CLPRIM_IDLE = 81, |
298 | PERF_PAPC_CLPRIM_BUSY = 82, |
299 | PERF_PAPC_CLPRIM_STALLED = 83, |
300 | PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, |
301 | PERF_PAPC_CLIPSM_IDLE = 85, |
302 | PERF_PAPC_CLIPSM_BUSY = 86, |
303 | PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, |
304 | PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, |
305 | PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, |
306 | PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, |
307 | PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, |
308 | PERF_PAPC_CLIPGA_IDLE = 92, |
309 | PERF_PAPC_CLIPGA_BUSY = 93, |
310 | PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, |
311 | PERF_PAPC_CLIPGA_STALLED = 95, |
312 | PERF_PAPC_CLIP_IDLE = 96, |
313 | PERF_PAPC_CLIP_BUSY = 97, |
314 | PERF_PAPC_SU_IDLE = 98, |
315 | PERF_PAPC_SU_BUSY = 99, |
316 | PERF_PAPC_SU_STARVED_CLIP = 100, |
317 | PERF_PAPC_SU_STALLED_SC = 101, |
318 | PERF_PAPC_SU_FACENESS_CULL = 102, |
319 | }; |
320 | |
321 | enum a2xx_sc_perfcnt_select { |
322 | SC_SR_WINDOW_VALID = 0, |
323 | SC_CW_WINDOW_VALID = 1, |
324 | SC_QM_WINDOW_VALID = 2, |
325 | SC_FW_WINDOW_VALID = 3, |
326 | SC_EZ_WINDOW_VALID = 4, |
327 | SC_IT_WINDOW_VALID = 5, |
328 | SC_STARVED_BY_PA = 6, |
329 | SC_STALLED_BY_RB_TILE = 7, |
330 | SC_STALLED_BY_RB_SAMP = 8, |
331 | SC_STARVED_BY_RB_EZ = 9, |
332 | SC_STALLED_BY_SAMPLE_FF = 10, |
333 | SC_STALLED_BY_SQ = 11, |
334 | SC_STALLED_BY_SP = 12, |
335 | SC_TOTAL_NO_PRIMS = 13, |
336 | SC_NON_EMPTY_PRIMS = 14, |
337 | SC_NO_TILES_PASSING_QM = 15, |
338 | SC_NO_PIXELS_PRE_EZ = 16, |
339 | SC_NO_PIXELS_POST_EZ = 17, |
340 | }; |
341 | |
342 | enum a2xx_vgt_perfcount_select { |
343 | VGT_SQ_EVENT_WINDOW_ACTIVE = 0, |
344 | VGT_SQ_SEND = 1, |
345 | VGT_SQ_STALLED = 2, |
346 | VGT_SQ_STARVED_BUSY = 3, |
347 | VGT_SQ_STARVED_IDLE = 4, |
348 | VGT_SQ_STATIC = 5, |
349 | VGT_PA_EVENT_WINDOW_ACTIVE = 6, |
350 | VGT_PA_CLIP_V_SEND = 7, |
351 | VGT_PA_CLIP_V_STALLED = 8, |
352 | VGT_PA_CLIP_V_STARVED_BUSY = 9, |
353 | VGT_PA_CLIP_V_STARVED_IDLE = 10, |
354 | VGT_PA_CLIP_V_STATIC = 11, |
355 | VGT_PA_CLIP_P_SEND = 12, |
356 | VGT_PA_CLIP_P_STALLED = 13, |
357 | VGT_PA_CLIP_P_STARVED_BUSY = 14, |
358 | VGT_PA_CLIP_P_STARVED_IDLE = 15, |
359 | VGT_PA_CLIP_P_STATIC = 16, |
360 | VGT_PA_CLIP_S_SEND = 17, |
361 | VGT_PA_CLIP_S_STALLED = 18, |
362 | VGT_PA_CLIP_S_STARVED_BUSY = 19, |
363 | VGT_PA_CLIP_S_STARVED_IDLE = 20, |
364 | VGT_PA_CLIP_S_STATIC = 21, |
365 | RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, |
366 | RBIU_IMMED_DATA_FIFO_STARVED = 23, |
367 | RBIU_IMMED_DATA_FIFO_STALLED = 24, |
368 | RBIU_DMA_REQUEST_FIFO_STARVED = 25, |
369 | RBIU_DMA_REQUEST_FIFO_STALLED = 26, |
370 | RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, |
371 | RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, |
372 | BIN_PRIM_NEAR_CULL = 29, |
373 | BIN_PRIM_ZERO_CULL = 30, |
374 | BIN_PRIM_FAR_CULL = 31, |
375 | BIN_PRIM_BIN_CULL = 32, |
376 | BIN_PRIM_FACE_CULL = 33, |
377 | SPARE34 = 34, |
378 | SPARE35 = 35, |
379 | SPARE36 = 36, |
380 | SPARE37 = 37, |
381 | SPARE38 = 38, |
382 | SPARE39 = 39, |
383 | TE_SU_IN_VALID = 40, |
384 | TE_SU_IN_READ = 41, |
385 | TE_SU_IN_PRIM = 42, |
386 | TE_SU_IN_EOP = 43, |
387 | TE_SU_IN_NULL_PRIM = 44, |
388 | TE_WK_IN_VALID = 45, |
389 | TE_WK_IN_READ = 46, |
390 | TE_OUT_PRIM_VALID = 47, |
391 | TE_OUT_PRIM_READ = 48, |
392 | }; |
393 | |
394 | enum a2xx_tcr_perfcount_select { |
395 | DGMMPD_IPMUX0_STALL = 0, |
396 | DGMMPD_IPMUX_ALL_STALL = 4, |
397 | OPMUX0_L2_WRITES = 5, |
398 | }; |
399 | |
400 | enum a2xx_tp_perfcount_select { |
401 | POINT_QUADS = 0, |
402 | BILIN_QUADS = 1, |
403 | ANISO_QUADS = 2, |
404 | MIP_QUADS = 3, |
405 | VOL_QUADS = 4, |
406 | MIP_VOL_QUADS = 5, |
407 | MIP_ANISO_QUADS = 6, |
408 | VOL_ANISO_QUADS = 7, |
409 | ANISO_2_1_QUADS = 8, |
410 | ANISO_4_1_QUADS = 9, |
411 | ANISO_6_1_QUADS = 10, |
412 | ANISO_8_1_QUADS = 11, |
413 | ANISO_10_1_QUADS = 12, |
414 | ANISO_12_1_QUADS = 13, |
415 | ANISO_14_1_QUADS = 14, |
416 | ANISO_16_1_QUADS = 15, |
417 | MIP_VOL_ANISO_QUADS = 16, |
418 | ALIGN_2_QUADS = 17, |
419 | ALIGN_4_QUADS = 18, |
420 | PIX_0_QUAD = 19, |
421 | PIX_1_QUAD = 20, |
422 | PIX_2_QUAD = 21, |
423 | PIX_3_QUAD = 22, |
424 | PIX_4_QUAD = 23, |
425 | TP_MIPMAP_LOD0 = 24, |
426 | TP_MIPMAP_LOD1 = 25, |
427 | TP_MIPMAP_LOD2 = 26, |
428 | TP_MIPMAP_LOD3 = 27, |
429 | TP_MIPMAP_LOD4 = 28, |
430 | TP_MIPMAP_LOD5 = 29, |
431 | TP_MIPMAP_LOD6 = 30, |
432 | TP_MIPMAP_LOD7 = 31, |
433 | TP_MIPMAP_LOD8 = 32, |
434 | TP_MIPMAP_LOD9 = 33, |
435 | TP_MIPMAP_LOD10 = 34, |
436 | TP_MIPMAP_LOD11 = 35, |
437 | TP_MIPMAP_LOD12 = 36, |
438 | TP_MIPMAP_LOD13 = 37, |
439 | TP_MIPMAP_LOD14 = 38, |
440 | }; |
441 | |
442 | enum a2xx_tcm_perfcount_select { |
443 | QUAD0_RD_LAT_FIFO_EMPTY = 0, |
444 | QUAD0_RD_LAT_FIFO_4TH_FULL = 3, |
445 | QUAD0_RD_LAT_FIFO_HALF_FULL = 4, |
446 | QUAD0_RD_LAT_FIFO_FULL = 5, |
447 | QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, |
448 | READ_STARVED_QUAD0 = 28, |
449 | READ_STARVED = 32, |
450 | READ_STALLED_QUAD0 = 33, |
451 | READ_STALLED = 37, |
452 | VALID_READ_QUAD0 = 38, |
453 | TC_TP_STARVED_QUAD0 = 42, |
454 | TC_TP_STARVED = 46, |
455 | }; |
456 | |
457 | enum a2xx_tcf_perfcount_select { |
458 | VALID_CYCLES = 0, |
459 | SINGLE_PHASES = 1, |
460 | ANISO_PHASES = 2, |
461 | MIP_PHASES = 3, |
462 | VOL_PHASES = 4, |
463 | MIP_VOL_PHASES = 5, |
464 | MIP_ANISO_PHASES = 6, |
465 | VOL_ANISO_PHASES = 7, |
466 | ANISO_2_1_PHASES = 8, |
467 | ANISO_4_1_PHASES = 9, |
468 | ANISO_6_1_PHASES = 10, |
469 | ANISO_8_1_PHASES = 11, |
470 | ANISO_10_1_PHASES = 12, |
471 | ANISO_12_1_PHASES = 13, |
472 | ANISO_14_1_PHASES = 14, |
473 | ANISO_16_1_PHASES = 15, |
474 | MIP_VOL_ANISO_PHASES = 16, |
475 | ALIGN_2_PHASES = 17, |
476 | ALIGN_4_PHASES = 18, |
477 | TPC_BUSY = 19, |
478 | TPC_STALLED = 20, |
479 | TPC_STARVED = 21, |
480 | TPC_WORKING = 22, |
481 | TPC_WALKER_BUSY = 23, |
482 | TPC_WALKER_STALLED = 24, |
483 | TPC_WALKER_WORKING = 25, |
484 | TPC_ALIGNER_BUSY = 26, |
485 | TPC_ALIGNER_STALLED = 27, |
486 | TPC_ALIGNER_STALLED_BY_BLEND = 28, |
487 | TPC_ALIGNER_STALLED_BY_CACHE = 29, |
488 | TPC_ALIGNER_WORKING = 30, |
489 | TPC_BLEND_BUSY = 31, |
490 | TPC_BLEND_SYNC = 32, |
491 | TPC_BLEND_STARVED = 33, |
492 | TPC_BLEND_WORKING = 34, |
493 | OPCODE_0x00 = 35, |
494 | OPCODE_0x01 = 36, |
495 | OPCODE_0x04 = 37, |
496 | OPCODE_0x10 = 38, |
497 | OPCODE_0x11 = 39, |
498 | OPCODE_0x12 = 40, |
499 | OPCODE_0x13 = 41, |
500 | OPCODE_0x18 = 42, |
501 | OPCODE_0x19 = 43, |
502 | OPCODE_0x1A = 44, |
503 | OPCODE_OTHER = 45, |
504 | IN_FIFO_0_EMPTY = 56, |
505 | IN_FIFO_0_LT_HALF_FULL = 57, |
506 | IN_FIFO_0_HALF_FULL = 58, |
507 | IN_FIFO_0_FULL = 59, |
508 | IN_FIFO_TPC_EMPTY = 72, |
509 | IN_FIFO_TPC_LT_HALF_FULL = 73, |
510 | IN_FIFO_TPC_HALF_FULL = 74, |
511 | IN_FIFO_TPC_FULL = 75, |
512 | TPC_TC_XFC = 76, |
513 | TPC_TC_STATE = 77, |
514 | TC_STALL = 78, |
515 | QUAD0_TAPS = 79, |
516 | QUADS = 83, |
517 | TCA_SYNC_STALL = 84, |
518 | TAG_STALL = 85, |
519 | TCB_SYNC_STALL = 88, |
520 | TCA_VALID = 89, |
521 | PROBES_VALID = 90, |
522 | MISS_STALL = 91, |
523 | FETCH_FIFO_STALL = 92, |
524 | TCO_STALL = 93, |
525 | ANY_STALL = 94, |
526 | TAG_MISSES = 95, |
527 | TAG_HITS = 96, |
528 | SUB_TAG_MISSES = 97, |
529 | SET0_INVALIDATES = 98, |
530 | SET1_INVALIDATES = 99, |
531 | SET2_INVALIDATES = 100, |
532 | SET3_INVALIDATES = 101, |
533 | SET0_TAG_MISSES = 102, |
534 | SET1_TAG_MISSES = 103, |
535 | SET2_TAG_MISSES = 104, |
536 | SET3_TAG_MISSES = 105, |
537 | SET0_TAG_HITS = 106, |
538 | SET1_TAG_HITS = 107, |
539 | SET2_TAG_HITS = 108, |
540 | SET3_TAG_HITS = 109, |
541 | SET0_SUB_TAG_MISSES = 110, |
542 | SET1_SUB_TAG_MISSES = 111, |
543 | SET2_SUB_TAG_MISSES = 112, |
544 | SET3_SUB_TAG_MISSES = 113, |
545 | SET0_EVICT1 = 114, |
546 | SET0_EVICT2 = 115, |
547 | SET0_EVICT3 = 116, |
548 | SET0_EVICT4 = 117, |
549 | SET0_EVICT5 = 118, |
550 | SET0_EVICT6 = 119, |
551 | SET0_EVICT7 = 120, |
552 | SET0_EVICT8 = 121, |
553 | SET1_EVICT1 = 130, |
554 | SET1_EVICT2 = 131, |
555 | SET1_EVICT3 = 132, |
556 | SET1_EVICT4 = 133, |
557 | SET1_EVICT5 = 134, |
558 | SET1_EVICT6 = 135, |
559 | SET1_EVICT7 = 136, |
560 | SET1_EVICT8 = 137, |
561 | SET2_EVICT1 = 146, |
562 | SET2_EVICT2 = 147, |
563 | SET2_EVICT3 = 148, |
564 | SET2_EVICT4 = 149, |
565 | SET2_EVICT5 = 150, |
566 | SET2_EVICT6 = 151, |
567 | SET2_EVICT7 = 152, |
568 | SET2_EVICT8 = 153, |
569 | SET3_EVICT1 = 162, |
570 | SET3_EVICT2 = 163, |
571 | SET3_EVICT3 = 164, |
572 | SET3_EVICT4 = 165, |
573 | SET3_EVICT5 = 166, |
574 | SET3_EVICT6 = 167, |
575 | SET3_EVICT7 = 168, |
576 | SET3_EVICT8 = 169, |
577 | FF_EMPTY = 178, |
578 | FF_LT_HALF_FULL = 179, |
579 | FF_HALF_FULL = 180, |
580 | FF_FULL = 181, |
581 | FF_XFC = 182, |
582 | FF_STALLED = 183, |
583 | FG_MASKS = 184, |
584 | FG_LEFT_MASKS = 185, |
585 | FG_LEFT_MASK_STALLED = 186, |
586 | FG_LEFT_NOT_DONE_STALL = 187, |
587 | FG_LEFT_FG_STALL = 188, |
588 | FG_LEFT_SECTORS = 189, |
589 | FG0_REQUESTS = 195, |
590 | FG0_STALLED = 196, |
591 | MEM_REQ512 = 199, |
592 | MEM_REQ_SENT = 200, |
593 | MEM_LOCAL_READ_REQ = 202, |
594 | TC0_MH_STALLED = 203, |
595 | }; |
596 | |
597 | enum a2xx_sq_perfcnt_select { |
598 | SQ_PIXEL_VECTORS_SUB = 0, |
599 | SQ_VERTEX_VECTORS_SUB = 1, |
600 | SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, |
601 | SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, |
602 | SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, |
603 | SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, |
604 | SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, |
605 | SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, |
606 | SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, |
607 | SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, |
608 | SQ_EXPORT_CYCLES = 10, |
609 | SQ_ALU_CST_WRITTEN = 11, |
610 | SQ_TEX_CST_WRITTEN = 12, |
611 | SQ_ALU_CST_STALL = 13, |
612 | SQ_ALU_TEX_STALL = 14, |
613 | SQ_INST_WRITTEN = 15, |
614 | SQ_BOOLEAN_WRITTEN = 16, |
615 | SQ_LOOPS_WRITTEN = 17, |
616 | SQ_PIXEL_SWAP_IN = 18, |
617 | SQ_PIXEL_SWAP_OUT = 19, |
618 | SQ_VERTEX_SWAP_IN = 20, |
619 | SQ_VERTEX_SWAP_OUT = 21, |
620 | SQ_ALU_VTX_INST_ISSUED = 22, |
621 | SQ_TEX_VTX_INST_ISSUED = 23, |
622 | SQ_VC_VTX_INST_ISSUED = 24, |
623 | SQ_CF_VTX_INST_ISSUED = 25, |
624 | SQ_ALU_PIX_INST_ISSUED = 26, |
625 | SQ_TEX_PIX_INST_ISSUED = 27, |
626 | SQ_VC_PIX_INST_ISSUED = 28, |
627 | SQ_CF_PIX_INST_ISSUED = 29, |
628 | SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, |
629 | SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, |
630 | SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, |
631 | SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, |
632 | SQ_ALU_NOPS = 34, |
633 | SQ_PRED_SKIP = 35, |
634 | SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, |
635 | SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, |
636 | SQ_SYNC_TEX_STALL_VTX = 38, |
637 | SQ_SYNC_VC_STALL_VTX = 39, |
638 | SQ_CONSTANTS_USED_SIMD0 = 40, |
639 | SQ_CONSTANTS_SENT_SP_SIMD0 = 41, |
640 | SQ_GPR_STALL_VTX = 42, |
641 | SQ_GPR_STALL_PIX = 43, |
642 | SQ_VTX_RS_STALL = 44, |
643 | SQ_PIX_RS_STALL = 45, |
644 | SQ_SX_PC_FULL = 46, |
645 | SQ_SX_EXP_BUFF_FULL = 47, |
646 | SQ_SX_POS_BUFF_FULL = 48, |
647 | SQ_INTERP_QUADS = 49, |
648 | SQ_INTERP_ACTIVE = 50, |
649 | SQ_IN_PIXEL_STALL = 51, |
650 | SQ_IN_VTX_STALL = 52, |
651 | SQ_VTX_CNT = 53, |
652 | SQ_VTX_VECTOR2 = 54, |
653 | SQ_VTX_VECTOR3 = 55, |
654 | SQ_VTX_VECTOR4 = 56, |
655 | SQ_PIXEL_VECTOR1 = 57, |
656 | SQ_PIXEL_VECTOR23 = 58, |
657 | SQ_PIXEL_VECTOR4 = 59, |
658 | SQ_CONSTANTS_USED_SIMD1 = 60, |
659 | SQ_CONSTANTS_SENT_SP_SIMD1 = 61, |
660 | SQ_SX_MEM_EXP_FULL = 62, |
661 | SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, |
662 | SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, |
663 | SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, |
664 | SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, |
665 | SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, |
666 | SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, |
667 | SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, |
668 | SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, |
669 | SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, |
670 | SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, |
671 | SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, |
672 | SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, |
673 | SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, |
674 | SQ_PERFCOUNT_VTX_POP_THREAD = 76, |
675 | SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, |
676 | SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, |
677 | SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, |
678 | SQ_PERFCOUNT_PIX_POP_THREAD = 80, |
679 | SQ_SYNC_TEX_STALL_PIX = 81, |
680 | SQ_SYNC_VC_STALL_PIX = 82, |
681 | SQ_CONSTANTS_USED_SIMD2 = 83, |
682 | SQ_CONSTANTS_SENT_SP_SIMD2 = 84, |
683 | SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, |
684 | SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, |
685 | SQ_ALU0_FIFO_FULL_SIMD0 = 87, |
686 | SQ_ALU1_FIFO_FULL_SIMD0 = 88, |
687 | SQ_ALU0_FIFO_FULL_SIMD1 = 89, |
688 | SQ_ALU1_FIFO_FULL_SIMD1 = 90, |
689 | SQ_ALU0_FIFO_FULL_SIMD2 = 91, |
690 | SQ_ALU1_FIFO_FULL_SIMD2 = 92, |
691 | SQ_ALU0_FIFO_FULL_SIMD3 = 93, |
692 | SQ_ALU1_FIFO_FULL_SIMD3 = 94, |
693 | VC_PERF_STATIC = 95, |
694 | VC_PERF_STALLED = 96, |
695 | VC_PERF_STARVED = 97, |
696 | VC_PERF_SEND = 98, |
697 | VC_PERF_ACTUAL_STARVED = 99, |
698 | PIXEL_THREAD_0_ACTIVE = 100, |
699 | VERTEX_THREAD_0_ACTIVE = 101, |
700 | PIXEL_THREAD_0_NUMBER = 102, |
701 | VERTEX_THREAD_0_NUMBER = 103, |
702 | VERTEX_EVENT_NUMBER = 104, |
703 | PIXEL_EVENT_NUMBER = 105, |
704 | PTRBUFF_EF_PUSH = 106, |
705 | PTRBUFF_EF_POP_EVENT = 107, |
706 | PTRBUFF_EF_POP_NEW_VTX = 108, |
707 | PTRBUFF_EF_POP_DEALLOC = 109, |
708 | PTRBUFF_EF_POP_PVECTOR = 110, |
709 | PTRBUFF_EF_POP_PVECTOR_X = 111, |
710 | PTRBUFF_EF_POP_PVECTOR_VNZ = 112, |
711 | PTRBUFF_PB_DEALLOC = 113, |
712 | PTRBUFF_PI_STATE_PPB_POP = 114, |
713 | PTRBUFF_PI_RTR = 115, |
714 | PTRBUFF_PI_READ_EN = 116, |
715 | PTRBUFF_PI_BUFF_SWAP = 117, |
716 | PTRBUFF_SQ_FREE_BUFF = 118, |
717 | PTRBUFF_SQ_DEC = 119, |
718 | PTRBUFF_SC_VALID_CNTL_EVENT = 120, |
719 | PTRBUFF_SC_VALID_IJ_XFER = 121, |
720 | PTRBUFF_SC_NEW_VECTOR_1_Q = 122, |
721 | PTRBUFF_QUAL_NEW_VECTOR = 123, |
722 | PTRBUFF_QUAL_EVENT = 124, |
723 | PTRBUFF_END_BUFFER = 125, |
724 | PTRBUFF_FILL_QUAD = 126, |
725 | VERTS_WRITTEN_SPI = 127, |
726 | TP_FETCH_INSTR_EXEC = 128, |
727 | TP_FETCH_INSTR_REQ = 129, |
728 | TP_DATA_RETURN = 130, |
729 | SPI_WRITE_CYCLES_SP = 131, |
730 | SPI_WRITES_SP = 132, |
731 | SP_ALU_INSTR_EXEC = 133, |
732 | SP_CONST_ADDR_TO_SQ = 134, |
733 | SP_PRED_KILLS_TO_SQ = 135, |
734 | SP_EXPORT_CYCLES_TO_SX = 136, |
735 | SP_EXPORTS_TO_SX = 137, |
736 | SQ_CYCLES_ELAPSED = 138, |
737 | SQ_TCFS_OPT_ALLOC_EXEC = 139, |
738 | SQ_TCFS_NO_OPT_ALLOC = 140, |
739 | SQ_ALU0_NO_OPT_ALLOC = 141, |
740 | SQ_ALU1_NO_OPT_ALLOC = 142, |
741 | SQ_TCFS_ARB_XFC_CNT = 143, |
742 | SQ_ALU0_ARB_XFC_CNT = 144, |
743 | SQ_ALU1_ARB_XFC_CNT = 145, |
744 | SQ_TCFS_CFS_UPDATE_CNT = 146, |
745 | SQ_ALU0_CFS_UPDATE_CNT = 147, |
746 | SQ_ALU1_CFS_UPDATE_CNT = 148, |
747 | SQ_VTX_PUSH_THREAD_CNT = 149, |
748 | SQ_VTX_POP_THREAD_CNT = 150, |
749 | SQ_PIX_PUSH_THREAD_CNT = 151, |
750 | SQ_PIX_POP_THREAD_CNT = 152, |
751 | SQ_PIX_TOTAL = 153, |
752 | SQ_PIX_KILLED = 154, |
753 | }; |
754 | |
755 | enum a2xx_sx_perfcnt_select { |
756 | SX_EXPORT_VECTORS = 0, |
757 | SX_DUMMY_QUADS = 1, |
758 | SX_ALPHA_FAIL = 2, |
759 | SX_RB_QUAD_BUSY = 3, |
760 | SX_RB_COLOR_BUSY = 4, |
761 | SX_RB_QUAD_STALL = 5, |
762 | SX_RB_COLOR_STALL = 6, |
763 | }; |
764 | |
765 | enum a2xx_rbbm_perfcount1_sel { |
766 | RBBM1_COUNT = 0, |
767 | RBBM1_NRT_BUSY = 1, |
768 | RBBM1_RB_BUSY = 2, |
769 | RBBM1_SQ_CNTX0_BUSY = 3, |
770 | RBBM1_SQ_CNTX17_BUSY = 4, |
771 | RBBM1_VGT_BUSY = 5, |
772 | RBBM1_VGT_NODMA_BUSY = 6, |
773 | RBBM1_PA_BUSY = 7, |
774 | RBBM1_SC_CNTX_BUSY = 8, |
775 | RBBM1_TPC_BUSY = 9, |
776 | RBBM1_TC_BUSY = 10, |
777 | RBBM1_SX_BUSY = 11, |
778 | RBBM1_CP_COHER_BUSY = 12, |
779 | RBBM1_CP_NRT_BUSY = 13, |
780 | RBBM1_GFX_IDLE_STALL = 14, |
781 | RBBM1_INTERRUPT = 15, |
782 | }; |
783 | |
784 | enum a2xx_cp_perfcount_sel { |
785 | ALWAYS_COUNT = 0, |
786 | TRANS_FIFO_FULL = 1, |
787 | TRANS_FIFO_AF = 2, |
788 | RCIU_PFPTRANS_WAIT = 3, |
789 | RCIU_NRTTRANS_WAIT = 6, |
790 | CSF_NRT_READ_WAIT = 8, |
791 | CSF_I1_FIFO_FULL = 9, |
792 | CSF_I2_FIFO_FULL = 10, |
793 | CSF_ST_FIFO_FULL = 11, |
794 | CSF_RING_ROQ_FULL = 13, |
795 | CSF_I1_ROQ_FULL = 14, |
796 | CSF_I2_ROQ_FULL = 15, |
797 | CSF_ST_ROQ_FULL = 16, |
798 | MIU_TAG_MEM_FULL = 18, |
799 | MIU_WRITECLEAN = 19, |
800 | MIU_NRT_WRITE_STALLED = 22, |
801 | MIU_NRT_READ_STALLED = 23, |
802 | ME_WRITE_CONFIRM_FIFO_FULL = 24, |
803 | ME_VS_DEALLOC_FIFO_FULL = 25, |
804 | ME_PS_DEALLOC_FIFO_FULL = 26, |
805 | ME_REGS_VS_EVENT_FIFO_FULL = 27, |
806 | ME_REGS_PS_EVENT_FIFO_FULL = 28, |
807 | ME_REGS_CF_EVENT_FIFO_FULL = 29, |
808 | ME_MICRO_RB_STARVED = 30, |
809 | ME_MICRO_I1_STARVED = 31, |
810 | ME_MICRO_I2_STARVED = 32, |
811 | ME_MICRO_ST_STARVED = 33, |
812 | RCIU_RBBM_DWORD_SENT = 40, |
813 | ME_BUSY_CLOCKS = 41, |
814 | ME_WAIT_CONTEXT_AVAIL = 42, |
815 | PFP_TYPE0_PACKET = 43, |
816 | PFP_TYPE3_PACKET = 44, |
817 | CSF_RB_WPTR_NEQ_RPTR = 45, |
818 | CSF_I1_SIZE_NEQ_ZERO = 46, |
819 | CSF_I2_SIZE_NEQ_ZERO = 47, |
820 | CSF_RBI1I2_FETCHING = 48, |
821 | }; |
822 | |
823 | enum a2xx_rb_perfcnt_select { |
824 | RBPERF_CNTX_BUSY = 0, |
825 | RBPERF_CNTX_BUSY_MAX = 1, |
826 | RBPERF_SX_QUAD_STARVED = 2, |
827 | RBPERF_SX_QUAD_STARVED_MAX = 3, |
828 | RBPERF_GA_GC_CH0_SYS_REQ = 4, |
829 | RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, |
830 | RBPERF_GA_GC_CH1_SYS_REQ = 6, |
831 | RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, |
832 | RBPERF_MH_STARVED = 8, |
833 | RBPERF_MH_STARVED_MAX = 9, |
834 | RBPERF_AZ_BC_COLOR_BUSY = 10, |
835 | RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, |
836 | RBPERF_AZ_BC_Z_BUSY = 12, |
837 | RBPERF_AZ_BC_Z_BUSY_MAX = 13, |
838 | RBPERF_RB_SC_TILE_RTR_N = 14, |
839 | RBPERF_RB_SC_TILE_RTR_N_MAX = 15, |
840 | RBPERF_RB_SC_SAMP_RTR_N = 16, |
841 | RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, |
842 | RBPERF_RB_SX_QUAD_RTR_N = 18, |
843 | RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, |
844 | RBPERF_RB_SX_COLOR_RTR_N = 20, |
845 | RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, |
846 | RBPERF_RB_SC_SAMP_LZ_BUSY = 22, |
847 | RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, |
848 | RBPERF_ZXP_STALL = 24, |
849 | RBPERF_ZXP_STALL_MAX = 25, |
850 | RBPERF_EVENT_PENDING = 26, |
851 | RBPERF_EVENT_PENDING_MAX = 27, |
852 | RBPERF_RB_MH_VALID = 28, |
853 | RBPERF_RB_MH_VALID_MAX = 29, |
854 | RBPERF_SX_RB_QUAD_SEND = 30, |
855 | RBPERF_SX_RB_COLOR_SEND = 31, |
856 | RBPERF_SC_RB_TILE_SEND = 32, |
857 | RBPERF_SC_RB_SAMPLE_SEND = 33, |
858 | RBPERF_SX_RB_MEM_EXPORT = 34, |
859 | RBPERF_SX_RB_QUAD_EVENT = 35, |
860 | RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, |
861 | RBPERF_SC_RB_TILE_EVENT_ALL = 37, |
862 | RBPERF_RB_SC_EZ_SEND = 38, |
863 | RBPERF_RB_SX_INDEX_SEND = 39, |
864 | RBPERF_GMEM_INTFO_RD = 40, |
865 | RBPERF_GMEM_INTF1_RD = 41, |
866 | RBPERF_GMEM_INTFO_WR = 42, |
867 | RBPERF_GMEM_INTF1_WR = 43, |
868 | RBPERF_RB_CP_CONTEXT_DONE = 44, |
869 | RBPERF_RB_CP_CACHE_FLUSH = 45, |
870 | RBPERF_ZPASS_DONE = 46, |
871 | RBPERF_ZCMD_VALID = 47, |
872 | RBPERF_CCMD_VALID = 48, |
873 | RBPERF_ACCUM_GRANT = 49, |
874 | RBPERF_ACCUM_C0_GRANT = 50, |
875 | RBPERF_ACCUM_C1_GRANT = 51, |
876 | RBPERF_ACCUM_FULL_BE_WR = 52, |
877 | RBPERF_ACCUM_REQUEST_NO_GRANT = 53, |
878 | RBPERF_ACCUM_TIMEOUT_PULSE = 54, |
879 | RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, |
880 | RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, |
881 | }; |
882 | |
883 | enum a2xx_mh_perfcnt_select { |
884 | CP_R0_REQUESTS = 0, |
885 | CP_R1_REQUESTS = 1, |
886 | CP_R2_REQUESTS = 2, |
887 | CP_R3_REQUESTS = 3, |
888 | CP_R4_REQUESTS = 4, |
889 | CP_TOTAL_READ_REQUESTS = 5, |
890 | CP_TOTAL_WRITE_REQUESTS = 6, |
891 | CP_TOTAL_REQUESTS = 7, |
892 | CP_DATA_BYTES_WRITTEN = 8, |
893 | CP_WRITE_CLEAN_RESPONSES = 9, |
894 | CP_R0_READ_BURSTS_RECEIVED = 10, |
895 | CP_R1_READ_BURSTS_RECEIVED = 11, |
896 | CP_R2_READ_BURSTS_RECEIVED = 12, |
897 | CP_R3_READ_BURSTS_RECEIVED = 13, |
898 | CP_R4_READ_BURSTS_RECEIVED = 14, |
899 | CP_TOTAL_READ_BURSTS_RECEIVED = 15, |
900 | CP_R0_DATA_BEATS_READ = 16, |
901 | CP_R1_DATA_BEATS_READ = 17, |
902 | CP_R2_DATA_BEATS_READ = 18, |
903 | CP_R3_DATA_BEATS_READ = 19, |
904 | CP_R4_DATA_BEATS_READ = 20, |
905 | CP_TOTAL_DATA_BEATS_READ = 21, |
906 | VGT_R0_REQUESTS = 22, |
907 | VGT_R1_REQUESTS = 23, |
908 | VGT_TOTAL_REQUESTS = 24, |
909 | VGT_R0_READ_BURSTS_RECEIVED = 25, |
910 | VGT_R1_READ_BURSTS_RECEIVED = 26, |
911 | VGT_TOTAL_READ_BURSTS_RECEIVED = 27, |
912 | VGT_R0_DATA_BEATS_READ = 28, |
913 | VGT_R1_DATA_BEATS_READ = 29, |
914 | VGT_TOTAL_DATA_BEATS_READ = 30, |
915 | TC_TOTAL_REQUESTS = 31, |
916 | TC_ROQ_REQUESTS = 32, |
917 | TC_INFO_SENT = 33, |
918 | TC_READ_BURSTS_RECEIVED = 34, |
919 | TC_DATA_BEATS_READ = 35, |
920 | TCD_BURSTS_READ = 36, |
921 | RB_REQUESTS = 37, |
922 | RB_DATA_BYTES_WRITTEN = 38, |
923 | RB_WRITE_CLEAN_RESPONSES = 39, |
924 | AXI_READ_REQUESTS_ID_0 = 40, |
925 | AXI_READ_REQUESTS_ID_1 = 41, |
926 | AXI_READ_REQUESTS_ID_2 = 42, |
927 | AXI_READ_REQUESTS_ID_3 = 43, |
928 | AXI_READ_REQUESTS_ID_4 = 44, |
929 | AXI_READ_REQUESTS_ID_5 = 45, |
930 | AXI_READ_REQUESTS_ID_6 = 46, |
931 | AXI_READ_REQUESTS_ID_7 = 47, |
932 | AXI_TOTAL_READ_REQUESTS = 48, |
933 | AXI_WRITE_REQUESTS_ID_0 = 49, |
934 | AXI_WRITE_REQUESTS_ID_1 = 50, |
935 | AXI_WRITE_REQUESTS_ID_2 = 51, |
936 | AXI_WRITE_REQUESTS_ID_3 = 52, |
937 | AXI_WRITE_REQUESTS_ID_4 = 53, |
938 | AXI_WRITE_REQUESTS_ID_5 = 54, |
939 | AXI_WRITE_REQUESTS_ID_6 = 55, |
940 | AXI_WRITE_REQUESTS_ID_7 = 56, |
941 | AXI_TOTAL_WRITE_REQUESTS = 57, |
942 | AXI_TOTAL_REQUESTS_ID_0 = 58, |
943 | AXI_TOTAL_REQUESTS_ID_1 = 59, |
944 | AXI_TOTAL_REQUESTS_ID_2 = 60, |
945 | AXI_TOTAL_REQUESTS_ID_3 = 61, |
946 | AXI_TOTAL_REQUESTS_ID_4 = 62, |
947 | AXI_TOTAL_REQUESTS_ID_5 = 63, |
948 | AXI_TOTAL_REQUESTS_ID_6 = 64, |
949 | AXI_TOTAL_REQUESTS_ID_7 = 65, |
950 | AXI_TOTAL_REQUESTS = 66, |
951 | AXI_READ_CHANNEL_BURSTS_ID_0 = 67, |
952 | AXI_READ_CHANNEL_BURSTS_ID_1 = 68, |
953 | AXI_READ_CHANNEL_BURSTS_ID_2 = 69, |
954 | AXI_READ_CHANNEL_BURSTS_ID_3 = 70, |
955 | AXI_READ_CHANNEL_BURSTS_ID_4 = 71, |
956 | AXI_READ_CHANNEL_BURSTS_ID_5 = 72, |
957 | AXI_READ_CHANNEL_BURSTS_ID_6 = 73, |
958 | AXI_READ_CHANNEL_BURSTS_ID_7 = 74, |
959 | AXI_READ_CHANNEL_TOTAL_BURSTS = 75, |
960 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, |
961 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, |
962 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, |
963 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, |
964 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, |
965 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, |
966 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, |
967 | AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, |
968 | AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, |
969 | AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, |
970 | AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, |
971 | AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, |
972 | AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, |
973 | AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, |
974 | AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, |
975 | AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, |
976 | AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, |
977 | AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, |
978 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, |
979 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, |
980 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, |
981 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, |
982 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, |
983 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, |
984 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, |
985 | AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, |
986 | AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, |
987 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, |
988 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, |
989 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, |
990 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, |
991 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, |
992 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, |
993 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, |
994 | AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, |
995 | AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, |
996 | TOTAL_MMU_MISSES = 112, |
997 | MMU_READ_MISSES = 113, |
998 | MMU_WRITE_MISSES = 114, |
999 | TOTAL_MMU_HITS = 115, |
1000 | MMU_READ_HITS = 116, |
1001 | MMU_WRITE_HITS = 117, |
1002 | SPLIT_MODE_TC_HITS = 118, |
1003 | SPLIT_MODE_TC_MISSES = 119, |
1004 | SPLIT_MODE_NON_TC_HITS = 120, |
1005 | SPLIT_MODE_NON_TC_MISSES = 121, |
1006 | STALL_AWAITING_TLB_MISS_FETCH = 122, |
1007 | MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, |
1008 | MMU_TLB_MISS_DATA_BEATS_READ = 124, |
1009 | CP_CYCLES_HELD_OFF = 125, |
1010 | VGT_CYCLES_HELD_OFF = 126, |
1011 | TC_CYCLES_HELD_OFF = 127, |
1012 | TC_ROQ_CYCLES_HELD_OFF = 128, |
1013 | TC_CYCLES_HELD_OFF_TCD_FULL = 129, |
1014 | RB_CYCLES_HELD_OFF = 130, |
1015 | TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, |
1016 | TLB_MISS_CYCLES_HELD_OFF = 132, |
1017 | AXI_READ_REQUEST_HELD_OFF = 133, |
1018 | AXI_WRITE_REQUEST_HELD_OFF = 134, |
1019 | AXI_REQUEST_HELD_OFF = 135, |
1020 | AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, |
1021 | AXI_WRITE_DATA_HELD_OFF = 137, |
1022 | CP_SAME_PAGE_BANK_REQUESTS = 138, |
1023 | VGT_SAME_PAGE_BANK_REQUESTS = 139, |
1024 | TC_SAME_PAGE_BANK_REQUESTS = 140, |
1025 | TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, |
1026 | RB_SAME_PAGE_BANK_REQUESTS = 142, |
1027 | TOTAL_SAME_PAGE_BANK_REQUESTS = 143, |
1028 | CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, |
1029 | VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, |
1030 | TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, |
1031 | RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, |
1032 | TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, |
1033 | TOTAL_MH_READ_REQUESTS = 149, |
1034 | TOTAL_MH_WRITE_REQUESTS = 150, |
1035 | TOTAL_MH_REQUESTS = 151, |
1036 | MH_BUSY = 152, |
1037 | CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, |
1038 | VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, |
1039 | TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, |
1040 | RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, |
1041 | TC_ROQ_N_VALID_ENTRIES = 157, |
1042 | ARQ_N_ENTRIES = 158, |
1043 | WDB_N_ENTRIES = 159, |
1044 | MH_READ_LATENCY_OUTST_REQ_SUM = 160, |
1045 | MC_READ_LATENCY_OUTST_REQ_SUM = 161, |
1046 | MC_TOTAL_READ_REQUESTS = 162, |
1047 | ELAPSED_CYCLES_MH_GATED_CLK = 163, |
1048 | ELAPSED_CLK_CYCLES = 164, |
1049 | CP_W_16B_REQUESTS = 165, |
1050 | CP_W_32B_REQUESTS = 166, |
1051 | TC_16B_REQUESTS = 167, |
1052 | TC_32B_REQUESTS = 168, |
1053 | PA_REQUESTS = 169, |
1054 | PA_DATA_BYTES_WRITTEN = 170, |
1055 | PA_WRITE_CLEAN_RESPONSES = 171, |
1056 | PA_CYCLES_HELD_OFF = 172, |
1057 | AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, |
1058 | AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, |
1059 | AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, |
1060 | AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, |
1061 | AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, |
1062 | AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, |
1063 | AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, |
1064 | AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, |
1065 | AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, |
1066 | }; |
1067 | |
1068 | enum perf_mode_cnt { |
1069 | PERF_STATE_RESET = 0, |
1070 | PERF_STATE_ENABLE = 1, |
1071 | PERF_STATE_FREEZE = 2, |
1072 | }; |
1073 | |
1074 | enum adreno_mmu_clnt_beh { |
1075 | BEH_NEVR = 0, |
1076 | BEH_TRAN_RNG = 1, |
1077 | BEH_TRAN_FLT = 2, |
1078 | }; |
1079 | |
1080 | enum sq_tex_clamp { |
1081 | SQ_TEX_WRAP = 0, |
1082 | SQ_TEX_MIRROR = 1, |
1083 | SQ_TEX_CLAMP_LAST_TEXEL = 2, |
1084 | SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, |
1085 | SQ_TEX_CLAMP_HALF_BORDER = 4, |
1086 | SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, |
1087 | SQ_TEX_CLAMP_BORDER = 6, |
1088 | SQ_TEX_MIRROR_ONCE_BORDER = 7, |
1089 | }; |
1090 | |
1091 | enum sq_tex_swiz { |
1092 | SQ_TEX_X = 0, |
1093 | SQ_TEX_Y = 1, |
1094 | SQ_TEX_Z = 2, |
1095 | SQ_TEX_W = 3, |
1096 | SQ_TEX_ZERO = 4, |
1097 | SQ_TEX_ONE = 5, |
1098 | }; |
1099 | |
1100 | enum sq_tex_filter { |
1101 | SQ_TEX_FILTER_POINT = 0, |
1102 | SQ_TEX_FILTER_BILINEAR = 1, |
1103 | SQ_TEX_FILTER_BASEMAP = 2, |
1104 | SQ_TEX_FILTER_USE_FETCH_CONST = 3, |
1105 | }; |
1106 | |
1107 | enum sq_tex_aniso_filter { |
1108 | SQ_TEX_ANISO_FILTER_DISABLED = 0, |
1109 | SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, |
1110 | SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, |
1111 | SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, |
1112 | SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, |
1113 | SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, |
1114 | SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, |
1115 | }; |
1116 | |
1117 | enum sq_tex_dimension { |
1118 | SQ_TEX_DIMENSION_1D = 0, |
1119 | SQ_TEX_DIMENSION_2D = 1, |
1120 | SQ_TEX_DIMENSION_3D = 2, |
1121 | SQ_TEX_DIMENSION_CUBE = 3, |
1122 | }; |
1123 | |
1124 | enum sq_tex_border_color { |
1125 | SQ_TEX_BORDER_COLOR_BLACK = 0, |
1126 | SQ_TEX_BORDER_COLOR_WHITE = 1, |
1127 | SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, |
1128 | SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, |
1129 | }; |
1130 | |
1131 | enum sq_tex_sign { |
1132 | SQ_TEX_SIGN_UNSIGNED = 0, |
1133 | SQ_TEX_SIGN_SIGNED = 1, |
1134 | SQ_TEX_SIGN_UNSIGNED_BIASED = 2, |
1135 | SQ_TEX_SIGN_GAMMA = 3, |
1136 | }; |
1137 | |
1138 | enum sq_tex_endian { |
1139 | SQ_TEX_ENDIAN_NONE = 0, |
1140 | SQ_TEX_ENDIAN_8IN16 = 1, |
1141 | SQ_TEX_ENDIAN_8IN32 = 2, |
1142 | SQ_TEX_ENDIAN_16IN32 = 3, |
1143 | }; |
1144 | |
1145 | enum sq_tex_clamp_policy { |
1146 | SQ_TEX_CLAMP_POLICY_D3D = 0, |
1147 | SQ_TEX_CLAMP_POLICY_OGL = 1, |
1148 | }; |
1149 | |
1150 | enum sq_tex_num_format { |
1151 | SQ_TEX_NUM_FORMAT_FRAC = 0, |
1152 | SQ_TEX_NUM_FORMAT_INT = 1, |
1153 | }; |
1154 | |
1155 | enum sq_tex_type { |
1156 | SQ_TEX_TYPE_0 = 0, |
1157 | SQ_TEX_TYPE_1 = 1, |
1158 | SQ_TEX_TYPE_2 = 2, |
1159 | SQ_TEX_TYPE_3 = 3, |
1160 | }; |
1161 | |
1162 | #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 |
1163 | |
1164 | #define REG_A2XX_RBBM_CNTL 0x0000003b |
1165 | |
1166 | #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c |
1167 | |
1168 | #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 |
1169 | |
1170 | #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 |
1171 | |
1172 | #define REG_A2XX_MH_MMU_CONFIG 0x00000040 |
1173 | #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 |
1174 | #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 |
1175 | #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 |
1176 | #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 |
1177 | static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1178 | { |
1179 | return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; |
1180 | } |
1181 | #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 |
1182 | #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 |
1183 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1184 | { |
1185 | return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; |
1186 | } |
1187 | #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 |
1188 | #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 |
1189 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1190 | { |
1191 | return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; |
1192 | } |
1193 | #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 |
1194 | #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 |
1195 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1196 | { |
1197 | return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; |
1198 | } |
1199 | #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 |
1200 | #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 |
1201 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1202 | { |
1203 | return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; |
1204 | } |
1205 | #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 |
1206 | #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 |
1207 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1208 | { |
1209 | return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; |
1210 | } |
1211 | #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 |
1212 | #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 |
1213 | static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1214 | { |
1215 | return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; |
1216 | } |
1217 | #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 |
1218 | #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 |
1219 | static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1220 | { |
1221 | return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; |
1222 | } |
1223 | #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 |
1224 | #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 |
1225 | static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1226 | { |
1227 | return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; |
1228 | } |
1229 | #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 |
1230 | #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 |
1231 | static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1232 | { |
1233 | return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; |
1234 | } |
1235 | #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 |
1236 | #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 |
1237 | static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
1238 | { |
1239 | return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; |
1240 | } |
1241 | |
1242 | #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 |
1243 | #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff |
1244 | #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 |
1245 | static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) |
1246 | { |
1247 | return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; |
1248 | } |
1249 | #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 |
1250 | #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 |
1251 | static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) |
1252 | { |
1253 | return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; |
1254 | } |
1255 | |
1256 | #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 |
1257 | |
1258 | #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 |
1259 | |
1260 | #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 |
1261 | |
1262 | #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 |
1263 | #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 |
1264 | #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 |
1265 | |
1266 | #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 |
1267 | |
1268 | #define REG_A2XX_MH_MMU_MPU_END 0x00000047 |
1269 | |
1270 | #define REG_A2XX_NQWAIT_UNTIL 0x00000394 |
1271 | |
1272 | #define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395 |
1273 | |
1274 | #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396 |
1275 | |
1276 | #define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397 |
1277 | |
1278 | #define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398 |
1279 | |
1280 | #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399 |
1281 | |
1282 | #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a |
1283 | |
1284 | #define REG_A2XX_RBBM_DEBUG 0x0000039b |
1285 | |
1286 | #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c |
1287 | #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 |
1288 | #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 |
1289 | #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 |
1290 | #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 |
1291 | #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 |
1292 | #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 |
1293 | #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 |
1294 | #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 |
1295 | #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 |
1296 | #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 |
1297 | #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 |
1298 | #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 |
1299 | #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 |
1300 | #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 |
1301 | #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 |
1302 | #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 |
1303 | #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 |
1304 | #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 |
1305 | #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 |
1306 | #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 |
1307 | #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 |
1308 | #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 |
1309 | #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 |
1310 | #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 |
1311 | #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 |
1312 | #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 |
1313 | #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 |
1314 | #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 |
1315 | #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 |
1316 | #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 |
1317 | #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 |
1318 | #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 |
1319 | |
1320 | #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d |
1321 | #define A2XX_RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE 0x00000001 |
1322 | #define A2XX_RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE 0x00000002 |
1323 | #define A2XX_RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE 0x00000004 |
1324 | #define A2XX_RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE 0x00000008 |
1325 | #define A2XX_RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010 |
1326 | #define A2XX_RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE 0x00000020 |
1327 | #define A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040 |
1328 | #define A2XX_RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE 0x00000080 |
1329 | #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE 0x00000100 |
1330 | #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE 0x00000200 |
1331 | #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE 0x00000400 |
1332 | #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE 0x00000800 |
1333 | |
1334 | #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 |
1335 | |
1336 | #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 |
1337 | |
1338 | #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 |
1339 | |
1340 | #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 |
1341 | #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 |
1342 | #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 |
1343 | #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 |
1344 | |
1345 | #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 |
1346 | |
1347 | #define REG_A2XX_RBBM_INT_ACK 0x000003b6 |
1348 | |
1349 | #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 |
1350 | #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 |
1351 | #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 |
1352 | #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 |
1353 | #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 |
1354 | |
1355 | #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 |
1356 | |
1357 | #define REG_A2XX_RBBM_PERIPHID2 0x000003fa |
1358 | |
1359 | #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 |
1360 | #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK 0x00000007 |
1361 | #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT 0 |
1362 | static inline uint32_t A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val) |
1363 | { |
1364 | return ((val) << A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT) & A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK; |
1365 | } |
1366 | |
1367 | #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 |
1368 | |
1369 | #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 |
1370 | |
1371 | #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 |
1372 | |
1373 | #define REG_A2XX_RBBM_STATUS 0x000005d0 |
1374 | #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f |
1375 | #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 |
1376 | static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) |
1377 | { |
1378 | return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; |
1379 | } |
1380 | #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 |
1381 | #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 |
1382 | #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 |
1383 | #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 |
1384 | #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 |
1385 | #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 |
1386 | #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 |
1387 | #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 |
1388 | #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 |
1389 | #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 |
1390 | #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 |
1391 | #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 |
1392 | #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 |
1393 | #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 |
1394 | #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 |
1395 | #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 |
1396 | #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 |
1397 | #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 |
1398 | #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 |
1399 | |
1400 | #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 |
1401 | #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f |
1402 | #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 |
1403 | static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) |
1404 | { |
1405 | return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; |
1406 | } |
1407 | #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 |
1408 | #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 |
1409 | #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 |
1410 | #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 |
1411 | #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 |
1412 | #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 |
1413 | static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) |
1414 | { |
1415 | return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; |
1416 | } |
1417 | #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 |
1418 | #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 |
1419 | #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 |
1420 | #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 |
1421 | #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 |
1422 | static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) |
1423 | { |
1424 | return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; |
1425 | } |
1426 | #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 |
1427 | #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 |
1428 | #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 |
1429 | #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 |
1430 | #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 |
1431 | |
1432 | #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 |
1433 | #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 |
1434 | #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 |
1435 | #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 |
1436 | |
1437 | #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 |
1438 | |
1439 | #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 |
1440 | |
1441 | #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 |
1442 | |
1443 | #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 |
1444 | |
1445 | #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 |
1446 | #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f |
1447 | #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 |
1448 | static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) |
1449 | { |
1450 | assert(!(val & 0x1f)); |
1451 | return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; |
1452 | } |
1453 | #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 |
1454 | #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 |
1455 | static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) |
1456 | { |
1457 | assert(!(val & 0x1f)); |
1458 | return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; |
1459 | } |
1460 | |
1461 | #define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) |
1462 | |
1463 | static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
1464 | |
1465 | static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } |
1466 | |
1467 | static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } |
1468 | |
1469 | #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 |
1470 | |
1471 | #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 |
1472 | |
1473 | #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 |
1474 | |
1475 | #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 |
1476 | |
1477 | #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 |
1478 | |
1479 | #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 |
1480 | |
1481 | #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 |
1482 | |
1483 | #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 |
1484 | #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 |
1485 | #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 |
1486 | static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) |
1487 | { |
1488 | return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; |
1489 | } |
1490 | |
1491 | #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 |
1492 | #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 |
1493 | #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 |
1494 | #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 |
1495 | static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) |
1496 | { |
1497 | return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; |
1498 | } |
1499 | #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 |
1500 | #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 |
1501 | static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) |
1502 | { |
1503 | return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; |
1504 | } |
1505 | |
1506 | #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 |
1507 | |
1508 | #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 |
1509 | #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff |
1510 | #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 |
1511 | static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) |
1512 | { |
1513 | return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; |
1514 | } |
1515 | #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 |
1516 | #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 |
1517 | static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) |
1518 | { |
1519 | return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; |
1520 | } |
1521 | |
1522 | #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 |
1523 | |
1524 | #define REG_A2XX_SQ_INT_CNTL 0x00000d34 |
1525 | |
1526 | #define REG_A2XX_SQ_INT_STATUS 0x00000d35 |
1527 | |
1528 | #define REG_A2XX_SQ_INT_ACK 0x00000d36 |
1529 | |
1530 | #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae |
1531 | |
1532 | #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf |
1533 | |
1534 | #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 |
1535 | |
1536 | #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 |
1537 | |
1538 | #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 |
1539 | |
1540 | #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 |
1541 | |
1542 | #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 |
1543 | |
1544 | #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 |
1545 | |
1546 | #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 |
1547 | |
1548 | #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 |
1549 | |
1550 | #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 |
1551 | |
1552 | #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 |
1553 | |
1554 | #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba |
1555 | |
1556 | #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb |
1557 | |
1558 | #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc |
1559 | |
1560 | #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd |
1561 | |
1562 | #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe |
1563 | |
1564 | #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf |
1565 | |
1566 | #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 |
1567 | |
1568 | #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 |
1569 | |
1570 | #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 |
1571 | #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 |
1572 | |
1573 | #define REG_A2XX_TP0_CHICKEN 0x00000e1e |
1574 | |
1575 | #define REG_A2XX_RB_BC_CONTROL 0x00000f01 |
1576 | #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 |
1577 | #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 |
1578 | #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 |
1579 | static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) |
1580 | { |
1581 | return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; |
1582 | } |
1583 | #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 |
1584 | #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 |
1585 | #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 |
1586 | #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 |
1587 | #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 |
1588 | #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 |
1589 | #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 |
1590 | static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) |
1591 | { |
1592 | return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; |
1593 | } |
1594 | #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 |
1595 | #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 |
1596 | #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 |
1597 | #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 |
1598 | #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 |
1599 | #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 |
1600 | static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) |
1601 | { |
1602 | return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; |
1603 | } |
1604 | #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 |
1605 | #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 |
1606 | #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 |
1607 | static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) |
1608 | { |
1609 | return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; |
1610 | } |
1611 | #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 |
1612 | #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 |
1613 | static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) |
1614 | { |
1615 | return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; |
1616 | } |
1617 | #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 |
1618 | #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 |
1619 | #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 |
1620 | |
1621 | #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 |
1622 | |
1623 | #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 |
1624 | |
1625 | #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 |
1626 | |
1627 | #define REG_A2XX_RB_SURFACE_INFO 0x00002000 |
1628 | #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff |
1629 | #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 |
1630 | static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) |
1631 | { |
1632 | return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; |
1633 | } |
1634 | #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 |
1635 | #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 |
1636 | static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) |
1637 | { |
1638 | return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; |
1639 | } |
1640 | |
1641 | #define REG_A2XX_RB_COLOR_INFO 0x00002001 |
1642 | #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f |
1643 | #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 |
1644 | static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) |
1645 | { |
1646 | return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; |
1647 | } |
1648 | #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 |
1649 | #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 |
1650 | static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) |
1651 | { |
1652 | return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; |
1653 | } |
1654 | #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 |
1655 | #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 |
1656 | #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 |
1657 | static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) |
1658 | { |
1659 | return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; |
1660 | } |
1661 | #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 |
1662 | #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 |
1663 | static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) |
1664 | { |
1665 | return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; |
1666 | } |
1667 | #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 |
1668 | #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 |
1669 | static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) |
1670 | { |
1671 | assert(!(val & 0xfff)); |
1672 | return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; |
1673 | } |
1674 | |
1675 | #define REG_A2XX_RB_DEPTH_INFO 0x00002002 |
1676 | #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 |
1677 | #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 |
1678 | static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) |
1679 | { |
1680 | return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; |
1681 | } |
1682 | #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 |
1683 | #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 |
1684 | static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) |
1685 | { |
1686 | assert(!(val & 0xfff)); |
1687 | return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; |
1688 | } |
1689 | |
1690 | #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 |
1691 | |
1692 | #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 |
1693 | |
1694 | #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e |
1695 | #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
1696 | #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff |
1697 | #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 |
1698 | static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) |
1699 | { |
1700 | return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; |
1701 | } |
1702 | #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 |
1703 | #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 |
1704 | static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) |
1705 | { |
1706 | return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; |
1707 | } |
1708 | |
1709 | #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f |
1710 | #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
1711 | #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff |
1712 | #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 |
1713 | static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) |
1714 | { |
1715 | return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; |
1716 | } |
1717 | #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 |
1718 | #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 |
1719 | static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) |
1720 | { |
1721 | return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; |
1722 | } |
1723 | |
1724 | #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 |
1725 | #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff |
1726 | #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 |
1727 | static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) |
1728 | { |
1729 | return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; |
1730 | } |
1731 | #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 |
1732 | #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 |
1733 | static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) |
1734 | { |
1735 | return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; |
1736 | } |
1737 | #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 |
1738 | |
1739 | #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 |
1740 | #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
1741 | #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff |
1742 | #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 |
1743 | static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) |
1744 | { |
1745 | return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; |
1746 | } |
1747 | #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 |
1748 | #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 |
1749 | static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) |
1750 | { |
1751 | return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; |
1752 | } |
1753 | |
1754 | #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 |
1755 | #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
1756 | #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff |
1757 | #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 |
1758 | static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) |
1759 | { |
1760 | return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; |
1761 | } |
1762 | #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 |
1763 | #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 |
1764 | static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) |
1765 | { |
1766 | return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; |
1767 | } |
1768 | |
1769 | #define REG_A2XX_UNKNOWN_2010 0x00002010 |
1770 | |
1771 | #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 |
1772 | |
1773 | #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 |
1774 | |
1775 | #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 |
1776 | |
1777 | #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 |
1778 | |
1779 | #define REG_A2XX_RB_COLOR_MASK 0x00002104 |
1780 | #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 |
1781 | #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 |
1782 | #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 |
1783 | #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 |
1784 | |
1785 | #define REG_A2XX_RB_BLEND_RED 0x00002105 |
1786 | |
1787 | #define REG_A2XX_RB_BLEND_GREEN 0x00002106 |
1788 | |
1789 | #define REG_A2XX_RB_BLEND_BLUE 0x00002107 |
1790 | |
1791 | #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 |
1792 | |
1793 | #define REG_A2XX_RB_FOG_COLOR 0x00002109 |
1794 | #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff |
1795 | #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 |
1796 | static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) |
1797 | { |
1798 | return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; |
1799 | } |
1800 | #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 |
1801 | #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 |
1802 | static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) |
1803 | { |
1804 | return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; |
1805 | } |
1806 | #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 |
1807 | #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 |
1808 | static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) |
1809 | { |
1810 | return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; |
1811 | } |
1812 | |
1813 | #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c |
1814 | #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff |
1815 | #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 |
1816 | static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) |
1817 | { |
1818 | return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; |
1819 | } |
1820 | #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 |
1821 | #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 |
1822 | static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) |
1823 | { |
1824 | return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; |
1825 | } |
1826 | #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 |
1827 | #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 |
1828 | static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) |
1829 | { |
1830 | return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; |
1831 | } |
1832 | |
1833 | #define REG_A2XX_RB_STENCILREFMASK 0x0000210d |
1834 | #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff |
1835 | #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 |
1836 | static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) |
1837 | { |
1838 | return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; |
1839 | } |
1840 | #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 |
1841 | #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 |
1842 | static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) |
1843 | { |
1844 | return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; |
1845 | } |
1846 | #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 |
1847 | #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 |
1848 | static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) |
1849 | { |
1850 | return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; |
1851 | } |
1852 | |
1853 | #define REG_A2XX_RB_ALPHA_REF 0x0000210e |
1854 | |
1855 | #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f |
1856 | #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff |
1857 | #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 |
1858 | static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) |
1859 | { |
1860 | return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; |
1861 | } |
1862 | |
1863 | #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 |
1864 | #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff |
1865 | #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 |
1866 | static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) |
1867 | { |
1868 | return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; |
1869 | } |
1870 | |
1871 | #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 |
1872 | #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff |
1873 | #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 |
1874 | static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) |
1875 | { |
1876 | return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; |
1877 | } |
1878 | |
1879 | #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 |
1880 | #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff |
1881 | #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 |
1882 | static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) |
1883 | { |
1884 | return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; |
1885 | } |
1886 | |
1887 | #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 |
1888 | #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff |
1889 | #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 |
1890 | static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) |
1891 | { |
1892 | return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; |
1893 | } |
1894 | |
1895 | #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 |
1896 | #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff |
1897 | #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 |
1898 | static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) |
1899 | { |
1900 | return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; |
1901 | } |
1902 | |
1903 | #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 |
1904 | #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff |
1905 | #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 |
1906 | static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) |
1907 | { |
1908 | return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; |
1909 | } |
1910 | #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 |
1911 | #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 |
1912 | static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) |
1913 | { |
1914 | return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; |
1915 | } |
1916 | #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 |
1917 | #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 |
1918 | #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 |
1919 | #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 |
1920 | #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 |
1921 | #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 |
1922 | static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) |
1923 | { |
1924 | return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; |
1925 | } |
1926 | #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 |
1927 | #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 |
1928 | static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) |
1929 | { |
1930 | return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; |
1931 | } |
1932 | #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 |
1933 | #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 |
1934 | static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) |
1935 | { |
1936 | return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; |
1937 | } |
1938 | #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 |
1939 | |
1940 | #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 |
1941 | #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 |
1942 | #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 |
1943 | #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c |
1944 | #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 |
1945 | static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) |
1946 | { |
1947 | return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; |
1948 | } |
1949 | #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 |
1950 | #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 |
1951 | static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) |
1952 | { |
1953 | return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; |
1954 | } |
1955 | #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 |
1956 | #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 |
1957 | #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 |
1958 | |
1959 | #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 |
1960 | #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff |
1961 | #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 |
1962 | static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) |
1963 | { |
1964 | return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; |
1965 | } |
1966 | #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 |
1967 | #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 |
1968 | static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) |
1969 | { |
1970 | return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; |
1971 | } |
1972 | |
1973 | #define REG_A2XX_SQ_WRAPPING_0 0x00002183 |
1974 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f |
1975 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 |
1976 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) |
1977 | { |
1978 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; |
1979 | } |
1980 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 |
1981 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 |
1982 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) |
1983 | { |
1984 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; |
1985 | } |
1986 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 |
1987 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 |
1988 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) |
1989 | { |
1990 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; |
1991 | } |
1992 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 |
1993 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 |
1994 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) |
1995 | { |
1996 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; |
1997 | } |
1998 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 |
1999 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 |
2000 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) |
2001 | { |
2002 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; |
2003 | } |
2004 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 |
2005 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 |
2006 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) |
2007 | { |
2008 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; |
2009 | } |
2010 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 |
2011 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 |
2012 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) |
2013 | { |
2014 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; |
2015 | } |
2016 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 |
2017 | #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 |
2018 | static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) |
2019 | { |
2020 | return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; |
2021 | } |
2022 | |
2023 | #define REG_A2XX_SQ_WRAPPING_1 0x00002184 |
2024 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f |
2025 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 |
2026 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) |
2027 | { |
2028 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; |
2029 | } |
2030 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 |
2031 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 |
2032 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) |
2033 | { |
2034 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; |
2035 | } |
2036 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 |
2037 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 |
2038 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) |
2039 | { |
2040 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; |
2041 | } |
2042 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 |
2043 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 |
2044 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) |
2045 | { |
2046 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; |
2047 | } |
2048 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 |
2049 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 |
2050 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) |
2051 | { |
2052 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; |
2053 | } |
2054 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 |
2055 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 |
2056 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) |
2057 | { |
2058 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; |
2059 | } |
2060 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 |
2061 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 |
2062 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) |
2063 | { |
2064 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; |
2065 | } |
2066 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 |
2067 | #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 |
2068 | static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) |
2069 | { |
2070 | return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; |
2071 | } |
2072 | |
2073 | #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 |
2074 | #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff |
2075 | #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 |
2076 | static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) |
2077 | { |
2078 | return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; |
2079 | } |
2080 | #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 |
2081 | #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 |
2082 | static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) |
2083 | { |
2084 | return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; |
2085 | } |
2086 | |
2087 | #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 |
2088 | #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff |
2089 | #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 |
2090 | static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) |
2091 | { |
2092 | return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; |
2093 | } |
2094 | #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 |
2095 | #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 |
2096 | static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) |
2097 | { |
2098 | return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; |
2099 | } |
2100 | |
2101 | #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 |
2102 | |
2103 | #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc |
2104 | #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f |
2105 | #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 |
2106 | static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) |
2107 | { |
2108 | return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; |
2109 | } |
2110 | #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 |
2111 | #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 |
2112 | static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) |
2113 | { |
2114 | return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; |
2115 | } |
2116 | #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 |
2117 | #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 |
2118 | static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) |
2119 | { |
2120 | return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; |
2121 | } |
2122 | #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 |
2123 | #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 |
2124 | static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) |
2125 | { |
2126 | return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; |
2127 | } |
2128 | #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 |
2129 | #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 |
2130 | #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 |
2131 | #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 |
2132 | #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 |
2133 | static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) |
2134 | { |
2135 | return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; |
2136 | } |
2137 | |
2138 | #define REG_A2XX_VGT_IMMED_DATA 0x000021fd |
2139 | |
2140 | #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 |
2141 | #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 |
2142 | #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 |
2143 | #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 |
2144 | #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 |
2145 | #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 |
2146 | #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 |
2147 | static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) |
2148 | { |
2149 | return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; |
2150 | } |
2151 | #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 |
2152 | #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 |
2153 | #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 |
2154 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) |
2155 | { |
2156 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; |
2157 | } |
2158 | #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 |
2159 | #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 |
2160 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) |
2161 | { |
2162 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; |
2163 | } |
2164 | #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 |
2165 | #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 |
2166 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) |
2167 | { |
2168 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; |
2169 | } |
2170 | #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 |
2171 | #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 |
2172 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) |
2173 | { |
2174 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; |
2175 | } |
2176 | #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 |
2177 | #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 |
2178 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) |
2179 | { |
2180 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; |
2181 | } |
2182 | #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 |
2183 | #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 |
2184 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) |
2185 | { |
2186 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; |
2187 | } |
2188 | #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 |
2189 | #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 |
2190 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) |
2191 | { |
2192 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; |
2193 | } |
2194 | #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 |
2195 | #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 |
2196 | static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) |
2197 | { |
2198 | return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; |
2199 | } |
2200 | |
2201 | #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 |
2202 | #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f |
2203 | #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 |
2204 | static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) |
2205 | { |
2206 | return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; |
2207 | } |
2208 | #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 |
2209 | #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 |
2210 | static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) |
2211 | { |
2212 | return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; |
2213 | } |
2214 | #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 |
2215 | #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 |
2216 | static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) |
2217 | { |
2218 | return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; |
2219 | } |
2220 | #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 |
2221 | #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 |
2222 | static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) |
2223 | { |
2224 | return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; |
2225 | } |
2226 | #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 |
2227 | #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 |
2228 | static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) |
2229 | { |
2230 | return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; |
2231 | } |
2232 | #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 |
2233 | #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 |
2234 | static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) |
2235 | { |
2236 | return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; |
2237 | } |
2238 | #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 |
2239 | #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 |
2240 | |
2241 | #define REG_A2XX_RB_COLORCONTROL 0x00002202 |
2242 | #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 |
2243 | #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 |
2244 | static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) |
2245 | { |
2246 | return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; |
2247 | } |
2248 | #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 |
2249 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 |
2250 | #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 |
2251 | #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 |
2252 | #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 |
2253 | #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 |
2254 | #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 |
2255 | static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) |
2256 | { |
2257 | return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; |
2258 | } |
2259 | #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 |
2260 | #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 |
2261 | static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) |
2262 | { |
2263 | return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; |
2264 | } |
2265 | #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 |
2266 | #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 |
2267 | static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) |
2268 | { |
2269 | return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; |
2270 | } |
2271 | #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 |
2272 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 |
2273 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 |
2274 | static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) |
2275 | { |
2276 | return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; |
2277 | } |
2278 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 |
2279 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 |
2280 | static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) |
2281 | { |
2282 | return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; |
2283 | } |
2284 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 |
2285 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 |
2286 | static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) |
2287 | { |
2288 | return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; |
2289 | } |
2290 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 |
2291 | #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 |
2292 | static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) |
2293 | { |
2294 | return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; |
2295 | } |
2296 | |
2297 | #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 |
2298 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 |
2299 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 |
2300 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) |
2301 | { |
2302 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; |
2303 | } |
2304 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 |
2305 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 |
2306 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) |
2307 | { |
2308 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; |
2309 | } |
2310 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 |
2311 | #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 |
2312 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) |
2313 | { |
2314 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; |
2315 | } |
2316 | |
2317 | #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 |
2318 | #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 |
2319 | #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 |
2320 | #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 |
2321 | #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 |
2322 | static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) |
2323 | { |
2324 | return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; |
2325 | } |
2326 | #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 |
2327 | #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 |
2328 | #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 |
2329 | #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 |
2330 | #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 |
2331 | |
2332 | #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 |
2333 | #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 |
2334 | #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 |
2335 | #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 |
2336 | #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 |
2337 | #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 |
2338 | static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) |
2339 | { |
2340 | return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; |
2341 | } |
2342 | #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 |
2343 | #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 |
2344 | static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) |
2345 | { |
2346 | return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; |
2347 | } |
2348 | #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 |
2349 | #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 |
2350 | static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) |
2351 | { |
2352 | return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; |
2353 | } |
2354 | #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 |
2355 | #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 |
2356 | #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 |
2357 | #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 |
2358 | #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 |
2359 | #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 |
2360 | #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 |
2361 | #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 |
2362 | #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 |
2363 | #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 |
2364 | #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 |
2365 | #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 |
2366 | #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 |
2367 | #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 |
2368 | #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 |
2369 | #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 |
2370 | |
2371 | #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 |
2372 | #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 |
2373 | #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 |
2374 | #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 |
2375 | #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 |
2376 | #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 |
2377 | #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 |
2378 | #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 |
2379 | #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 |
2380 | #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 |
2381 | #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 |
2382 | |
2383 | #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 |
2384 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 |
2385 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 |
2386 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) |
2387 | { |
2388 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; |
2389 | } |
2390 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 |
2391 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 |
2392 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) |
2393 | { |
2394 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; |
2395 | } |
2396 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 |
2397 | #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 |
2398 | static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) |
2399 | { |
2400 | return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; |
2401 | } |
2402 | |
2403 | #define REG_A2XX_RB_MODECONTROL 0x00002208 |
2404 | #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 |
2405 | #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 |
2406 | static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) |
2407 | { |
2408 | return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; |
2409 | } |
2410 | |
2411 | #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 |
2412 | |
2413 | #define REG_A2XX_RB_SAMPLE_POS 0x0000220a |
2414 | |
2415 | #define REG_A2XX_CLEAR_COLOR 0x0000220b |
2416 | #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff |
2417 | #define A2XX_CLEAR_COLOR_RED__SHIFT 0 |
2418 | static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) |
2419 | { |
2420 | return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; |
2421 | } |
2422 | #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 |
2423 | #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 |
2424 | static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) |
2425 | { |
2426 | return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; |
2427 | } |
2428 | #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 |
2429 | #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 |
2430 | static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) |
2431 | { |
2432 | return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; |
2433 | } |
2434 | #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 |
2435 | #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 |
2436 | static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) |
2437 | { |
2438 | return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; |
2439 | } |
2440 | |
2441 | #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 |
2442 | |
2443 | #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 |
2444 | #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff |
2445 | #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 |
2446 | static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) |
2447 | { |
2448 | return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; |
2449 | } |
2450 | #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 |
2451 | #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 |
2452 | static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) |
2453 | { |
2454 | return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; |
2455 | } |
2456 | |
2457 | #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 |
2458 | #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff |
2459 | #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 |
2460 | static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) |
2461 | { |
2462 | return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; |
2463 | } |
2464 | #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 |
2465 | #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 |
2466 | static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) |
2467 | { |
2468 | return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; |
2469 | } |
2470 | |
2471 | #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 |
2472 | #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff |
2473 | #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 |
2474 | static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) |
2475 | { |
2476 | return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; |
2477 | } |
2478 | |
2479 | #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 |
2480 | #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff |
2481 | #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 |
2482 | static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) |
2483 | { |
2484 | return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; |
2485 | } |
2486 | #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 |
2487 | #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 |
2488 | static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) |
2489 | { |
2490 | return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; |
2491 | } |
2492 | #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 |
2493 | #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 |
2494 | static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) |
2495 | { |
2496 | return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; |
2497 | } |
2498 | #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 |
2499 | #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 |
2500 | static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) |
2501 | { |
2502 | return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; |
2503 | } |
2504 | |
2505 | #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 |
2506 | #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 |
2507 | #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e |
2508 | #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 |
2509 | static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) |
2510 | { |
2511 | return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; |
2512 | } |
2513 | #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 |
2514 | |
2515 | #define REG_A2XX_VGT_ENHANCE 0x00002294 |
2516 | |
2517 | #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 |
2518 | #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff |
2519 | #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 |
2520 | static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) |
2521 | { |
2522 | return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; |
2523 | } |
2524 | #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 |
2525 | #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 |
2526 | #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 |
2527 | |
2528 | #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 |
2529 | #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 |
2530 | #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 |
2531 | static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) |
2532 | { |
2533 | return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; |
2534 | } |
2535 | #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 |
2536 | #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 |
2537 | static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) |
2538 | { |
2539 | return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; |
2540 | } |
2541 | |
2542 | #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 |
2543 | #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 |
2544 | #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 |
2545 | static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) |
2546 | { |
2547 | return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; |
2548 | } |
2549 | #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 |
2550 | #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 |
2551 | static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) |
2552 | { |
2553 | return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; |
2554 | } |
2555 | #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 |
2556 | #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 |
2557 | static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) |
2558 | { |
2559 | return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; |
2560 | } |
2561 | |
2562 | #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 |
2563 | #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff |
2564 | #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 |
2565 | static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) |
2566 | { |
2567 | return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; |
2568 | } |
2569 | |
2570 | #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 |
2571 | #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff |
2572 | #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 |
2573 | static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) |
2574 | { |
2575 | return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; |
2576 | } |
2577 | |
2578 | #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 |
2579 | #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff |
2580 | #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 |
2581 | static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) |
2582 | { |
2583 | return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; |
2584 | } |
2585 | |
2586 | #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 |
2587 | #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff |
2588 | #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 |
2589 | static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) |
2590 | { |
2591 | return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; |
2592 | } |
2593 | |
2594 | #define REG_A2XX_SQ_VS_CONST 0x00002307 |
2595 | #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff |
2596 | #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 |
2597 | static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) |
2598 | { |
2599 | return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; |
2600 | } |
2601 | #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 |
2602 | #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 |
2603 | static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) |
2604 | { |
2605 | return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; |
2606 | } |
2607 | |
2608 | #define REG_A2XX_SQ_PS_CONST 0x00002308 |
2609 | #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff |
2610 | #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 |
2611 | static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) |
2612 | { |
2613 | return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; |
2614 | } |
2615 | #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 |
2616 | #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 |
2617 | static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) |
2618 | { |
2619 | return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; |
2620 | } |
2621 | |
2622 | #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 |
2623 | |
2624 | #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a |
2625 | |
2626 | #define REG_A2XX_PA_SC_AA_MASK 0x00002312 |
2627 | |
2628 | #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 |
2629 | #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 |
2630 | #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 |
2631 | static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) |
2632 | { |
2633 | return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; |
2634 | } |
2635 | |
2636 | #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 |
2637 | #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 |
2638 | #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 |
2639 | static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) |
2640 | { |
2641 | return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; |
2642 | } |
2643 | |
2644 | #define REG_A2XX_RB_COPY_CONTROL 0x00002318 |
2645 | #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 |
2646 | #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 |
2647 | static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) |
2648 | { |
2649 | return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; |
2650 | } |
2651 | #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 |
2652 | #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 |
2653 | #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 |
2654 | static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) |
2655 | { |
2656 | return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; |
2657 | } |
2658 | |
2659 | #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 |
2660 | |
2661 | #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a |
2662 | #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff |
2663 | #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 |
2664 | static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) |
2665 | { |
2666 | assert(!(val & 0x1f)); |
2667 | return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; |
2668 | } |
2669 | |
2670 | #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b |
2671 | #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 |
2672 | #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 |
2673 | static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) |
2674 | { |
2675 | return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; |
2676 | } |
2677 | #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 |
2678 | #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 |
2679 | #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 |
2680 | static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) |
2681 | { |
2682 | return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; |
2683 | } |
2684 | #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 |
2685 | #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 |
2686 | static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) |
2687 | { |
2688 | return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; |
2689 | } |
2690 | #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 |
2691 | #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 |
2692 | static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) |
2693 | { |
2694 | return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; |
2695 | } |
2696 | #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 |
2697 | #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 |
2698 | static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) |
2699 | { |
2700 | return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; |
2701 | } |
2702 | #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 |
2703 | #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 |
2704 | #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 |
2705 | #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 |
2706 | |
2707 | #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c |
2708 | #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff |
2709 | #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 |
2710 | static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) |
2711 | { |
2712 | return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; |
2713 | } |
2714 | #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 |
2715 | #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 |
2716 | static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) |
2717 | { |
2718 | return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; |
2719 | } |
2720 | |
2721 | #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d |
2722 | |
2723 | #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 |
2724 | |
2725 | #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 |
2726 | |
2727 | #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 |
2728 | |
2729 | #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 |
2730 | |
2731 | #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 |
2732 | |
2733 | #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 |
2734 | |
2735 | #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381 |
2736 | |
2737 | #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382 |
2738 | |
2739 | #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 |
2740 | |
2741 | #define REG_A2XX_SQ_CONSTANT_0 0x00004000 |
2742 | |
2743 | #define REG_A2XX_SQ_FETCH_0 0x00004800 |
2744 | |
2745 | #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 |
2746 | |
2747 | #define REG_A2XX_SQ_CF_LOOP 0x00004908 |
2748 | |
2749 | #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 |
2750 | |
2751 | #define REG_A2XX_COHER_BASE_PM4 0x00000a2a |
2752 | |
2753 | #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b |
2754 | |
2755 | #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 |
2756 | |
2757 | #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 |
2758 | |
2759 | #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a |
2760 | |
2761 | #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b |
2762 | |
2763 | #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c |
2764 | |
2765 | #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d |
2766 | |
2767 | #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e |
2768 | |
2769 | #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f |
2770 | |
2771 | #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 |
2772 | |
2773 | #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 |
2774 | |
2775 | #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 |
2776 | |
2777 | #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 |
2778 | |
2779 | #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 |
2780 | |
2781 | #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 |
2782 | |
2783 | #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a |
2784 | |
2785 | #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 |
2786 | |
2787 | #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 |
2788 | |
2789 | #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a |
2790 | |
2791 | #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b |
2792 | |
2793 | #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c |
2794 | |
2795 | #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e |
2796 | |
2797 | #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 |
2798 | |
2799 | #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 |
2800 | |
2801 | #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d |
2802 | |
2803 | #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f |
2804 | |
2805 | #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 |
2806 | |
2807 | #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 |
2808 | |
2809 | #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 |
2810 | |
2811 | #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 |
2812 | |
2813 | #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 |
2814 | |
2815 | #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 |
2816 | |
2817 | #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 |
2818 | |
2819 | #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a |
2820 | |
2821 | #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f |
2822 | |
2823 | #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 |
2824 | |
2825 | #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 |
2826 | |
2827 | #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 |
2828 | |
2829 | #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 |
2830 | |
2831 | #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 |
2832 | |
2833 | #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 |
2834 | |
2835 | #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 |
2836 | |
2837 | #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 |
2838 | |
2839 | #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 |
2840 | |
2841 | #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 |
2842 | |
2843 | #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 |
2844 | |
2845 | #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a |
2846 | |
2847 | #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d |
2848 | |
2849 | #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 |
2850 | |
2851 | #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 |
2852 | |
2853 | #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 |
2854 | |
2855 | #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 |
2856 | |
2857 | #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c |
2858 | |
2859 | #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f |
2860 | |
2861 | #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 |
2862 | |
2863 | #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 |
2864 | |
2865 | #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 |
2866 | |
2867 | #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b |
2868 | |
2869 | #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b |
2870 | |
2871 | #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e |
2872 | |
2873 | #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 |
2874 | |
2875 | #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 |
2876 | |
2877 | #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 |
2878 | |
2879 | #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a |
2880 | |
2881 | #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d |
2882 | |
2883 | #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 |
2884 | |
2885 | #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 |
2886 | |
2887 | #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 |
2888 | |
2889 | #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 |
2890 | |
2891 | #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c |
2892 | |
2893 | #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c |
2894 | |
2895 | #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f |
2896 | |
2897 | #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 |
2898 | |
2899 | #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 |
2900 | |
2901 | #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 |
2902 | |
2903 | #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b |
2904 | |
2905 | #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e |
2906 | |
2907 | #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 |
2908 | |
2909 | #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 |
2910 | |
2911 | #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 |
2912 | |
2913 | #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a |
2914 | |
2915 | #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d |
2916 | |
2917 | #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 |
2918 | |
2919 | #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 |
2920 | |
2921 | #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca |
2922 | |
2923 | #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb |
2924 | |
2925 | #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc |
2926 | |
2927 | #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd |
2928 | |
2929 | #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce |
2930 | |
2931 | #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf |
2932 | |
2933 | #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 |
2934 | |
2935 | #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 |
2936 | |
2937 | #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 |
2938 | |
2939 | #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 |
2940 | |
2941 | #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 |
2942 | |
2943 | #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 |
2944 | |
2945 | #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 |
2946 | |
2947 | #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 |
2948 | |
2949 | #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a |
2950 | |
2951 | #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 |
2952 | |
2953 | #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b |
2954 | |
2955 | #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 |
2956 | |
2957 | #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c |
2958 | |
2959 | #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 |
2960 | |
2961 | #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d |
2962 | |
2963 | #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 |
2964 | |
2965 | #define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05 |
2966 | |
2967 | #define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06 |
2968 | |
2969 | #define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07 |
2970 | |
2971 | #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 |
2972 | |
2973 | #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 |
2974 | |
2975 | #define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a |
2976 | |
2977 | #define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b |
2978 | |
2979 | #define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c |
2980 | |
2981 | #define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d |
2982 | |
2983 | #define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e |
2984 | |
2985 | #define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f |
2986 | |
2987 | #define REG_A2XX_SQ_TEX_0 0x00000000 |
2988 | #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 |
2989 | #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 |
2990 | static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) |
2991 | { |
2992 | return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; |
2993 | } |
2994 | #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c |
2995 | #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 |
2996 | static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) |
2997 | { |
2998 | return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; |
2999 | } |
3000 | #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 |
3001 | #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 |
3002 | static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) |
3003 | { |
3004 | return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; |
3005 | } |
3006 | #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 |
3007 | #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 |
3008 | static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) |
3009 | { |
3010 | return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; |
3011 | } |
3012 | #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 |
3013 | #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 |
3014 | static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) |
3015 | { |
3016 | return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; |
3017 | } |
3018 | #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 |
3019 | #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 |
3020 | static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) |
3021 | { |
3022 | return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; |
3023 | } |
3024 | #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 |
3025 | #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 |
3026 | static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) |
3027 | { |
3028 | return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; |
3029 | } |
3030 | #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 |
3031 | #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 |
3032 | static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) |
3033 | { |
3034 | return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; |
3035 | } |
3036 | #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 |
3037 | #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 |
3038 | static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) |
3039 | { |
3040 | assert(!(val & 0x1f)); |
3041 | return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; |
3042 | } |
3043 | #define A2XX_SQ_TEX_0_TILED 0x80000000 |
3044 | |
3045 | #define REG_A2XX_SQ_TEX_1 0x00000001 |
3046 | #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f |
3047 | #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 |
3048 | static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) |
3049 | { |
3050 | return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; |
3051 | } |
3052 | #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 |
3053 | #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 |
3054 | static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) |
3055 | { |
3056 | return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; |
3057 | } |
3058 | #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 |
3059 | #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 |
3060 | static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) |
3061 | { |
3062 | return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; |
3063 | } |
3064 | #define A2XX_SQ_TEX_1_STACKED 0x00000400 |
3065 | #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 |
3066 | #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 |
3067 | static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) |
3068 | { |
3069 | return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; |
3070 | } |
3071 | #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 |
3072 | #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 |
3073 | static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) |
3074 | { |
3075 | assert(!(val & 0xfff)); |
3076 | return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; |
3077 | } |
3078 | |
3079 | #define REG_A2XX_SQ_TEX_2 0x00000002 |
3080 | #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff |
3081 | #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 |
3082 | static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) |
3083 | { |
3084 | return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; |
3085 | } |
3086 | #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 |
3087 | #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 |
3088 | static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) |
3089 | { |
3090 | return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; |
3091 | } |
3092 | #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 |
3093 | #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 |
3094 | static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) |
3095 | { |
3096 | return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; |
3097 | } |
3098 | |
3099 | #define REG_A2XX_SQ_TEX_3 0x00000003 |
3100 | #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 |
3101 | #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 |
3102 | static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) |
3103 | { |
3104 | return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; |
3105 | } |
3106 | #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e |
3107 | #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 |
3108 | static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) |
3109 | { |
3110 | return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; |
3111 | } |
3112 | #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 |
3113 | #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 |
3114 | static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) |
3115 | { |
3116 | return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; |
3117 | } |
3118 | #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 |
3119 | #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 |
3120 | static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) |
3121 | { |
3122 | return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; |
3123 | } |
3124 | #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 |
3125 | #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 |
3126 | static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) |
3127 | { |
3128 | return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; |
3129 | } |
3130 | #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 |
3131 | #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 |
3132 | static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) |
3133 | { |
3134 | return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; |
3135 | } |
3136 | #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 |
3137 | #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 |
3138 | static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) |
3139 | { |
3140 | return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; |
3141 | } |
3142 | #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 |
3143 | #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 |
3144 | static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) |
3145 | { |
3146 | return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; |
3147 | } |
3148 | #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 |
3149 | #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 |
3150 | static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) |
3151 | { |
3152 | return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; |
3153 | } |
3154 | #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 |
3155 | #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 |
3156 | static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) |
3157 | { |
3158 | return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; |
3159 | } |
3160 | #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 |
3161 | #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 |
3162 | static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) |
3163 | { |
3164 | return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; |
3165 | } |
3166 | |
3167 | #define REG_A2XX_SQ_TEX_4 0x00000004 |
3168 | #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 |
3169 | #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 |
3170 | static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) |
3171 | { |
3172 | return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; |
3173 | } |
3174 | #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 |
3175 | #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 |
3176 | static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) |
3177 | { |
3178 | return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; |
3179 | } |
3180 | #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c |
3181 | #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 |
3182 | static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) |
3183 | { |
3184 | return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; |
3185 | } |
3186 | #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 |
3187 | #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 |
3188 | static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) |
3189 | { |
3190 | return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; |
3191 | } |
3192 | #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 |
3193 | #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 |
3194 | #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 |
3195 | #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 |
3196 | static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) |
3197 | { |
3198 | return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; |
3199 | } |
3200 | #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 |
3201 | #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 |
3202 | static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) |
3203 | { |
3204 | return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; |
3205 | } |
3206 | #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 |
3207 | #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 |
3208 | static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) |
3209 | { |
3210 | return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; |
3211 | } |
3212 | |
3213 | #define REG_A2XX_SQ_TEX_5 0x00000005 |
3214 | #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 |
3215 | #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 |
3216 | static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) |
3217 | { |
3218 | return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; |
3219 | } |
3220 | #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 |
3221 | #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 |
3222 | #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 |
3223 | static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) |
3224 | { |
3225 | return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; |
3226 | } |
3227 | #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 |
3228 | #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 |
3229 | static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) |
3230 | { |
3231 | return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; |
3232 | } |
3233 | #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 |
3234 | #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 |
3235 | static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) |
3236 | { |
3237 | return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; |
3238 | } |
3239 | #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 |
3240 | #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 |
3241 | #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 |
3242 | static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) |
3243 | { |
3244 | assert(!(val & 0xfff)); |
3245 | return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; |
3246 | } |
3247 | |
3248 | #ifdef __cplusplus |
3249 | #endif |
3250 | |
3251 | #endif /* A2XX_XML */ |
3252 | |