1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2016 Maxime Ripard |
4 | * |
5 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
6 | */ |
7 | |
8 | #ifndef _SUN4I_HDMI_H_ |
9 | #define _SUN4I_HDMI_H_ |
10 | |
11 | #include <drm/drm_connector.h> |
12 | #include <drm/drm_encoder.h> |
13 | #include <linux/regmap.h> |
14 | |
15 | #include <media/cec-pin.h> |
16 | |
17 | #define SUN4I_HDMI_CTRL_REG 0x004 |
18 | #define SUN4I_HDMI_CTRL_ENABLE BIT(31) |
19 | |
20 | #define SUN4I_HDMI_IRQ_REG 0x008 |
21 | #define SUN4I_HDMI_IRQ_STA_MASK 0x73 |
22 | #define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) |
23 | #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) |
24 | |
25 | #define SUN4I_HDMI_HPD_REG 0x00c |
26 | #define SUN4I_HDMI_HPD_HIGH BIT(0) |
27 | |
28 | #define SUN4I_HDMI_VID_CTRL_REG 0x010 |
29 | #define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) |
30 | #define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) |
31 | |
32 | #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 |
33 | #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 |
34 | #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c |
35 | #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 |
36 | |
37 | #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0))) |
38 | #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16) |
39 | |
40 | #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 |
41 | #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16) |
42 | #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) |
43 | #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) |
44 | |
45 | #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n)) |
46 | |
47 | #define SUN4I_HDMI_PAD_CTRL0_REG 0x200 |
48 | #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) |
49 | #define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30) |
50 | #define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29) |
51 | #define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) |
52 | #define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) |
53 | #define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) |
54 | #define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) |
55 | #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) |
56 | |
57 | #define SUN4I_HDMI_PAD_CTRL1_REG 0x204 |
58 | #define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */ |
59 | #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) |
60 | #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) |
61 | #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) |
62 | #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) |
63 | #define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18) |
64 | #define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17) |
65 | #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) |
66 | #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) |
67 | #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10) |
68 | #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) |
69 | #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3) |
70 | |
71 | /* These bits seem to invert the TMDS data channels */ |
72 | #define SUN4I_HDMI_PAD_CTRL1_INVERT_R BIT(2) |
73 | #define SUN4I_HDMI_PAD_CTRL1_INVERT_G BIT(1) |
74 | #define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0) |
75 | |
76 | #define SUN4I_HDMI_PLL_CTRL_REG 0x208 |
77 | #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) |
78 | #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) |
79 | #define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29) |
80 | #define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28) |
81 | #define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27) |
82 | #define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25) |
83 | #define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20) |
84 | #define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17) |
85 | #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12) |
86 | #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8) |
87 | #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4) |
88 | #define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4) |
89 | #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf) |
90 | |
91 | #define SUN4I_HDMI_PLL_DBG0_REG 0x20c |
92 | #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21) |
93 | #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) |
94 | #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 |
95 | |
96 | #define SUN4I_HDMI_CEC 0x214 |
97 | #define SUN4I_HDMI_CEC_ENABLE BIT(11) |
98 | #define SUN4I_HDMI_CEC_TX BIT(9) |
99 | #define SUN4I_HDMI_CEC_RX BIT(8) |
100 | |
101 | #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) |
102 | #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) |
103 | |
104 | #define SUN4I_HDMI_UNKNOWN_REG 0x300 |
105 | #define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) |
106 | |
107 | #define SUN4I_HDMI_DDC_CTRL_REG 0x500 |
108 | #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) |
109 | #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) |
110 | #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) |
111 | #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8) |
112 | #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) |
113 | #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) |
114 | |
115 | #define SUN4I_HDMI_DDC_ADDR_REG 0x504 |
116 | #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) |
117 | #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) |
118 | #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) |
119 | #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) |
120 | |
121 | #define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c |
122 | #define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) |
123 | #define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) |
124 | #define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) |
125 | #define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) |
126 | #define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) |
127 | #define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) |
128 | #define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) |
129 | #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) |
130 | |
131 | #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 |
132 | #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) |
133 | #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4) |
134 | #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4) |
135 | #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) |
136 | #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf) |
137 | #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0) |
138 | #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) |
139 | |
140 | #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 |
141 | |
142 | #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c |
143 | #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) |
144 | |
145 | #define SUN4I_HDMI_DDC_CMD_REG 0x520 |
146 | #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 |
147 | #define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 |
148 | #define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 |
149 | |
150 | #define SUN4I_HDMI_DDC_CLK_REG 0x528 |
151 | #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3) |
152 | #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7) |
153 | |
154 | #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540 |
155 | #define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) |
156 | #define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) |
157 | |
158 | #define SUN4I_HDMI_DDC_FIFO_SIZE 16 |
159 | |
160 | /* A31 specific */ |
161 | #define SUN6I_HDMI_DDC_CTRL_REG 0x500 |
162 | #define SUN6I_HDMI_DDC_CTRL_RESET BIT(31) |
163 | #define SUN6I_HDMI_DDC_CTRL_START_CMD BIT(27) |
164 | #define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6) |
165 | #define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4) |
166 | #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0) |
167 | |
168 | #define SUN6I_HDMI_DDC_CMD_REG 0x508 |
169 | #define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count) ((count) << 16) |
170 | /* command types in lower 3 bits are the same as sun4i */ |
171 | |
172 | #define SUN6I_HDMI_DDC_ADDR_REG 0x50c |
173 | #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) |
174 | #define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) |
175 | #define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) |
176 | #define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1) |
177 | |
178 | #define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514 |
179 | #define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT BIT(8) |
180 | /* lower 8 bits are the same as sun4i */ |
181 | |
182 | #define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518 |
183 | #define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15) |
184 | /* lower 9 bits are the same as sun4i */ |
185 | |
186 | #define SUN6I_HDMI_DDC_CLK_REG 0x520 |
187 | /* DDC CLK bit fields are the same, but the formula is not */ |
188 | |
189 | #define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580 |
190 | |
191 | enum sun4i_hdmi_pkt_type { |
192 | SUN4I_HDMI_PKT_AVI = 2, |
193 | SUN4I_HDMI_PKT_END = 15, |
194 | }; |
195 | |
196 | struct sun4i_hdmi_variant { |
197 | bool has_ddc_parent_clk; |
198 | bool has_reset_control; |
199 | |
200 | u32 pad_ctrl0_init_val; |
201 | u32 pad_ctrl1_init_val; |
202 | u32 pll_ctrl_init_val; |
203 | |
204 | struct reg_field ddc_clk_reg; |
205 | u8 ddc_clk_pre_divider; |
206 | u8 ddc_clk_m_offset; |
207 | |
208 | u8 tmds_clk_div_offset; |
209 | |
210 | /* Register fields for I2C adapter */ |
211 | struct reg_field field_ddc_en; |
212 | struct reg_field field_ddc_start; |
213 | struct reg_field field_ddc_reset; |
214 | struct reg_field field_ddc_addr_reg; |
215 | struct reg_field field_ddc_slave_addr; |
216 | struct reg_field field_ddc_int_mask; |
217 | struct reg_field field_ddc_int_status; |
218 | struct reg_field field_ddc_fifo_clear; |
219 | struct reg_field field_ddc_fifo_rx_thres; |
220 | struct reg_field field_ddc_fifo_tx_thres; |
221 | struct reg_field field_ddc_byte_count; |
222 | struct reg_field field_ddc_cmd; |
223 | struct reg_field field_ddc_sda_en; |
224 | struct reg_field field_ddc_sck_en; |
225 | |
226 | /* DDC FIFO register offset */ |
227 | u32 ddc_fifo_reg; |
228 | |
229 | /* |
230 | * DDC FIFO threshold boundary conditions |
231 | * |
232 | * This is used to cope with the threshold boundary condition |
233 | * being slightly different on sun5i and sun6i. |
234 | * |
235 | * On sun5i the threshold is exclusive, i.e. does not include, |
236 | * the value of the threshold. ( > for RX; < for TX ) |
237 | * On sun6i the threshold is inclusive, i.e. includes, the |
238 | * value of the threshold. ( >= for RX; <= for TX ) |
239 | */ |
240 | bool ddc_fifo_thres_incl; |
241 | |
242 | bool ddc_fifo_has_dir; |
243 | }; |
244 | |
245 | struct sun4i_hdmi { |
246 | struct drm_connector connector; |
247 | struct drm_encoder encoder; |
248 | struct device *dev; |
249 | |
250 | void __iomem *base; |
251 | struct regmap *regmap; |
252 | |
253 | /* Reset control */ |
254 | struct reset_control *reset; |
255 | |
256 | /* Parent clocks */ |
257 | struct clk *bus_clk; |
258 | struct clk *mod_clk; |
259 | struct clk *ddc_parent_clk; |
260 | struct clk *pll0_clk; |
261 | struct clk *pll1_clk; |
262 | |
263 | /* And the clocks we create */ |
264 | struct clk *ddc_clk; |
265 | struct clk *tmds_clk; |
266 | |
267 | struct i2c_adapter *i2c; |
268 | struct i2c_adapter *ddc_i2c; |
269 | |
270 | /* Regmap fields for I2C adapter */ |
271 | struct regmap_field *field_ddc_en; |
272 | struct regmap_field *field_ddc_start; |
273 | struct regmap_field *field_ddc_reset; |
274 | struct regmap_field *field_ddc_addr_reg; |
275 | struct regmap_field *field_ddc_slave_addr; |
276 | struct regmap_field *field_ddc_int_mask; |
277 | struct regmap_field *field_ddc_int_status; |
278 | struct regmap_field *field_ddc_fifo_clear; |
279 | struct regmap_field *field_ddc_fifo_rx_thres; |
280 | struct regmap_field *field_ddc_fifo_tx_thres; |
281 | struct regmap_field *field_ddc_byte_count; |
282 | struct regmap_field *field_ddc_cmd; |
283 | struct regmap_field *field_ddc_sda_en; |
284 | struct regmap_field *field_ddc_sck_en; |
285 | |
286 | struct sun4i_drv *drv; |
287 | |
288 | struct cec_adapter *cec_adap; |
289 | |
290 | const struct sun4i_hdmi_variant *variant; |
291 | }; |
292 | |
293 | int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); |
294 | int sun4i_tmds_create(struct sun4i_hdmi *hdmi); |
295 | int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); |
296 | |
297 | #endif /* _SUN4I_HDMI_H_ */ |
298 | |