1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2012-2015, NVIDIA Corporation.
4 */
5
6#ifndef HOST1X_DEV_H
7#define HOST1X_DEV_H
8
9#include <linux/device.h>
10#include <linux/iommu.h>
11#include <linux/iova.h>
12#include <linux/platform_device.h>
13#include <linux/reset.h>
14
15#include "cdma.h"
16#include "channel.h"
17#include "context.h"
18#include "intr.h"
19#include "job.h"
20#include "syncpt.h"
21
22struct host1x_syncpt;
23struct host1x_syncpt_base;
24struct host1x_channel;
25struct host1x_cdma;
26struct host1x_job;
27struct push_buffer;
28struct output;
29struct dentry;
30
31struct host1x_channel_ops {
32 int (*init)(struct host1x_channel *channel, struct host1x *host,
33 unsigned int id);
34 int (*submit)(struct host1x_job *job);
35};
36
37struct host1x_cdma_ops {
38 void (*start)(struct host1x_cdma *cdma);
39 void (*stop)(struct host1x_cdma *cdma);
40 void (*flush)(struct host1x_cdma *cdma);
41 int (*timeout_init)(struct host1x_cdma *cdma);
42 void (*timeout_destroy)(struct host1x_cdma *cdma);
43 void (*freeze)(struct host1x_cdma *cdma);
44 void (*resume)(struct host1x_cdma *cdma, u32 getptr);
45 void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr,
46 u32 syncpt_incrs, u32 syncval, u32 nr_slots);
47};
48
49struct host1x_pushbuffer_ops {
50 void (*init)(struct push_buffer *pb);
51};
52
53struct host1x_debug_ops {
54 void (*debug_init)(struct dentry *de);
55 void (*show_channel_cdma)(struct host1x *host,
56 struct host1x_channel *ch,
57 struct output *o);
58 void (*show_channel_fifo)(struct host1x *host,
59 struct host1x_channel *ch,
60 struct output *o);
61 void (*show_mlocks)(struct host1x *host, struct output *output);
62
63};
64
65struct host1x_syncpt_ops {
66 void (*restore)(struct host1x_syncpt *syncpt);
67 void (*restore_wait_base)(struct host1x_syncpt *syncpt);
68 void (*load_wait_base)(struct host1x_syncpt *syncpt);
69 u32 (*load)(struct host1x_syncpt *syncpt);
70 int (*cpu_incr)(struct host1x_syncpt *syncpt);
71 void (*assign_to_channel)(struct host1x_syncpt *syncpt,
72 struct host1x_channel *channel);
73 void (*enable_protection)(struct host1x *host);
74};
75
76struct host1x_intr_ops {
77 int (*init_host_sync)(struct host1x *host, u32 cpm);
78 void (*set_syncpt_threshold)(
79 struct host1x *host, unsigned int id, u32 thresh);
80 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
81 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
82 void (*disable_all_syncpt_intrs)(struct host1x *host);
83 int (*free_syncpt_irq)(struct host1x *host);
84};
85
86struct host1x_sid_entry {
87 unsigned int base;
88 unsigned int offset;
89 unsigned int limit;
90};
91
92struct host1x_table_desc {
93 unsigned int base;
94 unsigned int count;
95};
96
97struct host1x_info {
98 unsigned int nb_channels; /* host1x: number of channels supported */
99 unsigned int nb_pts; /* host1x: number of syncpoints supported */
100 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
101 unsigned int nb_mlocks; /* host1x: number of mlocks supported */
102 int (*init)(struct host1x *host1x); /* initialize per SoC ops */
103 unsigned int sync_offset; /* offset of syncpoint registers */
104 u64 dma_mask; /* mask of addressable memory */
105 bool has_wide_gather; /* supports GATHER_W opcode */
106 bool has_hypervisor; /* has hypervisor registers */
107 bool has_common; /* has common registers separate from hypervisor */
108 unsigned int num_sid_entries;
109 const struct host1x_sid_entry *sid_table;
110 struct host1x_table_desc streamid_vm_table;
111 struct host1x_table_desc classid_vm_table;
112 struct host1x_table_desc mmio_vm_table;
113 /*
114 * On T20-T148, the boot chain may setup DC to increment syncpoints
115 * 26/27 on VBLANK. As such we cannot use these syncpoints until
116 * the display driver disables VBLANK increments.
117 */
118 bool reserve_vblank_syncpts;
119};
120
121struct host1x {
122 const struct host1x_info *info;
123
124 void __iomem *regs;
125 void __iomem *hv_regs; /* hypervisor region */
126 void __iomem *common_regs;
127 int syncpt_irqs[8];
128 int num_syncpt_irqs;
129 struct host1x_syncpt *syncpt;
130 struct host1x_syncpt_base *bases;
131 struct device *dev;
132 struct clk *clk;
133 struct reset_control_bulk_data resets[2];
134 unsigned int nresets;
135
136 struct iommu_group *group;
137 struct iommu_domain *domain;
138 struct iova_domain iova;
139 dma_addr_t iova_end;
140
141 struct mutex intr_mutex;
142
143 const struct host1x_syncpt_ops *syncpt_op;
144 const struct host1x_intr_ops *intr_op;
145 const struct host1x_channel_ops *channel_op;
146 const struct host1x_cdma_ops *cdma_op;
147 const struct host1x_pushbuffer_ops *cdma_pb_op;
148 const struct host1x_debug_ops *debug_op;
149
150 struct host1x_syncpt *nop_sp;
151
152 struct mutex syncpt_mutex;
153
154 struct host1x_channel_list channel_list;
155 struct host1x_memory_context_list context_list;
156
157 struct dentry *debugfs;
158
159 struct mutex devices_lock;
160 struct list_head devices;
161
162 struct list_head list;
163
164 struct device_dma_parameters dma_parms;
165
166 struct host1x_bo_cache cache;
167};
168
169void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
170void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
171u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
172void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
173u32 host1x_sync_readl(struct host1x *host1x, u32 r);
174void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v);
175u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);
176
177static inline void host1x_hw_syncpt_restore(struct host1x *host,
178 struct host1x_syncpt *sp)
179{
180 host->syncpt_op->restore(sp);
181}
182
183static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host,
184 struct host1x_syncpt *sp)
185{
186 host->syncpt_op->restore_wait_base(sp);
187}
188
189static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host,
190 struct host1x_syncpt *sp)
191{
192 host->syncpt_op->load_wait_base(sp);
193}
194
195static inline u32 host1x_hw_syncpt_load(struct host1x *host,
196 struct host1x_syncpt *sp)
197{
198 return host->syncpt_op->load(sp);
199}
200
201static inline int host1x_hw_syncpt_cpu_incr(struct host1x *host,
202 struct host1x_syncpt *sp)
203{
204 return host->syncpt_op->cpu_incr(sp);
205}
206
207static inline void host1x_hw_syncpt_assign_to_channel(
208 struct host1x *host, struct host1x_syncpt *sp,
209 struct host1x_channel *ch)
210{
211 return host->syncpt_op->assign_to_channel(sp, ch);
212}
213
214static inline void host1x_hw_syncpt_enable_protection(struct host1x *host)
215{
216 return host->syncpt_op->enable_protection(host);
217}
218
219static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm)
220{
221 return host->intr_op->init_host_sync(host, cpm);
222}
223
224static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host,
225 unsigned int id,
226 u32 thresh)
227{
228 host->intr_op->set_syncpt_threshold(host, id, thresh);
229}
230
231static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host,
232 unsigned int id)
233{
234 host->intr_op->enable_syncpt_intr(host, id);
235}
236
237static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host,
238 unsigned int id)
239{
240 host->intr_op->disable_syncpt_intr(host, id);
241}
242
243static inline void host1x_hw_intr_disable_all_syncpt_intrs(struct host1x *host)
244{
245 host->intr_op->disable_all_syncpt_intrs(host);
246}
247
248static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host)
249{
250 return host->intr_op->free_syncpt_irq(host);
251}
252
253static inline int host1x_hw_channel_init(struct host1x *host,
254 struct host1x_channel *channel,
255 unsigned int id)
256{
257 return host->channel_op->init(channel, host, id);
258}
259
260static inline int host1x_hw_channel_submit(struct host1x *host,
261 struct host1x_job *job)
262{
263 return host->channel_op->submit(job);
264}
265
266static inline void host1x_hw_cdma_start(struct host1x *host,
267 struct host1x_cdma *cdma)
268{
269 host->cdma_op->start(cdma);
270}
271
272static inline void host1x_hw_cdma_stop(struct host1x *host,
273 struct host1x_cdma *cdma)
274{
275 host->cdma_op->stop(cdma);
276}
277
278static inline void host1x_hw_cdma_flush(struct host1x *host,
279 struct host1x_cdma *cdma)
280{
281 host->cdma_op->flush(cdma);
282}
283
284static inline int host1x_hw_cdma_timeout_init(struct host1x *host,
285 struct host1x_cdma *cdma)
286{
287 return host->cdma_op->timeout_init(cdma);
288}
289
290static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host,
291 struct host1x_cdma *cdma)
292{
293 host->cdma_op->timeout_destroy(cdma);
294}
295
296static inline void host1x_hw_cdma_freeze(struct host1x *host,
297 struct host1x_cdma *cdma)
298{
299 host->cdma_op->freeze(cdma);
300}
301
302static inline void host1x_hw_cdma_resume(struct host1x *host,
303 struct host1x_cdma *cdma, u32 getptr)
304{
305 host->cdma_op->resume(cdma, getptr);
306}
307
308static inline void host1x_hw_cdma_timeout_cpu_incr(struct host1x *host,
309 struct host1x_cdma *cdma,
310 u32 getptr,
311 u32 syncpt_incrs,
312 u32 syncval, u32 nr_slots)
313{
314 host->cdma_op->timeout_cpu_incr(cdma, getptr, syncpt_incrs, syncval,
315 nr_slots);
316}
317
318static inline void host1x_hw_pushbuffer_init(struct host1x *host,
319 struct push_buffer *pb)
320{
321 host->cdma_pb_op->init(pb);
322}
323
324static inline void host1x_hw_debug_init(struct host1x *host, struct dentry *de)
325{
326 if (host->debug_op && host->debug_op->debug_init)
327 host->debug_op->debug_init(de);
328}
329
330static inline void host1x_hw_show_channel_cdma(struct host1x *host,
331 struct host1x_channel *channel,
332 struct output *o)
333{
334 host->debug_op->show_channel_cdma(host, channel, o);
335}
336
337static inline void host1x_hw_show_channel_fifo(struct host1x *host,
338 struct host1x_channel *channel,
339 struct output *o)
340{
341 host->debug_op->show_channel_fifo(host, channel, o);
342}
343
344static inline void host1x_hw_show_mlocks(struct host1x *host, struct output *o)
345{
346 host->debug_op->show_mlocks(host, o);
347}
348
349extern struct platform_driver tegra_mipi_driver;
350
351#endif
352

source code of linux/drivers/gpu/host1x/dev.h