1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8#include <linux/interrupt.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/sysfs.h>
15#include <linux/spi/spi.h>
16#include <linux/regulator/consumer.h>
17#include <linux/err.h>
18#include <linux/sched.h>
19#include <linux/delay.h>
20#include <linux/of.h>
21
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/buffer.h>
25#include <linux/iio/trigger.h>
26#include <linux/iio/trigger_consumer.h>
27#include <linux/iio/triggered_buffer.h>
28#include <linux/iio/adc/ad_sigma_delta.h>
29
30/* Registers */
31#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
33#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
34#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
35#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
36#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
37#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
38#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
39 /* (AD7792)/24-bit (AD7192)) */
40#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
41 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
42
43/* Communications Register Bit Designations (AD7192_REG_COMM) */
44#define AD7192_COMM_WEN BIT(7) /* Write Enable */
45#define AD7192_COMM_WRITE 0 /* Write Operation */
46#define AD7192_COMM_READ BIT(6) /* Read Operation */
47#define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */
48#define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
49
50/* Status Register Bit Designations (AD7192_REG_STAT) */
51#define AD7192_STAT_RDY BIT(7) /* Ready */
52#define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
53#define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
54#define AD7192_STAT_PARITY BIT(4) /* Parity */
55#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
56#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
58
59/* Mode Register Bit Designations (AD7192_REG_MODE) */
60#define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */
61#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
62#define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */
63#define AD7192_MODE_AVG_MASK GENMASK(17, 16)
64 /* Fast Settling Filter Average Select Mask (AD7193 only) */
65#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
66#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 /* Filter Update Rate Select Mask */
71#define AD7192_MODE_RATE_MASK GENMASK(9, 0)
72
73/* Mode Register: AD7192_MODE_SEL options */
74#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
75#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
76#define AD7192_MODE_IDLE 2 /* Idle Mode */
77#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
78#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
79#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
80#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
81#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
82
83/* Mode Register: AD7192_MODE_CLKSRC options */
84#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
85 /* from MCLK1 to MCLK2 */
86#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
87#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
88 /* available at the MCLK2 pin */
89#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
90 /* at the MCLK2 pin */
91
92/* Configuration Register Bit Designations (AD7192_REG_CONF) */
93
94#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
95#define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
96#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
97#define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */
98#define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
99#define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
100#define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
101#define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
102#define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */
103
104#define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
105#define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
106#define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
107#define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
108#define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
109#define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
110#define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
111#define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
112
113#define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
114#define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
115#define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
116#define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
117#define AD7193_CH_TEMP 0x100 /* Temp senseor */
118#define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
119#define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
120#define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
121#define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
122#define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
123#define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
124#define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
125#define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
126#define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
127#define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
128
129/* ID Register Bit Designations (AD7192_REG_ID) */
130#define CHIPID_AD7190 0x4
131#define CHIPID_AD7192 0x0
132#define CHIPID_AD7193 0x2
133#define CHIPID_AD7195 0x6
134#define AD7192_ID_MASK GENMASK(3, 0)
135
136/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
137#define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
138#define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
139#define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
140#define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
141#define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
142#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
143#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
144
145#define AD7192_EXT_FREQ_MHZ_MIN 2457600
146#define AD7192_EXT_FREQ_MHZ_MAX 5120000
147#define AD7192_INT_FREQ_MHZ 4915200
148
149#define AD7192_NO_SYNC_FILTER 1
150#define AD7192_SYNC3_FILTER 3
151#define AD7192_SYNC4_FILTER 4
152
153/* NOTE:
154 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
155 * In order to avoid contentions on the SPI bus, it's therefore necessary
156 * to use spi bus locking.
157 *
158 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
159 */
160
161enum {
162 AD7192_SYSCALIB_ZERO_SCALE,
163 AD7192_SYSCALIB_FULL_SCALE,
164};
165
166enum {
167 ID_AD7190,
168 ID_AD7192,
169 ID_AD7193,
170 ID_AD7195,
171};
172
173struct ad7192_chip_info {
174 unsigned int chip_id;
175 const char *name;
176 const struct iio_chan_spec *channels;
177 u8 num_channels;
178 const struct iio_info *info;
179};
180
181struct ad7192_state {
182 const struct ad7192_chip_info *chip_info;
183 struct regulator *avdd;
184 struct regulator *vref;
185 struct clk *mclk;
186 u16 int_vref_mv;
187 u32 fclk;
188 u32 mode;
189 u32 conf;
190 u32 scale_avail[8][2];
191 u32 oversampling_ratio_avail[4];
192 u8 gpocon;
193 u8 clock_sel;
194 struct mutex lock; /* protect sensor state */
195 u8 syscalib_mode[8];
196
197 struct ad_sigma_delta sd;
198};
199
200static const char * const ad7192_syscalib_modes[] = {
201 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
202 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
203};
204
205static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
206 const struct iio_chan_spec *chan,
207 unsigned int mode)
208{
209 struct ad7192_state *st = iio_priv(indio_dev);
210
211 st->syscalib_mode[chan->channel] = mode;
212
213 return 0;
214}
215
216static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
217 const struct iio_chan_spec *chan)
218{
219 struct ad7192_state *st = iio_priv(indio_dev);
220
221 return st->syscalib_mode[chan->channel];
222}
223
224static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
225 uintptr_t private,
226 const struct iio_chan_spec *chan,
227 const char *buf, size_t len)
228{
229 struct ad7192_state *st = iio_priv(indio_dev);
230 bool sys_calib;
231 int ret, temp;
232
233 ret = kstrtobool(s: buf, res: &sys_calib);
234 if (ret)
235 return ret;
236
237 temp = st->syscalib_mode[chan->channel];
238 if (sys_calib) {
239 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
240 ret = ad_sd_calibrate(sigma_delta: &st->sd, AD7192_MODE_CAL_SYS_ZERO,
241 channel: chan->address);
242 else
243 ret = ad_sd_calibrate(sigma_delta: &st->sd, AD7192_MODE_CAL_SYS_FULL,
244 channel: chan->address);
245 }
246
247 return ret ? ret : len;
248}
249
250static const struct iio_enum ad7192_syscalib_mode_enum = {
251 .items = ad7192_syscalib_modes,
252 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
253 .set = ad7192_set_syscalib_mode,
254 .get = ad7192_get_syscalib_mode
255};
256
257static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
258 {
259 .name = "sys_calibration",
260 .write = ad7192_write_syscalib,
261 .shared = IIO_SEPARATE,
262 },
263 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
264 &ad7192_syscalib_mode_enum),
265 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
266 &ad7192_syscalib_mode_enum),
267 {}
268};
269
270static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
271{
272 return container_of(sd, struct ad7192_state, sd);
273}
274
275static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
276{
277 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
278
279 st->conf &= ~AD7192_CONF_CHAN_MASK;
280 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);
281
282 return ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: st->conf);
283}
284
285static int ad7192_set_mode(struct ad_sigma_delta *sd,
286 enum ad_sigma_delta_mode mode)
287{
288 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
289
290 st->mode &= ~AD7192_MODE_SEL_MASK;
291 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);
292
293 return ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE, size: 3, val: st->mode);
294}
295
296static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
297{
298 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
299 unsigned int mode = st->mode;
300 int ret;
301
302 mode &= ~AD7192_MODE_STA_MASK;
303 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);
304
305 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE, size: 3, val: mode);
306 if (ret < 0)
307 return ret;
308
309 st->mode = mode;
310
311 return 0;
312}
313
314static int ad7192_disable_all(struct ad_sigma_delta *sd)
315{
316 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
317 u32 conf = st->conf;
318 int ret;
319
320 conf &= ~AD7192_CONF_CHAN_MASK;
321
322 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: conf);
323 if (ret < 0)
324 return ret;
325
326 st->conf = conf;
327
328 return 0;
329}
330
331static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
332 .set_channel = ad7192_set_channel,
333 .append_status = ad7192_append_status,
334 .disable_all = ad7192_disable_all,
335 .set_mode = ad7192_set_mode,
336 .has_registers = true,
337 .addr_shift = 3,
338 .read_mask = BIT(6),
339 .status_ch_mask = GENMASK(3, 0),
340 .num_slots = 4,
341 .irq_flags = IRQF_TRIGGER_FALLING,
342};
343
344static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
345 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
346 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
347 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
348 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
349 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
350 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
351 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
352 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
353};
354
355static int ad7192_calibrate_all(struct ad7192_state *st)
356{
357 return ad_sd_calibrate_all(sigma_delta: &st->sd, cd: ad7192_calib_arr,
358 ARRAY_SIZE(ad7192_calib_arr));
359}
360
361static inline bool ad7192_valid_external_frequency(u32 freq)
362{
363 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
364 freq <= AD7192_EXT_FREQ_MHZ_MAX);
365}
366
367static int ad7192_of_clock_select(struct ad7192_state *st)
368{
369 struct device_node *np = st->sd.spi->dev.of_node;
370 unsigned int clock_sel;
371
372 clock_sel = AD7192_CLK_INT;
373
374 /* use internal clock */
375 if (!st->mclk) {
376 if (of_property_read_bool(np, propname: "adi,int-clock-output-enable"))
377 clock_sel = AD7192_CLK_INT_CO;
378 } else {
379 if (of_property_read_bool(np, propname: "adi,clock-xtal"))
380 clock_sel = AD7192_CLK_EXT_MCLK1_2;
381 else
382 clock_sel = AD7192_CLK_EXT_MCLK2;
383 }
384
385 return clock_sel;
386}
387
388static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np)
389{
390 struct ad7192_state *st = iio_priv(indio_dev);
391 bool rej60_en, refin2_en;
392 bool buf_en, bipolar, burnout_curr_en;
393 unsigned long long scale_uv;
394 int i, ret, id;
395
396 /* reset the serial interface */
397 ret = ad_sd_reset(sigma_delta: &st->sd, reset_length: 48);
398 if (ret < 0)
399 return ret;
400 usleep_range(min: 500, max: 1000); /* Wait for at least 500us */
401
402 /* write/read test for device presence */
403 ret = ad_sd_read_reg(sigma_delta: &st->sd, AD7192_REG_ID, size: 1, val: &id);
404 if (ret)
405 return ret;
406
407 id = FIELD_GET(AD7192_ID_MASK, id);
408
409 if (id != st->chip_info->chip_id)
410 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n",
411 id, st->chip_info->chip_id);
412
413 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |
414 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |
415 FIELD_PREP(AD7192_MODE_RATE_MASK, 480);
416
417 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);
418
419 rej60_en = of_property_read_bool(np, propname: "adi,rejection-60-Hz-enable");
420 if (rej60_en)
421 st->mode |= AD7192_MODE_REJ60;
422
423 refin2_en = of_property_read_bool(np, propname: "adi,refin2-pins-enable");
424 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
425 st->conf |= AD7192_CONF_REFSEL;
426
427 st->conf &= ~AD7192_CONF_CHOP;
428
429 buf_en = of_property_read_bool(np, propname: "adi,buffer-enable");
430 if (buf_en)
431 st->conf |= AD7192_CONF_BUF;
432
433 bipolar = of_property_read_bool(np, propname: "bipolar");
434 if (!bipolar)
435 st->conf |= AD7192_CONF_UNIPOLAR;
436
437 burnout_curr_en = of_property_read_bool(np,
438 propname: "adi,burnout-currents-enable");
439 if (burnout_curr_en && buf_en) {
440 st->conf |= AD7192_CONF_BURN;
441 } else if (burnout_curr_en) {
442 dev_warn(&st->sd.spi->dev,
443 "Can't enable burnout currents: see CHOP or buffer\n");
444 }
445
446 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE, size: 3, val: st->mode);
447 if (ret)
448 return ret;
449
450 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: st->conf);
451 if (ret)
452 return ret;
453
454 ret = ad7192_calibrate_all(st);
455 if (ret)
456 return ret;
457
458 /* Populate available ADC input ranges */
459 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
460 scale_uv = ((u64)st->int_vref_mv * 100000000)
461 >> (indio_dev->channels[0].scan_type.realbits -
462 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));
463 scale_uv >>= i;
464
465 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
466 st->scale_avail[i][0] = scale_uv;
467 }
468
469 st->oversampling_ratio_avail[0] = 1;
470 st->oversampling_ratio_avail[1] = 2;
471 st->oversampling_ratio_avail[2] = 8;
472 st->oversampling_ratio_avail[3] = 16;
473
474 return 0;
475}
476
477static ssize_t ad7192_show_ac_excitation(struct device *dev,
478 struct device_attribute *attr,
479 char *buf)
480{
481 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
482 struct ad7192_state *st = iio_priv(indio_dev);
483
484 return sysfs_emit(buf, fmt: "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));
485}
486
487static ssize_t ad7192_show_bridge_switch(struct device *dev,
488 struct device_attribute *attr,
489 char *buf)
490{
491 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
492 struct ad7192_state *st = iio_priv(indio_dev);
493
494 return sysfs_emit(buf, fmt: "%ld\n",
495 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));
496}
497
498static ssize_t ad7192_set(struct device *dev,
499 struct device_attribute *attr,
500 const char *buf,
501 size_t len)
502{
503 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
504 struct ad7192_state *st = iio_priv(indio_dev);
505 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
506 int ret;
507 bool val;
508
509 ret = kstrtobool(s: buf, res: &val);
510 if (ret < 0)
511 return ret;
512
513 ret = iio_device_claim_direct_mode(indio_dev);
514 if (ret)
515 return ret;
516
517 switch ((u32)this_attr->address) {
518 case AD7192_REG_GPOCON:
519 if (val)
520 st->gpocon |= AD7192_GPOCON_BPDSW;
521 else
522 st->gpocon &= ~AD7192_GPOCON_BPDSW;
523
524 ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_GPOCON, size: 1, val: st->gpocon);
525 break;
526 case AD7192_REG_CONF:
527 if (val)
528 st->conf |= AD7192_CONF_ACX;
529 else
530 st->conf &= ~AD7192_CONF_ACX;
531
532 ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: st->conf);
533 break;
534 default:
535 ret = -EINVAL;
536 }
537
538 iio_device_release_direct_mode(indio_dev);
539
540 return ret ? ret : len;
541}
542
543static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)
544{
545 u8 avg_factor_selected, oversampling_ratio;
546
547 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);
548
549 if (!avg_factor_selected && !chop_en)
550 return 1;
551
552 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];
553
554 if (sinc3_en)
555 return AD7192_SYNC3_FILTER + oversampling_ratio - 1;
556
557 return AD7192_SYNC4_FILTER + oversampling_ratio - 1;
558}
559
560static int ad7192_get_f_order(struct ad7192_state *st)
561{
562 bool sinc3_en, chop_en;
563
564 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);
565 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);
566
567 return ad7192_compute_f_order(st, sinc3_en, chop_en);
568}
569
570static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,
571 bool chop_en)
572{
573 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);
574
575 return DIV_ROUND_CLOSEST(st->fclk,
576 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
577}
578
579static int ad7192_get_f_adc(struct ad7192_state *st)
580{
581 unsigned int f_order = ad7192_get_f_order(st);
582
583 return DIV_ROUND_CLOSEST(st->fclk,
584 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
585}
586
587static void ad7192_get_available_filter_freq(struct ad7192_state *st,
588 int *freq)
589{
590 unsigned int fadc;
591
592 /* Formulas for filter at page 25 of the datasheet */
593 fadc = ad7192_compute_f_adc(st, sinc3_en: false, chop_en: true);
594 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
595
596 fadc = ad7192_compute_f_adc(st, sinc3_en: true, chop_en: true);
597 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
598
599 fadc = ad7192_compute_f_adc(st, sinc3_en: false, chop_en: false);
600 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
601
602 fadc = ad7192_compute_f_adc(st, sinc3_en: true, chop_en: false);
603 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
604}
605
606static ssize_t ad7192_show_filter_avail(struct device *dev,
607 struct device_attribute *attr,
608 char *buf)
609{
610 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
611 struct ad7192_state *st = iio_priv(indio_dev);
612 unsigned int freq_avail[4], i;
613 size_t len = 0;
614
615 ad7192_get_available_filter_freq(st, freq: freq_avail);
616
617 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
618 len += sysfs_emit_at(buf, at: len, fmt: "%d.%03d ", freq_avail[i] / 1000,
619 freq_avail[i] % 1000);
620
621 buf[len - 1] = '\n';
622
623 return len;
624}
625
626static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
627 0444, ad7192_show_filter_avail, NULL, 0);
628
629static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
630 ad7192_show_bridge_switch, ad7192_set,
631 AD7192_REG_GPOCON);
632
633static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
634 ad7192_show_ac_excitation, ad7192_set,
635 AD7192_REG_CONF);
636
637static struct attribute *ad7192_attributes[] = {
638 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
639 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
640 NULL
641};
642
643static const struct attribute_group ad7192_attribute_group = {
644 .attrs = ad7192_attributes,
645};
646
647static struct attribute *ad7195_attributes[] = {
648 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
649 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
650 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
651 NULL
652};
653
654static const struct attribute_group ad7195_attribute_group = {
655 .attrs = ad7195_attributes,
656};
657
658static unsigned int ad7192_get_temp_scale(bool unipolar)
659{
660 return unipolar ? 2815 * 2 : 2815;
661}
662
663static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
664 int val, int val2)
665{
666 int freq_avail[4], i, ret, freq;
667 unsigned int diff_new, diff_old;
668 int idx = 0;
669
670 diff_old = U32_MAX;
671 freq = val * 1000 + val2;
672
673 ad7192_get_available_filter_freq(st, freq: freq_avail);
674
675 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
676 diff_new = abs(freq - freq_avail[i]);
677 if (diff_new < diff_old) {
678 diff_old = diff_new;
679 idx = i;
680 }
681 }
682
683 switch (idx) {
684 case 0:
685 st->mode &= ~AD7192_MODE_SINC3;
686
687 st->conf |= AD7192_CONF_CHOP;
688 break;
689 case 1:
690 st->mode |= AD7192_MODE_SINC3;
691
692 st->conf |= AD7192_CONF_CHOP;
693 break;
694 case 2:
695 st->mode &= ~AD7192_MODE_SINC3;
696
697 st->conf &= ~AD7192_CONF_CHOP;
698 break;
699 case 3:
700 st->mode |= AD7192_MODE_SINC3;
701
702 st->conf &= ~AD7192_CONF_CHOP;
703 break;
704 }
705
706 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE, size: 3, val: st->mode);
707 if (ret < 0)
708 return ret;
709
710 return ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: st->conf);
711}
712
713static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
714{
715 unsigned int fadc;
716
717 fadc = ad7192_get_f_adc(st);
718
719 if (FIELD_GET(AD7192_CONF_CHOP, st->conf))
720 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
721 if (FIELD_GET(AD7192_MODE_SINC3, st->mode))
722 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
723 else
724 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
725}
726
727static int ad7192_read_raw(struct iio_dev *indio_dev,
728 struct iio_chan_spec const *chan,
729 int *val,
730 int *val2,
731 long m)
732{
733 struct ad7192_state *st = iio_priv(indio_dev);
734 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);
735 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);
736
737 switch (m) {
738 case IIO_CHAN_INFO_RAW:
739 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
740 case IIO_CHAN_INFO_SCALE:
741 switch (chan->type) {
742 case IIO_VOLTAGE:
743 mutex_lock(&st->lock);
744 *val = st->scale_avail[gain][0];
745 *val2 = st->scale_avail[gain][1];
746 mutex_unlock(lock: &st->lock);
747 return IIO_VAL_INT_PLUS_NANO;
748 case IIO_TEMP:
749 *val = 0;
750 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
751 return IIO_VAL_INT_PLUS_NANO;
752 default:
753 return -EINVAL;
754 }
755 case IIO_CHAN_INFO_OFFSET:
756 if (!unipolar)
757 *val = -(1 << (chan->scan_type.realbits - 1));
758 else
759 *val = 0;
760 /* Kelvin to Celsius */
761 if (chan->type == IIO_TEMP)
762 *val -= 273 * ad7192_get_temp_scale(unipolar);
763 return IIO_VAL_INT;
764 case IIO_CHAN_INFO_SAMP_FREQ:
765 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);
766 return IIO_VAL_INT;
767 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
768 *val = ad7192_get_3db_filter_freq(st);
769 *val2 = 1000;
770 return IIO_VAL_FRACTIONAL;
771 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
772 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];
773 return IIO_VAL_INT;
774 }
775
776 return -EINVAL;
777}
778
779static int ad7192_write_raw(struct iio_dev *indio_dev,
780 struct iio_chan_spec const *chan,
781 int val,
782 int val2,
783 long mask)
784{
785 struct ad7192_state *st = iio_priv(indio_dev);
786 int ret, i, div;
787 unsigned int tmp;
788
789 ret = iio_device_claim_direct_mode(indio_dev);
790 if (ret)
791 return ret;
792
793 switch (mask) {
794 case IIO_CHAN_INFO_SCALE:
795 ret = -EINVAL;
796 mutex_lock(&st->lock);
797 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
798 if (val2 == st->scale_avail[i][1]) {
799 ret = 0;
800 tmp = st->conf;
801 st->conf &= ~AD7192_CONF_GAIN_MASK;
802 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);
803 if (tmp == st->conf)
804 break;
805 ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF,
806 size: 3, val: st->conf);
807 ad7192_calibrate_all(st);
808 break;
809 }
810 mutex_unlock(lock: &st->lock);
811 break;
812 case IIO_CHAN_INFO_SAMP_FREQ:
813 if (!val) {
814 ret = -EINVAL;
815 break;
816 }
817
818 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
819 if (div < 1 || div > 1023) {
820 ret = -EINVAL;
821 break;
822 }
823
824 st->mode &= ~AD7192_MODE_RATE_MASK;
825 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);
826 ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE, size: 3, val: st->mode);
827 break;
828 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
829 ret = ad7192_set_3db_filter_freq(st, val, val2: val2 / 1000);
830 break;
831 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
832 ret = -EINVAL;
833 mutex_lock(&st->lock);
834 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)
835 if (val == st->oversampling_ratio_avail[i]) {
836 ret = 0;
837 tmp = st->mode;
838 st->mode &= ~AD7192_MODE_AVG_MASK;
839 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);
840 if (tmp == st->mode)
841 break;
842 ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_MODE,
843 size: 3, val: st->mode);
844 break;
845 }
846 mutex_unlock(lock: &st->lock);
847 break;
848 default:
849 ret = -EINVAL;
850 }
851
852 iio_device_release_direct_mode(indio_dev);
853
854 return ret;
855}
856
857static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
858 struct iio_chan_spec const *chan,
859 long mask)
860{
861 switch (mask) {
862 case IIO_CHAN_INFO_SCALE:
863 return IIO_VAL_INT_PLUS_NANO;
864 case IIO_CHAN_INFO_SAMP_FREQ:
865 return IIO_VAL_INT;
866 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
867 return IIO_VAL_INT_PLUS_MICRO;
868 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
869 return IIO_VAL_INT;
870 default:
871 return -EINVAL;
872 }
873}
874
875static int ad7192_read_avail(struct iio_dev *indio_dev,
876 struct iio_chan_spec const *chan,
877 const int **vals, int *type, int *length,
878 long mask)
879{
880 struct ad7192_state *st = iio_priv(indio_dev);
881
882 switch (mask) {
883 case IIO_CHAN_INFO_SCALE:
884 *vals = (int *)st->scale_avail;
885 *type = IIO_VAL_INT_PLUS_NANO;
886 /* Values are stored in a 2D matrix */
887 *length = ARRAY_SIZE(st->scale_avail) * 2;
888
889 return IIO_AVAIL_LIST;
890 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
891 *vals = (int *)st->oversampling_ratio_avail;
892 *type = IIO_VAL_INT;
893 *length = ARRAY_SIZE(st->oversampling_ratio_avail);
894
895 return IIO_AVAIL_LIST;
896 }
897
898 return -EINVAL;
899}
900
901static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
902{
903 struct ad7192_state *st = iio_priv(indio_dev);
904 u32 conf = st->conf;
905 int ret;
906 int i;
907
908 conf &= ~AD7192_CONF_CHAN_MASK;
909 for_each_set_bit(i, scan_mask, 8)
910 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, i);
911
912 ret = ad_sd_write_reg(sigma_delta: &st->sd, AD7192_REG_CONF, size: 3, val: conf);
913 if (ret < 0)
914 return ret;
915
916 st->conf = conf;
917
918 return 0;
919}
920
921static const struct iio_info ad7192_info = {
922 .read_raw = ad7192_read_raw,
923 .write_raw = ad7192_write_raw,
924 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
925 .read_avail = ad7192_read_avail,
926 .attrs = &ad7192_attribute_group,
927 .validate_trigger = ad_sd_validate_trigger,
928 .update_scan_mode = ad7192_update_scan_mode,
929};
930
931static const struct iio_info ad7195_info = {
932 .read_raw = ad7192_read_raw,
933 .write_raw = ad7192_write_raw,
934 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
935 .read_avail = ad7192_read_avail,
936 .attrs = &ad7195_attribute_group,
937 .validate_trigger = ad_sd_validate_trigger,
938 .update_scan_mode = ad7192_update_scan_mode,
939};
940
941#define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \
942 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \
943 { \
944 .type = (_type), \
945 .differential = ((_channel2) == -1 ? 0 : 1), \
946 .indexed = 1, \
947 .channel = (_channel1), \
948 .channel2 = (_channel2), \
949 .address = (_address), \
950 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
951 BIT(IIO_CHAN_INFO_OFFSET), \
952 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
953 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
954 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
955 (_mask_all), \
956 .info_mask_shared_by_type_available = (_mask_type_av), \
957 .info_mask_shared_by_all_available = (_mask_all_av), \
958 .ext_info = (_ext_info), \
959 .scan_index = (_si), \
960 .scan_type = { \
961 .sign = 'u', \
962 .realbits = 24, \
963 .storagebits = 32, \
964 .endianness = IIO_BE, \
965 }, \
966 }
967
968#define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
969 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \
970 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
971
972#define AD719x_CHANNEL(_si, _channel1, _address) \
973 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
974 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
975
976#define AD719x_TEMP_CHANNEL(_si, _address) \
977 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
978
979#define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
980 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \
981 IIO_VOLTAGE, \
982 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
983 BIT(IIO_CHAN_INFO_SCALE), \
984 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
985 ad7192_calibsys_ext_info)
986
987#define AD7193_CHANNEL(_si, _channel1, _address) \
988 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
989
990static const struct iio_chan_spec ad7192_channels[] = {
991 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
992 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
993 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
994 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
995 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
996 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
997 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
998 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
999 IIO_CHAN_SOFT_TIMESTAMP(8),
1000};
1001
1002static const struct iio_chan_spec ad7193_channels[] = {
1003 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1004 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1005 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
1006 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
1007 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
1008 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
1009 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1010 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
1011 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
1012 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
1013 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
1014 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
1015 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
1016 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
1017 IIO_CHAN_SOFT_TIMESTAMP(14),
1018};
1019
1020static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
1021 [ID_AD7190] = {
1022 .chip_id = CHIPID_AD7190,
1023 .name = "ad7190",
1024 .channels = ad7192_channels,
1025 .num_channels = ARRAY_SIZE(ad7192_channels),
1026 .info = &ad7192_info,
1027 },
1028 [ID_AD7192] = {
1029 .chip_id = CHIPID_AD7192,
1030 .name = "ad7192",
1031 .channels = ad7192_channels,
1032 .num_channels = ARRAY_SIZE(ad7192_channels),
1033 .info = &ad7192_info,
1034 },
1035 [ID_AD7193] = {
1036 .chip_id = CHIPID_AD7193,
1037 .name = "ad7193",
1038 .channels = ad7193_channels,
1039 .num_channels = ARRAY_SIZE(ad7193_channels),
1040 .info = &ad7192_info,
1041 },
1042 [ID_AD7195] = {
1043 .chip_id = CHIPID_AD7195,
1044 .name = "ad7195",
1045 .channels = ad7192_channels,
1046 .num_channels = ARRAY_SIZE(ad7192_channels),
1047 .info = &ad7195_info,
1048 },
1049};
1050
1051static void ad7192_reg_disable(void *reg)
1052{
1053 regulator_disable(regulator: reg);
1054}
1055
1056static int ad7192_probe(struct spi_device *spi)
1057{
1058 struct ad7192_state *st;
1059 struct iio_dev *indio_dev;
1060 int ret;
1061
1062 if (!spi->irq) {
1063 dev_err(&spi->dev, "no IRQ?\n");
1064 return -ENODEV;
1065 }
1066
1067 indio_dev = devm_iio_device_alloc(parent: &spi->dev, sizeof_priv: sizeof(*st));
1068 if (!indio_dev)
1069 return -ENOMEM;
1070
1071 st = iio_priv(indio_dev);
1072
1073 mutex_init(&st->lock);
1074
1075 st->avdd = devm_regulator_get(dev: &spi->dev, id: "avdd");
1076 if (IS_ERR(ptr: st->avdd))
1077 return PTR_ERR(ptr: st->avdd);
1078
1079 ret = regulator_enable(regulator: st->avdd);
1080 if (ret) {
1081 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
1082 return ret;
1083 }
1084
1085 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
1086 if (ret)
1087 return ret;
1088
1089 ret = devm_regulator_get_enable(dev: &spi->dev, id: "dvdd");
1090 if (ret)
1091 return dev_err_probe(dev: &spi->dev, err: ret, fmt: "Failed to enable specified DVdd supply\n");
1092
1093 st->vref = devm_regulator_get_optional(dev: &spi->dev, id: "vref");
1094 if (IS_ERR(ptr: st->vref)) {
1095 if (PTR_ERR(ptr: st->vref) != -ENODEV)
1096 return PTR_ERR(ptr: st->vref);
1097
1098 ret = regulator_get_voltage(regulator: st->avdd);
1099 if (ret < 0)
1100 return dev_err_probe(dev: &spi->dev, err: ret,
1101 fmt: "Device tree error, AVdd voltage undefined\n");
1102 } else {
1103 ret = regulator_enable(regulator: st->vref);
1104 if (ret) {
1105 dev_err(&spi->dev, "Failed to enable specified Vref supply\n");
1106 return ret;
1107 }
1108
1109 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref);
1110 if (ret)
1111 return ret;
1112
1113 ret = regulator_get_voltage(regulator: st->vref);
1114 if (ret < 0)
1115 return dev_err_probe(dev: &spi->dev, err: ret,
1116 fmt: "Device tree error, Vref voltage undefined\n");
1117 }
1118 st->int_vref_mv = ret / 1000;
1119
1120 st->chip_info = of_device_get_match_data(dev: &spi->dev);
1121 if (!st->chip_info)
1122 st->chip_info = (void *)spi_get_device_id(sdev: spi)->driver_data;
1123 indio_dev->name = st->chip_info->name;
1124 indio_dev->modes = INDIO_DIRECT_MODE;
1125 indio_dev->channels = st->chip_info->channels;
1126 indio_dev->num_channels = st->chip_info->num_channels;
1127 indio_dev->info = st->chip_info->info;
1128
1129 ret = ad_sd_init(sigma_delta: &st->sd, indio_dev, spi, info: &ad7192_sigma_delta_info);
1130 if (ret)
1131 return ret;
1132
1133 ret = devm_ad_sd_setup_buffer_and_trigger(dev: &spi->dev, indio_dev);
1134 if (ret)
1135 return ret;
1136
1137 st->fclk = AD7192_INT_FREQ_MHZ;
1138
1139 st->mclk = devm_clk_get_optional_enabled(dev: &spi->dev, id: "mclk");
1140 if (IS_ERR(ptr: st->mclk))
1141 return PTR_ERR(ptr: st->mclk);
1142
1143 st->clock_sel = ad7192_of_clock_select(st);
1144
1145 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1146 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1147 st->fclk = clk_get_rate(clk: st->mclk);
1148 if (!ad7192_valid_external_frequency(freq: st->fclk)) {
1149 dev_err(&spi->dev,
1150 "External clock frequency out of bounds\n");
1151 return -EINVAL;
1152 }
1153 }
1154
1155 ret = ad7192_setup(indio_dev, np: spi->dev.of_node);
1156 if (ret)
1157 return ret;
1158
1159 return devm_iio_device_register(&spi->dev, indio_dev);
1160}
1161
1162static const struct of_device_id ad7192_of_match[] = {
1163 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1164 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1165 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1166 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1167 {}
1168};
1169MODULE_DEVICE_TABLE(of, ad7192_of_match);
1170
1171static const struct spi_device_id ad7192_ids[] = {
1172 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1173 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1174 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1175 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1176 {}
1177};
1178MODULE_DEVICE_TABLE(spi, ad7192_ids);
1179
1180static struct spi_driver ad7192_driver = {
1181 .driver = {
1182 .name = "ad7192",
1183 .of_match_table = ad7192_of_match,
1184 },
1185 .probe = ad7192_probe,
1186 .id_table = ad7192_ids,
1187};
1188module_spi_driver(ad7192_driver);
1189
1190MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1191MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1192MODULE_LICENSE("GPL v2");
1193MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1194

source code of linux/drivers/iio/adc/ad7192.c