1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * IIO driver for MCP356X/MCP356XR and MCP346X/MCP346XR series ADC chip family |
4 | * |
5 | * Copyright (C) 2022-2023 Microchip Technology Inc. and its subsidiaries |
6 | * |
7 | * Author: Marius Cristea <marius.cristea@microchip.com> |
8 | * |
9 | * Datasheet for MCP3561, MCP3562, MCP3564 can be found here: |
10 | * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf |
11 | * Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here: |
12 | * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf |
13 | * Datasheet for MCP3461, MCP3462, MCP3464 can be found here: |
14 | * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf |
15 | * Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here: |
16 | * https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf |
17 | */ |
18 | |
19 | #include <linux/bitfield.h> |
20 | #include <linux/iopoll.h> |
21 | #include <linux/regulator/consumer.h> |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/units.h> |
24 | #include <linux/util_macros.h> |
25 | |
26 | #include <linux/iio/iio.h> |
27 | #include <linux/iio/sysfs.h> |
28 | |
29 | #define MCP3564_ADCDATA_REG 0x00 |
30 | |
31 | #define MCP3564_CONFIG0_REG 0x01 |
32 | #define MCP3564_CONFIG0_ADC_MODE_MASK GENMASK(1, 0) |
33 | /* Current Source/Sink Selection Bits for Sensor Bias */ |
34 | #define MCP3564_CONFIG0_CS_SEL_MASK GENMASK(3, 2) |
35 | /* Internal clock is selected and AMCLK is present on the analog master clock output pin */ |
36 | #define MCP3564_CONFIG0_USE_INT_CLK_OUTPUT_EN 0x03 |
37 | /* Internal clock is selected and no clock output is present on the CLK pin */ |
38 | #define MCP3564_CONFIG0_USE_INT_CLK 0x02 |
39 | /* External digital clock */ |
40 | #define MCP3564_CONFIG0_USE_EXT_CLK 0x01 |
41 | /* External digital clock (default) */ |
42 | #define MCP3564_CONFIG0_USE_EXT_CLK_DEFAULT 0x00 |
43 | #define MCP3564_CONFIG0_CLK_SEL_MASK GENMASK(5, 4) |
44 | #define MCP3456_CONFIG0_BIT6_DEFAULT BIT(6) |
45 | #define MCP3456_CONFIG0_VREF_MASK BIT(7) |
46 | |
47 | #define MCP3564_CONFIG1_REG 0x02 |
48 | #define MCP3564_CONFIG1_OVERSPL_RATIO_MASK GENMASK(5, 2) |
49 | |
50 | #define MCP3564_CONFIG2_REG 0x03 |
51 | #define MCP3564_CONFIG2_AZ_REF_MASK BIT(1) |
52 | #define MCP3564_CONFIG2_AZ_MUX_MASK BIT(2) |
53 | |
54 | #define MCP3564_CONFIG2_HARDWARE_GAIN_MASK GENMASK(5, 3) |
55 | #define MCP3564_DEFAULT_HARDWARE_GAIN 0x01 |
56 | #define MCP3564_CONFIG2_BOOST_CURRENT_MASK GENMASK(7, 6) |
57 | |
58 | #define MCP3564_CONFIG3_REG 0x04 |
59 | #define MCP3464_CONFIG3_EN_GAINCAL_MASK BIT(0) |
60 | #define MCP3464_CONFIG3_EN_OFFCAL_MASK BIT(1) |
61 | #define MCP3464_CONFIG3_EN_CRCCOM_MASK BIT(2) |
62 | #define MCP3464_CONFIG3_CRC_FORMAT_MASK BIT(3) |
63 | /* |
64 | * ADC Output Data Format 32-bit (25-bit right justified data + Channel ID): |
65 | * CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data. |
66 | * It allows overrange with the SGN extension. |
67 | */ |
68 | #define MCP3464_CONFIG3_DATA_FMT_32B_WITH_CH_ID 3 |
69 | /* |
70 | * ADC Output Data Format 32-bit (25-bit right justified data): |
71 | * SGN extension (8-bit) + 24-bit ADC data. |
72 | * It allows overrange with the SGN extension. |
73 | */ |
74 | #define MCP3464_CONFIG3_DATA_FMT_32B_SGN_EXT 2 |
75 | /* |
76 | * ADC Output Data Format 32-bit (24-bit left justified data): |
77 | * 24-bit ADC data + 0x00 (8-bit). |
78 | * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000). |
79 | */ |
80 | #define MCP3464_CONFIG3_DATA_FMT_32B_LEFT_JUSTIFIED 1 |
81 | /* |
82 | * ADC Output Data Format 24-bit (default ADC coding): |
83 | * 24-bit ADC data. |
84 | * It does not allow overrange (ADC code locked to 0xFFFFFF or 0x800000). |
85 | */ |
86 | #define MCP3464_CONFIG3_DATA_FMT_24B 0 |
87 | #define MCP3464_CONFIG3_DATA_FORMAT_MASK GENMASK(5, 4) |
88 | |
89 | /* Continuous Conversion mode or continuous conversion cycle in SCAN mode. */ |
90 | #define MCP3464_CONFIG3_CONV_MODE_CONTINUOUS 3 |
91 | /* |
92 | * One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘10’ |
93 | * (standby) at the end of the conversion or at the end of the conversion cycle in SCAN mode. |
94 | */ |
95 | #define MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_STANDBY 2 |
96 | /* |
97 | * One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘0x’ (ADC |
98 | * Shutdown) at the end of the conversion or at the end of the conversion cycle in SCAN |
99 | * mode (default). |
100 | */ |
101 | #define MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_SHUTDOWN 0 |
102 | #define MCP3464_CONFIG3_CONV_MODE_MASK GENMASK(7, 6) |
103 | |
104 | #define MCP3564_IRQ_REG 0x05 |
105 | #define MCP3464_EN_STP_MASK BIT(0) |
106 | #define MCP3464_EN_FASTCMD_MASK BIT(1) |
107 | #define MCP3464_IRQ_MODE_0_MASK BIT(2) |
108 | #define MCP3464_IRQ_MODE_1_MASK BIT(3) |
109 | #define MCP3564_POR_STATUS_MASK BIT(4) |
110 | #define MCP3564_CRCCFG_STATUS_MASK BIT(5) |
111 | #define MCP3564_DATA_READY_MASK BIT(6) |
112 | |
113 | #define MCP3564_MUX_REG 0x06 |
114 | #define MCP3564_MUX_VIN_P_MASK GENMASK(7, 4) |
115 | #define MCP3564_MUX_VIN_N_MASK GENMASK(3, 0) |
116 | #define MCP3564_MUX_SET(x, y) (FIELD_PREP(MCP3564_MUX_VIN_P_MASK, (x)) | \ |
117 | FIELD_PREP(MCP3564_MUX_VIN_N_MASK, (y))) |
118 | |
119 | #define MCP3564_SCAN_REG 0x07 |
120 | #define MCP3564_SCAN_CH_SEL_MASK GENMASK(15, 0) |
121 | #define MCP3564_SCAN_CH_SEL_SET(x) FIELD_PREP(MCP3564_SCAN_CH_SEL_MASK, (x)) |
122 | #define MCP3564_SCAN_DELAY_TIME_MASK GENMASK(23, 21) |
123 | #define MCP3564_SCAN_DELAY_TIME_SET(x) FIELD_PREP(MCP3564_SCAN_DELAY_TIME_MASK, (x)) |
124 | #define MCP3564_SCAN_DEFAULT_VALUE 0 |
125 | |
126 | #define MCP3564_TIMER_REG 0x08 |
127 | #define MCP3564_TIMER_DEFAULT_VALUE 0 |
128 | |
129 | #define MCP3564_OFFSETCAL_REG 0x09 |
130 | #define MCP3564_DEFAULT_OFFSETCAL 0 |
131 | |
132 | #define MCP3564_GAINCAL_REG 0x0A |
133 | #define MCP3564_DEFAULT_GAINCAL 0x00800000 |
134 | |
135 | #define MCP3564_RESERVED_B_REG 0x0B |
136 | |
137 | #define MCP3564_RESERVED_C_REG 0x0C |
138 | #define MCP3564_C_REG_DEFAULT 0x50 |
139 | #define MCP3564R_C_REG_DEFAULT 0x30 |
140 | |
141 | #define MCP3564_LOCK_REG 0x0D |
142 | #define MCP3564_LOCK_WRITE_ACCESS_PASSWORD 0xA5 |
143 | #define MCP3564_RESERVED_E_REG 0x0E |
144 | #define MCP3564_CRCCFG_REG 0x0F |
145 | |
146 | #define MCP3564_CMD_HW_ADDR_MASK GENMASK(7, 6) |
147 | #define MCP3564_CMD_ADDR_MASK GENMASK(5, 2) |
148 | |
149 | #define MCP3564_HW_ADDR_MASK GENMASK(1, 0) |
150 | |
151 | #define MCP3564_FASTCMD_START 0x0A |
152 | #define MCP3564_FASTCMD_RESET 0x0E |
153 | |
154 | #define MCP3461_HW_ID 0x0008 |
155 | #define MCP3462_HW_ID 0x0009 |
156 | #define MCP3464_HW_ID 0x000B |
157 | |
158 | #define MCP3561_HW_ID 0x000C |
159 | #define MCP3562_HW_ID 0x000D |
160 | #define MCP3564_HW_ID 0x000F |
161 | #define MCP3564_HW_ID_MASK GENMASK(3, 0) |
162 | |
163 | #define MCP3564R_INT_VREF_MV 2400 |
164 | |
165 | #define MCP3564_DATA_READY_TIMEOUT_MS 2000 |
166 | |
167 | #define MCP3564_MAX_PGA 8 |
168 | #define MCP3564_MAX_BURNOUT_IDX 4 |
169 | #define MCP3564_MAX_CHANNELS 66 |
170 | |
171 | enum mcp3564_ids { |
172 | mcp3461, |
173 | mcp3462, |
174 | mcp3464, |
175 | mcp3561, |
176 | mcp3562, |
177 | mcp3564, |
178 | mcp3461r, |
179 | mcp3462r, |
180 | mcp3464r, |
181 | mcp3561r, |
182 | mcp3562r, |
183 | mcp3564r, |
184 | }; |
185 | |
186 | enum mcp3564_delay_time { |
187 | MCP3564_NO_DELAY, |
188 | MCP3564_DELAY_8_DMCLK, |
189 | MCP3564_DELAY_16_DMCLK, |
190 | MCP3564_DELAY_32_DMCLK, |
191 | MCP3564_DELAY_64_DMCLK, |
192 | MCP3564_DELAY_128_DMCLK, |
193 | MCP3564_DELAY_256_DMCLK, |
194 | MCP3564_DELAY_512_DMCLK |
195 | }; |
196 | |
197 | enum mcp3564_adc_conversion_mode { |
198 | MCP3564_ADC_MODE_DEFAULT, |
199 | MCP3564_ADC_MODE_SHUTDOWN, |
200 | MCP3564_ADC_MODE_STANDBY, |
201 | MCP3564_ADC_MODE_CONVERSION |
202 | }; |
203 | |
204 | enum mcp3564_adc_bias_current { |
205 | MCP3564_BOOST_CURRENT_x0_50, |
206 | MCP3564_BOOST_CURRENT_x0_66, |
207 | MCP3564_BOOST_CURRENT_x1_00, |
208 | MCP3564_BOOST_CURRENT_x2_00 |
209 | }; |
210 | |
211 | enum mcp3564_burnout { |
212 | MCP3564_CONFIG0_CS_SEL_0_0_uA, |
213 | MCP3564_CONFIG0_CS_SEL_0_9_uA, |
214 | MCP3564_CONFIG0_CS_SEL_3_7_uA, |
215 | MCP3564_CONFIG0_CS_SEL_15_uA |
216 | }; |
217 | |
218 | enum mcp3564_channel_names { |
219 | MCP3564_CH0, |
220 | MCP3564_CH1, |
221 | MCP3564_CH2, |
222 | MCP3564_CH3, |
223 | MCP3564_CH4, |
224 | MCP3564_CH5, |
225 | MCP3564_CH6, |
226 | MCP3564_CH7, |
227 | MCP3564_AGND, |
228 | MCP3564_AVDD, |
229 | MCP3564_RESERVED, /* do not use */ |
230 | MCP3564_REFIN_POZ, |
231 | MCP3564_REFIN_NEG, |
232 | MCP3564_TEMP_DIODE_P, |
233 | MCP3564_TEMP_DIODE_M, |
234 | MCP3564_INTERNAL_VCM, |
235 | }; |
236 | |
237 | enum mcp3564_oversampling { |
238 | MCP3564_OVERSAMPLING_RATIO_32, |
239 | MCP3564_OVERSAMPLING_RATIO_64, |
240 | MCP3564_OVERSAMPLING_RATIO_128, |
241 | MCP3564_OVERSAMPLING_RATIO_256, |
242 | MCP3564_OVERSAMPLING_RATIO_512, |
243 | MCP3564_OVERSAMPLING_RATIO_1024, |
244 | MCP3564_OVERSAMPLING_RATIO_2048, |
245 | MCP3564_OVERSAMPLING_RATIO_4096, |
246 | MCP3564_OVERSAMPLING_RATIO_8192, |
247 | MCP3564_OVERSAMPLING_RATIO_16384, |
248 | MCP3564_OVERSAMPLING_RATIO_20480, |
249 | MCP3564_OVERSAMPLING_RATIO_24576, |
250 | MCP3564_OVERSAMPLING_RATIO_40960, |
251 | MCP3564_OVERSAMPLING_RATIO_49152, |
252 | MCP3564_OVERSAMPLING_RATIO_81920, |
253 | MCP3564_OVERSAMPLING_RATIO_98304 |
254 | }; |
255 | |
256 | static const unsigned int mcp3564_oversampling_avail[] = { |
257 | [MCP3564_OVERSAMPLING_RATIO_32] = 32, |
258 | [MCP3564_OVERSAMPLING_RATIO_64] = 64, |
259 | [MCP3564_OVERSAMPLING_RATIO_128] = 128, |
260 | [MCP3564_OVERSAMPLING_RATIO_256] = 256, |
261 | [MCP3564_OVERSAMPLING_RATIO_512] = 512, |
262 | [MCP3564_OVERSAMPLING_RATIO_1024] = 1024, |
263 | [MCP3564_OVERSAMPLING_RATIO_2048] = 2048, |
264 | [MCP3564_OVERSAMPLING_RATIO_4096] = 4096, |
265 | [MCP3564_OVERSAMPLING_RATIO_8192] = 8192, |
266 | [MCP3564_OVERSAMPLING_RATIO_16384] = 16384, |
267 | [MCP3564_OVERSAMPLING_RATIO_20480] = 20480, |
268 | [MCP3564_OVERSAMPLING_RATIO_24576] = 24576, |
269 | [MCP3564_OVERSAMPLING_RATIO_40960] = 40960, |
270 | [MCP3564_OVERSAMPLING_RATIO_49152] = 49152, |
271 | [MCP3564_OVERSAMPLING_RATIO_81920] = 81920, |
272 | [MCP3564_OVERSAMPLING_RATIO_98304] = 98304 |
273 | }; |
274 | |
275 | /* |
276 | * Current Source/Sink Selection Bits for Sensor Bias (source on VIN+/sink on VIN-) |
277 | */ |
278 | static const int mcp3564_burnout_avail[][2] = { |
279 | [MCP3564_CONFIG0_CS_SEL_0_0_uA] = { 0, 0 }, |
280 | [MCP3564_CONFIG0_CS_SEL_0_9_uA] = { 0, 900 }, |
281 | [MCP3564_CONFIG0_CS_SEL_3_7_uA] = { 0, 3700 }, |
282 | [MCP3564_CONFIG0_CS_SEL_15_uA] = { 0, 15000 } |
283 | }; |
284 | |
285 | /* |
286 | * BOOST[1:0]: ADC Bias Current Selection |
287 | */ |
288 | static const char * const mcp3564_boost_current_avail[] = { |
289 | [MCP3564_BOOST_CURRENT_x0_50] = "0.5" , |
290 | [MCP3564_BOOST_CURRENT_x0_66] = "0.66" , |
291 | [MCP3564_BOOST_CURRENT_x1_00] = "1" , |
292 | [MCP3564_BOOST_CURRENT_x2_00] = "2" , |
293 | }; |
294 | |
295 | /* |
296 | * Calibration bias values |
297 | */ |
298 | static const int mcp3564_calib_bias[] = { |
299 | -8388608, /* min: -2^23 */ |
300 | 1, /* step: 1 */ |
301 | 8388607 /* max: 2^23 - 1 */ |
302 | }; |
303 | |
304 | /* |
305 | * Calibration scale values |
306 | * The Gain Error Calibration register (GAINCAL) is an |
307 | * unsigned 24-bit register that holds the digital gain error |
308 | * calibration value, GAINCAL which could be calculated by |
309 | * GAINCAL (V/V) = (GAINCAL[23:0])/8388608 |
310 | * The gain error calibration value range in equivalent voltage is [0; 2-2^(-23)] |
311 | */ |
312 | static const unsigned int mcp3564_calib_scale[] = { |
313 | 0, /* min: 0 */ |
314 | 1, /* step: 1/8388608 */ |
315 | 16777215 /* max: 2 - 2^(-23) */ |
316 | }; |
317 | |
318 | /* Programmable hardware gain x1/3, x1, x2, x4, x8, x16, x32, x64 */ |
319 | static const int mcp3564_hwgain_frac[] = { |
320 | 3, 10, |
321 | 1, 1, |
322 | 2, 1, |
323 | 4, 1, |
324 | 8, 1, |
325 | 16, 1, |
326 | 32, 1, |
327 | 64, 1 |
328 | }; |
329 | |
330 | static const char *mcp3564_channel_labels[2] = { |
331 | "burnout_current" , "temperature" , |
332 | }; |
333 | |
334 | /** |
335 | * struct mcp3564_chip_info - chip specific data |
336 | * @name: device name |
337 | * @num_channels: number of channels |
338 | * @resolution: ADC resolution |
339 | * @have_vref: does the hardware have an internal voltage reference? |
340 | */ |
341 | struct mcp3564_chip_info { |
342 | const char *name; |
343 | unsigned int num_channels; |
344 | unsigned int resolution; |
345 | bool have_vref; |
346 | }; |
347 | |
348 | /** |
349 | * struct mcp3564_state - working data for a ADC device |
350 | * @chip_info: chip specific data |
351 | * @spi: SPI device structure |
352 | * @vref: the regulator device used as a voltage reference in case |
353 | * external voltage reference is used |
354 | * @vref_mv: voltage reference value in miliVolts |
355 | * @lock: synchronize access to driver's state members |
356 | * @dev_addr: hardware device address |
357 | * @oversampling: the index inside oversampling list of the ADC |
358 | * @hwgain: the index inside hardware gain list of the ADC |
359 | * @scale_tbls: table with precalculated scale |
360 | * @calib_bias: calibration bias value |
361 | * @calib_scale: calibration scale value |
362 | * @current_boost_mode: the index inside current boost list of the ADC |
363 | * @burnout_mode: the index inside current bias list of the ADC |
364 | * @auto_zeroing_mux: set if ADC auto-zeroing algorithm is enabled |
365 | * @auto_zeroing_ref: set if ADC auto-Zeroing Reference Buffer Setting is enabled |
366 | * @have_vref: does the ADC have an internal voltage reference? |
367 | * @labels: table with channels labels |
368 | */ |
369 | struct mcp3564_state { |
370 | const struct mcp3564_chip_info *chip_info; |
371 | struct spi_device *spi; |
372 | struct regulator *vref; |
373 | unsigned short vref_mv; |
374 | struct mutex lock; /* Synchronize access to driver's state members */ |
375 | u8 dev_addr; |
376 | enum mcp3564_oversampling oversampling; |
377 | unsigned int hwgain; |
378 | unsigned int scale_tbls[MCP3564_MAX_PGA][2]; |
379 | int calib_bias; |
380 | int calib_scale; |
381 | unsigned int current_boost_mode; |
382 | enum mcp3564_burnout burnout_mode; |
383 | bool auto_zeroing_mux; |
384 | bool auto_zeroing_ref; |
385 | bool have_vref; |
386 | const char *labels[MCP3564_MAX_CHANNELS]; |
387 | }; |
388 | |
389 | static inline u8 mcp3564_cmd_write(u8 chip_addr, u8 reg) |
390 | { |
391 | return FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, chip_addr) | |
392 | FIELD_PREP(MCP3564_CMD_ADDR_MASK, reg) | |
393 | BIT(1); |
394 | } |
395 | |
396 | static inline u8 mcp3564_cmd_read(u8 chip_addr, u8 reg) |
397 | { |
398 | return FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, chip_addr) | |
399 | FIELD_PREP(MCP3564_CMD_ADDR_MASK, reg) | |
400 | BIT(0); |
401 | } |
402 | |
403 | static int mcp3564_read_8bits(struct mcp3564_state *adc, u8 reg, u8 *val) |
404 | { |
405 | int ret; |
406 | u8 tx_buf; |
407 | u8 rx_buf; |
408 | |
409 | tx_buf = mcp3564_cmd_read(chip_addr: adc->dev_addr, reg); |
410 | |
411 | ret = spi_write_then_read(spi: adc->spi, txbuf: &tx_buf, n_tx: sizeof(tx_buf), |
412 | rxbuf: &rx_buf, n_rx: sizeof(rx_buf)); |
413 | *val = rx_buf; |
414 | |
415 | return ret; |
416 | } |
417 | |
418 | static int mcp3564_read_16bits(struct mcp3564_state *adc, u8 reg, u16 *val) |
419 | { |
420 | int ret; |
421 | u8 tx_buf; |
422 | __be16 rx_buf; |
423 | |
424 | tx_buf = mcp3564_cmd_read(chip_addr: adc->dev_addr, reg); |
425 | |
426 | ret = spi_write_then_read(spi: adc->spi, txbuf: &tx_buf, n_tx: sizeof(tx_buf), |
427 | rxbuf: &rx_buf, n_rx: sizeof(rx_buf)); |
428 | *val = be16_to_cpu(rx_buf); |
429 | |
430 | return ret; |
431 | } |
432 | |
433 | static int mcp3564_read_32bits(struct mcp3564_state *adc, u8 reg, u32 *val) |
434 | { |
435 | int ret; |
436 | u8 tx_buf; |
437 | __be32 rx_buf; |
438 | |
439 | tx_buf = mcp3564_cmd_read(chip_addr: adc->dev_addr, reg); |
440 | |
441 | ret = spi_write_then_read(spi: adc->spi, txbuf: &tx_buf, n_tx: sizeof(tx_buf), |
442 | rxbuf: &rx_buf, n_rx: sizeof(rx_buf)); |
443 | *val = be32_to_cpu(rx_buf); |
444 | |
445 | return ret; |
446 | } |
447 | |
448 | static int mcp3564_write_8bits(struct mcp3564_state *adc, u8 reg, u8 val) |
449 | { |
450 | u8 tx_buf[2]; |
451 | |
452 | tx_buf[0] = mcp3564_cmd_write(chip_addr: adc->dev_addr, reg); |
453 | tx_buf[1] = val; |
454 | |
455 | return spi_write_then_read(spi: adc->spi, txbuf: tx_buf, n_tx: sizeof(tx_buf), NULL, n_rx: 0); |
456 | } |
457 | |
458 | static int mcp3564_write_24bits(struct mcp3564_state *adc, u8 reg, u32 val) |
459 | { |
460 | __be32 val_be; |
461 | |
462 | val |= (mcp3564_cmd_write(chip_addr: adc->dev_addr, reg) << 24); |
463 | val_be = cpu_to_be32(val); |
464 | |
465 | return spi_write_then_read(spi: adc->spi, txbuf: &val_be, n_tx: sizeof(val_be), NULL, n_rx: 0); |
466 | } |
467 | |
468 | static int mcp3564_fast_cmd(struct mcp3564_state *adc, u8 fast_cmd) |
469 | { |
470 | u8 val; |
471 | |
472 | val = FIELD_PREP(MCP3564_CMD_HW_ADDR_MASK, adc->dev_addr) | |
473 | FIELD_PREP(MCP3564_CMD_ADDR_MASK, fast_cmd); |
474 | |
475 | return spi_write_then_read(spi: adc->spi, txbuf: &val, n_tx: 1, NULL, n_rx: 0); |
476 | } |
477 | |
478 | static int mcp3564_update_8bits(struct mcp3564_state *adc, u8 reg, u32 mask, u8 val) |
479 | { |
480 | u8 tmp; |
481 | int ret; |
482 | |
483 | val &= mask; |
484 | |
485 | ret = mcp3564_read_8bits(adc, reg, val: &tmp); |
486 | if (ret < 0) |
487 | return ret; |
488 | |
489 | tmp &= ~mask; |
490 | tmp |= val; |
491 | |
492 | return mcp3564_write_8bits(adc, reg, val: tmp); |
493 | } |
494 | |
495 | static int mcp3564_set_current_boost_mode(struct iio_dev *indio_dev, |
496 | const struct iio_chan_spec *chan, |
497 | unsigned int mode) |
498 | { |
499 | struct mcp3564_state *adc = iio_priv(indio_dev); |
500 | int ret; |
501 | |
502 | dev_dbg(&indio_dev->dev, "%s: %d\n" , __func__, mode); |
503 | |
504 | mutex_lock(&adc->lock); |
505 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_BOOST_CURRENT_MASK, |
506 | FIELD_PREP(MCP3564_CONFIG2_BOOST_CURRENT_MASK, mode)); |
507 | |
508 | if (ret) |
509 | dev_err(&indio_dev->dev, "Failed to configure CONFIG2 register\n" ); |
510 | else |
511 | adc->current_boost_mode = mode; |
512 | |
513 | mutex_unlock(lock: &adc->lock); |
514 | |
515 | return ret; |
516 | } |
517 | |
518 | static int mcp3564_get_current_boost_mode(struct iio_dev *indio_dev, |
519 | const struct iio_chan_spec *chan) |
520 | { |
521 | struct mcp3564_state *adc = iio_priv(indio_dev); |
522 | |
523 | return adc->current_boost_mode; |
524 | } |
525 | |
526 | static const struct iio_enum mcp3564_current_boost_mode_enum = { |
527 | .items = mcp3564_boost_current_avail, |
528 | .num_items = ARRAY_SIZE(mcp3564_boost_current_avail), |
529 | .set = mcp3564_set_current_boost_mode, |
530 | .get = mcp3564_get_current_boost_mode, |
531 | }; |
532 | |
533 | static const struct iio_chan_spec_ext_info mcp3564_ext_info[] = { |
534 | IIO_ENUM("boost_current_gain" , IIO_SHARED_BY_ALL, &mcp3564_current_boost_mode_enum), |
535 | { |
536 | .name = "boost_current_gain_available" , |
537 | .shared = IIO_SHARED_BY_ALL, |
538 | .read = iio_enum_available_read, |
539 | .private = (uintptr_t)&mcp3564_current_boost_mode_enum, |
540 | }, |
541 | { } |
542 | }; |
543 | |
544 | static ssize_t mcp3564_auto_zeroing_mux_show(struct device *dev, |
545 | struct device_attribute *attr, |
546 | char *buf) |
547 | { |
548 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
549 | struct mcp3564_state *adc = iio_priv(indio_dev); |
550 | |
551 | return sysfs_emit(buf, fmt: "%d\n" , adc->auto_zeroing_mux); |
552 | } |
553 | |
554 | static ssize_t mcp3564_auto_zeroing_mux_store(struct device *dev, |
555 | struct device_attribute *attr, |
556 | const char *buf, size_t len) |
557 | { |
558 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
559 | struct mcp3564_state *adc = iio_priv(indio_dev); |
560 | bool auto_zero; |
561 | int ret; |
562 | |
563 | ret = kstrtobool(s: buf, res: &auto_zero); |
564 | if (ret) |
565 | return ret; |
566 | |
567 | mutex_lock(&adc->lock); |
568 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_AZ_MUX_MASK, |
569 | FIELD_PREP(MCP3564_CONFIG2_AZ_MUX_MASK, auto_zero)); |
570 | |
571 | if (ret) |
572 | dev_err(&indio_dev->dev, "Failed to update CONFIG2 register\n" ); |
573 | else |
574 | adc->auto_zeroing_mux = auto_zero; |
575 | |
576 | mutex_unlock(lock: &adc->lock); |
577 | |
578 | return ret ? ret : len; |
579 | } |
580 | |
581 | static ssize_t mcp3564_auto_zeroing_ref_show(struct device *dev, |
582 | struct device_attribute *attr, |
583 | char *buf) |
584 | { |
585 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
586 | struct mcp3564_state *adc = iio_priv(indio_dev); |
587 | |
588 | return sysfs_emit(buf, fmt: "%d\n" , adc->auto_zeroing_ref); |
589 | } |
590 | |
591 | static ssize_t mcp3564_auto_zeroing_ref_store(struct device *dev, |
592 | struct device_attribute *attr, |
593 | const char *buf, size_t len) |
594 | { |
595 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
596 | struct mcp3564_state *adc = iio_priv(indio_dev); |
597 | bool auto_zero; |
598 | int ret; |
599 | |
600 | ret = kstrtobool(s: buf, res: &auto_zero); |
601 | if (ret) |
602 | return ret; |
603 | |
604 | mutex_lock(&adc->lock); |
605 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, MCP3564_CONFIG2_AZ_REF_MASK, |
606 | FIELD_PREP(MCP3564_CONFIG2_AZ_REF_MASK, auto_zero)); |
607 | |
608 | if (ret) |
609 | dev_err(&indio_dev->dev, "Failed to update CONFIG2 register\n" ); |
610 | else |
611 | adc->auto_zeroing_ref = auto_zero; |
612 | |
613 | mutex_unlock(lock: &adc->lock); |
614 | |
615 | return ret ? ret : len; |
616 | } |
617 | |
618 | static const struct iio_chan_spec mcp3564_channel_template = { |
619 | .type = IIO_VOLTAGE, |
620 | .indexed = 1, |
621 | .differential = 1, |
622 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
623 | .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | |
624 | BIT(IIO_CHAN_INFO_CALIBSCALE) | |
625 | BIT(IIO_CHAN_INFO_CALIBBIAS) | |
626 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), |
627 | .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SCALE) | |
628 | BIT(IIO_CHAN_INFO_CALIBSCALE) | |
629 | BIT(IIO_CHAN_INFO_CALIBBIAS) | |
630 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), |
631 | .ext_info = mcp3564_ext_info, |
632 | }; |
633 | |
634 | static const struct iio_chan_spec mcp3564_temp_channel_template = { |
635 | .type = IIO_TEMP, |
636 | .channel = 0, |
637 | .address = ((MCP3564_TEMP_DIODE_P << 4) | MCP3564_TEMP_DIODE_M), |
638 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
639 | .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | |
640 | BIT(IIO_CHAN_INFO_CALIBSCALE) | |
641 | BIT(IIO_CHAN_INFO_CALIBBIAS) | |
642 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), |
643 | .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SCALE) | |
644 | BIT(IIO_CHAN_INFO_CALIBSCALE) | |
645 | BIT(IIO_CHAN_INFO_CALIBBIAS) | |
646 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), |
647 | }; |
648 | |
649 | static const struct iio_chan_spec mcp3564_burnout_channel_template = { |
650 | .type = IIO_CURRENT, |
651 | .output = true, |
652 | .channel = 0, |
653 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
654 | .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), |
655 | }; |
656 | |
657 | /* |
658 | * Number of channels could be calculated: |
659 | * num_channels = single_ended_input + differential_input + temperature + burnout |
660 | * Eg. for MCP3561 (only 2 channels available: CH0 and CH1) |
661 | * single_ended_input = (CH0 - GND), (CH1 - GND) = 2 |
662 | * differential_input = (CH0 - CH1), (CH0 - CH0) = 2 |
663 | * num_channels = 2 + 2 + 2 |
664 | * Generic formula is: |
665 | * num_channels = P^R(Number_of_single_ended_channels, 2) + 2 (temperature + burnout channels) |
666 | * P^R(Number_of_single_ended_channels, 2) is Permutations with Replacement of |
667 | * Number_of_single_ended_channels taken by 2 |
668 | */ |
669 | static const struct mcp3564_chip_info mcp3564_chip_infos_tbl[] = { |
670 | [mcp3461] = { |
671 | .name = "mcp3461" , |
672 | .num_channels = 6, |
673 | .resolution = 16, |
674 | .have_vref = false, |
675 | }, |
676 | [mcp3462] = { |
677 | .name = "mcp3462" , |
678 | .num_channels = 18, |
679 | .resolution = 16, |
680 | .have_vref = false, |
681 | }, |
682 | [mcp3464] = { |
683 | .name = "mcp3464" , |
684 | .num_channels = 66, |
685 | .resolution = 16, |
686 | .have_vref = false, |
687 | }, |
688 | [mcp3561] = { |
689 | .name = "mcp3561" , |
690 | .num_channels = 6, |
691 | .resolution = 24, |
692 | .have_vref = false, |
693 | }, |
694 | [mcp3562] = { |
695 | .name = "mcp3562" , |
696 | .num_channels = 18, |
697 | .resolution = 24, |
698 | .have_vref = false, |
699 | }, |
700 | [mcp3564] = { |
701 | .name = "mcp3564" , |
702 | .num_channels = 66, |
703 | .resolution = 24, |
704 | .have_vref = false, |
705 | }, |
706 | [mcp3461r] = { |
707 | .name = "mcp3461r" , |
708 | .num_channels = 6, |
709 | .resolution = 16, |
710 | .have_vref = false, |
711 | }, |
712 | [mcp3462r] = { |
713 | .name = "mcp3462r" , |
714 | .num_channels = 18, |
715 | .resolution = 16, |
716 | .have_vref = true, |
717 | }, |
718 | [mcp3464r] = { |
719 | .name = "mcp3464r" , |
720 | .num_channels = 66, |
721 | .resolution = 16, |
722 | .have_vref = true, |
723 | }, |
724 | [mcp3561r] = { |
725 | .name = "mcp3561r" , |
726 | .num_channels = 6, |
727 | .resolution = 24, |
728 | .have_vref = true, |
729 | }, |
730 | [mcp3562r] = { |
731 | .name = "mcp3562r" , |
732 | .num_channels = 18, |
733 | .resolution = 24, |
734 | .have_vref = true, |
735 | }, |
736 | [mcp3564r] = { |
737 | .name = "mcp3564r" , |
738 | .num_channels = 66, |
739 | .resolution = 24, |
740 | .have_vref = true, |
741 | }, |
742 | }; |
743 | |
744 | static int mcp3564_read_single_value(struct iio_dev *indio_dev, |
745 | struct iio_chan_spec const *channel, |
746 | int *val) |
747 | { |
748 | struct mcp3564_state *adc = iio_priv(indio_dev); |
749 | int ret; |
750 | u8 tmp; |
751 | int ret_read = 0; |
752 | |
753 | ret = mcp3564_write_8bits(adc, MCP3564_MUX_REG, val: channel->address); |
754 | if (ret) |
755 | return ret; |
756 | |
757 | /* Start ADC Conversion using fast command (overwrites ADC_MODE[1:0] = 11) */ |
758 | ret = mcp3564_fast_cmd(adc, MCP3564_FASTCMD_START); |
759 | if (ret) |
760 | return ret; |
761 | |
762 | /* |
763 | * Check if the conversion is ready. If not, wait a little bit, and |
764 | * in case of timeout exit with an error. |
765 | */ |
766 | ret = read_poll_timeout(mcp3564_read_8bits, ret_read, |
767 | ret_read || !(tmp & MCP3564_DATA_READY_MASK), |
768 | 20000, MCP3564_DATA_READY_TIMEOUT_MS * 1000, true, |
769 | adc, MCP3564_IRQ_REG, &tmp); |
770 | |
771 | /* failed to read status register */ |
772 | if (ret_read) |
773 | return ret_read; |
774 | |
775 | if (ret) |
776 | return ret; |
777 | |
778 | if (tmp & MCP3564_DATA_READY_MASK) |
779 | /* failing to finish conversion */ |
780 | return -EBUSY; |
781 | |
782 | return mcp3564_read_32bits(adc, MCP3564_ADCDATA_REG, val); |
783 | } |
784 | |
785 | static int mcp3564_read_avail(struct iio_dev *indio_dev, |
786 | struct iio_chan_spec const *channel, |
787 | const int **vals, int *type, |
788 | int *length, long mask) |
789 | { |
790 | struct mcp3564_state *adc = iio_priv(indio_dev); |
791 | |
792 | switch (mask) { |
793 | case IIO_CHAN_INFO_RAW: |
794 | if (!channel->output) |
795 | return -EINVAL; |
796 | |
797 | *vals = mcp3564_burnout_avail[0]; |
798 | *length = ARRAY_SIZE(mcp3564_burnout_avail) * 2; |
799 | *type = IIO_VAL_INT_PLUS_MICRO; |
800 | return IIO_AVAIL_LIST; |
801 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
802 | *vals = mcp3564_oversampling_avail; |
803 | *length = ARRAY_SIZE(mcp3564_oversampling_avail); |
804 | *type = IIO_VAL_INT; |
805 | return IIO_AVAIL_LIST; |
806 | case IIO_CHAN_INFO_SCALE: |
807 | *vals = (int *)adc->scale_tbls; |
808 | *length = ARRAY_SIZE(adc->scale_tbls) * 2; |
809 | *type = IIO_VAL_INT_PLUS_NANO; |
810 | return IIO_AVAIL_LIST; |
811 | case IIO_CHAN_INFO_CALIBBIAS: |
812 | *vals = mcp3564_calib_bias; |
813 | *type = IIO_VAL_INT; |
814 | return IIO_AVAIL_RANGE; |
815 | case IIO_CHAN_INFO_CALIBSCALE: |
816 | *vals = mcp3564_calib_scale; |
817 | *type = IIO_VAL_INT; |
818 | return IIO_AVAIL_RANGE; |
819 | default: |
820 | return -EINVAL; |
821 | } |
822 | } |
823 | |
824 | static int mcp3564_read_raw(struct iio_dev *indio_dev, |
825 | struct iio_chan_spec const *channel, |
826 | int *val, int *val2, long mask) |
827 | { |
828 | struct mcp3564_state *adc = iio_priv(indio_dev); |
829 | int ret; |
830 | |
831 | switch (mask) { |
832 | case IIO_CHAN_INFO_RAW: |
833 | if (channel->output) { |
834 | mutex_lock(&adc->lock); |
835 | *val = mcp3564_burnout_avail[adc->burnout_mode][0]; |
836 | *val2 = mcp3564_burnout_avail[adc->burnout_mode][1]; |
837 | mutex_unlock(lock: &adc->lock); |
838 | return IIO_VAL_INT_PLUS_MICRO; |
839 | } |
840 | |
841 | ret = mcp3564_read_single_value(indio_dev, channel, val); |
842 | if (ret) |
843 | return -EINVAL; |
844 | return IIO_VAL_INT; |
845 | case IIO_CHAN_INFO_SCALE: |
846 | mutex_lock(&adc->lock); |
847 | *val = adc->scale_tbls[adc->hwgain][0]; |
848 | *val2 = adc->scale_tbls[adc->hwgain][1]; |
849 | mutex_unlock(lock: &adc->lock); |
850 | return IIO_VAL_INT_PLUS_NANO; |
851 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
852 | *val = mcp3564_oversampling_avail[adc->oversampling]; |
853 | return IIO_VAL_INT; |
854 | case IIO_CHAN_INFO_CALIBBIAS: |
855 | *val = adc->calib_bias; |
856 | return IIO_VAL_INT; |
857 | case IIO_CHAN_INFO_CALIBSCALE: |
858 | *val = adc->calib_scale; |
859 | return IIO_VAL_INT; |
860 | default: |
861 | return -EINVAL; |
862 | } |
863 | } |
864 | |
865 | static int mcp3564_write_raw_get_fmt(struct iio_dev *indio_dev, |
866 | struct iio_chan_spec const *chan, |
867 | long info) |
868 | { |
869 | switch (info) { |
870 | case IIO_CHAN_INFO_RAW: |
871 | return IIO_VAL_INT_PLUS_MICRO; |
872 | case IIO_CHAN_INFO_CALIBBIAS: |
873 | case IIO_CHAN_INFO_CALIBSCALE: |
874 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
875 | return IIO_VAL_INT; |
876 | case IIO_CHAN_INFO_SCALE: |
877 | return IIO_VAL_INT_PLUS_NANO; |
878 | default: |
879 | return -EINVAL; |
880 | } |
881 | } |
882 | |
883 | static int mcp3564_write_raw(struct iio_dev *indio_dev, |
884 | struct iio_chan_spec const *channel, int val, |
885 | int val2, long mask) |
886 | { |
887 | struct mcp3564_state *adc = iio_priv(indio_dev); |
888 | int tmp; |
889 | unsigned int hwgain; |
890 | enum mcp3564_burnout burnout; |
891 | int ret = 0; |
892 | |
893 | switch (mask) { |
894 | case IIO_CHAN_INFO_RAW: |
895 | if (!channel->output) |
896 | return -EINVAL; |
897 | |
898 | for (burnout = 0; burnout < MCP3564_MAX_BURNOUT_IDX; burnout++) |
899 | if (val == mcp3564_burnout_avail[burnout][0] && |
900 | val2 == mcp3564_burnout_avail[burnout][1]) |
901 | break; |
902 | |
903 | if (burnout == MCP3564_MAX_BURNOUT_IDX) |
904 | return -EINVAL; |
905 | |
906 | if (burnout == adc->burnout_mode) |
907 | return ret; |
908 | |
909 | mutex_lock(&adc->lock); |
910 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG0_REG, |
911 | MCP3564_CONFIG0_CS_SEL_MASK, |
912 | FIELD_PREP(MCP3564_CONFIG0_CS_SEL_MASK, burnout)); |
913 | |
914 | if (ret) |
915 | dev_err(&indio_dev->dev, "Failed to configure burnout current\n" ); |
916 | else |
917 | adc->burnout_mode = burnout; |
918 | mutex_unlock(lock: &adc->lock); |
919 | return ret; |
920 | case IIO_CHAN_INFO_CALIBBIAS: |
921 | if (val < mcp3564_calib_bias[0] || val > mcp3564_calib_bias[2]) |
922 | return -EINVAL; |
923 | |
924 | mutex_lock(&adc->lock); |
925 | ret = mcp3564_write_24bits(adc, MCP3564_OFFSETCAL_REG, val); |
926 | if (!ret) |
927 | adc->calib_bias = val; |
928 | mutex_unlock(lock: &adc->lock); |
929 | return ret; |
930 | case IIO_CHAN_INFO_CALIBSCALE: |
931 | if (val < mcp3564_calib_scale[0] || val > mcp3564_calib_scale[2]) |
932 | return -EINVAL; |
933 | |
934 | if (adc->calib_scale == val) |
935 | return ret; |
936 | |
937 | mutex_lock(&adc->lock); |
938 | ret = mcp3564_write_24bits(adc, MCP3564_GAINCAL_REG, val); |
939 | if (!ret) |
940 | adc->calib_scale = val; |
941 | mutex_unlock(lock: &adc->lock); |
942 | return ret; |
943 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
944 | if (val < 0) |
945 | return -EINVAL; |
946 | |
947 | tmp = find_closest(val, mcp3564_oversampling_avail, |
948 | ARRAY_SIZE(mcp3564_oversampling_avail)); |
949 | |
950 | if (adc->oversampling == tmp) |
951 | return ret; |
952 | |
953 | mutex_lock(&adc->lock); |
954 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG1_REG, |
955 | MCP3564_CONFIG1_OVERSPL_RATIO_MASK, |
956 | FIELD_PREP(MCP3564_CONFIG1_OVERSPL_RATIO_MASK, |
957 | adc->oversampling)); |
958 | if (!ret) |
959 | adc->oversampling = tmp; |
960 | mutex_unlock(lock: &adc->lock); |
961 | return ret; |
962 | case IIO_CHAN_INFO_SCALE: |
963 | for (hwgain = 0; hwgain < MCP3564_MAX_PGA; hwgain++) |
964 | if (val == adc->scale_tbls[hwgain][0] && |
965 | val2 == adc->scale_tbls[hwgain][1]) |
966 | break; |
967 | |
968 | if (hwgain == MCP3564_MAX_PGA) |
969 | return -EINVAL; |
970 | |
971 | if (hwgain == adc->hwgain) |
972 | return ret; |
973 | |
974 | mutex_lock(&adc->lock); |
975 | ret = mcp3564_update_8bits(adc, MCP3564_CONFIG2_REG, |
976 | MCP3564_CONFIG2_HARDWARE_GAIN_MASK, |
977 | FIELD_PREP(MCP3564_CONFIG2_HARDWARE_GAIN_MASK, hwgain)); |
978 | if (!ret) |
979 | adc->hwgain = hwgain; |
980 | |
981 | mutex_unlock(lock: &adc->lock); |
982 | return ret; |
983 | default: |
984 | return -EINVAL; |
985 | } |
986 | } |
987 | |
988 | static int mcp3564_read_label(struct iio_dev *indio_dev, |
989 | struct iio_chan_spec const *chan, char *label) |
990 | { |
991 | struct mcp3564_state *adc = iio_priv(indio_dev); |
992 | |
993 | return sprintf(buf: label, fmt: "%s\n" , adc->labels[chan->scan_index]); |
994 | } |
995 | |
996 | static int mcp3564_parse_fw_children(struct iio_dev *indio_dev) |
997 | { |
998 | struct mcp3564_state *adc = iio_priv(indio_dev); |
999 | struct device *dev = &adc->spi->dev; |
1000 | struct iio_chan_spec *channels; |
1001 | struct fwnode_handle *child; |
1002 | struct iio_chan_spec chanspec = mcp3564_channel_template; |
1003 | struct iio_chan_spec temp_chanspec = mcp3564_temp_channel_template; |
1004 | struct iio_chan_spec burnout_chanspec = mcp3564_burnout_channel_template; |
1005 | int chan_idx = 0; |
1006 | unsigned int num_ch; |
1007 | u32 inputs[2]; |
1008 | const char *node_name; |
1009 | const char *label; |
1010 | int ret; |
1011 | |
1012 | num_ch = device_get_child_node_count(dev); |
1013 | if (num_ch == 0) |
1014 | return dev_err_probe(dev: &indio_dev->dev, err: -ENODEV, |
1015 | fmt: "FW has no channels defined\n" ); |
1016 | |
1017 | /* Reserve space for burnout and temperature channel */ |
1018 | num_ch += 2; |
1019 | |
1020 | if (num_ch > adc->chip_info->num_channels) |
1021 | return dev_err_probe(dev, err: -EINVAL, fmt: "Too many channels %d > %d\n" , |
1022 | num_ch, adc->chip_info->num_channels); |
1023 | |
1024 | channels = devm_kcalloc(dev, n: num_ch, size: sizeof(*channels), GFP_KERNEL); |
1025 | if (!channels) |
1026 | return dev_err_probe(dev, err: -ENOMEM, fmt: "Can't allocate memory\n" ); |
1027 | |
1028 | device_for_each_child_node(dev, child) { |
1029 | node_name = fwnode_get_name(fwnode: child); |
1030 | |
1031 | if (fwnode_property_present(fwnode: child, propname: "diff-channels" )) { |
1032 | ret = fwnode_property_read_u32_array(fwnode: child, |
1033 | propname: "diff-channels" , |
1034 | val: inputs, |
1035 | ARRAY_SIZE(inputs)); |
1036 | chanspec.differential = 1; |
1037 | } else { |
1038 | ret = fwnode_property_read_u32(fwnode: child, propname: "reg" , val: &inputs[0]); |
1039 | |
1040 | chanspec.differential = 0; |
1041 | inputs[1] = MCP3564_AGND; |
1042 | } |
1043 | if (ret) { |
1044 | fwnode_handle_put(fwnode: child); |
1045 | return ret; |
1046 | } |
1047 | |
1048 | if (inputs[0] > MCP3564_INTERNAL_VCM || |
1049 | inputs[1] > MCP3564_INTERNAL_VCM) { |
1050 | fwnode_handle_put(fwnode: child); |
1051 | return dev_err_probe(dev: &indio_dev->dev, err: -EINVAL, |
1052 | fmt: "Channel index > %d, for %s\n" , |
1053 | MCP3564_INTERNAL_VCM + 1, |
1054 | node_name); |
1055 | } |
1056 | |
1057 | chanspec.address = (inputs[0] << 4) | inputs[1]; |
1058 | chanspec.channel = inputs[0]; |
1059 | chanspec.channel2 = inputs[1]; |
1060 | chanspec.scan_index = chan_idx; |
1061 | |
1062 | if (fwnode_property_present(fwnode: child, propname: "label" )) { |
1063 | fwnode_property_read_string(fwnode: child, propname: "label" , val: &label); |
1064 | adc->labels[chan_idx] = label; |
1065 | } |
1066 | |
1067 | channels[chan_idx] = chanspec; |
1068 | chan_idx++; |
1069 | } |
1070 | |
1071 | /* Add burnout current channel */ |
1072 | burnout_chanspec.scan_index = chan_idx; |
1073 | channels[chan_idx] = burnout_chanspec; |
1074 | adc->labels[chan_idx] = mcp3564_channel_labels[0]; |
1075 | chanspec.scan_index = chan_idx; |
1076 | chan_idx++; |
1077 | |
1078 | /* Add temperature channel */ |
1079 | temp_chanspec.scan_index = chan_idx; |
1080 | channels[chan_idx] = temp_chanspec; |
1081 | adc->labels[chan_idx] = mcp3564_channel_labels[1]; |
1082 | chan_idx++; |
1083 | |
1084 | indio_dev->num_channels = chan_idx; |
1085 | indio_dev->channels = channels; |
1086 | |
1087 | return 0; |
1088 | } |
1089 | |
1090 | static void mcp3564_disable_reg(void *reg) |
1091 | { |
1092 | regulator_disable(regulator: reg); |
1093 | } |
1094 | |
1095 | static void mcp3564_fill_scale_tbls(struct mcp3564_state *adc) |
1096 | { |
1097 | unsigned int pow = adc->chip_info->resolution - 1; |
1098 | int ref; |
1099 | unsigned int i; |
1100 | int tmp0; |
1101 | u64 tmp1; |
1102 | |
1103 | for (i = 0; i < MCP3564_MAX_PGA; i++) { |
1104 | ref = adc->vref_mv; |
1105 | tmp1 = ((u64)ref * NANO) >> pow; |
1106 | div_u64_rem(dividend: tmp1, NANO, remainder: &tmp0); |
1107 | |
1108 | tmp1 = tmp1 * mcp3564_hwgain_frac[(2 * i) + 1]; |
1109 | tmp0 = (int)div_u64(dividend: tmp1, divisor: mcp3564_hwgain_frac[2 * i]); |
1110 | |
1111 | adc->scale_tbls[i][1] = tmp0; |
1112 | } |
1113 | } |
1114 | |
1115 | static int mcp3564_config(struct iio_dev *indio_dev) |
1116 | { |
1117 | struct mcp3564_state *adc = iio_priv(indio_dev); |
1118 | struct device *dev = &adc->spi->dev; |
1119 | const struct spi_device_id *dev_id; |
1120 | u8 tmp_reg; |
1121 | u16 tmp_u16; |
1122 | enum mcp3564_ids ids; |
1123 | int ret = 0; |
1124 | unsigned int tmp = 0x01; |
1125 | bool err = false; |
1126 | |
1127 | /* |
1128 | * The address is set on a per-device basis by fuses in the factory, |
1129 | * configured on request. If not requested, the fuses are set for 0x1. |
1130 | * The device address is part of the device markings to avoid |
1131 | * potential confusion. This address is coded on two bits, so four possible |
1132 | * addresses are available when multiple devices are present on the same |
1133 | * SPI bus with only one Chip Select line for all devices. |
1134 | */ |
1135 | device_property_read_u32(dev, propname: "microchip,hw-device-address" , val: &tmp); |
1136 | |
1137 | if (tmp > 3) { |
1138 | dev_err_probe(dev, err: tmp, |
1139 | fmt: "invalid device address. Must be in range 0-3.\n" ); |
1140 | return -EINVAL; |
1141 | } |
1142 | |
1143 | adc->dev_addr = FIELD_GET(MCP3564_HW_ADDR_MASK, tmp); |
1144 | |
1145 | dev_dbg(dev, "use HW device address %i\n" , adc->dev_addr); |
1146 | |
1147 | ret = mcp3564_read_8bits(adc, MCP3564_RESERVED_C_REG, val: &tmp_reg); |
1148 | if (ret < 0) |
1149 | return ret; |
1150 | |
1151 | switch (tmp_reg) { |
1152 | case MCP3564_C_REG_DEFAULT: |
1153 | adc->have_vref = false; |
1154 | break; |
1155 | case MCP3564R_C_REG_DEFAULT: |
1156 | adc->have_vref = true; |
1157 | break; |
1158 | default: |
1159 | dev_info(dev, "Unknown chip found: %d\n" , tmp_reg); |
1160 | err = true; |
1161 | } |
1162 | |
1163 | if (!err) { |
1164 | ret = mcp3564_read_16bits(adc, MCP3564_RESERVED_E_REG, val: &tmp_u16); |
1165 | if (ret < 0) |
1166 | return ret; |
1167 | |
1168 | switch (tmp_u16 & MCP3564_HW_ID_MASK) { |
1169 | case MCP3461_HW_ID: |
1170 | if (adc->have_vref) |
1171 | ids = mcp3461r; |
1172 | else |
1173 | ids = mcp3461; |
1174 | break; |
1175 | case MCP3462_HW_ID: |
1176 | if (adc->have_vref) |
1177 | ids = mcp3462r; |
1178 | else |
1179 | ids = mcp3462; |
1180 | break; |
1181 | case MCP3464_HW_ID: |
1182 | if (adc->have_vref) |
1183 | ids = mcp3464r; |
1184 | else |
1185 | ids = mcp3464; |
1186 | break; |
1187 | case MCP3561_HW_ID: |
1188 | if (adc->have_vref) |
1189 | ids = mcp3561r; |
1190 | else |
1191 | ids = mcp3561; |
1192 | break; |
1193 | case MCP3562_HW_ID: |
1194 | if (adc->have_vref) |
1195 | ids = mcp3562r; |
1196 | else |
1197 | ids = mcp3562; |
1198 | break; |
1199 | case MCP3564_HW_ID: |
1200 | if (adc->have_vref) |
1201 | ids = mcp3564r; |
1202 | else |
1203 | ids = mcp3564; |
1204 | break; |
1205 | default: |
1206 | dev_info(dev, "Unknown chip found: %d\n" , tmp_u16); |
1207 | err = true; |
1208 | } |
1209 | } |
1210 | |
1211 | if (err) { |
1212 | /* |
1213 | * If failed to identify the hardware based on internal registers, |
1214 | * try using fallback compatible in device tree to deal with some newer part number. |
1215 | */ |
1216 | adc->chip_info = spi_get_device_match_data(sdev: adc->spi); |
1217 | if (!adc->chip_info) { |
1218 | dev_id = spi_get_device_id(sdev: adc->spi); |
1219 | adc->chip_info = (const struct mcp3564_chip_info *)dev_id->driver_data; |
1220 | } |
1221 | |
1222 | adc->have_vref = adc->chip_info->have_vref; |
1223 | } else { |
1224 | adc->chip_info = &mcp3564_chip_infos_tbl[ids]; |
1225 | } |
1226 | |
1227 | dev_dbg(dev, "Found %s chip\n" , adc->chip_info->name); |
1228 | |
1229 | adc->vref = devm_regulator_get_optional(dev, id: "vref" ); |
1230 | if (IS_ERR(ptr: adc->vref)) { |
1231 | if (PTR_ERR(ptr: adc->vref) != -ENODEV) |
1232 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc->vref), |
1233 | fmt: "failed to get regulator\n" ); |
1234 | |
1235 | /* Check if chip has internal vref */ |
1236 | if (!adc->have_vref) |
1237 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc->vref), |
1238 | fmt: "Unknown Vref\n" ); |
1239 | adc->vref = NULL; |
1240 | dev_dbg(dev, "%s: Using internal Vref\n" , __func__); |
1241 | } else { |
1242 | ret = regulator_enable(regulator: adc->vref); |
1243 | if (ret) |
1244 | return ret; |
1245 | |
1246 | ret = devm_add_action_or_reset(dev, mcp3564_disable_reg, |
1247 | adc->vref); |
1248 | if (ret) |
1249 | return ret; |
1250 | |
1251 | dev_dbg(dev, "%s: Using External Vref\n" , __func__); |
1252 | |
1253 | ret = regulator_get_voltage(regulator: adc->vref); |
1254 | if (ret < 0) |
1255 | return dev_err_probe(dev, err: ret, |
1256 | fmt: "Failed to read vref regulator\n" ); |
1257 | |
1258 | adc->vref_mv = ret / MILLI; |
1259 | } |
1260 | |
1261 | ret = mcp3564_parse_fw_children(indio_dev); |
1262 | if (ret) |
1263 | return ret; |
1264 | |
1265 | /* |
1266 | * Command sequence that ensures a recovery with the desired settings |
1267 | * in any cases of loss-of-power scenario (Full Chip Reset): |
1268 | * - Write LOCK register to 0xA5 |
1269 | * - Write IRQ register to 0x03 |
1270 | * - Send "Device Full Reset" fast command |
1271 | * - Wait 1ms for "Full Reset" to complete |
1272 | */ |
1273 | ret = mcp3564_write_8bits(adc, MCP3564_LOCK_REG, MCP3564_LOCK_WRITE_ACCESS_PASSWORD); |
1274 | if (ret) |
1275 | return ret; |
1276 | |
1277 | ret = mcp3564_write_8bits(adc, MCP3564_IRQ_REG, val: 0x03); |
1278 | if (ret) |
1279 | return ret; |
1280 | |
1281 | ret = mcp3564_fast_cmd(adc, MCP3564_FASTCMD_RESET); |
1282 | if (ret) |
1283 | return ret; |
1284 | |
1285 | /* |
1286 | * After Full reset wait some time to be able to fully reset the part and place |
1287 | * it back in a default configuration. |
1288 | * From datasheet: POR (Power On Reset Time) is ~1us |
1289 | * 1ms should be enough. |
1290 | */ |
1291 | mdelay(1); |
1292 | |
1293 | /* set a gain of 1x for GAINCAL */ |
1294 | ret = mcp3564_write_24bits(adc, MCP3564_GAINCAL_REG, MCP3564_DEFAULT_GAINCAL); |
1295 | if (ret) |
1296 | return ret; |
1297 | |
1298 | adc->calib_scale = MCP3564_DEFAULT_GAINCAL; |
1299 | |
1300 | ret = mcp3564_write_24bits(adc, MCP3564_OFFSETCAL_REG, MCP3564_DEFAULT_OFFSETCAL); |
1301 | if (ret) |
1302 | return ret; |
1303 | |
1304 | ret = mcp3564_write_24bits(adc, MCP3564_TIMER_REG, MCP3564_TIMER_DEFAULT_VALUE); |
1305 | if (ret) |
1306 | return ret; |
1307 | |
1308 | ret = mcp3564_write_24bits(adc, MCP3564_SCAN_REG, |
1309 | MCP3564_SCAN_DELAY_TIME_SET(MCP3564_NO_DELAY) | |
1310 | MCP3564_SCAN_CH_SEL_SET(MCP3564_SCAN_DEFAULT_VALUE)); |
1311 | if (ret) |
1312 | return ret; |
1313 | |
1314 | ret = mcp3564_write_8bits(adc, MCP3564_MUX_REG, MCP3564_MUX_SET(MCP3564_CH0, MCP3564_CH1)); |
1315 | if (ret) |
1316 | return ret; |
1317 | |
1318 | ret = mcp3564_write_8bits(adc, MCP3564_IRQ_REG, |
1319 | FIELD_PREP(MCP3464_EN_FASTCMD_MASK, 1) | |
1320 | FIELD_PREP(MCP3464_EN_STP_MASK, 1)); |
1321 | if (ret) |
1322 | return ret; |
1323 | |
1324 | tmp_reg = FIELD_PREP(MCP3464_CONFIG3_CONV_MODE_MASK, |
1325 | MCP3464_CONFIG3_CONV_MODE_ONE_SHOT_STANDBY); |
1326 | tmp_reg |= FIELD_PREP(MCP3464_CONFIG3_DATA_FORMAT_MASK, |
1327 | MCP3464_CONFIG3_DATA_FMT_32B_SGN_EXT); |
1328 | tmp_reg |= MCP3464_CONFIG3_EN_OFFCAL_MASK; |
1329 | tmp_reg |= MCP3464_CONFIG3_EN_GAINCAL_MASK; |
1330 | |
1331 | ret = mcp3564_write_8bits(adc, MCP3564_CONFIG3_REG, val: tmp_reg); |
1332 | if (ret) |
1333 | return ret; |
1334 | |
1335 | tmp_reg = FIELD_PREP(MCP3564_CONFIG2_BOOST_CURRENT_MASK, MCP3564_BOOST_CURRENT_x1_00); |
1336 | tmp_reg |= FIELD_PREP(MCP3564_CONFIG2_HARDWARE_GAIN_MASK, 0x01); |
1337 | tmp_reg |= FIELD_PREP(MCP3564_CONFIG2_AZ_MUX_MASK, 1); |
1338 | |
1339 | ret = mcp3564_write_8bits(adc, MCP3564_CONFIG2_REG, val: tmp_reg); |
1340 | if (ret) |
1341 | return ret; |
1342 | |
1343 | adc->hwgain = 0x01; |
1344 | adc->auto_zeroing_mux = true; |
1345 | adc->auto_zeroing_ref = false; |
1346 | adc->current_boost_mode = MCP3564_BOOST_CURRENT_x1_00; |
1347 | |
1348 | tmp_reg = FIELD_PREP(MCP3564_CONFIG1_OVERSPL_RATIO_MASK, MCP3564_OVERSAMPLING_RATIO_98304); |
1349 | |
1350 | ret = mcp3564_write_8bits(adc, MCP3564_CONFIG1_REG, val: tmp_reg); |
1351 | if (ret) |
1352 | return ret; |
1353 | |
1354 | adc->oversampling = MCP3564_OVERSAMPLING_RATIO_98304; |
1355 | |
1356 | tmp_reg = FIELD_PREP(MCP3564_CONFIG0_ADC_MODE_MASK, MCP3564_ADC_MODE_STANDBY); |
1357 | tmp_reg |= FIELD_PREP(MCP3564_CONFIG0_CS_SEL_MASK, MCP3564_CONFIG0_CS_SEL_0_0_uA); |
1358 | tmp_reg |= FIELD_PREP(MCP3564_CONFIG0_CLK_SEL_MASK, MCP3564_CONFIG0_USE_INT_CLK); |
1359 | tmp_reg |= MCP3456_CONFIG0_BIT6_DEFAULT; |
1360 | |
1361 | if (!adc->vref) { |
1362 | tmp_reg |= FIELD_PREP(MCP3456_CONFIG0_VREF_MASK, 1); |
1363 | adc->vref_mv = MCP3564R_INT_VREF_MV; |
1364 | } |
1365 | |
1366 | ret = mcp3564_write_8bits(adc, MCP3564_CONFIG0_REG, val: tmp_reg); |
1367 | |
1368 | adc->burnout_mode = MCP3564_CONFIG0_CS_SEL_0_0_uA; |
1369 | |
1370 | return ret; |
1371 | } |
1372 | |
1373 | static IIO_DEVICE_ATTR(auto_zeroing_ref_enable, 0644, |
1374 | mcp3564_auto_zeroing_ref_show, |
1375 | mcp3564_auto_zeroing_ref_store, 0); |
1376 | |
1377 | static IIO_DEVICE_ATTR(auto_zeroing_mux_enable, 0644, |
1378 | mcp3564_auto_zeroing_mux_show, |
1379 | mcp3564_auto_zeroing_mux_store, 0); |
1380 | |
1381 | static struct attribute *mcp3564_attributes[] = { |
1382 | &iio_dev_attr_auto_zeroing_mux_enable.dev_attr.attr, |
1383 | NULL |
1384 | }; |
1385 | |
1386 | static struct attribute *mcp3564r_attributes[] = { |
1387 | &iio_dev_attr_auto_zeroing_mux_enable.dev_attr.attr, |
1388 | &iio_dev_attr_auto_zeroing_ref_enable.dev_attr.attr, |
1389 | NULL |
1390 | }; |
1391 | |
1392 | static struct attribute_group mcp3564_attribute_group = { |
1393 | .attrs = mcp3564_attributes, |
1394 | }; |
1395 | |
1396 | static struct attribute_group mcp3564r_attribute_group = { |
1397 | .attrs = mcp3564r_attributes, |
1398 | }; |
1399 | |
1400 | static const struct iio_info mcp3564_info = { |
1401 | .read_raw = mcp3564_read_raw, |
1402 | .read_avail = mcp3564_read_avail, |
1403 | .write_raw = mcp3564_write_raw, |
1404 | .write_raw_get_fmt = mcp3564_write_raw_get_fmt, |
1405 | .read_label = mcp3564_read_label, |
1406 | .attrs = &mcp3564_attribute_group, |
1407 | }; |
1408 | |
1409 | static const struct iio_info mcp3564r_info = { |
1410 | .read_raw = mcp3564_read_raw, |
1411 | .read_avail = mcp3564_read_avail, |
1412 | .write_raw = mcp3564_write_raw, |
1413 | .write_raw_get_fmt = mcp3564_write_raw_get_fmt, |
1414 | .read_label = mcp3564_read_label, |
1415 | .attrs = &mcp3564r_attribute_group, |
1416 | }; |
1417 | |
1418 | static int mcp3564_probe(struct spi_device *spi) |
1419 | { |
1420 | int ret; |
1421 | struct iio_dev *indio_dev; |
1422 | struct mcp3564_state *adc; |
1423 | |
1424 | indio_dev = devm_iio_device_alloc(parent: &spi->dev, sizeof_priv: sizeof(*adc)); |
1425 | if (!indio_dev) |
1426 | return -ENOMEM; |
1427 | |
1428 | adc = iio_priv(indio_dev); |
1429 | adc->spi = spi; |
1430 | |
1431 | dev_dbg(&spi->dev, "%s: probe(spi = 0x%p)\n" , __func__, spi); |
1432 | |
1433 | /* |
1434 | * Do any chip specific initialization, e.g: |
1435 | * read/write some registers |
1436 | * enable/disable certain channels |
1437 | * change the sampling rate to the requested value |
1438 | */ |
1439 | ret = mcp3564_config(indio_dev); |
1440 | if (ret) |
1441 | return dev_err_probe(dev: &spi->dev, err: ret, |
1442 | fmt: "Can't configure MCP356X device\n" ); |
1443 | |
1444 | dev_dbg(&spi->dev, "%s: Vref (mV): %d\n" , __func__, adc->vref_mv); |
1445 | |
1446 | mcp3564_fill_scale_tbls(adc); |
1447 | |
1448 | indio_dev->name = adc->chip_info->name; |
1449 | indio_dev->modes = INDIO_DIRECT_MODE; |
1450 | |
1451 | if (!adc->vref) |
1452 | indio_dev->info = &mcp3564r_info; |
1453 | else |
1454 | indio_dev->info = &mcp3564_info; |
1455 | |
1456 | mutex_init(&adc->lock); |
1457 | |
1458 | ret = devm_iio_device_register(&spi->dev, indio_dev); |
1459 | if (ret) |
1460 | return dev_err_probe(dev: &spi->dev, err: ret, |
1461 | fmt: "Can't register IIO device\n" ); |
1462 | |
1463 | return 0; |
1464 | } |
1465 | |
1466 | static const struct of_device_id mcp3564_dt_ids[] = { |
1467 | { .compatible = "microchip,mcp3461" , .data = &mcp3564_chip_infos_tbl[mcp3461] }, |
1468 | { .compatible = "microchip,mcp3462" , .data = &mcp3564_chip_infos_tbl[mcp3462] }, |
1469 | { .compatible = "microchip,mcp3464" , .data = &mcp3564_chip_infos_tbl[mcp3464] }, |
1470 | { .compatible = "microchip,mcp3561" , .data = &mcp3564_chip_infos_tbl[mcp3561] }, |
1471 | { .compatible = "microchip,mcp3562" , .data = &mcp3564_chip_infos_tbl[mcp3562] }, |
1472 | { .compatible = "microchip,mcp3564" , .data = &mcp3564_chip_infos_tbl[mcp3564] }, |
1473 | { .compatible = "microchip,mcp3461r" , .data = &mcp3564_chip_infos_tbl[mcp3461r] }, |
1474 | { .compatible = "microchip,mcp3462r" , .data = &mcp3564_chip_infos_tbl[mcp3462r] }, |
1475 | { .compatible = "microchip,mcp3464r" , .data = &mcp3564_chip_infos_tbl[mcp3464r] }, |
1476 | { .compatible = "microchip,mcp3561r" , .data = &mcp3564_chip_infos_tbl[mcp3561r] }, |
1477 | { .compatible = "microchip,mcp3562r" , .data = &mcp3564_chip_infos_tbl[mcp3562r] }, |
1478 | { .compatible = "microchip,mcp3564r" , .data = &mcp3564_chip_infos_tbl[mcp3564r] }, |
1479 | { } |
1480 | }; |
1481 | MODULE_DEVICE_TABLE(of, mcp3564_dt_ids); |
1482 | |
1483 | static const struct spi_device_id mcp3564_id[] = { |
1484 | { "mcp3461" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3461] }, |
1485 | { "mcp3462" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3462] }, |
1486 | { "mcp3464" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3464] }, |
1487 | { "mcp3561" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3561] }, |
1488 | { "mcp3562" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3562] }, |
1489 | { "mcp3564" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3564] }, |
1490 | { "mcp3461r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3461r] }, |
1491 | { "mcp3462r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3462r] }, |
1492 | { "mcp3464r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3464r] }, |
1493 | { "mcp3561r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3561r] }, |
1494 | { "mcp3562r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3562r] }, |
1495 | { "mcp3564r" , (kernel_ulong_t)&mcp3564_chip_infos_tbl[mcp3564r] }, |
1496 | { } |
1497 | }; |
1498 | MODULE_DEVICE_TABLE(spi, mcp3564_id); |
1499 | |
1500 | static struct spi_driver mcp3564_driver = { |
1501 | .driver = { |
1502 | .name = "mcp3564" , |
1503 | .of_match_table = mcp3564_dt_ids, |
1504 | }, |
1505 | .probe = mcp3564_probe, |
1506 | .id_table = mcp3564_id, |
1507 | }; |
1508 | |
1509 | module_spi_driver(mcp3564_driver); |
1510 | |
1511 | MODULE_AUTHOR("Marius Cristea <marius.cristea@microchip.com>" ); |
1512 | MODULE_DESCRIPTION("Microchip MCP346x/MCP346xR and MCP356x/MCP356xR ADCs" ); |
1513 | MODULE_LICENSE("GPL v2" ); |
1514 | |