1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for Microchip MCP3911, Two-channel Analog Front End |
4 | * |
5 | * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com> |
6 | * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se> |
7 | */ |
8 | #include <linux/bitfield.h> |
9 | #include <linux/bits.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/err.h> |
13 | #include <linux/module.h> |
14 | #include <linux/mod_devicetable.h> |
15 | #include <linux/property.h> |
16 | #include <linux/regulator/consumer.h> |
17 | #include <linux/spi/spi.h> |
18 | |
19 | #include <linux/iio/iio.h> |
20 | #include <linux/iio/buffer.h> |
21 | #include <linux/iio/triggered_buffer.h> |
22 | #include <linux/iio/trigger_consumer.h> |
23 | #include <linux/iio/trigger.h> |
24 | |
25 | #include <asm/unaligned.h> |
26 | |
27 | #define MCP3911_REG_CHANNEL0 0x00 |
28 | #define MCP3911_REG_CHANNEL1 0x03 |
29 | #define MCP3911_REG_MOD 0x06 |
30 | #define MCP3911_REG_PHASE 0x07 |
31 | #define MCP3911_REG_GAIN 0x09 |
32 | #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch)) |
33 | #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch)) |
34 | |
35 | #define MCP3911_REG_STATUSCOM 0x0a |
36 | #define MCP3911_STATUSCOM_DRHIZ BIT(12) |
37 | #define MCP3911_STATUSCOM_READ GENMASK(7, 6) |
38 | #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) |
39 | #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) |
40 | #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) |
41 | #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) |
42 | |
43 | #define MCP3911_REG_CONFIG 0x0c |
44 | #define MCP3911_CONFIG_CLKEXT BIT(1) |
45 | #define MCP3911_CONFIG_VREFEXT BIT(2) |
46 | #define MCP3911_CONFIG_OSR GENMASK(13, 11) |
47 | |
48 | #define MCP3911_REG_OFFCAL_CH0 0x0e |
49 | #define MCP3911_REG_GAINCAL_CH0 0x11 |
50 | #define MCP3911_REG_OFFCAL_CH1 0x14 |
51 | #define MCP3911_REG_GAINCAL_CH1 0x17 |
52 | #define MCP3911_REG_VREFCAL 0x1a |
53 | |
54 | #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3) |
55 | #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6) |
56 | |
57 | /* Internal voltage reference in mV */ |
58 | #define MCP3911_INT_VREF_MV 1200 |
59 | |
60 | #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff) |
61 | #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) |
62 | #define MCP3911_REG_MASK GENMASK(4, 1) |
63 | |
64 | #define MCP3911_NUM_SCALES 6 |
65 | |
66 | /* Registers compatible with MCP3910 */ |
67 | #define MCP3910_REG_STATUSCOM 0x0c |
68 | #define MCP3910_STATUSCOM_READ GENMASK(23, 22) |
69 | #define MCP3910_STATUSCOM_DRHIZ BIT(20) |
70 | |
71 | #define MCP3910_REG_GAIN 0x0b |
72 | |
73 | #define MCP3910_REG_CONFIG0 0x0d |
74 | #define MCP3910_CONFIG0_EN_OFFCAL BIT(23) |
75 | #define MCP3910_CONFIG0_OSR GENMASK(15, 13) |
76 | |
77 | #define MCP3910_REG_CONFIG1 0x0e |
78 | #define MCP3910_CONFIG1_CLKEXT BIT(6) |
79 | #define MCP3910_CONFIG1_VREFEXT BIT(7) |
80 | |
81 | #define MCP3910_REG_OFFCAL_CH0 0x0f |
82 | #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6) |
83 | |
84 | /* Maximal number of channels used by the MCP39XX family */ |
85 | #define MCP39XX_MAX_NUM_CHANNELS 8 |
86 | |
87 | static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; |
88 | static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2]; |
89 | |
90 | enum mcp3911_id { |
91 | MCP3910, |
92 | MCP3911, |
93 | MCP3912, |
94 | MCP3913, |
95 | MCP3914, |
96 | MCP3918, |
97 | MCP3919, |
98 | }; |
99 | |
100 | struct mcp3911; |
101 | struct mcp3911_chip_info { |
102 | const struct iio_chan_spec *channels; |
103 | unsigned int num_channels; |
104 | |
105 | int (*config)(struct mcp3911 *adc); |
106 | int (*get_osr)(struct mcp3911 *adc, u32 *val); |
107 | int (*set_osr)(struct mcp3911 *adc, u32 val); |
108 | int (*enable_offset)(struct mcp3911 *adc, bool enable); |
109 | int (*get_offset)(struct mcp3911 *adc, int channel, int *val); |
110 | int (*set_offset)(struct mcp3911 *adc, int channel, int val); |
111 | int (*set_scale)(struct mcp3911 *adc, int channel, u32 val); |
112 | }; |
113 | |
114 | struct mcp3911 { |
115 | struct spi_device *spi; |
116 | struct mutex lock; |
117 | struct regulator *vref; |
118 | struct clk *clki; |
119 | u32 dev_addr; |
120 | struct iio_trigger *trig; |
121 | u32 gain[MCP39XX_MAX_NUM_CHANNELS]; |
122 | const struct mcp3911_chip_info *chip; |
123 | struct { |
124 | u32 channels[MCP39XX_MAX_NUM_CHANNELS]; |
125 | s64 ts __aligned(8); |
126 | } scan; |
127 | |
128 | u8 tx_buf __aligned(IIO_DMA_MINALIGN); |
129 | u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3]; |
130 | }; |
131 | |
132 | static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) |
133 | { |
134 | int ret; |
135 | |
136 | reg = MCP3911_REG_READ(reg, adc->dev_addr); |
137 | ret = spi_write_then_read(spi: adc->spi, txbuf: ®, n_tx: 1, rxbuf: val, n_rx: len); |
138 | if (ret < 0) |
139 | return ret; |
140 | |
141 | be32_to_cpus(val); |
142 | *val >>= ((4 - len) * 8); |
143 | dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n" , *val, |
144 | FIELD_GET(MCP3911_REG_MASK, reg)); |
145 | return ret; |
146 | } |
147 | |
148 | static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) |
149 | { |
150 | dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n" , val, reg); |
151 | |
152 | val <<= (3 - len) * 8; |
153 | cpu_to_be32s(&val); |
154 | val |= MCP3911_REG_WRITE(reg, adc->dev_addr); |
155 | |
156 | return spi_write(spi: adc->spi, buf: &val, len: len + 1); |
157 | } |
158 | |
159 | static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) |
160 | { |
161 | u32 tmp; |
162 | int ret; |
163 | |
164 | ret = mcp3911_read(adc, reg, val: &tmp, len); |
165 | if (ret) |
166 | return ret; |
167 | |
168 | val &= mask; |
169 | val |= tmp & ~mask; |
170 | return mcp3911_write(adc, reg, val, len); |
171 | } |
172 | |
173 | static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) |
174 | { |
175 | unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; |
176 | unsigned int value = enable ? mask : 0; |
177 | |
178 | return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, val: value, len: 3); |
179 | } |
180 | |
181 | static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) |
182 | { |
183 | return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, len: 3); |
184 | } |
185 | |
186 | static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) |
187 | { |
188 | int ret; |
189 | |
190 | ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, len: 3); |
191 | if (ret) |
192 | return ret; |
193 | |
194 | return adc->chip->enable_offset(adc, 1); |
195 | } |
196 | |
197 | static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) |
198 | { |
199 | unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; |
200 | unsigned int value = enable ? mask : 0; |
201 | |
202 | return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, val: value, len: 2); |
203 | } |
204 | |
205 | static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) |
206 | { |
207 | return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, len: 3); |
208 | } |
209 | |
210 | static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) |
211 | { |
212 | int ret; |
213 | |
214 | ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, len: 3); |
215 | if (ret) |
216 | return ret; |
217 | |
218 | return adc->chip->enable_offset(adc, 1); |
219 | } |
220 | |
221 | static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) |
222 | { |
223 | int ret; |
224 | unsigned int osr; |
225 | |
226 | ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, len: 3); |
227 | if (ret) |
228 | return ret; |
229 | |
230 | osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); |
231 | *val = 32 << osr; |
232 | return 0; |
233 | } |
234 | |
235 | static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) |
236 | { |
237 | unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); |
238 | unsigned int mask = MCP3910_CONFIG0_OSR; |
239 | |
240 | return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, val: osr, len: 3); |
241 | } |
242 | |
243 | static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) |
244 | { |
245 | unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); |
246 | unsigned int mask = MCP3911_CONFIG_OSR; |
247 | |
248 | return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, val: osr, len: 2); |
249 | } |
250 | |
251 | static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) |
252 | { |
253 | int ret; |
254 | unsigned int osr; |
255 | |
256 | ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, len: 2); |
257 | if (ret) |
258 | return ret; |
259 | |
260 | osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); |
261 | *val = 32 << osr; |
262 | return ret; |
263 | } |
264 | |
265 | static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) |
266 | { |
267 | return mcp3911_update(adc, MCP3910_REG_GAIN, |
268 | MCP3911_GAIN_MASK(channel), |
269 | MCP3911_GAIN_VAL(channel, val), len: 3); |
270 | } |
271 | |
272 | static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) |
273 | { |
274 | return mcp3911_update(adc, MCP3911_REG_GAIN, |
275 | MCP3911_GAIN_MASK(channel), |
276 | MCP3911_GAIN_VAL(channel, val), len: 1); |
277 | } |
278 | |
279 | static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, |
280 | struct iio_chan_spec const *chan, |
281 | long mask) |
282 | { |
283 | switch (mask) { |
284 | case IIO_CHAN_INFO_SCALE: |
285 | return IIO_VAL_INT_PLUS_NANO; |
286 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
287 | return IIO_VAL_INT; |
288 | default: |
289 | return IIO_VAL_INT_PLUS_NANO; |
290 | } |
291 | } |
292 | |
293 | static int mcp3911_read_avail(struct iio_dev *indio_dev, |
294 | struct iio_chan_spec const *chan, |
295 | const int **vals, int *type, int *length, |
296 | long info) |
297 | { |
298 | switch (info) { |
299 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
300 | *type = IIO_VAL_INT; |
301 | *vals = mcp3911_osr_table; |
302 | *length = ARRAY_SIZE(mcp3911_osr_table); |
303 | return IIO_AVAIL_LIST; |
304 | case IIO_CHAN_INFO_SCALE: |
305 | *type = IIO_VAL_INT_PLUS_NANO; |
306 | *vals = (int *)mcp3911_scale_table; |
307 | *length = ARRAY_SIZE(mcp3911_scale_table) * 2; |
308 | return IIO_AVAIL_LIST; |
309 | default: |
310 | return -EINVAL; |
311 | } |
312 | } |
313 | |
314 | static int mcp3911_read_raw(struct iio_dev *indio_dev, |
315 | struct iio_chan_spec const *channel, int *val, |
316 | int *val2, long mask) |
317 | { |
318 | struct mcp3911 *adc = iio_priv(indio_dev); |
319 | int ret = -EINVAL; |
320 | |
321 | mutex_lock(&adc->lock); |
322 | switch (mask) { |
323 | case IIO_CHAN_INFO_RAW: |
324 | ret = mcp3911_read(adc, |
325 | MCP3911_CHANNEL(channel->channel), val, len: 3); |
326 | if (ret) |
327 | goto out; |
328 | |
329 | *val = sign_extend32(value: *val, index: 23); |
330 | |
331 | ret = IIO_VAL_INT; |
332 | break; |
333 | |
334 | case IIO_CHAN_INFO_OFFSET: |
335 | |
336 | ret = adc->chip->get_offset(adc, channel->channel, val); |
337 | if (ret) |
338 | goto out; |
339 | |
340 | ret = IIO_VAL_INT; |
341 | break; |
342 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
343 | ret = adc->chip->get_osr(adc, val); |
344 | if (ret) |
345 | goto out; |
346 | |
347 | ret = IIO_VAL_INT; |
348 | break; |
349 | |
350 | case IIO_CHAN_INFO_SCALE: |
351 | *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0]; |
352 | *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1]; |
353 | ret = IIO_VAL_INT_PLUS_NANO; |
354 | break; |
355 | } |
356 | |
357 | out: |
358 | mutex_unlock(lock: &adc->lock); |
359 | return ret; |
360 | } |
361 | |
362 | static int mcp3911_write_raw(struct iio_dev *indio_dev, |
363 | struct iio_chan_spec const *channel, int val, |
364 | int val2, long mask) |
365 | { |
366 | struct mcp3911 *adc = iio_priv(indio_dev); |
367 | int ret = -EINVAL; |
368 | |
369 | mutex_lock(&adc->lock); |
370 | switch (mask) { |
371 | case IIO_CHAN_INFO_SCALE: |
372 | for (int i = 0; i < MCP3911_NUM_SCALES; i++) { |
373 | if (val == mcp3911_scale_table[i][0] && |
374 | val2 == mcp3911_scale_table[i][1]) { |
375 | |
376 | adc->gain[channel->channel] = BIT(i); |
377 | ret = adc->chip->set_scale(adc, channel->channel, i); |
378 | } |
379 | } |
380 | break; |
381 | case IIO_CHAN_INFO_OFFSET: |
382 | if (val2 != 0) { |
383 | ret = -EINVAL; |
384 | goto out; |
385 | } |
386 | |
387 | ret = adc->chip->set_offset(adc, channel->channel, val); |
388 | break; |
389 | |
390 | case IIO_CHAN_INFO_OVERSAMPLING_RATIO: |
391 | for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { |
392 | if (val == mcp3911_osr_table[i]) { |
393 | ret = adc->chip->set_osr(adc, i); |
394 | break; |
395 | } |
396 | } |
397 | break; |
398 | } |
399 | |
400 | out: |
401 | mutex_unlock(lock: &adc->lock); |
402 | return ret; |
403 | } |
404 | |
405 | static int mcp3911_calc_scale_table(struct mcp3911 *adc) |
406 | { |
407 | struct device *dev = &adc->spi->dev; |
408 | u32 ref = MCP3911_INT_VREF_MV; |
409 | u32 div; |
410 | int ret; |
411 | u64 tmp; |
412 | |
413 | if (adc->vref) { |
414 | ret = regulator_get_voltage(regulator: adc->vref); |
415 | if (ret < 0) { |
416 | return dev_err_probe(dev, err: ret, fmt: "failed to get vref voltage\n" ); |
417 | } |
418 | |
419 | ref = ret / 1000; |
420 | } |
421 | |
422 | /* |
423 | * For 24-bit Conversion |
424 | * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5 |
425 | * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5) |
426 | * |
427 | * ref = Reference voltage |
428 | * div = (2^23 * 1.5 * gain) = 12582912 * gain |
429 | */ |
430 | for (int i = 0; i < MCP3911_NUM_SCALES; i++) { |
431 | div = 12582912 * BIT(i); |
432 | tmp = div_s64(dividend: (s64)ref * 1000000000LL, divisor: div); |
433 | |
434 | mcp3911_scale_table[i][0] = 0; |
435 | mcp3911_scale_table[i][1] = tmp; |
436 | } |
437 | |
438 | return 0; |
439 | } |
440 | |
441 | #define MCP3911_CHAN(idx) { \ |
442 | .type = IIO_VOLTAGE, \ |
443 | .indexed = 1, \ |
444 | .channel = idx, \ |
445 | .scan_index = idx, \ |
446 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ |
447 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ |
448 | BIT(IIO_CHAN_INFO_OFFSET) | \ |
449 | BIT(IIO_CHAN_INFO_SCALE), \ |
450 | .info_mask_shared_by_type_available = \ |
451 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ |
452 | .info_mask_separate_available = \ |
453 | BIT(IIO_CHAN_INFO_SCALE), \ |
454 | .scan_type = { \ |
455 | .sign = 's', \ |
456 | .realbits = 24, \ |
457 | .storagebits = 32, \ |
458 | .endianness = IIO_BE, \ |
459 | }, \ |
460 | } |
461 | |
462 | static const struct iio_chan_spec mcp3910_channels[] = { |
463 | MCP3911_CHAN(0), |
464 | MCP3911_CHAN(1), |
465 | IIO_CHAN_SOFT_TIMESTAMP(2), |
466 | }; |
467 | |
468 | static const struct iio_chan_spec mcp3911_channels[] = { |
469 | MCP3911_CHAN(0), |
470 | MCP3911_CHAN(1), |
471 | IIO_CHAN_SOFT_TIMESTAMP(2), |
472 | }; |
473 | |
474 | static const struct iio_chan_spec mcp3912_channels[] = { |
475 | MCP3911_CHAN(0), |
476 | MCP3911_CHAN(1), |
477 | MCP3911_CHAN(2), |
478 | MCP3911_CHAN(3), |
479 | IIO_CHAN_SOFT_TIMESTAMP(4), |
480 | }; |
481 | |
482 | static const struct iio_chan_spec mcp3913_channels[] = { |
483 | MCP3911_CHAN(0), |
484 | MCP3911_CHAN(1), |
485 | MCP3911_CHAN(2), |
486 | MCP3911_CHAN(3), |
487 | MCP3911_CHAN(4), |
488 | MCP3911_CHAN(5), |
489 | IIO_CHAN_SOFT_TIMESTAMP(6), |
490 | }; |
491 | |
492 | static const struct iio_chan_spec mcp3914_channels[] = { |
493 | MCP3911_CHAN(0), |
494 | MCP3911_CHAN(1), |
495 | MCP3911_CHAN(2), |
496 | MCP3911_CHAN(3), |
497 | MCP3911_CHAN(4), |
498 | MCP3911_CHAN(5), |
499 | MCP3911_CHAN(6), |
500 | MCP3911_CHAN(7), |
501 | IIO_CHAN_SOFT_TIMESTAMP(8), |
502 | }; |
503 | |
504 | static const struct iio_chan_spec mcp3918_channels[] = { |
505 | MCP3911_CHAN(0), |
506 | IIO_CHAN_SOFT_TIMESTAMP(1), |
507 | }; |
508 | |
509 | static const struct iio_chan_spec mcp3919_channels[] = { |
510 | MCP3911_CHAN(0), |
511 | MCP3911_CHAN(1), |
512 | MCP3911_CHAN(2), |
513 | IIO_CHAN_SOFT_TIMESTAMP(3), |
514 | }; |
515 | |
516 | static irqreturn_t mcp3911_trigger_handler(int irq, void *p) |
517 | { |
518 | struct iio_poll_func *pf = p; |
519 | struct iio_dev *indio_dev = pf->indio_dev; |
520 | struct mcp3911 *adc = iio_priv(indio_dev); |
521 | struct device *dev = &adc->spi->dev; |
522 | struct spi_transfer xfer[] = { |
523 | { |
524 | .tx_buf = &adc->tx_buf, |
525 | .len = 1, |
526 | }, { |
527 | .rx_buf = adc->rx_buf, |
528 | .len = (adc->chip->num_channels - 1) * 3, |
529 | }, |
530 | }; |
531 | int scan_index; |
532 | int i = 0; |
533 | int ret; |
534 | |
535 | mutex_lock(&adc->lock); |
536 | adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); |
537 | ret = spi_sync_transfer(spi: adc->spi, xfers: xfer, ARRAY_SIZE(xfer)); |
538 | if (ret < 0) { |
539 | dev_warn(dev, "failed to get conversion data\n" ); |
540 | goto out; |
541 | } |
542 | |
543 | for_each_set_bit(scan_index, indio_dev->active_scan_mask, indio_dev->masklength) { |
544 | const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index]; |
545 | |
546 | adc->scan.channels[i] = get_unaligned_be24(p: &adc->rx_buf[scan_chan->channel * 3]); |
547 | i++; |
548 | } |
549 | iio_push_to_buffers_with_timestamp(indio_dev, data: &adc->scan, |
550 | timestamp: iio_get_time_ns(indio_dev)); |
551 | out: |
552 | mutex_unlock(lock: &adc->lock); |
553 | iio_trigger_notify_done(trig: indio_dev->trig); |
554 | |
555 | return IRQ_HANDLED; |
556 | } |
557 | |
558 | static const struct iio_info mcp3911_info = { |
559 | .read_raw = mcp3911_read_raw, |
560 | .write_raw = mcp3911_write_raw, |
561 | .read_avail = mcp3911_read_avail, |
562 | .write_raw_get_fmt = mcp3911_write_raw_get_fmt, |
563 | }; |
564 | |
565 | static int mcp3911_config(struct mcp3911 *adc) |
566 | { |
567 | struct device *dev = &adc->spi->dev; |
568 | u32 regval; |
569 | int ret; |
570 | |
571 | ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val: ®val, len: 2); |
572 | if (ret) |
573 | return ret; |
574 | |
575 | regval &= ~MCP3911_CONFIG_VREFEXT; |
576 | if (adc->vref) { |
577 | dev_dbg(dev, "use external voltage reference\n" ); |
578 | regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); |
579 | } else { |
580 | dev_dbg(dev, "use internal voltage reference (1.2V)\n" ); |
581 | regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); |
582 | } |
583 | |
584 | regval &= ~MCP3911_CONFIG_CLKEXT; |
585 | if (adc->clki) { |
586 | dev_dbg(dev, "use external clock as clocksource\n" ); |
587 | regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); |
588 | } else { |
589 | dev_dbg(dev, "use crystal oscillator as clocksource\n" ); |
590 | regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); |
591 | } |
592 | |
593 | ret = mcp3911_write(adc, MCP3911_REG_CONFIG, val: regval, len: 2); |
594 | if (ret) |
595 | return ret; |
596 | |
597 | ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, val: ®val, len: 2); |
598 | if (ret) |
599 | return ret; |
600 | |
601 | /* Address counter incremented, cycle through register types */ |
602 | regval &= ~MCP3911_STATUSCOM_READ; |
603 | regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); |
604 | |
605 | regval &= ~MCP3911_STATUSCOM_DRHIZ; |
606 | if (device_property_read_bool(dev, propname: "microchip,data-ready-hiz" )) |
607 | regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0); |
608 | else |
609 | regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1); |
610 | |
611 | /* Disable offset to ignore any old values in offset register */ |
612 | regval &= ~MCP3911_STATUSCOM_EN_OFFCAL; |
613 | |
614 | ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, val: regval, len: 2); |
615 | if (ret) |
616 | return ret; |
617 | |
618 | /* Set gain to 1 for all channels */ |
619 | ret = mcp3911_read(adc, MCP3911_REG_GAIN, val: ®val, len: 1); |
620 | if (ret) |
621 | return ret; |
622 | |
623 | for (int i = 0; i < adc->chip->num_channels - 1; i++) { |
624 | adc->gain[i] = 1; |
625 | regval &= ~MCP3911_GAIN_MASK(i); |
626 | } |
627 | |
628 | return mcp3911_write(adc, MCP3911_REG_GAIN, val: regval, len: 1); |
629 | } |
630 | |
631 | static int mcp3910_config(struct mcp3911 *adc) |
632 | { |
633 | struct device *dev = &adc->spi->dev; |
634 | u32 regval; |
635 | int ret; |
636 | |
637 | ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, val: ®val, len: 3); |
638 | if (ret) |
639 | return ret; |
640 | |
641 | regval &= ~MCP3910_CONFIG1_VREFEXT; |
642 | if (adc->vref) { |
643 | dev_dbg(dev, "use external voltage reference\n" ); |
644 | regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1); |
645 | } else { |
646 | dev_dbg(dev, "use internal voltage reference (1.2V)\n" ); |
647 | regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0); |
648 | } |
649 | |
650 | regval &= ~MCP3910_CONFIG1_CLKEXT; |
651 | if (adc->clki) { |
652 | dev_dbg(dev, "use external clock as clocksource\n" ); |
653 | regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1); |
654 | } else { |
655 | dev_dbg(dev, "use crystal oscillator as clocksource\n" ); |
656 | regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0); |
657 | } |
658 | |
659 | ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, val: regval, len: 3); |
660 | if (ret) |
661 | return ret; |
662 | |
663 | ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, val: ®val, len: 3); |
664 | if (ret) |
665 | return ret; |
666 | |
667 | /* Address counter incremented, cycle through register types */ |
668 | regval &= ~MCP3910_STATUSCOM_READ; |
669 | regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02); |
670 | |
671 | regval &= ~MCP3910_STATUSCOM_DRHIZ; |
672 | if (device_property_read_bool(dev, propname: "microchip,data-ready-hiz" )) |
673 | regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0); |
674 | else |
675 | regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1); |
676 | |
677 | ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, val: regval, len: 3); |
678 | if (ret) |
679 | return ret; |
680 | |
681 | /* Set gain to 1 for all channels */ |
682 | ret = mcp3911_read(adc, MCP3910_REG_GAIN, val: ®val, len: 3); |
683 | if (ret) |
684 | return ret; |
685 | |
686 | for (int i = 0; i < adc->chip->num_channels - 1; i++) { |
687 | adc->gain[i] = 1; |
688 | regval &= ~MCP3911_GAIN_MASK(i); |
689 | } |
690 | ret = mcp3911_write(adc, MCP3910_REG_GAIN, val: regval, len: 3); |
691 | if (ret) |
692 | return ret; |
693 | |
694 | /* Disable offset to ignore any old values in offset register */ |
695 | return adc->chip->enable_offset(adc, 0); |
696 | } |
697 | |
698 | static void mcp3911_cleanup_regulator(void *vref) |
699 | { |
700 | regulator_disable(regulator: vref); |
701 | } |
702 | |
703 | static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable) |
704 | { |
705 | struct mcp3911 *adc = iio_trigger_get_drvdata(trig); |
706 | |
707 | if (enable) |
708 | enable_irq(irq: adc->spi->irq); |
709 | else |
710 | disable_irq(irq: adc->spi->irq); |
711 | |
712 | return 0; |
713 | } |
714 | |
715 | static const struct iio_trigger_ops mcp3911_trigger_ops = { |
716 | .validate_device = iio_trigger_validate_own_device, |
717 | .set_trigger_state = mcp3911_set_trigger_state, |
718 | }; |
719 | |
720 | static int mcp3911_probe(struct spi_device *spi) |
721 | { |
722 | struct device *dev = &spi->dev; |
723 | struct iio_dev *indio_dev; |
724 | struct mcp3911 *adc; |
725 | int ret; |
726 | |
727 | indio_dev = devm_iio_device_alloc(parent: dev, sizeof_priv: sizeof(*adc)); |
728 | if (!indio_dev) |
729 | return -ENOMEM; |
730 | |
731 | adc = iio_priv(indio_dev); |
732 | adc->spi = spi; |
733 | adc->chip = spi_get_device_match_data(sdev: spi); |
734 | |
735 | adc->vref = devm_regulator_get_optional(dev, id: "vref" ); |
736 | if (IS_ERR(ptr: adc->vref)) { |
737 | if (PTR_ERR(ptr: adc->vref) == -ENODEV) { |
738 | adc->vref = NULL; |
739 | } else { |
740 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc->vref), fmt: "failed to get regulator\n" ); |
741 | } |
742 | |
743 | } else { |
744 | ret = regulator_enable(regulator: adc->vref); |
745 | if (ret) |
746 | return ret; |
747 | |
748 | ret = devm_add_action_or_reset(dev, mcp3911_cleanup_regulator, adc->vref); |
749 | if (ret) |
750 | return ret; |
751 | } |
752 | |
753 | adc->clki = devm_clk_get_enabled(dev, NULL); |
754 | if (IS_ERR(ptr: adc->clki)) { |
755 | if (PTR_ERR(ptr: adc->clki) == -ENOENT) { |
756 | adc->clki = NULL; |
757 | } else { |
758 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc->clki), fmt: "failed to get adc clk\n" ); |
759 | } |
760 | } |
761 | |
762 | /* |
763 | * Fallback to "device-addr" due to historical mismatch between |
764 | * dt-bindings and implementation. |
765 | */ |
766 | ret = device_property_read_u32(dev, propname: "microchip,device-addr" , val: &adc->dev_addr); |
767 | if (ret) |
768 | device_property_read_u32(dev, propname: "device-addr" , val: &adc->dev_addr); |
769 | if (adc->dev_addr > 3) { |
770 | return dev_err_probe(dev, err: -EINVAL, |
771 | fmt: "invalid device address (%i). Must be in range 0-3.\n" , |
772 | adc->dev_addr); |
773 | } |
774 | dev_dbg(dev, "use device address %i\n" , adc->dev_addr); |
775 | |
776 | ret = adc->chip->config(adc); |
777 | if (ret) |
778 | return ret; |
779 | |
780 | ret = mcp3911_calc_scale_table(adc); |
781 | if (ret) |
782 | return ret; |
783 | |
784 | /* Set gain to 1 for all channels */ |
785 | for (int i = 0; i < adc->chip->num_channels - 1; i++) { |
786 | adc->gain[i] = 1; |
787 | ret = mcp3911_update(adc, MCP3911_REG_GAIN, |
788 | MCP3911_GAIN_MASK(i), |
789 | MCP3911_GAIN_VAL(i, 0), len: 1); |
790 | if (ret) |
791 | return ret; |
792 | } |
793 | |
794 | indio_dev->name = spi_get_device_id(sdev: spi)->name; |
795 | indio_dev->modes = INDIO_DIRECT_MODE; |
796 | indio_dev->info = &mcp3911_info; |
797 | spi_set_drvdata(spi, data: indio_dev); |
798 | |
799 | indio_dev->channels = adc->chip->channels; |
800 | indio_dev->num_channels = adc->chip->num_channels; |
801 | |
802 | mutex_init(&adc->lock); |
803 | |
804 | if (spi->irq > 0) { |
805 | adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d" , indio_dev->name, |
806 | iio_device_id(indio_dev)); |
807 | if (!adc->trig) |
808 | return -ENOMEM; |
809 | |
810 | adc->trig->ops = &mcp3911_trigger_ops; |
811 | iio_trigger_set_drvdata(trig: adc->trig, data: adc); |
812 | ret = devm_iio_trigger_register(dev, trig_info: adc->trig); |
813 | if (ret) |
814 | return ret; |
815 | |
816 | /* |
817 | * The device generates interrupts as long as it is powered up. |
818 | * Some platforms might not allow the option to power it down so |
819 | * don't enable the interrupt to avoid extra load on the system. |
820 | */ |
821 | ret = devm_request_irq(dev, irq: spi->irq, handler: &iio_trigger_generic_data_rdy_poll, |
822 | IRQF_NO_AUTOEN | IRQF_ONESHOT, |
823 | devname: indio_dev->name, dev_id: adc->trig); |
824 | if (ret) |
825 | return ret; |
826 | } |
827 | |
828 | ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, |
829 | mcp3911_trigger_handler, NULL); |
830 | if (ret) |
831 | return ret; |
832 | |
833 | return devm_iio_device_register(dev, indio_dev); |
834 | } |
835 | |
836 | static const struct mcp3911_chip_info mcp3911_chip_info[] = { |
837 | [MCP3910] = { |
838 | .channels = mcp3910_channels, |
839 | .num_channels = ARRAY_SIZE(mcp3910_channels), |
840 | .config = mcp3910_config, |
841 | .get_osr = mcp3910_get_osr, |
842 | .set_osr = mcp3910_set_osr, |
843 | .enable_offset = mcp3910_enable_offset, |
844 | .get_offset = mcp3910_get_offset, |
845 | .set_offset = mcp3910_set_offset, |
846 | .set_scale = mcp3910_set_scale, |
847 | }, |
848 | [MCP3911] = { |
849 | .channels = mcp3911_channels, |
850 | .num_channels = ARRAY_SIZE(mcp3911_channels), |
851 | .config = mcp3911_config, |
852 | .get_osr = mcp3911_get_osr, |
853 | .set_osr = mcp3911_set_osr, |
854 | .enable_offset = mcp3911_enable_offset, |
855 | .get_offset = mcp3911_get_offset, |
856 | .set_offset = mcp3911_set_offset, |
857 | .set_scale = mcp3911_set_scale, |
858 | }, |
859 | [MCP3912] = { |
860 | .channels = mcp3912_channels, |
861 | .num_channels = ARRAY_SIZE(mcp3912_channels), |
862 | .config = mcp3910_config, |
863 | .get_osr = mcp3910_get_osr, |
864 | .set_osr = mcp3910_set_osr, |
865 | .enable_offset = mcp3910_enable_offset, |
866 | .get_offset = mcp3910_get_offset, |
867 | .set_offset = mcp3910_set_offset, |
868 | .set_scale = mcp3910_set_scale, |
869 | }, |
870 | [MCP3913] = { |
871 | .channels = mcp3913_channels, |
872 | .num_channels = ARRAY_SIZE(mcp3913_channels), |
873 | .config = mcp3910_config, |
874 | .get_osr = mcp3910_get_osr, |
875 | .set_osr = mcp3910_set_osr, |
876 | .enable_offset = mcp3910_enable_offset, |
877 | .get_offset = mcp3910_get_offset, |
878 | .set_offset = mcp3910_set_offset, |
879 | .set_scale = mcp3910_set_scale, |
880 | }, |
881 | [MCP3914] = { |
882 | .channels = mcp3914_channels, |
883 | .num_channels = ARRAY_SIZE(mcp3914_channels), |
884 | .config = mcp3910_config, |
885 | .get_osr = mcp3910_get_osr, |
886 | .set_osr = mcp3910_set_osr, |
887 | .enable_offset = mcp3910_enable_offset, |
888 | .get_offset = mcp3910_get_offset, |
889 | .set_offset = mcp3910_set_offset, |
890 | .set_scale = mcp3910_set_scale, |
891 | }, |
892 | [MCP3918] = { |
893 | .channels = mcp3918_channels, |
894 | .num_channels = ARRAY_SIZE(mcp3918_channels), |
895 | .config = mcp3910_config, |
896 | .get_osr = mcp3910_get_osr, |
897 | .set_osr = mcp3910_set_osr, |
898 | .enable_offset = mcp3910_enable_offset, |
899 | .get_offset = mcp3910_get_offset, |
900 | .set_offset = mcp3910_set_offset, |
901 | .set_scale = mcp3910_set_scale, |
902 | }, |
903 | [MCP3919] = { |
904 | .channels = mcp3919_channels, |
905 | .num_channels = ARRAY_SIZE(mcp3919_channels), |
906 | .config = mcp3910_config, |
907 | .get_osr = mcp3910_get_osr, |
908 | .set_osr = mcp3910_set_osr, |
909 | .enable_offset = mcp3910_enable_offset, |
910 | .get_offset = mcp3910_get_offset, |
911 | .set_offset = mcp3910_set_offset, |
912 | .set_scale = mcp3910_set_scale, |
913 | }, |
914 | }; |
915 | static const struct of_device_id mcp3911_dt_ids[] = { |
916 | { .compatible = "microchip,mcp3910" , .data = &mcp3911_chip_info[MCP3910] }, |
917 | { .compatible = "microchip,mcp3911" , .data = &mcp3911_chip_info[MCP3911] }, |
918 | { .compatible = "microchip,mcp3912" , .data = &mcp3911_chip_info[MCP3912] }, |
919 | { .compatible = "microchip,mcp3913" , .data = &mcp3911_chip_info[MCP3913] }, |
920 | { .compatible = "microchip,mcp3914" , .data = &mcp3911_chip_info[MCP3914] }, |
921 | { .compatible = "microchip,mcp3918" , .data = &mcp3911_chip_info[MCP3918] }, |
922 | { .compatible = "microchip,mcp3919" , .data = &mcp3911_chip_info[MCP3919] }, |
923 | { } |
924 | }; |
925 | MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); |
926 | |
927 | static const struct spi_device_id mcp3911_id[] = { |
928 | { "mcp3910" , (kernel_ulong_t)&mcp3911_chip_info[MCP3910] }, |
929 | { "mcp3911" , (kernel_ulong_t)&mcp3911_chip_info[MCP3911] }, |
930 | { "mcp3912" , (kernel_ulong_t)&mcp3911_chip_info[MCP3912] }, |
931 | { "mcp3913" , (kernel_ulong_t)&mcp3911_chip_info[MCP3913] }, |
932 | { "mcp3914" , (kernel_ulong_t)&mcp3911_chip_info[MCP3914] }, |
933 | { "mcp3918" , (kernel_ulong_t)&mcp3911_chip_info[MCP3918] }, |
934 | { "mcp3919" , (kernel_ulong_t)&mcp3911_chip_info[MCP3919] }, |
935 | { } |
936 | }; |
937 | MODULE_DEVICE_TABLE(spi, mcp3911_id); |
938 | |
939 | static struct spi_driver mcp3911_driver = { |
940 | .driver = { |
941 | .name = "mcp3911" , |
942 | .of_match_table = mcp3911_dt_ids, |
943 | }, |
944 | .probe = mcp3911_probe, |
945 | .id_table = mcp3911_id, |
946 | }; |
947 | module_spi_driver(mcp3911_driver); |
948 | |
949 | MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>" ); |
950 | MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>" ); |
951 | MODULE_DESCRIPTION("Microchip Technology MCP3911" ); |
952 | MODULE_LICENSE("GPL v2" ); |
953 | |