1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2019 Brian Masney <masneyb@onstation.org> |
4 | * |
5 | * Based on MSM bus code from downstream MSM kernel sources. |
6 | * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. |
7 | * |
8 | * Based on qcs404.c |
9 | * Copyright (C) 2019 Linaro Ltd |
10 | * |
11 | * Here's a rough representation that shows the various buses that form the |
12 | * Network On Chip (NOC) for the msm8974: |
13 | * |
14 | * Multimedia Subsystem (MMSS) |
15 | * |----------+-----------------------------------+-----------| |
16 | * | | |
17 | * | | |
18 | * Config | Bus Interface | Memory Controller |
19 | * |------------+-+-----------| |------------+-+-----------| |
20 | * | | |
21 | * | | |
22 | * | System | |
23 | * |--------------+-+---------------------------------+-+-------------| |
24 | * | | |
25 | * | | |
26 | * Peripheral | On Chip | Memory (OCMEM) |
27 | * |------------+-------------| |------------+-------------| |
28 | */ |
29 | |
30 | #include <dt-bindings/interconnect/qcom,msm8974.h> |
31 | |
32 | #include <linux/args.h> |
33 | #include <linux/clk.h> |
34 | #include <linux/device.h> |
35 | #include <linux/interconnect-provider.h> |
36 | #include <linux/io.h> |
37 | #include <linux/module.h> |
38 | #include <linux/of.h> |
39 | #include <linux/platform_device.h> |
40 | #include <linux/slab.h> |
41 | |
42 | #include "icc-rpm.h" |
43 | |
44 | enum { |
45 | MSM8974_BIMC_MAS_AMPSS_M0 = 1, |
46 | MSM8974_BIMC_MAS_AMPSS_M1, |
47 | MSM8974_BIMC_MAS_MSS_PROC, |
48 | MSM8974_BIMC_TO_MNOC, |
49 | MSM8974_BIMC_TO_SNOC, |
50 | MSM8974_BIMC_SLV_EBI_CH0, |
51 | MSM8974_BIMC_SLV_AMPSS_L2, |
52 | MSM8974_CNOC_MAS_RPM_INST, |
53 | MSM8974_CNOC_MAS_RPM_DATA, |
54 | MSM8974_CNOC_MAS_RPM_SYS, |
55 | MSM8974_CNOC_MAS_DEHR, |
56 | MSM8974_CNOC_MAS_QDSS_DAP, |
57 | MSM8974_CNOC_MAS_SPDM, |
58 | MSM8974_CNOC_MAS_TIC, |
59 | MSM8974_CNOC_SLV_CLK_CTL, |
60 | MSM8974_CNOC_SLV_CNOC_MSS, |
61 | MSM8974_CNOC_SLV_SECURITY, |
62 | MSM8974_CNOC_SLV_TCSR, |
63 | MSM8974_CNOC_SLV_TLMM, |
64 | MSM8974_CNOC_SLV_CRYPTO_0_CFG, |
65 | MSM8974_CNOC_SLV_CRYPTO_1_CFG, |
66 | MSM8974_CNOC_SLV_IMEM_CFG, |
67 | MSM8974_CNOC_SLV_MESSAGE_RAM, |
68 | MSM8974_CNOC_SLV_BIMC_CFG, |
69 | MSM8974_CNOC_SLV_BOOT_ROM, |
70 | MSM8974_CNOC_SLV_PMIC_ARB, |
71 | MSM8974_CNOC_SLV_SPDM_WRAPPER, |
72 | MSM8974_CNOC_SLV_DEHR_CFG, |
73 | MSM8974_CNOC_SLV_MPM, |
74 | MSM8974_CNOC_SLV_QDSS_CFG, |
75 | MSM8974_CNOC_SLV_RBCPR_CFG, |
76 | MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, |
77 | MSM8974_CNOC_TO_SNOC, |
78 | MSM8974_CNOC_SLV_CNOC_ONOC_CFG, |
79 | MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, |
80 | MSM8974_CNOC_SLV_CNOC_MNOC_CFG, |
81 | MSM8974_CNOC_SLV_PNOC_CFG, |
82 | MSM8974_CNOC_SLV_SNOC_MPU_CFG, |
83 | MSM8974_CNOC_SLV_SNOC_CFG, |
84 | MSM8974_CNOC_SLV_EBI1_DLL_CFG, |
85 | MSM8974_CNOC_SLV_PHY_APU_CFG, |
86 | MSM8974_CNOC_SLV_EBI1_PHY_CFG, |
87 | MSM8974_CNOC_SLV_RPM, |
88 | MSM8974_CNOC_SLV_SERVICE_CNOC, |
89 | MSM8974_MNOC_MAS_GRAPHICS_3D, |
90 | MSM8974_MNOC_MAS_JPEG, |
91 | MSM8974_MNOC_MAS_MDP_PORT0, |
92 | MSM8974_MNOC_MAS_VIDEO_P0, |
93 | MSM8974_MNOC_MAS_VIDEO_P1, |
94 | MSM8974_MNOC_MAS_VFE, |
95 | MSM8974_MNOC_TO_CNOC, |
96 | MSM8974_MNOC_TO_BIMC, |
97 | MSM8974_MNOC_SLV_CAMERA_CFG, |
98 | MSM8974_MNOC_SLV_DISPLAY_CFG, |
99 | MSM8974_MNOC_SLV_OCMEM_CFG, |
100 | MSM8974_MNOC_SLV_CPR_CFG, |
101 | MSM8974_MNOC_SLV_CPR_XPU_CFG, |
102 | MSM8974_MNOC_SLV_MISC_CFG, |
103 | MSM8974_MNOC_SLV_MISC_XPU_CFG, |
104 | MSM8974_MNOC_SLV_VENUS_CFG, |
105 | MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, |
106 | MSM8974_MNOC_SLV_MMSS_CLK_CFG, |
107 | MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, |
108 | MSM8974_MNOC_SLV_MNOC_MPU_CFG, |
109 | MSM8974_MNOC_SLV_ONOC_MPU_CFG, |
110 | MSM8974_MNOC_SLV_SERVICE_MNOC, |
111 | MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, |
112 | MSM8974_OCMEM_MAS_JPEG_OCMEM, |
113 | MSM8974_OCMEM_MAS_MDP_OCMEM, |
114 | MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, |
115 | MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, |
116 | MSM8974_OCMEM_MAS_VFE_OCMEM, |
117 | MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, |
118 | MSM8974_OCMEM_SLV_SERVICE_ONOC, |
119 | MSM8974_OCMEM_VNOC_TO_SNOC, |
120 | MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, |
121 | MSM8974_OCMEM_VNOC_MAS_GFX3D, |
122 | MSM8974_OCMEM_SLV_OCMEM, |
123 | MSM8974_PNOC_MAS_PNOC_CFG, |
124 | MSM8974_PNOC_MAS_SDCC_1, |
125 | MSM8974_PNOC_MAS_SDCC_3, |
126 | MSM8974_PNOC_MAS_SDCC_4, |
127 | MSM8974_PNOC_MAS_SDCC_2, |
128 | MSM8974_PNOC_MAS_TSIF, |
129 | MSM8974_PNOC_MAS_BAM_DMA, |
130 | MSM8974_PNOC_MAS_BLSP_2, |
131 | MSM8974_PNOC_MAS_USB_HSIC, |
132 | MSM8974_PNOC_MAS_BLSP_1, |
133 | MSM8974_PNOC_MAS_USB_HS, |
134 | MSM8974_PNOC_TO_SNOC, |
135 | MSM8974_PNOC_SLV_SDCC_1, |
136 | MSM8974_PNOC_SLV_SDCC_3, |
137 | MSM8974_PNOC_SLV_SDCC_2, |
138 | MSM8974_PNOC_SLV_SDCC_4, |
139 | MSM8974_PNOC_SLV_TSIF, |
140 | MSM8974_PNOC_SLV_BAM_DMA, |
141 | MSM8974_PNOC_SLV_BLSP_2, |
142 | MSM8974_PNOC_SLV_USB_HSIC, |
143 | MSM8974_PNOC_SLV_BLSP_1, |
144 | MSM8974_PNOC_SLV_USB_HS, |
145 | MSM8974_PNOC_SLV_PDM, |
146 | MSM8974_PNOC_SLV_PERIPH_APU_CFG, |
147 | MSM8974_PNOC_SLV_PNOC_MPU_CFG, |
148 | MSM8974_PNOC_SLV_PRNG, |
149 | MSM8974_PNOC_SLV_SERVICE_PNOC, |
150 | MSM8974_SNOC_MAS_LPASS_AHB, |
151 | MSM8974_SNOC_MAS_QDSS_BAM, |
152 | MSM8974_SNOC_MAS_SNOC_CFG, |
153 | MSM8974_SNOC_TO_BIMC, |
154 | MSM8974_SNOC_TO_CNOC, |
155 | MSM8974_SNOC_TO_PNOC, |
156 | MSM8974_SNOC_TO_OCMEM_VNOC, |
157 | MSM8974_SNOC_MAS_CRYPTO_CORE0, |
158 | MSM8974_SNOC_MAS_CRYPTO_CORE1, |
159 | MSM8974_SNOC_MAS_LPASS_PROC, |
160 | MSM8974_SNOC_MAS_MSS, |
161 | MSM8974_SNOC_MAS_MSS_NAV, |
162 | MSM8974_SNOC_MAS_OCMEM_DMA, |
163 | MSM8974_SNOC_MAS_WCSS, |
164 | MSM8974_SNOC_MAS_QDSS_ETR, |
165 | MSM8974_SNOC_MAS_USB3, |
166 | MSM8974_SNOC_SLV_AMPSS, |
167 | MSM8974_SNOC_SLV_LPASS, |
168 | MSM8974_SNOC_SLV_USB3, |
169 | MSM8974_SNOC_SLV_WCSS, |
170 | MSM8974_SNOC_SLV_OCIMEM, |
171 | MSM8974_SNOC_SLV_SNOC_OCMEM, |
172 | MSM8974_SNOC_SLV_SERVICE_SNOC, |
173 | MSM8974_SNOC_SLV_QDSS_STM, |
174 | }; |
175 | |
176 | #define RPM_BUS_MASTER_REQ 0x73616d62 |
177 | #define RPM_BUS_SLAVE_REQ 0x766c7362 |
178 | |
179 | #define to_msm8974_icc_provider(_provider) \ |
180 | container_of(_provider, struct msm8974_icc_provider, provider) |
181 | |
182 | static const struct clk_bulk_data msm8974_icc_bus_clocks[] = { |
183 | { .id = "bus" }, |
184 | { .id = "bus_a" }, |
185 | }; |
186 | |
187 | /** |
188 | * struct msm8974_icc_provider - Qualcomm specific interconnect provider |
189 | * @provider: generic interconnect provider |
190 | * @bus_clks: the clk_bulk_data table of bus clocks |
191 | * @num_clks: the total number of clk_bulk_data entries |
192 | */ |
193 | struct msm8974_icc_provider { |
194 | struct icc_provider provider; |
195 | struct clk_bulk_data *bus_clks; |
196 | int num_clks; |
197 | }; |
198 | |
199 | #define MSM8974_ICC_MAX_LINKS 3 |
200 | |
201 | /** |
202 | * struct msm8974_icc_node - Qualcomm specific interconnect nodes |
203 | * @name: the node name used in debugfs |
204 | * @id: a unique node identifier |
205 | * @links: an array of nodes where we can go next while traversing |
206 | * @num_links: the total number of @links |
207 | * @buswidth: width of the interconnect between a node and the bus (bytes) |
208 | * @mas_rpm_id: RPM ID for devices that are bus masters |
209 | * @slv_rpm_id: RPM ID for devices that are bus slaves |
210 | * @rate: current bus clock rate in Hz |
211 | */ |
212 | struct msm8974_icc_node { |
213 | unsigned char *name; |
214 | u16 id; |
215 | u16 links[MSM8974_ICC_MAX_LINKS]; |
216 | u16 num_links; |
217 | u16 buswidth; |
218 | int mas_rpm_id; |
219 | int slv_rpm_id; |
220 | u64 rate; |
221 | }; |
222 | |
223 | struct msm8974_icc_desc { |
224 | struct msm8974_icc_node * const *nodes; |
225 | size_t num_nodes; |
226 | }; |
227 | |
228 | #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ |
229 | ...) \ |
230 | static struct msm8974_icc_node _name = { \ |
231 | .name = #_name, \ |
232 | .id = _id, \ |
233 | .buswidth = _buswidth, \ |
234 | .mas_rpm_id = _mas_rpm_id, \ |
235 | .slv_rpm_id = _slv_rpm_id, \ |
236 | .num_links = COUNT_ARGS(__VA_ARGS__), \ |
237 | .links = { __VA_ARGS__ }, \ |
238 | } |
239 | |
240 | DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1); |
241 | DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1); |
242 | DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1); |
243 | DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0); |
244 | DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0); |
245 | DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); |
246 | DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); |
247 | |
248 | static struct msm8974_icc_node * const msm8974_bimc_nodes[] = { |
249 | [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0, |
250 | [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1, |
251 | [BIMC_MAS_MSS_PROC] = &mas_mss_proc, |
252 | [BIMC_TO_MNOC] = &bimc_to_mnoc, |
253 | [BIMC_TO_SNOC] = &bimc_to_snoc, |
254 | [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0, |
255 | [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2, |
256 | }; |
257 | |
258 | static const struct msm8974_icc_desc msm8974_bimc = { |
259 | .nodes = msm8974_bimc_nodes, |
260 | .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes), |
261 | }; |
262 | |
263 | DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1); |
264 | DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1); |
265 | DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1); |
266 | DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1); |
267 | DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1); |
268 | DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1); |
269 | DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1); |
270 | DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47); |
271 | DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48); |
272 | DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49); |
273 | DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50); |
274 | DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51); |
275 | DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52); |
276 | DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53); |
277 | DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54); |
278 | DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55); |
279 | DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56); |
280 | DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57); |
281 | DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59); |
282 | DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60); |
283 | DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61); |
284 | DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62); |
285 | DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63); |
286 | DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64); |
287 | DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65); |
288 | DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75); |
289 | DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68); |
290 | DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58); |
291 | DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66); |
292 | DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69); |
293 | DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67); |
294 | DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70); |
295 | DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71); |
296 | DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72); |
297 | DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); |
298 | DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); |
299 | DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); |
300 | |
301 | static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = { |
302 | [CNOC_MAS_RPM_INST] = &mas_rpm_inst, |
303 | [CNOC_MAS_RPM_DATA] = &mas_rpm_data, |
304 | [CNOC_MAS_RPM_SYS] = &mas_rpm_sys, |
305 | [CNOC_MAS_DEHR] = &mas_dehr, |
306 | [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap, |
307 | [CNOC_MAS_SPDM] = &mas_spdm, |
308 | [CNOC_MAS_TIC] = &mas_tic, |
309 | [CNOC_SLV_CLK_CTL] = &slv_clk_ctl, |
310 | [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss, |
311 | [CNOC_SLV_SECURITY] = &slv_security, |
312 | [CNOC_SLV_TCSR] = &slv_tcsr, |
313 | [CNOC_SLV_TLMM] = &slv_tlmm, |
314 | [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, |
315 | [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg, |
316 | [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg, |
317 | [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram, |
318 | [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg, |
319 | [CNOC_SLV_BOOT_ROM] = &slv_boot_rom, |
320 | [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb, |
321 | [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper, |
322 | [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg, |
323 | [CNOC_SLV_MPM] = &slv_mpm, |
324 | [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg, |
325 | [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg, |
326 | [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg, |
327 | [CNOC_TO_SNOC] = &cnoc_to_snoc, |
328 | [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg, |
329 | [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, |
330 | [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, |
331 | [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg, |
332 | [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, |
333 | [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg, |
334 | [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg, |
335 | [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg, |
336 | [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, |
337 | [CNOC_SLV_RPM] = &slv_rpm, |
338 | [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc, |
339 | }; |
340 | |
341 | static const struct msm8974_icc_desc msm8974_cnoc = { |
342 | .nodes = msm8974_cnoc_nodes, |
343 | .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes), |
344 | }; |
345 | |
346 | DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC); |
347 | DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC); |
348 | DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC); |
349 | DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1); |
350 | DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1); |
351 | DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC); |
352 | DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1); |
353 | DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC); |
354 | DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3); |
355 | DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4); |
356 | DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5); |
357 | DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6); |
358 | DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7); |
359 | DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8); |
360 | DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9); |
361 | DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10); |
362 | DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11); |
363 | DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12); |
364 | DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13); |
365 | DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); |
366 | DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); |
367 | DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); |
368 | |
369 | static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = { |
370 | [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d, |
371 | [MNOC_MAS_JPEG] = &mas_jpeg, |
372 | [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0, |
373 | [MNOC_MAS_VIDEO_P0] = &mas_video_p0, |
374 | [MNOC_MAS_VIDEO_P1] = &mas_video_p1, |
375 | [MNOC_MAS_VFE] = &mas_vfe, |
376 | [MNOC_TO_CNOC] = &mnoc_to_cnoc, |
377 | [MNOC_TO_BIMC] = &mnoc_to_bimc, |
378 | [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg, |
379 | [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg, |
380 | [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg, |
381 | [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg, |
382 | [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg, |
383 | [MNOC_SLV_MISC_CFG] = &slv_misc_cfg, |
384 | [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg, |
385 | [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg, |
386 | [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg, |
387 | [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, |
388 | [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, |
389 | [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, |
390 | [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg, |
391 | [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc, |
392 | }; |
393 | |
394 | static const struct msm8974_icc_desc msm8974_mnoc = { |
395 | .nodes = msm8974_mnoc_nodes, |
396 | .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes), |
397 | }; |
398 | |
399 | DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM); |
400 | DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1); |
401 | DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1); |
402 | DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1); |
403 | DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1); |
404 | DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1); |
405 | DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1); |
406 | DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19); |
407 | DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18); |
408 | |
409 | /* Virtual NoC is needed for connection to OCMEM */ |
410 | DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC); |
411 | DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); |
412 | DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); |
413 | |
414 | static struct msm8974_icc_node * const msm8974_onoc_nodes[] = { |
415 | [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc, |
416 | [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem, |
417 | [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem, |
418 | [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem, |
419 | [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem, |
420 | [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem, |
421 | [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg, |
422 | [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc, |
423 | [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc, |
424 | [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc, |
425 | [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d, |
426 | [OCMEM_SLV_OCMEM] = &slv_ocmem, |
427 | }; |
428 | |
429 | static const struct msm8974_icc_desc msm8974_onoc = { |
430 | .nodes = msm8974_onoc_nodes, |
431 | .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes), |
432 | }; |
433 | |
434 | DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1); |
435 | DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC); |
436 | DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC); |
437 | DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC); |
438 | DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC); |
439 | DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC); |
440 | DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1); |
441 | DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC); |
442 | DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC); |
443 | DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC); |
444 | DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC); |
445 | DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG); |
446 | DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31); |
447 | DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32); |
448 | DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33); |
449 | DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34); |
450 | DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35); |
451 | DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36); |
452 | DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37); |
453 | DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38); |
454 | DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39); |
455 | DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40); |
456 | DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41); |
457 | DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42); |
458 | DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); |
459 | DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC); |
460 | DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); |
461 | |
462 | static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = { |
463 | [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg, |
464 | [PNOC_MAS_SDCC_1] = &mas_sdcc_1, |
465 | [PNOC_MAS_SDCC_3] = &mas_sdcc_3, |
466 | [PNOC_MAS_SDCC_4] = &mas_sdcc_4, |
467 | [PNOC_MAS_SDCC_2] = &mas_sdcc_2, |
468 | [PNOC_MAS_TSIF] = &mas_tsif, |
469 | [PNOC_MAS_BAM_DMA] = &mas_bam_dma, |
470 | [PNOC_MAS_BLSP_2] = &mas_blsp_2, |
471 | [PNOC_MAS_USB_HSIC] = &mas_usb_hsic, |
472 | [PNOC_MAS_BLSP_1] = &mas_blsp_1, |
473 | [PNOC_MAS_USB_HS] = &mas_usb_hs, |
474 | [PNOC_TO_SNOC] = &pnoc_to_snoc, |
475 | [PNOC_SLV_SDCC_1] = &slv_sdcc_1, |
476 | [PNOC_SLV_SDCC_3] = &slv_sdcc_3, |
477 | [PNOC_SLV_SDCC_2] = &slv_sdcc_2, |
478 | [PNOC_SLV_SDCC_4] = &slv_sdcc_4, |
479 | [PNOC_SLV_TSIF] = &slv_tsif, |
480 | [PNOC_SLV_BAM_DMA] = &slv_bam_dma, |
481 | [PNOC_SLV_BLSP_2] = &slv_blsp_2, |
482 | [PNOC_SLV_USB_HSIC] = &slv_usb_hsic, |
483 | [PNOC_SLV_BLSP_1] = &slv_blsp_1, |
484 | [PNOC_SLV_USB_HS] = &slv_usb_hs, |
485 | [PNOC_SLV_PDM] = &slv_pdm, |
486 | [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg, |
487 | [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg, |
488 | [PNOC_SLV_PRNG] = &slv_prng, |
489 | [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc, |
490 | }; |
491 | |
492 | static const struct msm8974_icc_desc msm8974_pnoc = { |
493 | .nodes = msm8974_pnoc_nodes, |
494 | .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes), |
495 | }; |
496 | |
497 | DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1); |
498 | DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1); |
499 | DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1); |
500 | DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC); |
501 | DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25); |
502 | DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC); |
503 | DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); |
504 | DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC); |
505 | DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1); |
506 | DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC); |
507 | DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1); |
508 | DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1); |
509 | DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1); |
510 | DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1); |
511 | DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1); |
512 | DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC); |
513 | DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20); |
514 | DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21); |
515 | DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22); |
516 | DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23); |
517 | DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26); |
518 | DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); |
519 | DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); |
520 | DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); |
521 | |
522 | static struct msm8974_icc_node * const msm8974_snoc_nodes[] = { |
523 | [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb, |
524 | [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam, |
525 | [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg, |
526 | [SNOC_TO_BIMC] = &snoc_to_bimc, |
527 | [SNOC_TO_CNOC] = &snoc_to_cnoc, |
528 | [SNOC_TO_PNOC] = &snoc_to_pnoc, |
529 | [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc, |
530 | [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0, |
531 | [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1, |
532 | [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc, |
533 | [SNOC_MAS_MSS] = &mas_mss, |
534 | [SNOC_MAS_MSS_NAV] = &mas_mss_nav, |
535 | [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma, |
536 | [SNOC_MAS_WCSS] = &mas_wcss, |
537 | [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr, |
538 | [SNOC_MAS_USB3] = &mas_usb3, |
539 | [SNOC_SLV_AMPSS] = &slv_ampss, |
540 | [SNOC_SLV_LPASS] = &slv_lpass, |
541 | [SNOC_SLV_USB3] = &slv_usb3, |
542 | [SNOC_SLV_WCSS] = &slv_wcss, |
543 | [SNOC_SLV_OCIMEM] = &slv_ocimem, |
544 | [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem, |
545 | [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc, |
546 | [SNOC_SLV_QDSS_STM] = &slv_qdss_stm, |
547 | }; |
548 | |
549 | static const struct msm8974_icc_desc msm8974_snoc = { |
550 | .nodes = msm8974_snoc_nodes, |
551 | .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes), |
552 | }; |
553 | |
554 | static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type, |
555 | char *name, int id, u64 val) |
556 | { |
557 | int ret; |
558 | |
559 | if (id == -1) |
560 | return; |
561 | |
562 | /* |
563 | * Setting the bandwidth requests for some nodes fails and this same |
564 | * behavior occurs on the downstream MSM 3.4 kernel sources based on |
565 | * errors like this in that kernel: |
566 | * |
567 | * msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource |
568 | * AXI: msm_bus_rpm_req(): RPM: Ack failed |
569 | * AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000 |
570 | * |
571 | * Since there's no publicly available documentation for this hardware, |
572 | * and the bandwidth for some nodes in the path can be set properly, |
573 | * let's not return an error. |
574 | */ |
575 | ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id, |
576 | val); |
577 | if (ret) |
578 | dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n" , |
579 | name, id, ret); |
580 | } |
581 | |
582 | static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst) |
583 | { |
584 | struct msm8974_icc_node *src_qn, *dst_qn; |
585 | struct msm8974_icc_provider *qp; |
586 | u64 sum_bw, max_peak_bw, rate; |
587 | u32 agg_avg = 0, agg_peak = 0; |
588 | struct icc_provider *provider; |
589 | struct icc_node *n; |
590 | int ret, i; |
591 | |
592 | src_qn = src->data; |
593 | dst_qn = dst->data; |
594 | provider = src->provider; |
595 | qp = to_msm8974_icc_provider(provider); |
596 | |
597 | list_for_each_entry(n, &provider->nodes, node_list) |
598 | provider->aggregate(n, 0, n->avg_bw, n->peak_bw, |
599 | &agg_avg, &agg_peak); |
600 | |
601 | sum_bw = icc_units_to_bps(agg_avg); |
602 | max_peak_bw = icc_units_to_bps(agg_peak); |
603 | |
604 | /* Set bandwidth on source node */ |
605 | msm8974_icc_rpm_smd_send(dev: provider->dev, RPM_BUS_MASTER_REQ, |
606 | name: src_qn->name, id: src_qn->mas_rpm_id, val: sum_bw); |
607 | |
608 | msm8974_icc_rpm_smd_send(dev: provider->dev, RPM_BUS_SLAVE_REQ, |
609 | name: src_qn->name, id: src_qn->slv_rpm_id, val: sum_bw); |
610 | |
611 | /* Set bandwidth on destination node */ |
612 | msm8974_icc_rpm_smd_send(dev: provider->dev, RPM_BUS_MASTER_REQ, |
613 | name: dst_qn->name, id: dst_qn->mas_rpm_id, val: sum_bw); |
614 | |
615 | msm8974_icc_rpm_smd_send(dev: provider->dev, RPM_BUS_SLAVE_REQ, |
616 | name: dst_qn->name, id: dst_qn->slv_rpm_id, val: sum_bw); |
617 | |
618 | rate = max(sum_bw, max_peak_bw); |
619 | |
620 | do_div(rate, src_qn->buswidth); |
621 | |
622 | rate = min_t(u32, rate, INT_MAX); |
623 | |
624 | if (src_qn->rate == rate) |
625 | return 0; |
626 | |
627 | for (i = 0; i < qp->num_clks; i++) { |
628 | ret = clk_set_rate(clk: qp->bus_clks[i].clk, rate); |
629 | if (ret) { |
630 | dev_err(provider->dev, "%s clk_set_rate error: %d\n" , |
631 | qp->bus_clks[i].id, ret); |
632 | ret = 0; |
633 | } |
634 | } |
635 | |
636 | src_qn->rate = rate; |
637 | |
638 | return 0; |
639 | } |
640 | |
641 | static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) |
642 | { |
643 | *avg = 0; |
644 | *peak = 0; |
645 | |
646 | return 0; |
647 | } |
648 | |
649 | static int msm8974_icc_probe(struct platform_device *pdev) |
650 | { |
651 | const struct msm8974_icc_desc *desc; |
652 | struct msm8974_icc_node * const *qnodes; |
653 | struct msm8974_icc_provider *qp; |
654 | struct device *dev = &pdev->dev; |
655 | struct icc_onecell_data *data; |
656 | struct icc_provider *provider; |
657 | struct icc_node *node; |
658 | size_t num_nodes, i; |
659 | int ret; |
660 | |
661 | /* wait for the RPM proxy */ |
662 | if (!qcom_icc_rpm_smd_available()) |
663 | return -EPROBE_DEFER; |
664 | |
665 | desc = of_device_get_match_data(dev); |
666 | if (!desc) |
667 | return -EINVAL; |
668 | |
669 | qnodes = desc->nodes; |
670 | num_nodes = desc->num_nodes; |
671 | |
672 | qp = devm_kzalloc(dev, size: sizeof(*qp), GFP_KERNEL); |
673 | if (!qp) |
674 | return -ENOMEM; |
675 | |
676 | data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), |
677 | GFP_KERNEL); |
678 | if (!data) |
679 | return -ENOMEM; |
680 | data->num_nodes = num_nodes; |
681 | |
682 | qp->bus_clks = devm_kmemdup(dev, src: msm8974_icc_bus_clocks, |
683 | len: sizeof(msm8974_icc_bus_clocks), GFP_KERNEL); |
684 | if (!qp->bus_clks) |
685 | return -ENOMEM; |
686 | |
687 | qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks); |
688 | ret = devm_clk_bulk_get(dev, num_clks: qp->num_clks, clks: qp->bus_clks); |
689 | if (ret) |
690 | return ret; |
691 | |
692 | ret = clk_bulk_prepare_enable(num_clks: qp->num_clks, clks: qp->bus_clks); |
693 | if (ret) |
694 | return ret; |
695 | |
696 | provider = &qp->provider; |
697 | provider->dev = dev; |
698 | provider->set = msm8974_icc_set; |
699 | provider->aggregate = icc_std_aggregate; |
700 | provider->xlate = of_icc_xlate_onecell; |
701 | provider->data = data; |
702 | provider->get_bw = msm8974_get_bw; |
703 | |
704 | icc_provider_init(provider); |
705 | |
706 | for (i = 0; i < num_nodes; i++) { |
707 | size_t j; |
708 | |
709 | node = icc_node_create(id: qnodes[i]->id); |
710 | if (IS_ERR(ptr: node)) { |
711 | ret = PTR_ERR(ptr: node); |
712 | goto err_remove_nodes; |
713 | } |
714 | |
715 | node->name = qnodes[i]->name; |
716 | node->data = qnodes[i]; |
717 | icc_node_add(node, provider); |
718 | |
719 | dev_dbg(dev, "registered node %s\n" , node->name); |
720 | |
721 | /* populate links */ |
722 | for (j = 0; j < qnodes[i]->num_links; j++) |
723 | icc_link_create(node, dst_id: qnodes[i]->links[j]); |
724 | |
725 | data->nodes[i] = node; |
726 | } |
727 | |
728 | ret = icc_provider_register(provider); |
729 | if (ret) |
730 | goto err_remove_nodes; |
731 | |
732 | platform_set_drvdata(pdev, data: qp); |
733 | |
734 | return 0; |
735 | |
736 | err_remove_nodes: |
737 | icc_nodes_remove(provider); |
738 | clk_bulk_disable_unprepare(num_clks: qp->num_clks, clks: qp->bus_clks); |
739 | |
740 | return ret; |
741 | } |
742 | |
743 | static void msm8974_icc_remove(struct platform_device *pdev) |
744 | { |
745 | struct msm8974_icc_provider *qp = platform_get_drvdata(pdev); |
746 | |
747 | icc_provider_deregister(provider: &qp->provider); |
748 | icc_nodes_remove(provider: &qp->provider); |
749 | clk_bulk_disable_unprepare(num_clks: qp->num_clks, clks: qp->bus_clks); |
750 | } |
751 | |
752 | static const struct of_device_id msm8974_noc_of_match[] = { |
753 | { .compatible = "qcom,msm8974-bimc" , .data = &msm8974_bimc}, |
754 | { .compatible = "qcom,msm8974-cnoc" , .data = &msm8974_cnoc}, |
755 | { .compatible = "qcom,msm8974-mmssnoc" , .data = &msm8974_mnoc}, |
756 | { .compatible = "qcom,msm8974-ocmemnoc" , .data = &msm8974_onoc}, |
757 | { .compatible = "qcom,msm8974-pnoc" , .data = &msm8974_pnoc}, |
758 | { .compatible = "qcom,msm8974-snoc" , .data = &msm8974_snoc}, |
759 | { }, |
760 | }; |
761 | MODULE_DEVICE_TABLE(of, msm8974_noc_of_match); |
762 | |
763 | static struct platform_driver msm8974_noc_driver = { |
764 | .probe = msm8974_icc_probe, |
765 | .remove_new = msm8974_icc_remove, |
766 | .driver = { |
767 | .name = "qnoc-msm8974" , |
768 | .of_match_table = msm8974_noc_of_match, |
769 | .sync_state = icc_sync_state, |
770 | }, |
771 | }; |
772 | module_platform_driver(msm8974_noc_driver); |
773 | MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver" ); |
774 | MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>" ); |
775 | MODULE_LICENSE("GPL v2" ); |
776 | |