1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2021, Linaro Limited |
5 | */ |
6 | |
7 | #include <linux/device.h> |
8 | #include <linux/interconnect.h> |
9 | #include <linux/interconnect-provider.h> |
10 | #include <linux/module.h> |
11 | #include <linux/mod_devicetable.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/property.h> |
14 | #include <dt-bindings/interconnect/qcom,sm8450.h> |
15 | |
16 | #include "bcm-voter.h" |
17 | #include "icc-common.h" |
18 | #include "icc-rpmh.h" |
19 | #include "sm8450.h" |
20 | |
21 | static struct qcom_icc_node qhm_qspi = { |
22 | .name = "qhm_qspi" , |
23 | .id = SM8450_MASTER_QSPI_0, |
24 | .channels = 1, |
25 | .buswidth = 4, |
26 | .num_links = 1, |
27 | .links = { SM8450_SLAVE_A1NOC_SNOC }, |
28 | }; |
29 | |
30 | static struct qcom_icc_node qhm_qup1 = { |
31 | .name = "qhm_qup1" , |
32 | .id = SM8450_MASTER_QUP_1, |
33 | .channels = 1, |
34 | .buswidth = 4, |
35 | .num_links = 1, |
36 | .links = { SM8450_SLAVE_A1NOC_SNOC }, |
37 | }; |
38 | |
39 | static struct qcom_icc_node qnm_a1noc_cfg = { |
40 | .name = "qnm_a1noc_cfg" , |
41 | .id = SM8450_MASTER_A1NOC_CFG, |
42 | .channels = 1, |
43 | .buswidth = 4, |
44 | .num_links = 1, |
45 | .links = { SM8450_SLAVE_SERVICE_A1NOC }, |
46 | }; |
47 | |
48 | static struct qcom_icc_node xm_sdc4 = { |
49 | .name = "xm_sdc4" , |
50 | .id = SM8450_MASTER_SDCC_4, |
51 | .channels = 1, |
52 | .buswidth = 8, |
53 | .num_links = 1, |
54 | .links = { SM8450_SLAVE_A1NOC_SNOC }, |
55 | }; |
56 | |
57 | static struct qcom_icc_node xm_ufs_mem = { |
58 | .name = "xm_ufs_mem" , |
59 | .id = SM8450_MASTER_UFS_MEM, |
60 | .channels = 1, |
61 | .buswidth = 8, |
62 | .num_links = 1, |
63 | .links = { SM8450_SLAVE_A1NOC_SNOC }, |
64 | }; |
65 | |
66 | static struct qcom_icc_node xm_usb3_0 = { |
67 | .name = "xm_usb3_0" , |
68 | .id = SM8450_MASTER_USB3_0, |
69 | .channels = 1, |
70 | .buswidth = 8, |
71 | .num_links = 1, |
72 | .links = { SM8450_SLAVE_A1NOC_SNOC }, |
73 | }; |
74 | |
75 | static struct qcom_icc_node qhm_qdss_bam = { |
76 | .name = "qhm_qdss_bam" , |
77 | .id = SM8450_MASTER_QDSS_BAM, |
78 | .channels = 1, |
79 | .buswidth = 4, |
80 | .num_links = 1, |
81 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
82 | }; |
83 | |
84 | static struct qcom_icc_node qhm_qup0 = { |
85 | .name = "qhm_qup0" , |
86 | .id = SM8450_MASTER_QUP_0, |
87 | .channels = 1, |
88 | .buswidth = 4, |
89 | .num_links = 1, |
90 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
91 | }; |
92 | |
93 | static struct qcom_icc_node qhm_qup2 = { |
94 | .name = "qhm_qup2" , |
95 | .id = SM8450_MASTER_QUP_2, |
96 | .channels = 1, |
97 | .buswidth = 4, |
98 | .num_links = 1, |
99 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
100 | }; |
101 | |
102 | static struct qcom_icc_node qnm_a2noc_cfg = { |
103 | .name = "qnm_a2noc_cfg" , |
104 | .id = SM8450_MASTER_A2NOC_CFG, |
105 | .channels = 1, |
106 | .buswidth = 4, |
107 | .num_links = 1, |
108 | .links = { SM8450_SLAVE_SERVICE_A2NOC }, |
109 | }; |
110 | |
111 | static struct qcom_icc_node qxm_crypto = { |
112 | .name = "qxm_crypto" , |
113 | .id = SM8450_MASTER_CRYPTO, |
114 | .channels = 1, |
115 | .buswidth = 8, |
116 | .num_links = 1, |
117 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
118 | }; |
119 | |
120 | static struct qcom_icc_node qxm_ipa = { |
121 | .name = "qxm_ipa" , |
122 | .id = SM8450_MASTER_IPA, |
123 | .channels = 1, |
124 | .buswidth = 8, |
125 | .num_links = 1, |
126 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
127 | }; |
128 | |
129 | static struct qcom_icc_node = { |
130 | .name = "qxm_sensorss_q6" , |
131 | .id = SM8450_MASTER_SENSORS_PROC, |
132 | .channels = 1, |
133 | .buswidth = 8, |
134 | .num_links = 1, |
135 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
136 | }; |
137 | |
138 | static struct qcom_icc_node qxm_sp = { |
139 | .name = "qxm_sp" , |
140 | .id = SM8450_MASTER_SP, |
141 | .channels = 1, |
142 | .buswidth = 8, |
143 | .num_links = 1, |
144 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
145 | }; |
146 | |
147 | static struct qcom_icc_node xm_qdss_etr_0 = { |
148 | .name = "xm_qdss_etr_0" , |
149 | .id = SM8450_MASTER_QDSS_ETR, |
150 | .channels = 1, |
151 | .buswidth = 8, |
152 | .num_links = 1, |
153 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
154 | }; |
155 | |
156 | static struct qcom_icc_node xm_qdss_etr_1 = { |
157 | .name = "xm_qdss_etr_1" , |
158 | .id = SM8450_MASTER_QDSS_ETR_1, |
159 | .channels = 1, |
160 | .buswidth = 8, |
161 | .num_links = 1, |
162 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
163 | }; |
164 | |
165 | static struct qcom_icc_node xm_sdc2 = { |
166 | .name = "xm_sdc2" , |
167 | .id = SM8450_MASTER_SDCC_2, |
168 | .channels = 1, |
169 | .buswidth = 8, |
170 | .num_links = 1, |
171 | .links = { SM8450_SLAVE_A2NOC_SNOC }, |
172 | }; |
173 | |
174 | static struct qcom_icc_node qup0_core_master = { |
175 | .name = "qup0_core_master" , |
176 | .id = SM8450_MASTER_QUP_CORE_0, |
177 | .channels = 1, |
178 | .buswidth = 4, |
179 | .num_links = 1, |
180 | .links = { SM8450_SLAVE_QUP_CORE_0 }, |
181 | }; |
182 | |
183 | static struct qcom_icc_node qup1_core_master = { |
184 | .name = "qup1_core_master" , |
185 | .id = SM8450_MASTER_QUP_CORE_1, |
186 | .channels = 1, |
187 | .buswidth = 4, |
188 | .num_links = 1, |
189 | .links = { SM8450_SLAVE_QUP_CORE_1 }, |
190 | }; |
191 | |
192 | static struct qcom_icc_node qup2_core_master = { |
193 | .name = "qup2_core_master" , |
194 | .id = SM8450_MASTER_QUP_CORE_2, |
195 | .channels = 1, |
196 | .buswidth = 4, |
197 | .num_links = 1, |
198 | .links = { SM8450_SLAVE_QUP_CORE_2 }, |
199 | }; |
200 | |
201 | static struct qcom_icc_node qnm_gemnoc_cnoc = { |
202 | .name = "qnm_gemnoc_cnoc" , |
203 | .id = SM8450_MASTER_GEM_NOC_CNOC, |
204 | .channels = 1, |
205 | .buswidth = 16, |
206 | .num_links = 51, |
207 | .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH, |
208 | SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG, |
209 | SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG, |
210 | SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG, |
211 | SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG, |
212 | SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM, |
213 | SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG, |
214 | SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG, |
215 | SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS, |
216 | SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM, |
217 | SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG, |
218 | SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG, |
219 | SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG, |
220 | SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0, |
221 | SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2, |
222 | SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4, |
223 | SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR, |
224 | SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG, |
225 | SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0, |
226 | SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG, |
227 | SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG, |
228 | SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG, |
229 | SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG, |
230 | SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM, |
231 | SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM, |
232 | SM8450_SLAVE_TCU }, |
233 | }; |
234 | |
235 | static struct qcom_icc_node qnm_gemnoc_pcie = { |
236 | .name = "qnm_gemnoc_pcie" , |
237 | .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC, |
238 | .channels = 1, |
239 | .buswidth = 8, |
240 | .num_links = 2, |
241 | .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 }, |
242 | }; |
243 | |
244 | static struct qcom_icc_node alm_gpu_tcu = { |
245 | .name = "alm_gpu_tcu" , |
246 | .id = SM8450_MASTER_GPU_TCU, |
247 | .channels = 1, |
248 | .buswidth = 8, |
249 | .num_links = 2, |
250 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
251 | }; |
252 | |
253 | static struct qcom_icc_node alm_sys_tcu = { |
254 | .name = "alm_sys_tcu" , |
255 | .id = SM8450_MASTER_SYS_TCU, |
256 | .channels = 1, |
257 | .buswidth = 8, |
258 | .num_links = 2, |
259 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
260 | }; |
261 | |
262 | static struct qcom_icc_node chm_apps = { |
263 | .name = "chm_apps" , |
264 | .id = SM8450_MASTER_APPSS_PROC, |
265 | .channels = 3, |
266 | .buswidth = 32, |
267 | .num_links = 3, |
268 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, |
269 | SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, |
270 | }; |
271 | |
272 | static struct qcom_icc_node qnm_gpu = { |
273 | .name = "qnm_gpu" , |
274 | .id = SM8450_MASTER_GFX3D, |
275 | .channels = 2, |
276 | .buswidth = 32, |
277 | .num_links = 2, |
278 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
279 | }; |
280 | |
281 | static struct qcom_icc_node qnm_mdsp = { |
282 | .name = "qnm_mdsp" , |
283 | .id = SM8450_MASTER_MSS_PROC, |
284 | .channels = 1, |
285 | .buswidth = 16, |
286 | .num_links = 3, |
287 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, |
288 | SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, |
289 | }; |
290 | |
291 | static struct qcom_icc_node qnm_mnoc_hf = { |
292 | .name = "qnm_mnoc_hf" , |
293 | .id = SM8450_MASTER_MNOC_HF_MEM_NOC, |
294 | .channels = 2, |
295 | .buswidth = 32, |
296 | .num_links = 1, |
297 | .links = { SM8450_SLAVE_LLCC }, |
298 | }; |
299 | |
300 | static struct qcom_icc_node qnm_mnoc_sf = { |
301 | .name = "qnm_mnoc_sf" , |
302 | .id = SM8450_MASTER_MNOC_SF_MEM_NOC, |
303 | .channels = 2, |
304 | .buswidth = 32, |
305 | .num_links = 2, |
306 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
307 | }; |
308 | |
309 | static struct qcom_icc_node qnm_nsp_gemnoc = { |
310 | .name = "qnm_nsp_gemnoc" , |
311 | .id = SM8450_MASTER_COMPUTE_NOC, |
312 | .channels = 2, |
313 | .buswidth = 32, |
314 | .num_links = 2, |
315 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
316 | }; |
317 | |
318 | static struct qcom_icc_node qnm_pcie = { |
319 | .name = "qnm_pcie" , |
320 | .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC, |
321 | .channels = 1, |
322 | .buswidth = 16, |
323 | .num_links = 2, |
324 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, |
325 | }; |
326 | |
327 | static struct qcom_icc_node qnm_snoc_gc = { |
328 | .name = "qnm_snoc_gc" , |
329 | .id = SM8450_MASTER_SNOC_GC_MEM_NOC, |
330 | .channels = 1, |
331 | .buswidth = 8, |
332 | .num_links = 1, |
333 | .links = { SM8450_SLAVE_LLCC }, |
334 | }; |
335 | |
336 | static struct qcom_icc_node qnm_snoc_sf = { |
337 | .name = "qnm_snoc_sf" , |
338 | .id = SM8450_MASTER_SNOC_SF_MEM_NOC, |
339 | .channels = 1, |
340 | .buswidth = 16, |
341 | .num_links = 3, |
342 | .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, |
343 | SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, |
344 | }; |
345 | |
346 | static struct qcom_icc_node qhm_config_noc = { |
347 | .name = "qhm_config_noc" , |
348 | .id = SM8450_MASTER_CNOC_LPASS_AG_NOC, |
349 | .channels = 1, |
350 | .buswidth = 4, |
351 | .num_links = 6, |
352 | .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG, |
353 | SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG, |
354 | SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, |
355 | }; |
356 | |
357 | static struct qcom_icc_node qxm_lpass_dsp = { |
358 | .name = "qxm_lpass_dsp" , |
359 | .id = SM8450_MASTER_LPASS_PROC, |
360 | .channels = 1, |
361 | .buswidth = 8, |
362 | .num_links = 4, |
363 | .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC, |
364 | SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, |
365 | }; |
366 | |
367 | static struct qcom_icc_node llcc_mc = { |
368 | .name = "llcc_mc" , |
369 | .id = SM8450_MASTER_LLCC, |
370 | .channels = 4, |
371 | .buswidth = 4, |
372 | .num_links = 1, |
373 | .links = { SM8450_SLAVE_EBI1 }, |
374 | }; |
375 | |
376 | static struct qcom_icc_node qnm_camnoc_hf = { |
377 | .name = "qnm_camnoc_hf" , |
378 | .id = SM8450_MASTER_CAMNOC_HF, |
379 | .channels = 2, |
380 | .buswidth = 32, |
381 | .num_links = 1, |
382 | .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, |
383 | }; |
384 | |
385 | static struct qcom_icc_node qnm_camnoc_icp = { |
386 | .name = "qnm_camnoc_icp" , |
387 | .id = SM8450_MASTER_CAMNOC_ICP, |
388 | .channels = 1, |
389 | .buswidth = 8, |
390 | .num_links = 1, |
391 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
392 | }; |
393 | |
394 | static struct qcom_icc_node qnm_camnoc_sf = { |
395 | .name = "qnm_camnoc_sf" , |
396 | .id = SM8450_MASTER_CAMNOC_SF, |
397 | .channels = 2, |
398 | .buswidth = 32, |
399 | .num_links = 1, |
400 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
401 | }; |
402 | |
403 | static struct qcom_icc_node qnm_mdp = { |
404 | .name = "qnm_mdp" , |
405 | .id = SM8450_MASTER_MDP, |
406 | .channels = 2, |
407 | .buswidth = 32, |
408 | .num_links = 1, |
409 | .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, |
410 | }; |
411 | |
412 | static struct qcom_icc_node qnm_mnoc_cfg = { |
413 | .name = "qnm_mnoc_cfg" , |
414 | .id = SM8450_MASTER_CNOC_MNOC_CFG, |
415 | .channels = 1, |
416 | .buswidth = 4, |
417 | .num_links = 1, |
418 | .links = { SM8450_SLAVE_SERVICE_MNOC }, |
419 | }; |
420 | |
421 | static struct qcom_icc_node qnm_rot = { |
422 | .name = "qnm_rot" , |
423 | .id = SM8450_MASTER_ROTATOR, |
424 | .channels = 1, |
425 | .buswidth = 32, |
426 | .num_links = 1, |
427 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
428 | }; |
429 | |
430 | static struct qcom_icc_node qnm_vapss_hcp = { |
431 | .name = "qnm_vapss_hcp" , |
432 | .id = SM8450_MASTER_CDSP_HCP, |
433 | .channels = 1, |
434 | .buswidth = 32, |
435 | .num_links = 1, |
436 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
437 | }; |
438 | |
439 | static struct qcom_icc_node qnm_video = { |
440 | .name = "qnm_video" , |
441 | .id = SM8450_MASTER_VIDEO, |
442 | .channels = 2, |
443 | .buswidth = 32, |
444 | .num_links = 1, |
445 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
446 | }; |
447 | |
448 | static struct qcom_icc_node qnm_video_cv_cpu = { |
449 | .name = "qnm_video_cv_cpu" , |
450 | .id = SM8450_MASTER_VIDEO_CV_PROC, |
451 | .channels = 1, |
452 | .buswidth = 8, |
453 | .num_links = 1, |
454 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
455 | }; |
456 | |
457 | static struct qcom_icc_node qnm_video_cvp = { |
458 | .name = "qnm_video_cvp" , |
459 | .id = SM8450_MASTER_VIDEO_PROC, |
460 | .channels = 1, |
461 | .buswidth = 32, |
462 | .num_links = 1, |
463 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
464 | }; |
465 | |
466 | static struct qcom_icc_node qnm_video_v_cpu = { |
467 | .name = "qnm_video_v_cpu" , |
468 | .id = SM8450_MASTER_VIDEO_V_PROC, |
469 | .channels = 1, |
470 | .buswidth = 8, |
471 | .num_links = 1, |
472 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, |
473 | }; |
474 | |
475 | static struct qcom_icc_node qhm_nsp_noc_config = { |
476 | .name = "qhm_nsp_noc_config" , |
477 | .id = SM8450_MASTER_CDSP_NOC_CFG, |
478 | .channels = 1, |
479 | .buswidth = 4, |
480 | .num_links = 1, |
481 | .links = { SM8450_SLAVE_SERVICE_NSP_NOC }, |
482 | }; |
483 | |
484 | static struct qcom_icc_node qxm_nsp = { |
485 | .name = "qxm_nsp" , |
486 | .id = SM8450_MASTER_CDSP_PROC, |
487 | .channels = 2, |
488 | .buswidth = 32, |
489 | .num_links = 1, |
490 | .links = { SM8450_SLAVE_CDSP_MEM_NOC }, |
491 | }; |
492 | |
493 | static struct qcom_icc_node qnm_pcie_anoc_cfg = { |
494 | .name = "qnm_pcie_anoc_cfg" , |
495 | .id = SM8450_MASTER_PCIE_ANOC_CFG, |
496 | .channels = 1, |
497 | .buswidth = 4, |
498 | .num_links = 1, |
499 | .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC }, |
500 | }; |
501 | |
502 | static struct qcom_icc_node xm_pcie3_0 = { |
503 | .name = "xm_pcie3_0" , |
504 | .id = SM8450_MASTER_PCIE_0, |
505 | .channels = 1, |
506 | .buswidth = 8, |
507 | .num_links = 1, |
508 | .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, |
509 | }; |
510 | |
511 | static struct qcom_icc_node xm_pcie3_1 = { |
512 | .name = "xm_pcie3_1" , |
513 | .id = SM8450_MASTER_PCIE_1, |
514 | .channels = 1, |
515 | .buswidth = 8, |
516 | .num_links = 1, |
517 | .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, |
518 | }; |
519 | |
520 | static struct qcom_icc_node qhm_gic = { |
521 | .name = "qhm_gic" , |
522 | .id = SM8450_MASTER_GIC_AHB, |
523 | .channels = 1, |
524 | .buswidth = 4, |
525 | .num_links = 1, |
526 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, |
527 | }; |
528 | |
529 | static struct qcom_icc_node qnm_aggre1_noc = { |
530 | .name = "qnm_aggre1_noc" , |
531 | .id = SM8450_MASTER_A1NOC_SNOC, |
532 | .channels = 1, |
533 | .buswidth = 16, |
534 | .num_links = 1, |
535 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, |
536 | }; |
537 | |
538 | static struct qcom_icc_node qnm_aggre2_noc = { |
539 | .name = "qnm_aggre2_noc" , |
540 | .id = SM8450_MASTER_A2NOC_SNOC, |
541 | .channels = 1, |
542 | .buswidth = 16, |
543 | .num_links = 1, |
544 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, |
545 | }; |
546 | |
547 | static struct qcom_icc_node qnm_lpass_noc = { |
548 | .name = "qnm_lpass_noc" , |
549 | .id = SM8450_MASTER_LPASS_ANOC, |
550 | .channels = 1, |
551 | .buswidth = 16, |
552 | .num_links = 1, |
553 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, |
554 | }; |
555 | |
556 | static struct qcom_icc_node qnm_snoc_cfg = { |
557 | .name = "qnm_snoc_cfg" , |
558 | .id = SM8450_MASTER_SNOC_CFG, |
559 | .channels = 1, |
560 | .buswidth = 4, |
561 | .num_links = 1, |
562 | .links = { SM8450_SLAVE_SERVICE_SNOC }, |
563 | }; |
564 | |
565 | static struct qcom_icc_node qxm_pimem = { |
566 | .name = "qxm_pimem" , |
567 | .id = SM8450_MASTER_PIMEM, |
568 | .channels = 1, |
569 | .buswidth = 8, |
570 | .num_links = 1, |
571 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, |
572 | }; |
573 | |
574 | static struct qcom_icc_node xm_gic = { |
575 | .name = "xm_gic" , |
576 | .id = SM8450_MASTER_GIC, |
577 | .channels = 1, |
578 | .buswidth = 8, |
579 | .num_links = 1, |
580 | .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, |
581 | }; |
582 | |
583 | static struct qcom_icc_node qnm_mnoc_hf_disp = { |
584 | .name = "qnm_mnoc_hf_disp" , |
585 | .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP, |
586 | .channels = 2, |
587 | .buswidth = 32, |
588 | .num_links = 1, |
589 | .links = { SM8450_SLAVE_LLCC_DISP }, |
590 | }; |
591 | |
592 | static struct qcom_icc_node qnm_mnoc_sf_disp = { |
593 | .name = "qnm_mnoc_sf_disp" , |
594 | .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP, |
595 | .channels = 2, |
596 | .buswidth = 32, |
597 | .num_links = 1, |
598 | .links = { SM8450_SLAVE_LLCC_DISP }, |
599 | }; |
600 | |
601 | static struct qcom_icc_node qnm_pcie_disp = { |
602 | .name = "qnm_pcie_disp" , |
603 | .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP, |
604 | .channels = 1, |
605 | .buswidth = 16, |
606 | .num_links = 1, |
607 | .links = { SM8450_SLAVE_LLCC_DISP }, |
608 | }; |
609 | |
610 | static struct qcom_icc_node llcc_mc_disp = { |
611 | .name = "llcc_mc_disp" , |
612 | .id = SM8450_MASTER_LLCC_DISP, |
613 | .channels = 4, |
614 | .buswidth = 4, |
615 | .num_links = 1, |
616 | .links = { SM8450_SLAVE_EBI1_DISP }, |
617 | }; |
618 | |
619 | static struct qcom_icc_node qnm_mdp_disp = { |
620 | .name = "qnm_mdp_disp" , |
621 | .id = SM8450_MASTER_MDP_DISP, |
622 | .channels = 2, |
623 | .buswidth = 32, |
624 | .num_links = 1, |
625 | .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP }, |
626 | }; |
627 | |
628 | static struct qcom_icc_node qnm_rot_disp = { |
629 | .name = "qnm_rot_disp" , |
630 | .id = SM8450_MASTER_ROTATOR_DISP, |
631 | .channels = 1, |
632 | .buswidth = 32, |
633 | .num_links = 1, |
634 | .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP }, |
635 | }; |
636 | |
637 | static struct qcom_icc_node qns_a1noc_snoc = { |
638 | .name = "qns_a1noc_snoc" , |
639 | .id = SM8450_SLAVE_A1NOC_SNOC, |
640 | .channels = 1, |
641 | .buswidth = 16, |
642 | .num_links = 1, |
643 | .links = { SM8450_MASTER_A1NOC_SNOC }, |
644 | }; |
645 | |
646 | static struct qcom_icc_node srvc_aggre1_noc = { |
647 | .name = "srvc_aggre1_noc" , |
648 | .id = SM8450_SLAVE_SERVICE_A1NOC, |
649 | .channels = 1, |
650 | .buswidth = 4, |
651 | .num_links = 0, |
652 | }; |
653 | |
654 | static struct qcom_icc_node qns_a2noc_snoc = { |
655 | .name = "qns_a2noc_snoc" , |
656 | .id = SM8450_SLAVE_A2NOC_SNOC, |
657 | .channels = 1, |
658 | .buswidth = 16, |
659 | .num_links = 1, |
660 | .links = { SM8450_MASTER_A2NOC_SNOC }, |
661 | }; |
662 | |
663 | static struct qcom_icc_node srvc_aggre2_noc = { |
664 | .name = "srvc_aggre2_noc" , |
665 | .id = SM8450_SLAVE_SERVICE_A2NOC, |
666 | .channels = 1, |
667 | .buswidth = 4, |
668 | .num_links = 0, |
669 | }; |
670 | |
671 | static struct qcom_icc_node qup0_core_slave = { |
672 | .name = "qup0_core_slave" , |
673 | .id = SM8450_SLAVE_QUP_CORE_0, |
674 | .channels = 1, |
675 | .buswidth = 4, |
676 | .num_links = 0, |
677 | }; |
678 | |
679 | static struct qcom_icc_node qup1_core_slave = { |
680 | .name = "qup1_core_slave" , |
681 | .id = SM8450_SLAVE_QUP_CORE_1, |
682 | .channels = 1, |
683 | .buswidth = 4, |
684 | .num_links = 0, |
685 | }; |
686 | |
687 | static struct qcom_icc_node qup2_core_slave = { |
688 | .name = "qup2_core_slave" , |
689 | .id = SM8450_SLAVE_QUP_CORE_2, |
690 | .channels = 1, |
691 | .buswidth = 4, |
692 | .num_links = 0, |
693 | }; |
694 | |
695 | static struct qcom_icc_node qhs_ahb2phy0 = { |
696 | .name = "qhs_ahb2phy0" , |
697 | .id = SM8450_SLAVE_AHB2PHY_SOUTH, |
698 | .channels = 1, |
699 | .buswidth = 4, |
700 | .num_links = 0, |
701 | }; |
702 | |
703 | static struct qcom_icc_node qhs_ahb2phy1 = { |
704 | .name = "qhs_ahb2phy1" , |
705 | .id = SM8450_SLAVE_AHB2PHY_NORTH, |
706 | .channels = 1, |
707 | .buswidth = 4, |
708 | .num_links = 0, |
709 | }; |
710 | |
711 | static struct qcom_icc_node qhs_aoss = { |
712 | .name = "qhs_aoss" , |
713 | .id = SM8450_SLAVE_AOSS, |
714 | .channels = 1, |
715 | .buswidth = 4, |
716 | .num_links = 0, |
717 | }; |
718 | |
719 | static struct qcom_icc_node qhs_camera_cfg = { |
720 | .name = "qhs_camera_cfg" , |
721 | .id = SM8450_SLAVE_CAMERA_CFG, |
722 | .channels = 1, |
723 | .buswidth = 4, |
724 | .num_links = 0, |
725 | }; |
726 | |
727 | static struct qcom_icc_node qhs_clk_ctl = { |
728 | .name = "qhs_clk_ctl" , |
729 | .id = SM8450_SLAVE_CLK_CTL, |
730 | .channels = 1, |
731 | .buswidth = 4, |
732 | .num_links = 0, |
733 | }; |
734 | |
735 | static struct qcom_icc_node qhs_compute_cfg = { |
736 | .name = "qhs_compute_cfg" , |
737 | .id = SM8450_SLAVE_CDSP_CFG, |
738 | .channels = 1, |
739 | .buswidth = 4, |
740 | .num_links = 1, |
741 | .links = { MASTER_CDSP_NOC_CFG }, |
742 | }; |
743 | |
744 | static struct qcom_icc_node qhs_cpr_cx = { |
745 | .name = "qhs_cpr_cx" , |
746 | .id = SM8450_SLAVE_RBCPR_CX_CFG, |
747 | .channels = 1, |
748 | .buswidth = 4, |
749 | .num_links = 0, |
750 | }; |
751 | |
752 | static struct qcom_icc_node qhs_cpr_mmcx = { |
753 | .name = "qhs_cpr_mmcx" , |
754 | .id = SM8450_SLAVE_RBCPR_MMCX_CFG, |
755 | .channels = 1, |
756 | .buswidth = 4, |
757 | .num_links = 0, |
758 | }; |
759 | |
760 | static struct qcom_icc_node qhs_cpr_mxa = { |
761 | .name = "qhs_cpr_mxa" , |
762 | .id = SM8450_SLAVE_RBCPR_MXA_CFG, |
763 | .channels = 1, |
764 | .buswidth = 4, |
765 | .num_links = 0, |
766 | }; |
767 | |
768 | static struct qcom_icc_node qhs_cpr_mxc = { |
769 | .name = "qhs_cpr_mxc" , |
770 | .id = SM8450_SLAVE_RBCPR_MXC_CFG, |
771 | .channels = 1, |
772 | .buswidth = 4, |
773 | .num_links = 0, |
774 | }; |
775 | |
776 | static struct qcom_icc_node qhs_crypto0_cfg = { |
777 | .name = "qhs_crypto0_cfg" , |
778 | .id = SM8450_SLAVE_CRYPTO_0_CFG, |
779 | .channels = 1, |
780 | .buswidth = 4, |
781 | .num_links = 0, |
782 | }; |
783 | |
784 | static struct qcom_icc_node qhs_cx_rdpm = { |
785 | .name = "qhs_cx_rdpm" , |
786 | .id = SM8450_SLAVE_CX_RDPM, |
787 | .channels = 1, |
788 | .buswidth = 4, |
789 | .num_links = 0, |
790 | }; |
791 | |
792 | static struct qcom_icc_node qhs_display_cfg = { |
793 | .name = "qhs_display_cfg" , |
794 | .id = SM8450_SLAVE_DISPLAY_CFG, |
795 | .channels = 1, |
796 | .buswidth = 4, |
797 | .num_links = 0, |
798 | }; |
799 | |
800 | static struct qcom_icc_node qhs_gpuss_cfg = { |
801 | .name = "qhs_gpuss_cfg" , |
802 | .id = SM8450_SLAVE_GFX3D_CFG, |
803 | .channels = 1, |
804 | .buswidth = 8, |
805 | .num_links = 0, |
806 | }; |
807 | |
808 | static struct qcom_icc_node qhs_imem_cfg = { |
809 | .name = "qhs_imem_cfg" , |
810 | .id = SM8450_SLAVE_IMEM_CFG, |
811 | .channels = 1, |
812 | .buswidth = 4, |
813 | .num_links = 0, |
814 | }; |
815 | |
816 | static struct qcom_icc_node qhs_ipa = { |
817 | .name = "qhs_ipa" , |
818 | .id = SM8450_SLAVE_IPA_CFG, |
819 | .channels = 1, |
820 | .buswidth = 4, |
821 | .num_links = 0, |
822 | }; |
823 | |
824 | static struct qcom_icc_node qhs_ipc_router = { |
825 | .name = "qhs_ipc_router" , |
826 | .id = SM8450_SLAVE_IPC_ROUTER_CFG, |
827 | .channels = 1, |
828 | .buswidth = 4, |
829 | .num_links = 0, |
830 | }; |
831 | |
832 | static struct qcom_icc_node qhs_lpass_cfg = { |
833 | .name = "qhs_lpass_cfg" , |
834 | .id = SM8450_SLAVE_LPASS, |
835 | .channels = 1, |
836 | .buswidth = 4, |
837 | .num_links = 1, |
838 | .links = { MASTER_CNOC_LPASS_AG_NOC }, |
839 | }; |
840 | |
841 | static struct qcom_icc_node qhs_mss_cfg = { |
842 | .name = "qhs_mss_cfg" , |
843 | .id = SM8450_SLAVE_CNOC_MSS, |
844 | .channels = 1, |
845 | .buswidth = 4, |
846 | .num_links = 0, |
847 | }; |
848 | |
849 | static struct qcom_icc_node qhs_mx_rdpm = { |
850 | .name = "qhs_mx_rdpm" , |
851 | .id = SM8450_SLAVE_MX_RDPM, |
852 | .channels = 1, |
853 | .buswidth = 4, |
854 | .num_links = 0, |
855 | }; |
856 | |
857 | static struct qcom_icc_node qhs_pcie0_cfg = { |
858 | .name = "qhs_pcie0_cfg" , |
859 | .id = SM8450_SLAVE_PCIE_0_CFG, |
860 | .channels = 1, |
861 | .buswidth = 4, |
862 | .num_links = 0, |
863 | }; |
864 | |
865 | static struct qcom_icc_node qhs_pcie1_cfg = { |
866 | .name = "qhs_pcie1_cfg" , |
867 | .id = SM8450_SLAVE_PCIE_1_CFG, |
868 | .channels = 1, |
869 | .buswidth = 4, |
870 | .num_links = 0, |
871 | }; |
872 | |
873 | static struct qcom_icc_node qhs_pdm = { |
874 | .name = "qhs_pdm" , |
875 | .id = SM8450_SLAVE_PDM, |
876 | .channels = 1, |
877 | .buswidth = 4, |
878 | .num_links = 0, |
879 | }; |
880 | |
881 | static struct qcom_icc_node qhs_pimem_cfg = { |
882 | .name = "qhs_pimem_cfg" , |
883 | .id = SM8450_SLAVE_PIMEM_CFG, |
884 | .channels = 1, |
885 | .buswidth = 4, |
886 | .num_links = 0, |
887 | }; |
888 | |
889 | static struct qcom_icc_node qhs_prng = { |
890 | .name = "qhs_prng" , |
891 | .id = SM8450_SLAVE_PRNG, |
892 | .channels = 1, |
893 | .buswidth = 4, |
894 | .num_links = 0, |
895 | }; |
896 | |
897 | static struct qcom_icc_node qhs_qdss_cfg = { |
898 | .name = "qhs_qdss_cfg" , |
899 | .id = SM8450_SLAVE_QDSS_CFG, |
900 | .channels = 1, |
901 | .buswidth = 4, |
902 | .num_links = 0, |
903 | }; |
904 | |
905 | static struct qcom_icc_node qhs_qspi = { |
906 | .name = "qhs_qspi" , |
907 | .id = SM8450_SLAVE_QSPI_0, |
908 | .channels = 1, |
909 | .buswidth = 4, |
910 | .num_links = 0, |
911 | }; |
912 | |
913 | static struct qcom_icc_node qhs_qup0 = { |
914 | .name = "qhs_qup0" , |
915 | .id = SM8450_SLAVE_QUP_0, |
916 | .channels = 1, |
917 | .buswidth = 4, |
918 | .num_links = 0, |
919 | }; |
920 | |
921 | static struct qcom_icc_node qhs_qup1 = { |
922 | .name = "qhs_qup1" , |
923 | .id = SM8450_SLAVE_QUP_1, |
924 | .channels = 1, |
925 | .buswidth = 4, |
926 | .num_links = 0, |
927 | }; |
928 | |
929 | static struct qcom_icc_node qhs_qup2 = { |
930 | .name = "qhs_qup2" , |
931 | .id = SM8450_SLAVE_QUP_2, |
932 | .channels = 1, |
933 | .buswidth = 4, |
934 | .num_links = 0, |
935 | }; |
936 | |
937 | static struct qcom_icc_node qhs_sdc2 = { |
938 | .name = "qhs_sdc2" , |
939 | .id = SM8450_SLAVE_SDCC_2, |
940 | .channels = 1, |
941 | .buswidth = 4, |
942 | .num_links = 0, |
943 | }; |
944 | |
945 | static struct qcom_icc_node qhs_sdc4 = { |
946 | .name = "qhs_sdc4" , |
947 | .id = SM8450_SLAVE_SDCC_4, |
948 | .channels = 1, |
949 | .buswidth = 4, |
950 | .num_links = 0, |
951 | }; |
952 | |
953 | static struct qcom_icc_node qhs_spss_cfg = { |
954 | .name = "qhs_spss_cfg" , |
955 | .id = SM8450_SLAVE_SPSS_CFG, |
956 | .channels = 1, |
957 | .buswidth = 4, |
958 | .num_links = 0, |
959 | }; |
960 | |
961 | static struct qcom_icc_node qhs_tcsr = { |
962 | .name = "qhs_tcsr" , |
963 | .id = SM8450_SLAVE_TCSR, |
964 | .channels = 1, |
965 | .buswidth = 4, |
966 | .num_links = 0, |
967 | }; |
968 | |
969 | static struct qcom_icc_node qhs_tlmm = { |
970 | .name = "qhs_tlmm" , |
971 | .id = SM8450_SLAVE_TLMM, |
972 | .channels = 1, |
973 | .buswidth = 4, |
974 | .num_links = 0, |
975 | }; |
976 | |
977 | static struct qcom_icc_node qhs_tme_cfg = { |
978 | .name = "qhs_tme_cfg" , |
979 | .id = SM8450_SLAVE_TME_CFG, |
980 | .channels = 1, |
981 | .buswidth = 4, |
982 | .num_links = 0, |
983 | }; |
984 | |
985 | static struct qcom_icc_node qhs_ufs_mem_cfg = { |
986 | .name = "qhs_ufs_mem_cfg" , |
987 | .id = SM8450_SLAVE_UFS_MEM_CFG, |
988 | .channels = 1, |
989 | .buswidth = 4, |
990 | .num_links = 0, |
991 | }; |
992 | |
993 | static struct qcom_icc_node qhs_usb3_0 = { |
994 | .name = "qhs_usb3_0" , |
995 | .id = SM8450_SLAVE_USB3_0, |
996 | .channels = 1, |
997 | .buswidth = 4, |
998 | .num_links = 0, |
999 | }; |
1000 | |
1001 | static struct qcom_icc_node qhs_venus_cfg = { |
1002 | .name = "qhs_venus_cfg" , |
1003 | .id = SM8450_SLAVE_VENUS_CFG, |
1004 | .channels = 1, |
1005 | .buswidth = 4, |
1006 | .num_links = 0, |
1007 | }; |
1008 | |
1009 | static struct qcom_icc_node qhs_vsense_ctrl_cfg = { |
1010 | .name = "qhs_vsense_ctrl_cfg" , |
1011 | .id = SM8450_SLAVE_VSENSE_CTRL_CFG, |
1012 | .channels = 1, |
1013 | .buswidth = 4, |
1014 | .num_links = 0, |
1015 | }; |
1016 | |
1017 | static struct qcom_icc_node qns_a1_noc_cfg = { |
1018 | .name = "qns_a1_noc_cfg" , |
1019 | .id = SM8450_SLAVE_A1NOC_CFG, |
1020 | .channels = 1, |
1021 | .buswidth = 4, |
1022 | .num_links = 1, |
1023 | .links = { SM8450_MASTER_A1NOC_CFG }, |
1024 | }; |
1025 | |
1026 | static struct qcom_icc_node qns_a2_noc_cfg = { |
1027 | .name = "qns_a2_noc_cfg" , |
1028 | .id = SM8450_SLAVE_A2NOC_CFG, |
1029 | .channels = 1, |
1030 | .buswidth = 4, |
1031 | .num_links = 1, |
1032 | .links = { SM8450_MASTER_A2NOC_CFG }, |
1033 | }; |
1034 | |
1035 | static struct qcom_icc_node = { |
1036 | .name = "qns_ddrss_cfg" , |
1037 | .id = SM8450_SLAVE_DDRSS_CFG, |
1038 | .channels = 1, |
1039 | .buswidth = 4, |
1040 | .num_links = 1, |
1041 | //FIXME where is link |
1042 | }; |
1043 | |
1044 | static struct qcom_icc_node qns_mnoc_cfg = { |
1045 | .name = "qns_mnoc_cfg" , |
1046 | .id = SM8450_SLAVE_CNOC_MNOC_CFG, |
1047 | .channels = 1, |
1048 | .buswidth = 4, |
1049 | .num_links = 1, |
1050 | .links = { SM8450_MASTER_CNOC_MNOC_CFG }, |
1051 | }; |
1052 | |
1053 | static struct qcom_icc_node qns_pcie_anoc_cfg = { |
1054 | .name = "qns_pcie_anoc_cfg" , |
1055 | .id = SM8450_SLAVE_PCIE_ANOC_CFG, |
1056 | .channels = 1, |
1057 | .buswidth = 4, |
1058 | .num_links = 1, |
1059 | .links = { SM8450_MASTER_PCIE_ANOC_CFG }, |
1060 | }; |
1061 | |
1062 | static struct qcom_icc_node qns_snoc_cfg = { |
1063 | .name = "qns_snoc_cfg" , |
1064 | .id = SM8450_SLAVE_SNOC_CFG, |
1065 | .channels = 1, |
1066 | .buswidth = 4, |
1067 | .num_links = 1, |
1068 | .links = { SM8450_MASTER_SNOC_CFG }, |
1069 | }; |
1070 | |
1071 | static struct qcom_icc_node qxs_imem = { |
1072 | .name = "qxs_imem" , |
1073 | .id = SM8450_SLAVE_IMEM, |
1074 | .channels = 1, |
1075 | .buswidth = 8, |
1076 | .num_links = 0, |
1077 | }; |
1078 | |
1079 | static struct qcom_icc_node qxs_pimem = { |
1080 | .name = "qxs_pimem" , |
1081 | .id = SM8450_SLAVE_PIMEM, |
1082 | .channels = 1, |
1083 | .buswidth = 8, |
1084 | .num_links = 0, |
1085 | }; |
1086 | |
1087 | static struct qcom_icc_node srvc_cnoc = { |
1088 | .name = "srvc_cnoc" , |
1089 | .id = SM8450_SLAVE_SERVICE_CNOC, |
1090 | .channels = 1, |
1091 | .buswidth = 4, |
1092 | .num_links = 0, |
1093 | }; |
1094 | |
1095 | static struct qcom_icc_node xs_pcie_0 = { |
1096 | .name = "xs_pcie_0" , |
1097 | .id = SM8450_SLAVE_PCIE_0, |
1098 | .channels = 1, |
1099 | .buswidth = 8, |
1100 | .num_links = 0, |
1101 | }; |
1102 | |
1103 | static struct qcom_icc_node xs_pcie_1 = { |
1104 | .name = "xs_pcie_1" , |
1105 | .id = SM8450_SLAVE_PCIE_1, |
1106 | .channels = 1, |
1107 | .buswidth = 8, |
1108 | .num_links = 0, |
1109 | }; |
1110 | |
1111 | static struct qcom_icc_node xs_qdss_stm = { |
1112 | .name = "xs_qdss_stm" , |
1113 | .id = SM8450_SLAVE_QDSS_STM, |
1114 | .channels = 1, |
1115 | .buswidth = 4, |
1116 | .num_links = 0, |
1117 | }; |
1118 | |
1119 | static struct qcom_icc_node xs_sys_tcu_cfg = { |
1120 | .name = "xs_sys_tcu_cfg" , |
1121 | .id = SM8450_SLAVE_TCU, |
1122 | .channels = 1, |
1123 | .buswidth = 8, |
1124 | .num_links = 0, |
1125 | }; |
1126 | |
1127 | static struct qcom_icc_node qns_gem_noc_cnoc = { |
1128 | .name = "qns_gem_noc_cnoc" , |
1129 | .id = SM8450_SLAVE_GEM_NOC_CNOC, |
1130 | .channels = 1, |
1131 | .buswidth = 16, |
1132 | .num_links = 1, |
1133 | .links = { SM8450_MASTER_GEM_NOC_CNOC }, |
1134 | }; |
1135 | |
1136 | static struct qcom_icc_node qns_llcc = { |
1137 | .name = "qns_llcc" , |
1138 | .id = SM8450_SLAVE_LLCC, |
1139 | .channels = 4, |
1140 | .buswidth = 16, |
1141 | .num_links = 1, |
1142 | .links = { SM8450_MASTER_LLCC }, |
1143 | }; |
1144 | |
1145 | static struct qcom_icc_node qns_pcie = { |
1146 | .name = "qns_pcie" , |
1147 | .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC, |
1148 | .channels = 1, |
1149 | .buswidth = 8, |
1150 | .num_links = 1, |
1151 | .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC }, |
1152 | }; |
1153 | |
1154 | static struct qcom_icc_node qhs_lpass_core = { |
1155 | .name = "qhs_lpass_core" , |
1156 | .id = SM8450_SLAVE_LPASS_CORE_CFG, |
1157 | .channels = 1, |
1158 | .buswidth = 4, |
1159 | .num_links = 0, |
1160 | }; |
1161 | |
1162 | static struct qcom_icc_node qhs_lpass_lpi = { |
1163 | .name = "qhs_lpass_lpi" , |
1164 | .id = SM8450_SLAVE_LPASS_LPI_CFG, |
1165 | .channels = 1, |
1166 | .buswidth = 4, |
1167 | .num_links = 0, |
1168 | }; |
1169 | |
1170 | static struct qcom_icc_node qhs_lpass_mpu = { |
1171 | .name = "qhs_lpass_mpu" , |
1172 | .id = SM8450_SLAVE_LPASS_MPU_CFG, |
1173 | .channels = 1, |
1174 | .buswidth = 4, |
1175 | .num_links = 0, |
1176 | }; |
1177 | |
1178 | static struct qcom_icc_node qhs_lpass_top = { |
1179 | .name = "qhs_lpass_top" , |
1180 | .id = SM8450_SLAVE_LPASS_TOP_CFG, |
1181 | .channels = 1, |
1182 | .buswidth = 4, |
1183 | .num_links = 0, |
1184 | }; |
1185 | |
1186 | static struct qcom_icc_node qns_sysnoc = { |
1187 | .name = "qns_sysnoc" , |
1188 | .id = SM8450_SLAVE_LPASS_SNOC, |
1189 | .channels = 1, |
1190 | .buswidth = 16, |
1191 | .num_links = 1, |
1192 | .links = { SM8450_MASTER_LPASS_ANOC }, |
1193 | }; |
1194 | |
1195 | static struct qcom_icc_node srvc_niu_aml_noc = { |
1196 | .name = "srvc_niu_aml_noc" , |
1197 | .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC, |
1198 | .channels = 1, |
1199 | .buswidth = 4, |
1200 | .num_links = 0, |
1201 | }; |
1202 | |
1203 | static struct qcom_icc_node srvc_niu_lpass_agnoc = { |
1204 | .name = "srvc_niu_lpass_agnoc" , |
1205 | .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC, |
1206 | .channels = 1, |
1207 | .buswidth = 4, |
1208 | .num_links = 0, |
1209 | }; |
1210 | |
1211 | static struct qcom_icc_node ebi = { |
1212 | .name = "ebi" , |
1213 | .id = SM8450_SLAVE_EBI1, |
1214 | .channels = 4, |
1215 | .buswidth = 4, |
1216 | .num_links = 0, |
1217 | }; |
1218 | |
1219 | static struct qcom_icc_node qns_mem_noc_hf = { |
1220 | .name = "qns_mem_noc_hf" , |
1221 | .id = SM8450_SLAVE_MNOC_HF_MEM_NOC, |
1222 | .channels = 2, |
1223 | .buswidth = 32, |
1224 | .num_links = 1, |
1225 | .links = { SM8450_MASTER_MNOC_HF_MEM_NOC }, |
1226 | }; |
1227 | |
1228 | static struct qcom_icc_node qns_mem_noc_sf = { |
1229 | .name = "qns_mem_noc_sf" , |
1230 | .id = SM8450_SLAVE_MNOC_SF_MEM_NOC, |
1231 | .channels = 2, |
1232 | .buswidth = 32, |
1233 | .num_links = 1, |
1234 | .links = { SM8450_MASTER_MNOC_SF_MEM_NOC }, |
1235 | }; |
1236 | |
1237 | static struct qcom_icc_node srvc_mnoc = { |
1238 | .name = "srvc_mnoc" , |
1239 | .id = SM8450_SLAVE_SERVICE_MNOC, |
1240 | .channels = 1, |
1241 | .buswidth = 4, |
1242 | .num_links = 0, |
1243 | }; |
1244 | |
1245 | static struct qcom_icc_node qns_nsp_gemnoc = { |
1246 | .name = "qns_nsp_gemnoc" , |
1247 | .id = SM8450_SLAVE_CDSP_MEM_NOC, |
1248 | .channels = 2, |
1249 | .buswidth = 32, |
1250 | .num_links = 1, |
1251 | .links = { SM8450_MASTER_COMPUTE_NOC }, |
1252 | }; |
1253 | |
1254 | static struct qcom_icc_node service_nsp_noc = { |
1255 | .name = "service_nsp_noc" , |
1256 | .id = SM8450_SLAVE_SERVICE_NSP_NOC, |
1257 | .channels = 1, |
1258 | .buswidth = 4, |
1259 | .num_links = 0, |
1260 | }; |
1261 | |
1262 | static struct qcom_icc_node qns_pcie_mem_noc = { |
1263 | .name = "qns_pcie_mem_noc" , |
1264 | .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC, |
1265 | .channels = 1, |
1266 | .buswidth = 16, |
1267 | .num_links = 1, |
1268 | .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC }, |
1269 | }; |
1270 | |
1271 | static struct qcom_icc_node srvc_pcie_aggre_noc = { |
1272 | .name = "srvc_pcie_aggre_noc" , |
1273 | .id = SM8450_SLAVE_SERVICE_PCIE_ANOC, |
1274 | .channels = 1, |
1275 | .buswidth = 4, |
1276 | .num_links = 0, |
1277 | }; |
1278 | |
1279 | static struct qcom_icc_node qns_gemnoc_gc = { |
1280 | .name = "qns_gemnoc_gc" , |
1281 | .id = SM8450_SLAVE_SNOC_GEM_NOC_GC, |
1282 | .channels = 1, |
1283 | .buswidth = 8, |
1284 | .num_links = 1, |
1285 | .links = { SM8450_MASTER_SNOC_GC_MEM_NOC }, |
1286 | }; |
1287 | |
1288 | static struct qcom_icc_node qns_gemnoc_sf = { |
1289 | .name = "qns_gemnoc_sf" , |
1290 | .id = SM8450_SLAVE_SNOC_GEM_NOC_SF, |
1291 | .channels = 1, |
1292 | .buswidth = 16, |
1293 | .num_links = 1, |
1294 | .links = { SM8450_MASTER_SNOC_SF_MEM_NOC }, |
1295 | }; |
1296 | |
1297 | static struct qcom_icc_node srvc_snoc = { |
1298 | .name = "srvc_snoc" , |
1299 | .id = SM8450_SLAVE_SERVICE_SNOC, |
1300 | .channels = 1, |
1301 | .buswidth = 4, |
1302 | .num_links = 0, |
1303 | }; |
1304 | |
1305 | static struct qcom_icc_node qns_llcc_disp = { |
1306 | .name = "qns_llcc_disp" , |
1307 | .id = SM8450_SLAVE_LLCC_DISP, |
1308 | .channels = 4, |
1309 | .buswidth = 16, |
1310 | .num_links = 1, |
1311 | .links = { SM8450_MASTER_LLCC_DISP }, |
1312 | }; |
1313 | |
1314 | static struct qcom_icc_node ebi_disp = { |
1315 | .name = "ebi_disp" , |
1316 | .id = SM8450_SLAVE_EBI1_DISP, |
1317 | .channels = 4, |
1318 | .buswidth = 4, |
1319 | .num_links = 0, |
1320 | }; |
1321 | |
1322 | static struct qcom_icc_node qns_mem_noc_hf_disp = { |
1323 | .name = "qns_mem_noc_hf_disp" , |
1324 | .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP, |
1325 | .channels = 2, |
1326 | .buswidth = 32, |
1327 | .num_links = 1, |
1328 | .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP }, |
1329 | }; |
1330 | |
1331 | static struct qcom_icc_node qns_mem_noc_sf_disp = { |
1332 | .name = "qns_mem_noc_sf_disp" , |
1333 | .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP, |
1334 | .channels = 2, |
1335 | .buswidth = 32, |
1336 | .num_links = 1, |
1337 | .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP }, |
1338 | }; |
1339 | |
1340 | static struct qcom_icc_bcm bcm_acv = { |
1341 | .name = "ACV" , |
1342 | .enable_mask = 0x8, |
1343 | .num_nodes = 1, |
1344 | .nodes = { &ebi }, |
1345 | }; |
1346 | |
1347 | static struct qcom_icc_bcm bcm_ce0 = { |
1348 | .name = "CE0" , |
1349 | .num_nodes = 1, |
1350 | .nodes = { &qxm_crypto }, |
1351 | }; |
1352 | |
1353 | static struct qcom_icc_bcm bcm_cn0 = { |
1354 | .name = "CN0" , |
1355 | .enable_mask = 0x1, |
1356 | .keepalive = true, |
1357 | .num_nodes = 55, |
1358 | .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, |
1359 | &qhs_ahb2phy0, &qhs_ahb2phy1, |
1360 | &qhs_aoss, &qhs_camera_cfg, |
1361 | &qhs_clk_ctl, &qhs_compute_cfg, |
1362 | &qhs_cpr_cx, &qhs_cpr_mmcx, |
1363 | &qhs_cpr_mxa, &qhs_cpr_mxc, |
1364 | &qhs_crypto0_cfg, &qhs_cx_rdpm, |
1365 | &qhs_display_cfg, &qhs_gpuss_cfg, |
1366 | &qhs_imem_cfg, &qhs_ipa, |
1367 | &qhs_ipc_router, &qhs_lpass_cfg, |
1368 | &qhs_mss_cfg, &qhs_mx_rdpm, |
1369 | &qhs_pcie0_cfg, &qhs_pcie1_cfg, |
1370 | &qhs_pdm, &qhs_pimem_cfg, |
1371 | &qhs_prng, &qhs_qdss_cfg, |
1372 | &qhs_qspi, &qhs_qup0, |
1373 | &qhs_qup1, &qhs_qup2, |
1374 | &qhs_sdc2, &qhs_sdc4, |
1375 | &qhs_spss_cfg, &qhs_tcsr, |
1376 | &qhs_tlmm, &qhs_tme_cfg, |
1377 | &qhs_ufs_mem_cfg, &qhs_usb3_0, |
1378 | &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, |
1379 | &qns_a1_noc_cfg, &qns_a2_noc_cfg, |
1380 | &qns_ddrss_cfg, &qns_mnoc_cfg, |
1381 | &qns_pcie_anoc_cfg, &qns_snoc_cfg, |
1382 | &qxs_imem, &qxs_pimem, |
1383 | &srvc_cnoc, &xs_pcie_0, |
1384 | &xs_pcie_1, &xs_qdss_stm, |
1385 | &xs_sys_tcu_cfg }, |
1386 | }; |
1387 | |
1388 | static struct qcom_icc_bcm bcm_co0 = { |
1389 | .name = "CO0" , |
1390 | .enable_mask = 0x1, |
1391 | .num_nodes = 2, |
1392 | .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, |
1393 | }; |
1394 | |
1395 | static struct qcom_icc_bcm bcm_mc0 = { |
1396 | .name = "MC0" , |
1397 | .keepalive = true, |
1398 | .num_nodes = 1, |
1399 | .nodes = { &ebi }, |
1400 | }; |
1401 | |
1402 | static struct qcom_icc_bcm bcm_mm0 = { |
1403 | .name = "MM0" , |
1404 | .keepalive = true, |
1405 | .num_nodes = 1, |
1406 | .nodes = { &qns_mem_noc_hf }, |
1407 | }; |
1408 | |
1409 | static struct qcom_icc_bcm bcm_mm1 = { |
1410 | .name = "MM1" , |
1411 | .enable_mask = 0x1, |
1412 | .num_nodes = 12, |
1413 | .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, |
1414 | &qnm_camnoc_sf, &qnm_mdp, |
1415 | &qnm_mnoc_cfg, &qnm_rot, |
1416 | &qnm_vapss_hcp, &qnm_video, |
1417 | &qnm_video_cv_cpu, &qnm_video_cvp, |
1418 | &qnm_video_v_cpu, &qns_mem_noc_sf }, |
1419 | }; |
1420 | |
1421 | static struct qcom_icc_bcm bcm_qup0 = { |
1422 | .name = "QUP0" , |
1423 | .keepalive = true, |
1424 | .vote_scale = 1, |
1425 | .num_nodes = 1, |
1426 | .nodes = { &qup0_core_slave }, |
1427 | }; |
1428 | |
1429 | static struct qcom_icc_bcm bcm_qup1 = { |
1430 | .name = "QUP1" , |
1431 | .keepalive = true, |
1432 | .vote_scale = 1, |
1433 | .num_nodes = 1, |
1434 | .nodes = { &qup1_core_slave }, |
1435 | }; |
1436 | |
1437 | static struct qcom_icc_bcm bcm_qup2 = { |
1438 | .name = "QUP2" , |
1439 | .keepalive = true, |
1440 | .vote_scale = 1, |
1441 | .num_nodes = 1, |
1442 | .nodes = { &qup2_core_slave }, |
1443 | }; |
1444 | |
1445 | static struct qcom_icc_bcm bcm_sh0 = { |
1446 | .name = "SH0" , |
1447 | .keepalive = true, |
1448 | .num_nodes = 1, |
1449 | .nodes = { &qns_llcc }, |
1450 | }; |
1451 | |
1452 | static struct qcom_icc_bcm bcm_sh1 = { |
1453 | .name = "SH1" , |
1454 | .enable_mask = 0x1, |
1455 | .num_nodes = 7, |
1456 | .nodes = { &alm_gpu_tcu, &alm_sys_tcu, |
1457 | &qnm_nsp_gemnoc, &qnm_pcie, |
1458 | &qnm_snoc_gc, &qns_gem_noc_cnoc, |
1459 | &qns_pcie }, |
1460 | }; |
1461 | |
1462 | static struct qcom_icc_bcm bcm_sn0 = { |
1463 | .name = "SN0" , |
1464 | .keepalive = true, |
1465 | .num_nodes = 1, |
1466 | .nodes = { &qns_gemnoc_sf }, |
1467 | }; |
1468 | |
1469 | static struct qcom_icc_bcm bcm_sn1 = { |
1470 | .name = "SN1" , |
1471 | .enable_mask = 0x1, |
1472 | .num_nodes = 4, |
1473 | .nodes = { &qhm_gic, &qxm_pimem, |
1474 | &xm_gic, &qns_gemnoc_gc }, |
1475 | }; |
1476 | |
1477 | static struct qcom_icc_bcm bcm_sn2 = { |
1478 | .name = "SN2" , |
1479 | .num_nodes = 1, |
1480 | .nodes = { &qnm_aggre1_noc }, |
1481 | }; |
1482 | |
1483 | static struct qcom_icc_bcm bcm_sn3 = { |
1484 | .name = "SN3" , |
1485 | .num_nodes = 1, |
1486 | .nodes = { &qnm_aggre2_noc }, |
1487 | }; |
1488 | |
1489 | static struct qcom_icc_bcm bcm_sn4 = { |
1490 | .name = "SN4" , |
1491 | .num_nodes = 1, |
1492 | .nodes = { &qnm_lpass_noc }, |
1493 | }; |
1494 | |
1495 | static struct qcom_icc_bcm bcm_sn7 = { |
1496 | .name = "SN7" , |
1497 | .num_nodes = 1, |
1498 | .nodes = { &qns_pcie_mem_noc }, |
1499 | }; |
1500 | |
1501 | static struct qcom_icc_bcm bcm_acv_disp = { |
1502 | .name = "ACV" , |
1503 | .enable_mask = 0x1, |
1504 | .num_nodes = 1, |
1505 | .nodes = { &ebi_disp }, |
1506 | }; |
1507 | |
1508 | static struct qcom_icc_bcm bcm_mc0_disp = { |
1509 | .name = "MC0" , |
1510 | .num_nodes = 1, |
1511 | .nodes = { &ebi_disp }, |
1512 | }; |
1513 | |
1514 | static struct qcom_icc_bcm bcm_mm0_disp = { |
1515 | .name = "MM0" , |
1516 | .num_nodes = 1, |
1517 | .nodes = { &qns_mem_noc_hf_disp }, |
1518 | }; |
1519 | |
1520 | static struct qcom_icc_bcm bcm_mm1_disp = { |
1521 | .name = "MM1" , |
1522 | .enable_mask = 0x1, |
1523 | .num_nodes = 3, |
1524 | .nodes = { &qnm_mdp_disp, &qnm_rot_disp, |
1525 | &qns_mem_noc_sf_disp }, |
1526 | }; |
1527 | |
1528 | static struct qcom_icc_bcm bcm_sh0_disp = { |
1529 | .name = "SH0" , |
1530 | .num_nodes = 1, |
1531 | .nodes = { &qns_llcc_disp }, |
1532 | }; |
1533 | |
1534 | static struct qcom_icc_bcm bcm_sh1_disp = { |
1535 | .name = "SH1" , |
1536 | .enable_mask = 0x1, |
1537 | .num_nodes = 1, |
1538 | .nodes = { &qnm_pcie_disp }, |
1539 | }; |
1540 | |
1541 | static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { |
1542 | }; |
1543 | |
1544 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { |
1545 | [MASTER_QSPI_0] = &qhm_qspi, |
1546 | [MASTER_QUP_1] = &qhm_qup1, |
1547 | [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, |
1548 | [MASTER_SDCC_4] = &xm_sdc4, |
1549 | [MASTER_UFS_MEM] = &xm_ufs_mem, |
1550 | [MASTER_USB3_0] = &xm_usb3_0, |
1551 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, |
1552 | [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, |
1553 | }; |
1554 | |
1555 | static const struct qcom_icc_desc sm8450_aggre1_noc = { |
1556 | .nodes = aggre1_noc_nodes, |
1557 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), |
1558 | .bcms = aggre1_noc_bcms, |
1559 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), |
1560 | }; |
1561 | |
1562 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { |
1563 | &bcm_ce0, |
1564 | }; |
1565 | |
1566 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { |
1567 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, |
1568 | [MASTER_QUP_0] = &qhm_qup0, |
1569 | [MASTER_QUP_2] = &qhm_qup2, |
1570 | [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, |
1571 | [MASTER_CRYPTO] = &qxm_crypto, |
1572 | [MASTER_IPA] = &qxm_ipa, |
1573 | [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, |
1574 | [MASTER_SP] = &qxm_sp, |
1575 | [MASTER_QDSS_ETR] = &xm_qdss_etr_0, |
1576 | [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, |
1577 | [MASTER_SDCC_2] = &xm_sdc2, |
1578 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, |
1579 | [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, |
1580 | }; |
1581 | |
1582 | static const struct qcom_icc_desc sm8450_aggre2_noc = { |
1583 | .nodes = aggre2_noc_nodes, |
1584 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), |
1585 | .bcms = aggre2_noc_bcms, |
1586 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), |
1587 | }; |
1588 | |
1589 | static struct qcom_icc_bcm * const clk_virt_bcms[] = { |
1590 | &bcm_qup0, |
1591 | &bcm_qup1, |
1592 | &bcm_qup2, |
1593 | }; |
1594 | |
1595 | static struct qcom_icc_node * const clk_virt_nodes[] = { |
1596 | [MASTER_QUP_CORE_0] = &qup0_core_master, |
1597 | [MASTER_QUP_CORE_1] = &qup1_core_master, |
1598 | [MASTER_QUP_CORE_2] = &qup2_core_master, |
1599 | [SLAVE_QUP_CORE_0] = &qup0_core_slave, |
1600 | [SLAVE_QUP_CORE_1] = &qup1_core_slave, |
1601 | [SLAVE_QUP_CORE_2] = &qup2_core_slave, |
1602 | }; |
1603 | |
1604 | static const struct qcom_icc_desc sm8450_clk_virt = { |
1605 | .nodes = clk_virt_nodes, |
1606 | .num_nodes = ARRAY_SIZE(clk_virt_nodes), |
1607 | .bcms = clk_virt_bcms, |
1608 | .num_bcms = ARRAY_SIZE(clk_virt_bcms), |
1609 | }; |
1610 | |
1611 | static struct qcom_icc_bcm * const config_noc_bcms[] = { |
1612 | &bcm_cn0, |
1613 | }; |
1614 | |
1615 | static struct qcom_icc_node * const config_noc_nodes[] = { |
1616 | [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, |
1617 | [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, |
1618 | [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, |
1619 | [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, |
1620 | [SLAVE_AOSS] = &qhs_aoss, |
1621 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, |
1622 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, |
1623 | [SLAVE_CDSP_CFG] = &qhs_compute_cfg, |
1624 | [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, |
1625 | [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, |
1626 | [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, |
1627 | [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, |
1628 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, |
1629 | [SLAVE_CX_RDPM] = &qhs_cx_rdpm, |
1630 | [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, |
1631 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, |
1632 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, |
1633 | [SLAVE_IPA_CFG] = &qhs_ipa, |
1634 | [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, |
1635 | [SLAVE_LPASS] = &qhs_lpass_cfg, |
1636 | [SLAVE_CNOC_MSS] = &qhs_mss_cfg, |
1637 | [SLAVE_MX_RDPM] = &qhs_mx_rdpm, |
1638 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, |
1639 | [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, |
1640 | [SLAVE_PDM] = &qhs_pdm, |
1641 | [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, |
1642 | [SLAVE_PRNG] = &qhs_prng, |
1643 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, |
1644 | [SLAVE_QSPI_0] = &qhs_qspi, |
1645 | [SLAVE_QUP_0] = &qhs_qup0, |
1646 | [SLAVE_QUP_1] = &qhs_qup1, |
1647 | [SLAVE_QUP_2] = &qhs_qup2, |
1648 | [SLAVE_SDCC_2] = &qhs_sdc2, |
1649 | [SLAVE_SDCC_4] = &qhs_sdc4, |
1650 | [SLAVE_SPSS_CFG] = &qhs_spss_cfg, |
1651 | [SLAVE_TCSR] = &qhs_tcsr, |
1652 | [SLAVE_TLMM] = &qhs_tlmm, |
1653 | [SLAVE_TME_CFG] = &qhs_tme_cfg, |
1654 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, |
1655 | [SLAVE_USB3_0] = &qhs_usb3_0, |
1656 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, |
1657 | [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, |
1658 | [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, |
1659 | [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, |
1660 | [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, |
1661 | [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, |
1662 | [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, |
1663 | [SLAVE_SNOC_CFG] = &qns_snoc_cfg, |
1664 | [SLAVE_IMEM] = &qxs_imem, |
1665 | [SLAVE_PIMEM] = &qxs_pimem, |
1666 | [SLAVE_SERVICE_CNOC] = &srvc_cnoc, |
1667 | [SLAVE_PCIE_0] = &xs_pcie_0, |
1668 | [SLAVE_PCIE_1] = &xs_pcie_1, |
1669 | [SLAVE_QDSS_STM] = &xs_qdss_stm, |
1670 | [SLAVE_TCU] = &xs_sys_tcu_cfg, |
1671 | }; |
1672 | |
1673 | static const struct qcom_icc_desc sm8450_config_noc = { |
1674 | .nodes = config_noc_nodes, |
1675 | .num_nodes = ARRAY_SIZE(config_noc_nodes), |
1676 | .bcms = config_noc_bcms, |
1677 | .num_bcms = ARRAY_SIZE(config_noc_bcms), |
1678 | }; |
1679 | |
1680 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { |
1681 | &bcm_sh0, |
1682 | &bcm_sh1, |
1683 | &bcm_sh0_disp, |
1684 | &bcm_sh1_disp, |
1685 | }; |
1686 | |
1687 | static struct qcom_icc_node * const gem_noc_nodes[] = { |
1688 | [MASTER_GPU_TCU] = &alm_gpu_tcu, |
1689 | [MASTER_SYS_TCU] = &alm_sys_tcu, |
1690 | [MASTER_APPSS_PROC] = &chm_apps, |
1691 | [MASTER_GFX3D] = &qnm_gpu, |
1692 | [MASTER_MSS_PROC] = &qnm_mdsp, |
1693 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, |
1694 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, |
1695 | [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, |
1696 | [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, |
1697 | [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, |
1698 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, |
1699 | [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, |
1700 | [SLAVE_LLCC] = &qns_llcc, |
1701 | [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, |
1702 | [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, |
1703 | [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp, |
1704 | [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, |
1705 | [SLAVE_LLCC_DISP] = &qns_llcc_disp, |
1706 | }; |
1707 | |
1708 | static const struct qcom_icc_desc sm8450_gem_noc = { |
1709 | .nodes = gem_noc_nodes, |
1710 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), |
1711 | .bcms = gem_noc_bcms, |
1712 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), |
1713 | }; |
1714 | |
1715 | static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { |
1716 | }; |
1717 | |
1718 | static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { |
1719 | [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, |
1720 | [MASTER_LPASS_PROC] = &qxm_lpass_dsp, |
1721 | [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, |
1722 | [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, |
1723 | [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, |
1724 | [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, |
1725 | [SLAVE_LPASS_SNOC] = &qns_sysnoc, |
1726 | [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, |
1727 | [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, |
1728 | }; |
1729 | |
1730 | static const struct qcom_icc_desc sm8450_lpass_ag_noc = { |
1731 | .nodes = lpass_ag_noc_nodes, |
1732 | .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), |
1733 | .bcms = lpass_ag_noc_bcms, |
1734 | .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), |
1735 | }; |
1736 | |
1737 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { |
1738 | &bcm_acv, |
1739 | &bcm_mc0, |
1740 | &bcm_acv_disp, |
1741 | &bcm_mc0_disp, |
1742 | }; |
1743 | |
1744 | static struct qcom_icc_node * const mc_virt_nodes[] = { |
1745 | [MASTER_LLCC] = &llcc_mc, |
1746 | [SLAVE_EBI1] = &ebi, |
1747 | [MASTER_LLCC_DISP] = &llcc_mc_disp, |
1748 | [SLAVE_EBI1_DISP] = &ebi_disp, |
1749 | }; |
1750 | |
1751 | static const struct qcom_icc_desc sm8450_mc_virt = { |
1752 | .nodes = mc_virt_nodes, |
1753 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), |
1754 | .bcms = mc_virt_bcms, |
1755 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), |
1756 | }; |
1757 | |
1758 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { |
1759 | &bcm_mm0, |
1760 | &bcm_mm1, |
1761 | &bcm_mm0_disp, |
1762 | &bcm_mm1_disp, |
1763 | }; |
1764 | |
1765 | static struct qcom_icc_node * const mmss_noc_nodes[] = { |
1766 | [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, |
1767 | [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, |
1768 | [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, |
1769 | [MASTER_MDP] = &qnm_mdp, |
1770 | [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, |
1771 | [MASTER_ROTATOR] = &qnm_rot, |
1772 | [MASTER_CDSP_HCP] = &qnm_vapss_hcp, |
1773 | [MASTER_VIDEO] = &qnm_video, |
1774 | [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, |
1775 | [MASTER_VIDEO_PROC] = &qnm_video_cvp, |
1776 | [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, |
1777 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, |
1778 | [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, |
1779 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, |
1780 | [MASTER_MDP_DISP] = &qnm_mdp_disp, |
1781 | [MASTER_ROTATOR_DISP] = &qnm_rot_disp, |
1782 | [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, |
1783 | [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, |
1784 | }; |
1785 | |
1786 | static const struct qcom_icc_desc sm8450_mmss_noc = { |
1787 | .nodes = mmss_noc_nodes, |
1788 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), |
1789 | .bcms = mmss_noc_bcms, |
1790 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), |
1791 | }; |
1792 | |
1793 | static struct qcom_icc_bcm * const nsp_noc_bcms[] = { |
1794 | &bcm_co0, |
1795 | }; |
1796 | |
1797 | static struct qcom_icc_node * const nsp_noc_nodes[] = { |
1798 | [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, |
1799 | [MASTER_CDSP_PROC] = &qxm_nsp, |
1800 | [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, |
1801 | [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, |
1802 | }; |
1803 | |
1804 | static const struct qcom_icc_desc sm8450_nsp_noc = { |
1805 | .nodes = nsp_noc_nodes, |
1806 | .num_nodes = ARRAY_SIZE(nsp_noc_nodes), |
1807 | .bcms = nsp_noc_bcms, |
1808 | .num_bcms = ARRAY_SIZE(nsp_noc_bcms), |
1809 | }; |
1810 | |
1811 | static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { |
1812 | &bcm_sn7, |
1813 | }; |
1814 | |
1815 | static struct qcom_icc_node * const pcie_anoc_nodes[] = { |
1816 | [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, |
1817 | [MASTER_PCIE_0] = &xm_pcie3_0, |
1818 | [MASTER_PCIE_1] = &xm_pcie3_1, |
1819 | [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, |
1820 | [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, |
1821 | }; |
1822 | |
1823 | static const struct qcom_icc_desc sm8450_pcie_anoc = { |
1824 | .nodes = pcie_anoc_nodes, |
1825 | .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), |
1826 | .bcms = pcie_anoc_bcms, |
1827 | .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), |
1828 | }; |
1829 | |
1830 | static struct qcom_icc_bcm * const system_noc_bcms[] = { |
1831 | &bcm_sn0, |
1832 | &bcm_sn1, |
1833 | &bcm_sn2, |
1834 | &bcm_sn3, |
1835 | &bcm_sn4, |
1836 | }; |
1837 | |
1838 | static struct qcom_icc_node * const system_noc_nodes[] = { |
1839 | [MASTER_GIC_AHB] = &qhm_gic, |
1840 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, |
1841 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, |
1842 | [MASTER_LPASS_ANOC] = &qnm_lpass_noc, |
1843 | [MASTER_SNOC_CFG] = &qnm_snoc_cfg, |
1844 | [MASTER_PIMEM] = &qxm_pimem, |
1845 | [MASTER_GIC] = &xm_gic, |
1846 | [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, |
1847 | [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, |
1848 | [SLAVE_SERVICE_SNOC] = &srvc_snoc, |
1849 | }; |
1850 | |
1851 | static const struct qcom_icc_desc sm8450_system_noc = { |
1852 | .nodes = system_noc_nodes, |
1853 | .num_nodes = ARRAY_SIZE(system_noc_nodes), |
1854 | .bcms = system_noc_bcms, |
1855 | .num_bcms = ARRAY_SIZE(system_noc_bcms), |
1856 | }; |
1857 | |
1858 | static const struct of_device_id qnoc_of_match[] = { |
1859 | { .compatible = "qcom,sm8450-aggre1-noc" , |
1860 | .data = &sm8450_aggre1_noc}, |
1861 | { .compatible = "qcom,sm8450-aggre2-noc" , |
1862 | .data = &sm8450_aggre2_noc}, |
1863 | { .compatible = "qcom,sm8450-clk-virt" , |
1864 | .data = &sm8450_clk_virt}, |
1865 | { .compatible = "qcom,sm8450-config-noc" , |
1866 | .data = &sm8450_config_noc}, |
1867 | { .compatible = "qcom,sm8450-gem-noc" , |
1868 | .data = &sm8450_gem_noc}, |
1869 | { .compatible = "qcom,sm8450-lpass-ag-noc" , |
1870 | .data = &sm8450_lpass_ag_noc}, |
1871 | { .compatible = "qcom,sm8450-mc-virt" , |
1872 | .data = &sm8450_mc_virt}, |
1873 | { .compatible = "qcom,sm8450-mmss-noc" , |
1874 | .data = &sm8450_mmss_noc}, |
1875 | { .compatible = "qcom,sm8450-nsp-noc" , |
1876 | .data = &sm8450_nsp_noc}, |
1877 | { .compatible = "qcom,sm8450-pcie-anoc" , |
1878 | .data = &sm8450_pcie_anoc}, |
1879 | { .compatible = "qcom,sm8450-system-noc" , |
1880 | .data = &sm8450_system_noc}, |
1881 | { } |
1882 | }; |
1883 | MODULE_DEVICE_TABLE(of, qnoc_of_match); |
1884 | |
1885 | static struct platform_driver qnoc_driver = { |
1886 | .probe = qcom_icc_rpmh_probe, |
1887 | .remove_new = qcom_icc_rpmh_remove, |
1888 | .driver = { |
1889 | .name = "qnoc-sm8450" , |
1890 | .of_match_table = qnoc_of_match, |
1891 | .sync_state = icc_sync_state, |
1892 | }, |
1893 | }; |
1894 | |
1895 | static int __init qnoc_driver_init(void) |
1896 | { |
1897 | return platform_driver_register(&qnoc_driver); |
1898 | } |
1899 | core_initcall(qnoc_driver_init); |
1900 | |
1901 | static void __exit qnoc_driver_exit(void) |
1902 | { |
1903 | platform_driver_unregister(&qnoc_driver); |
1904 | } |
1905 | module_exit(qnoc_driver_exit); |
1906 | |
1907 | MODULE_DESCRIPTION("sm8450 NoC driver" ); |
1908 | MODULE_LICENSE("GPL v2" ); |
1909 | |